diff options
Diffstat (limited to 'gnu/usr.bin/binutils/include')
45 files changed, 5884 insertions, 484 deletions
diff --git a/gnu/usr.bin/binutils/include/bin-bugs.h b/gnu/usr.bin/binutils/include/bin-bugs.h new file mode 100644 index 00000000000..cb14a66bf66 --- /dev/null +++ b/gnu/usr.bin/binutils/include/bin-bugs.h @@ -0,0 +1,3 @@ +#ifndef REPORT_BUGS_TO +#define REPORT_BUGS_TO "bug-gnu-utils@gnu.org" +#endif diff --git a/gnu/usr.bin/binutils/include/coff/go32exe.h b/gnu/usr.bin/binutils/include/coff/go32exe.h new file mode 100644 index 00000000000..5bd26c13401 --- /dev/null +++ b/gnu/usr.bin/binutils/include/coff/go32exe.h @@ -0,0 +1,20 @@ +/* COFF information for PC running go32. */ + +#define STUBSIZE 2048 + +struct external_filehdr_go32_exe { + char stub[STUBSIZE]; /* the stub to load the image */ + /* the standard COFF header */ + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ +}; + +#undef FILHDR +#define FILHDR struct external_filehdr_go32_exe +#undef FILHSZ +#define FILHSZ STUBSIZE+20 diff --git a/gnu/usr.bin/binutils/include/coff/mcore.h b/gnu/usr.bin/binutils/include/coff/mcore.h new file mode 100644 index 00000000000..0fa319c977f --- /dev/null +++ b/gnu/usr.bin/binutils/include/coff/mcore.h @@ -0,0 +1,246 @@ +/* Motorola MCore support for BFD. + Copyright (C) 1999 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file holds definitions specific to the MCore COFF/PE ABI. */ + +#ifndef _COFF_MORE_H +#define _COFF_MORE_H + + +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +#define IMAGE_REL_MCORE_ABSOLUTE 0x0000 +#define IMAGE_REL_MCORE_ADDR32 0x0001 +#define IMAGE_REL_MCORE_PCREL_IMM8BY4 0x0002 +#define IMAGE_REL_MCORE_PCREL_IMM11BY2 0x0003 +#define IMAGE_REL_MCORE_PCREL_IMM4BY2 0x0004 +#define IMAGE_REL_MCORE_PCREL_32 0x0005 +#define IMAGE_REL_MCORE_PCREL_JSR_IMM11BY2 0x0006 +#define IMAGE_REL_MCORE_RVA 0x0007 + +#define PEMCORE + +typedef struct +{ + char magic [2]; /* type of file */ + char vstamp [2]; /* version stamp */ + char tsize [4]; /* text size in bytes, padded to FW bdry*/ + char dsize [4]; /* initialized data " " */ + char bsize [4]; /* uninitialized data " " */ + char entry [4]; /* entry pt. */ + char text_start [4]; /* base of text used for this file */ + char data_start [4]; /* base of data used for this file */ +} +AOUTHDR; + +#define AOUTSZ 28 +#define AOUTHDRSZ 28 + +#define OMAGIC 0404 /* object files, eg as output */ +#define ZMAGIC 0413 /* demand load format, eg normal ld output */ +#define STMAGIC 0401 /* target shlib */ +#define SHMAGIC 0443 /* host shlib */ + +/* From winnt.h */ +#define IMAGE_NT_OPTIONAL_HDR_MAGIC 0x10b + + +/* Define some NT default values. */ +#define NT_SECTION_ALIGNMENT 0x1000 +#define NT_FILE_ALIGNMENT 0x200 +#define NT_DEF_RESERVE 0x100000 +#define NT_DEF_COMMIT 0x1000 + + +struct external_reloc +{ + char r_vaddr [4]; + char r_symndx [4]; + char r_type [2]; + char r_offset [4]; +}; + +#define RELOC struct external_reloc +#define RELSZ 14 + +#define MCOREMAGIC 0xb00 /* I just made this up */ + +#define MCOREBADMAG(x) (((x).f_magic!= MCOREMAGIC)) + +struct external_filehdr +{ + char f_magic [2]; /* magic number */ + char f_nscns [2]; /* number of sections */ + char f_timdat [4]; /* time & date stamp */ + char f_symptr [4]; /* file pointer to symtab */ + char f_nsyms [4]; /* number of symtab entries */ + char f_opthdr [2]; /* sizeof(optional hdr) */ + char f_flags [2]; /* flags */ +}; + +#define FILHDR struct external_filehdr +#define FILHSZ 20 + + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union + { + char e_name [E_SYMNMLEN]; + struct + { + char e_zeroes [4]; + char e_offset [4]; + } e; + } e; + + char e_value [4]; + char e_scnum [2]; + char e_type [2]; + char e_sclass [1]; + char e_numaux [1]; +}; + +#define N_BTMASK 0xf +#define N_TMASK 0x30 +#define N_BTSHFT 4 +#define N_TSHIFT 2 + +union external_auxent +{ + struct + { + char x_tagndx [4]; /* str, un, or enum tag indx */ + + union + { + struct + { + char x_lnno [2]; /* declaration line number */ + char x_size [2]; /* str/union/array size */ + } x_lnsz; + + char x_fsize [4]; /* size of function */ + + } x_misc; + + union + { + struct /* if ISFCN, tag, or .bb */ + { + char x_lnnoptr [4]; /* ptr to fcn line # */ + char x_endndx [4]; /* entry ndx past block end */ + } x_fcn; + + struct /* if ISARY, up to 4 dimen. */ + { + char x_dimen [E_DIMNUM][2]; + } x_ary; + + } x_fcnary; + + char x_tvndx [2]; /* tv index */ + + } x_sym; + + union + { + char x_fname [E_FILNMLEN]; + + struct + { + char x_zeroes [4]; + char x_offset [4]; + } x_n; + + } x_file; + + struct + { + char x_scnlen [4]; /* section length */ + char x_nreloc [2]; /* # relocation entries */ + char x_nlinno [2]; /* # line numbers */ + char x_checksum [4]; /* section COMDAT checksum */ + char x_associated [2]; /* COMDAT associated section index */ + char x_comdat [1]; /* COMDAT selection number */ + } x_scn; + + struct + { + char x_tvfill [4]; /* tv fill value */ + char x_tvlen [2]; /* length of .tv */ + char x_tvran [2][2]; /* tv range */ + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ +}; + +#define SYMENT struct external_syment +#define SYMESZ 18 +#define AUXENT union external_auxent +#define AUXESZ 18 + +/* 1 line number entry for every "breakpointable" source line in a section. + Line numbers are grouped on a per function basis; first entry in a function + grouping will have l_lnno = 0 and in place of physical address will be the + symbol table index of the function name. */ +struct external_lineno +{ + union + { + char l_symndx [4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr [4]; /* (physical) address of line number */ + } l_addr; + + char l_lnno [2]; /* line number */ +}; + +#define LINENO struct external_lineno +#define LINESZ 6 + +#define GET_LINENO_LNNO(abfd, ext) bfd_h_get_32 (abfd, (bfd_byte *) (ext->l_lnno)); +#define PUT_LINENO_LNNO(abfd,val, ext) bfd_h_put_32 (abfd, val, (bfd_byte *) (ext->l_lnno)); + +struct external_scnhdr +{ + char s_name [8]; /* section name */ + char s_paddr [4]; /* physical address, aliased s_nlib */ + char s_vaddr [4]; /* virtual address */ + char s_size [4]; /* section size */ + char s_scnptr [4]; /* file ptr to raw data for section */ + char s_relptr [4]; /* file ptr to relocation */ + char s_lnnoptr [4]; /* file ptr to line numbers */ + char s_nreloc [2]; /* number of relocation entries */ + char s_nlnno [2]; /* number of line number entries*/ + char s_flags [4]; /* flags */ +}; + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 40 + +/* Names of "special" sections. */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" + + + +#endif /* __COFF_MCORE_H */ diff --git a/gnu/usr.bin/binutils/include/coff/mipspe.h b/gnu/usr.bin/binutils/include/coff/mipspe.h new file mode 100644 index 00000000000..1927d991d3b --- /dev/null +++ b/gnu/usr.bin/binutils/include/coff/mipspe.h @@ -0,0 +1,223 @@ +/*** coff information for Windows CE with MIPS VR4111 */ + +/********************** FILE HEADER **********************/ + +struct external_filehdr { + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ +}; + + + +#define MIPS_ARCH_MAGIC_WINCE 0x0166 /* Windows CE - little endian */ +#define MIPS_PE_MAGIC 0x010b + +#define MIPSBADMAG(x) \ + ((x).f_magic!=MIPS_ARCH_MAGIC_WINCE) + +#define FILHDR struct external_filehdr +#define FILHSZ 20 + + +/********************** AOUT "OPTIONAL HEADER" **********************/ + + +typedef struct +{ + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry*/ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ +} +AOUTHDR; + + +#define AOUTHDRSZ 28 +#define AOUTSZ 28 + + + + +/* define some NT default values */ +/* #define NT_IMAGE_BASE 0x400000 moved to internal.h */ +#define NT_SECTION_ALIGNMENT 0x1000 +#define NT_FILE_ALIGNMENT 0x200 +#define NT_DEF_RESERVE 0x100000 +#define NT_DEF_COMMIT 0x1000 + +/********************** SECTION HEADER **********************/ + + +struct external_scnhdr { + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries*/ + char s_flags[4]; /* flags */ +}; + +/* + * names of "special" sections + */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" + + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 40 + + +/********************** LINE NUMBERS **********************/ + +/* 1 line number entry for every "breakpointable" source line in a section. + * Line numbers are grouped on a per function basis; first entry in a function + * grouping will have l_lnno = 0 and in place of physical address will be the + * symbol table index of the function name. + */ +struct external_lineno { + union { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[4]; /* (physical) address of line number */ + } l_addr; + char l_lnno[2]; /* line number */ +}; + +#define GET_LINENO_LNNO(abfd, ext) bfd_h_get_16(abfd, (bfd_byte *) (ext->l_lnno)); +#define PUT_LINENO_LNNO(abfd,val, ext) bfd_h_put_16(abfd,val, (bfd_byte *) (ext->l_lnno)); + +#define LINENO struct external_lineno +#define LINESZ 6 + + +/********************** SYMBOLS **********************/ + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union { + char e_name[E_SYMNMLEN]; + struct { + char e_zeroes[4]; + char e_offset[4]; + } e; + } e; + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; +}; + + + +#define N_BTMASK (017) +#define N_TMASK (060) +#define N_BTSHFT (4) +#define N_TSHIFT (2) + + +union external_auxent { + struct { + char x_tagndx[4]; /* str, un, or enum tag indx */ + union { + struct { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + char x_fsize[4]; /* size of function */ + } x_misc; + union { + struct { /* if ISFCN, tag, or .bb */ + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + struct { /* if ISARY, up to 4 dimen. */ + char x_dimen[E_DIMNUM][2]; + } x_ary; + } x_fcnary; + char x_tvndx[2]; /* tv index */ + } x_sym; + + union { + char x_fname[E_FILNMLEN]; + struct { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + } x_file; + + struct { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + char x_checksum[4]; /* section COMDAT checksum */ + char x_associated[2]; /* COMDAT associated section index */ + char x_comdat[1]; /* COMDAT selection number */ + } x_scn; + + struct { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ + + +}; + +#define SYMENT struct external_syment +#define SYMESZ 18 +#define AUXENT union external_auxent +#define AUXESZ 18 + + + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the h8 don't have room in the instruction for the entire + offset - eg the strange jump and high page addressing modes */ + +struct external_reloc { + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; + + +#define RELOC struct external_reloc +#define RELSZ 10 + +/* MIPS PE relocation types. */ + +#define MIPS_R_ABSOLUTE 0 /* ignored */ +#define MIPS_R_REFHALF 1 +#define MIPS_R_REFWORD 2 +#define MIPS_R_JMPADDR 3 +#define MIPS_R_REFHI 4 /* PAIR follows */ +#define MIPS_R_REFLO 5 +#define MIPS_R_GPREL 6 +#define MIPS_R_LITERAL 7 /* same as GPREL */ +#define MIPS_R_SECTION 10 +#define MIPS_R_SECREL 11 +#define MIPS_R_SECRELLO 12 +#define MIPS_R_SECRELHI 13 /* PAIR follows */ +#define MIPS_R_RVA 34 /* 0x22 */ +#define MIPS_R_PAIR 37 /* 0x25 - symndx is really a signed 16-bit addend */ diff --git a/gnu/usr.bin/binutils/include/coff/tic30.h b/gnu/usr.bin/binutils/include/coff/tic30.h new file mode 100644 index 00000000000..10b026cebe2 --- /dev/null +++ b/gnu/usr.bin/binutils/include/coff/tic30.h @@ -0,0 +1,203 @@ +/*** coff information for Texas Instruments TMS320C3X */ + +/********************** FILE HEADER **********************/ + +struct external_filehdr { + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ +}; + + +#define TIC30MAGIC 0xC000 + +#define TIC30BADMAG(x) (((x).f_magic!=TIC30MAGIC)) + +#define FILHDR struct external_filehdr +#define FILHSZ 20 + + +/********************** AOUT "OPTIONAL HEADER" **********************/ + + +typedef struct +{ + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry*/ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ +} +AOUTHDR; + + +#define AOUTHDRSZ 28 +#define AOUTSZ 28 + + + + +/********************** SECTION HEADER **********************/ + + +struct external_scnhdr { + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries*/ + char s_flags[4]; /* flags */ +}; + +/* + * names of "special" sections + */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" + + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 40 + + +/********************** LINE NUMBERS **********************/ + +/* 1 line number entry for every "breakpointable" source line in a section. + * Line numbers are grouped on a per function basis; first entry in a function + * grouping will have l_lnno = 0 and in place of physical address will be the + * symbol table index of the function name. + */ +struct external_lineno { + union { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[4]; /* (physical) address of line number */ + } l_addr; + char l_lnno[4]; /* line number */ +}; + +#define GET_LINENO_LNNO(abfd, ext) bfd_h_get_32(abfd, (bfd_byte *) (ext->l_lnno)); +#define PUT_LINENO_LNNO(abfd,val, ext) bfd_h_put_32(abfd,val, (bfd_byte *) (ext->l_lnno)); + +#define LINENO struct external_lineno +#define LINESZ 8 + + +/********************** SYMBOLS **********************/ + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union { + char e_name[E_SYMNMLEN]; + struct { + char e_zeroes[4]; + char e_offset[4]; + } e; + } e; + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; +}; + + + +#define N_BTMASK (017) +#define N_TMASK (060) +#define N_BTSHFT (4) +#define N_TSHIFT (2) + + +union external_auxent { + struct { + char x_tagndx[4]; /* str, un, or enum tag indx */ + union { + struct { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + char x_fsize[4]; /* size of function */ + } x_misc; + union { + struct { /* if ISFCN, tag, or .bb */ + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + struct { /* if ISARY, up to 4 dimen. */ + char x_dimen[E_DIMNUM][2]; + } x_ary; + } x_fcnary; + char x_tvndx[2]; /* tv index */ + } x_sym; + + union { + char x_fname[E_FILNMLEN]; + struct { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + } x_file; + + struct { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + } x_scn; + + struct { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ + + +}; + +#define SYMENT struct external_syment +#define SYMESZ 18 +#define AUXENT union external_auxent +#define AUXESZ 18 + + + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the z8k don't have room in the instruction for the entire + offset - eg with segments */ + +struct external_reloc { + char r_vaddr[4]; + char r_symndx[4]; + char r_offset[4]; + char r_type[2]; + char r_stuff[2]; +}; + + +#define RELOC struct external_reloc +#define RELSZ 16 + +/* TMS320C30 relocation types. */ + +#define R_TIC30_ABS16 0x100 /* 16 bit absolute. */ +#define R_TIC30_ABS24 0x101 /* 24 bit absolute. */ +#define R_TIC30_ABS32 0x102 /* 32 bit absolute. */ +#define R_TIC30_LDP 0x103 /* LDP bits 23-16 to 7-0. */ +#define R_TIC30_PC16 0x104 /* 16 bit pc relative. */ diff --git a/gnu/usr.bin/binutils/include/coff/tic80.h b/gnu/usr.bin/binutils/include/coff/tic80.h new file mode 100644 index 00000000000..5d938f7b1f0 --- /dev/null +++ b/gnu/usr.bin/binutils/include/coff/tic80.h @@ -0,0 +1,228 @@ +/*** coff information for TI TMS320C80 (MVP) */ + +/********************** FILE HEADER **********************/ + +struct external_filehdr { + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ + char f_target_id[2]; /* target id (TIc80 specific) */ +}; + +#define TIC80_ARCH_MAGIC 0x0C1 /* Goes in the file header magic number field */ +#define TIC80_TARGET_ID 0x95 /* Goes in the target id field */ + +#define TIC80BADMAG(x) ((x).f_magic != TIC80_ARCH_MAGIC) + +#define FILHDR struct external_filehdr +#define FILHSZ 22 + + +/********************** AOUT "OPTIONAL HEADER" **********************/ + + +typedef struct +{ + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry*/ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ +} +AOUTHDR; + +#define TIC80_AOUTHDR_MAGIC 0x108 /* Goes in the optional file header magic number field */ + +#define AOUTHDRSZ 28 +#define AOUTSZ 28 + + + + +/********************** SECTION HEADER **********************/ + + +struct external_scnhdr { + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries*/ + char s_flags[2]; /* flags */ + char s_reserved[1]; /* reserved (TIc80 specific) */ + char s_mempage[1]; /* memory page number (TIc80) */ +}; + +/* + * names of "special" sections + */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" +#define _CINIT ".cinit" +#define _CONST ".const" +#define _SWITCH ".switch" +#define _STACK ".stack" +#define _SYSMEM ".sysmem" + + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 40 + + +/********************** LINE NUMBERS **********************/ + +/* 1 line number entry for every "breakpointable" source line in a section. + * Line numbers are grouped on a per function basis; first entry in a function + * grouping will have l_lnno = 0 and in place of physical address will be the + * symbol table index of the function name. + */ +struct external_lineno { + union { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[4]; /* (physical) address of line number */ + } l_addr; + char l_lnno[2]; /* line number */ +}; + +#define GET_LINENO_LNNO(abfd, ext) bfd_h_get_16(abfd, (bfd_byte *) (ext->l_lnno)); +#define PUT_LINENO_LNNO(abfd,val, ext) bfd_h_put_16(abfd,val, (bfd_byte *) (ext->l_lnno)); + +#define LINENO struct external_lineno +#define LINESZ 6 + + +/********************** SYMBOLS **********************/ + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union { + char e_name[E_SYMNMLEN]; + struct { + char e_zeroes[4]; + char e_offset[4]; + } e; + } e; + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; +}; + + + +#define N_BTMASK (017) +#define N_TMASK (060) +#define N_BTSHFT (4) +#define N_TSHIFT (2) + +/* FIXME - need to correlate with TIc80 Code Generation Tools User's Guide, CG:A-25 */ +union external_auxent { + struct { + char x_tagndx[4]; /* str, un, or enum tag indx */ + union { + struct { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + char x_fsize[4]; /* size of function */ + } x_misc; + union { + struct { /* if ISFCN, tag, or .bb */ + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + struct { /* if ISARY, up to 4 dimen. */ + char x_dimen[E_DIMNUM][2]; + } x_ary; + } x_fcnary; + char x_tvndx[2]; /* tv index */ + } x_sym; + + union { + char x_fname[E_FILNMLEN]; + struct { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + } x_file; + + struct { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + } x_scn; + + struct { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ + + +}; + +#define SYMENT struct external_syment +#define SYMESZ 18 +#define AUXENT union external_auxent +#define AUXESZ 18 + + + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the h8 don't have room in the instruction for the entire + offset - eg the strange jump and high page addressing modes */ + +struct external_reloc { + char r_vaddr[4]; + char r_symndx[4]; + char r_reserved[2]; + char r_type[2]; +}; + + +#define RELOC struct external_reloc +#define RELSZ 12 + +/* TIc80 relocation types. */ + +#define R_ABS 0x00 /* Absolute address - no relocation */ +#define R_RELLONGX 0x11 /* PP: 32 bits, direct */ +#define R_PPBASE 0x34 /* PP: Global base address type */ +#define R_PPLBASE 0x35 /* PP: Local base address type */ +#define R_PP15 0x38 /* PP: Global 15 bit offset */ +#define R_PP15W 0x39 /* PP: Global 15 bit offset divided by 4 */ +#define R_PP15H 0x3A /* PP: Global 15 bit offset divided by 2 */ +#define R_PP16B 0x3B /* PP: Global 16 bit offset for bytes */ +#define R_PPL15 0x3C /* PP: Local 15 bit offset */ +#define R_PPL15W 0x3D /* PP: Local 15 bit offset divided by 4 */ +#define R_PPL15H 0x3E /* PP: Local 15 bit offset divided by 2 */ +#define R_PPL16B 0x3F /* PP: Local 16 bit offset for bytes */ +#define R_PPN15 0x40 /* PP: Global 15 bit negative offset */ +#define R_PPN15W 0x41 /* PP: Global 15 bit negative offset divided by 4 */ +#define R_PPN15H 0x42 /* PP: Global 15 bit negative offset divided by 2 */ +#define R_PPN16B 0x43 /* PP: Global 16 bit negative byte offset */ +#define R_PPLN15 0x44 /* PP: Local 15 bit negative offset */ +#define R_PPLN15W 0x45 /* PP: Local 15 bit negative offset divided by 4 */ +#define R_PPLN15H 0x46 /* PP: Local 15 bit negative offset divided by 2 */ +#define R_PPLN16B 0x47 /* PP: Local 16 bit negative byte offset */ +#define R_MPPCR15W 0x4E /* MP: 15 bit PC-relative divided by 4 */ +#define R_MPPCR 0x4F /* MP: 32 bit PC-relative divided by 4 */ diff --git a/gnu/usr.bin/binutils/include/elf/alpha.h b/gnu/usr.bin/binutils/include/elf/alpha.h index 8e12dd9aa32..1ae9d5efd6d 100644 --- a/gnu/usr.bin/binutils/include/elf/alpha.h +++ b/gnu/usr.bin/binutils/include/elf/alpha.h @@ -1,5 +1,5 @@ /* ALPHA ELF support for BFD. - Copyright (C) 1996 Free Software Foundation, Inc. + Copyright (C) 1996, 1998 Free Software Foundation, Inc. By Eric Youngdale, <eric@aib.com>. No processor supplement available for this platform. @@ -26,6 +26,14 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef _ELF_ALPHA_H #define _ELF_ALPHA_H +/* Processor specific flags for the ELF header e_flags field. */ + +/* All addresses must be below 2GB. */ +#define EF_ALPHA_32BIT 0x00000001 + +/* All relocations needed for relaxation with code movement are present. */ +#define EF_ALPHA_CANRELAX 0x00000002 + /* Processor specific section flags. */ /* This section must be in the global data area. */ @@ -50,43 +58,51 @@ typedef struct long ri_gp_value; } Elf64_RegInfo; -/* Alpha relocs. */ +/* Special values for the st_other field in the symbol table. */ -#define R_ALPHA_NONE 0 /* No reloc */ -#define R_ALPHA_REFLONG 1 /* Direct 32 bit */ -#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ -#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ -#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ -#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ -#define R_ALPHA_GPDISP 6 /* Add displacement to GP */ -#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ -#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ -#define R_ALPHA_SREL16 9 /* PC relative 16 bit */ -#define R_ALPHA_SREL32 10 /* PC relative 32 bit */ -#define R_ALPHA_SREL64 11 /* PC relative 64 bit */ +#define STO_ALPHA_NOPV 0x80 +#define STO_ALPHA_STD_GPLOAD 0x88 + +#include "elf/reloc-macros.h" + +/* Alpha relocs. */ +START_RELOC_NUMBERS (elf_alpha_reloc_type) + RELOC_NUMBER (R_ALPHA_NONE, 0) /* No reloc */ + RELOC_NUMBER (R_ALPHA_REFLONG, 1) /* Direct 32 bit */ + RELOC_NUMBER (R_ALPHA_REFQUAD, 2) /* Direct 64 bit */ + RELOC_NUMBER (R_ALPHA_GPREL32, 3) /* GP relative 32 bit */ + RELOC_NUMBER (R_ALPHA_LITERAL, 4) /* GP relative 16 bit w/optimization */ + RELOC_NUMBER (R_ALPHA_LITUSE, 5) /* Optimization hint for LITERAL */ + RELOC_NUMBER (R_ALPHA_GPDISP, 6) /* Add displacement to GP */ + RELOC_NUMBER (R_ALPHA_BRADDR, 7) /* PC+4 relative 23 bit shifted */ + RELOC_NUMBER (R_ALPHA_HINT, 8) /* PC+4 relative 16 bit shifted */ + RELOC_NUMBER (R_ALPHA_SREL16, 9) /* PC relative 16 bit */ + RELOC_NUMBER (R_ALPHA_SREL32, 10) /* PC relative 32 bit */ + RELOC_NUMBER (R_ALPHA_SREL64, 11) /* PC relative 64 bit */ /* Inherited these from ECOFF, but they are not particularly useful and are depreciated. And not implemented in the BFD, btw. */ -#define R_ALPHA_OP_PUSH 12 /* OP stack push */ -#define R_ALPHA_OP_STORE 13 /* OP stack pop and store */ -#define R_ALPHA_OP_PSUB 14 /* OP stack subtract */ -#define R_ALPHA_OP_PRSHIFT 15 /* OP stack right shift */ - -#define R_ALPHA_GPVALUE 16 -#define R_ALPHA_GPRELHIGH 17 -#define R_ALPHA_GPRELLOW 18 -#define R_ALPHA_IMMED_GP_16 19 -#define R_ALPHA_IMMED_GP_HI32 20 -#define R_ALPHA_IMMED_SCN_HI32 21 -#define R_ALPHA_IMMED_BR_HI32 22 -#define R_ALPHA_IMMED_LO32 23 + RELOC_NUMBER (R_ALPHA_OP_PUSH, 12) /* OP stack push */ + RELOC_NUMBER (R_ALPHA_OP_STORE, 13) /* OP stack pop and store */ + RELOC_NUMBER (R_ALPHA_OP_PSUB, 14) /* OP stack subtract */ + RELOC_NUMBER (R_ALPHA_OP_PRSHIFT, 15) /* OP stack right shift */ + + RELOC_NUMBER (R_ALPHA_GPVALUE, 16) + RELOC_NUMBER (R_ALPHA_GPRELHIGH, 17) + RELOC_NUMBER (R_ALPHA_GPRELLOW, 18) + RELOC_NUMBER (R_ALPHA_IMMED_GP_16, 19) + RELOC_NUMBER (R_ALPHA_IMMED_GP_HI32, 20) + RELOC_NUMBER (R_ALPHA_IMMED_SCN_HI32, 21) + RELOC_NUMBER (R_ALPHA_IMMED_BR_HI32, 22) + RELOC_NUMBER (R_ALPHA_IMMED_LO32, 23) /* These relocations are specific to shared libraries. */ -#define R_ALPHA_COPY 24 /* Copy symbol at runtime */ -#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ -#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ -#define R_ALPHA_RELATIVE 27 /* Adjust by program base */ + RELOC_NUMBER (R_ALPHA_COPY, 24) /* Copy symbol at runtime */ + RELOC_NUMBER (R_ALPHA_GLOB_DAT, 25) /* Create GOT entry */ + RELOC_NUMBER (R_ALPHA_JMP_SLOT, 26) /* Create PLT entry */ + RELOC_NUMBER (R_ALPHA_RELATIVE, 27) /* Adjust by program base */ -#define R_ALPHA_max 28 + EMPTY_RELOC (R_ALPHA_max) +END_RELOC_NUMBERS #endif /* _ELF_ALPHA_H */ diff --git a/gnu/usr.bin/binutils/include/elf/arc.h b/gnu/usr.bin/binutils/include/elf/arc.h new file mode 100644 index 00000000000..334b55fa6d0 --- /dev/null +++ b/gnu/usr.bin/binutils/include/elf/arc.h @@ -0,0 +1,54 @@ +/* ARC ELF support for BFD. + Copyright (C) 1995, 1997 Free Software Foundation, Inc. + Contributed by Doug Evans, (dje@cygnus.com) + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file holds definitions specific to the ARC ELF ABI. */ + +#ifndef _ELF_ARC_H +#define _ELF_ARC_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_arc_reloc_type) + RELOC_NUMBER (R_ARC_NONE, 0) + RELOC_NUMBER (R_ARC_32, 1) + RELOC_NUMBER (R_ARC_B26, 2) + RELOC_NUMBER (R_ARC_B22_PCREL, 3) + EMPTY_RELOC (R_ARC_max) +END_RELOC_NUMBERS + +/* Processor specific flags for the ELF header e_flags field. */ + +/* Four bit ARC machine type field. */ +#define EF_ARC_MACH 0x0000000f + +/* Various CPU types. */ +#define E_ARC_MACH_BASE 0x00000000 +#define E_ARC_MACH_UNUSED1 0x00000001 +#define E_ARC_MACH_UNUSED2 0x00000002 +#define E_ARC_MACH_UNUSED4 0x00000003 + +/* Leave bits 0xf0 alone in case we ever have more than 16 cpu types. + Highly unlikely, but what the heck. */ + +/* File contains position independent code. */ +#define EF_ARC_PIC 0x00000100 + +#endif /* _ELF_ARC_H */ diff --git a/gnu/usr.bin/binutils/include/elf/arm-oabi.h b/gnu/usr.bin/binutils/include/elf/arm-oabi.h new file mode 100644 index 00000000000..da5e7316eed --- /dev/null +++ b/gnu/usr.bin/binutils/include/elf/arm-oabi.h @@ -0,0 +1,88 @@ +/* ARM ELF support for BFD. + Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_ARM_H +#define _ELF_ARM_H + +#include "elf/reloc-macros.h" + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_ARM_RELEXEC 0x01 +#define EF_ARM_HASENTRY 0x02 +#define EF_INTERWORK 0x04 +#define EF_APCS_26 0x08 +#define EF_APCS_FLOAT 0x10 +#define EF_PIC 0x20 +#define EF_ALIGN8 0x40 /* 8-bit structure alignment is in use. */ +#define EF_NEW_ABI 0x80 +#define EF_OLD_ABI 0x100 + +/* Local aliases for some flags to match names used by COFF port. */ +#define F_INTERWORK EF_INTERWORK +#define F_APCS26 EF_APCS_26 +#define F_APCS_FLOAT EF_APCS_FLOAT +#define F_PIC EF_PIC + +/* Additional symbol types for Thumb. */ +#define STT_ARM_TFUNC STT_LOPROC /* A Thumb function. */ +#define STT_ARM_16BIT STT_HIPROC /* A Thumb label. */ + +/* ARM-specific values for sh_flags. */ +#define SHF_ENTRYSECT 0x10000000 /* Section contains an entry point. */ +#define SHF_COMDEF 0x80000000 /* Section may be multiply defined in the input to a link step. */ + +/* ARM-specific program header flags. */ +#define PF_ARM_SB 0x10000000 /* Segment contains the location addressed by the static base. */ + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_arm_reloc_type) + RELOC_NUMBER (R_ARM_NONE, 0) + RELOC_NUMBER (R_ARM_PC24, 1) + RELOC_NUMBER (R_ARM_ABS32, 2) + RELOC_NUMBER (R_ARM_REL32, 3) + RELOC_NUMBER (R_ARM_ABS8, 4) + RELOC_NUMBER (R_ARM_ABS16, 5) + RELOC_NUMBER (R_ARM_ABS12, 6) + RELOC_NUMBER (R_ARM_THM_ABS5, 7) + RELOC_NUMBER (R_ARM_THM_PC22, 8) + RELOC_NUMBER (R_ARM_SBREL32, 9) + RELOC_NUMBER (R_ARM_AMP_VCALL9, 10) + RELOC_NUMBER (R_ARM_THM_PC11, 11) /* Cygnus extension to abi: Thumb unconditional branch. */ + RELOC_NUMBER (R_ARM_THM_PC9, 12) /* Cygnus extension to abi: Thumb conditional branch. */ + RELOC_NUMBER (R_ARM_GNU_VTINHERIT, 13) + RELOC_NUMBER (R_ARM_GNU_VTENTRY, 14) + RELOC_NUMBER (R_ARM_COPY, 20) /* Copy symbol at runtime. */ + RELOC_NUMBER (R_ARM_GLOB_DAT, 21) /* Create GOT entry. */ + RELOC_NUMBER (R_ARM_JUMP_SLOT, 22) /* Create PLT entry. */ + RELOC_NUMBER (R_ARM_RELATIVE, 23) /* Adjust by program base. */ + RELOC_NUMBER (R_ARM_GOTOFF, 24) /* 32 bit offset to GOT. */ + RELOC_NUMBER (R_ARM_GOTPC, 25) /* 32 bit PC relative offset to GOT. */ + RELOC_NUMBER (R_ARM_GOT32, 26) /* 32 bit GOT entry. */ + RELOC_NUMBER (R_ARM_PLT32, 27) /* 32 bit PLT address. */ + FAKE_RELOC (FIRST_INVALID_RELOC, 28) + FAKE_RELOC (LAST_INVALID_RELOC, 249) + RELOC_NUMBER (R_ARM_RSBREL32, 250) + RELOC_NUMBER (R_ARM_THM_RPC22, 251) + RELOC_NUMBER (R_ARM_RREL32, 252) + RELOC_NUMBER (R_ARM_RABS32, 253) + RELOC_NUMBER (R_ARM_RPC24, 254) + RELOC_NUMBER (R_ARM_RBASE, 255) +END_RELOC_NUMBERS + +#endif diff --git a/gnu/usr.bin/binutils/include/elf/arm.h b/gnu/usr.bin/binutils/include/elf/arm.h new file mode 100644 index 00000000000..4d3405dd7e6 --- /dev/null +++ b/gnu/usr.bin/binutils/include/elf/arm.h @@ -0,0 +1,99 @@ +/* ARM ELF support for BFD. + Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_ARM_H +#define _ELF_ARM_H + +#include "elf/reloc-macros.h" + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_ARM_RELEXEC 0x01 +#define EF_ARM_HASENTRY 0x02 +#define EF_INTERWORK 0x04 +#define EF_APCS_26 0x08 +#define EF_APCS_FLOAT 0x10 +#define EF_PIC 0x20 +#define EF_ALIGN8 0x40 /* 8-bit structure alignment is in use. */ +#define EF_NEW_ABI 0x80 +#define EF_OLD_ABI 0x100 +#define EF_SOFT_FLOAT 0x200 + +/* Local aliases for some flags to match names used by COFF port. */ +#define F_INTERWORK EF_INTERWORK +#define F_APCS26 EF_APCS_26 +#define F_APCS_FLOAT EF_APCS_FLOAT +#define F_PIC EF_PIC +#define F_SOFT_FLOAT EF_SOFT_FLOAT + +/* Additional symbol types for Thumb. */ +#define STT_ARM_TFUNC STT_LOPROC /* A Thumb function. */ +#define STT_ARM_16BIT STT_HIPROC /* A Thumb label. */ + +/* ARM-specific values for sh_flags. */ +#define SHF_ENTRYSECT 0x10000000 /* Section contains an entry point. */ +#define SHF_COMDEF 0x80000000 /* Section may be multiply defined in the input to a link step. */ + +/* ARM-specific program header flags. */ +#define PF_ARM_SB 0x10000000 /* Segment contains the location addressed by the static base. */ + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_arm_reloc_type) + RELOC_NUMBER (R_ARM_NONE, 0) + RELOC_NUMBER (R_ARM_PC24, 1) + RELOC_NUMBER (R_ARM_ABS32, 2) + RELOC_NUMBER (R_ARM_REL32, 3) + RELOC_NUMBER (R_ARM_PC13, 4) + RELOC_NUMBER (R_ARM_ABS16, 5) + RELOC_NUMBER (R_ARM_ABS12, 6) + RELOC_NUMBER (R_ARM_THM_ABS5, 7) + RELOC_NUMBER (R_ARM_ABS8, 8) + RELOC_NUMBER (R_ARM_SBREL32, 9) + RELOC_NUMBER (R_ARM_THM_PC22, 10) + RELOC_NUMBER (R_ARM_THM_PC8, 11) + RELOC_NUMBER (R_ARM_AMP_VCALL9, 12) + RELOC_NUMBER (R_ARM_SWI24, 13) + RELOC_NUMBER (R_ARM_THM_SWI8, 14) + RELOC_NUMBER (R_ARM_XPC25, 15) + RELOC_NUMBER (R_ARM_THM_XPC22, 16) + RELOC_NUMBER (R_ARM_COPY, 20) /* copy symbol at runtime */ + RELOC_NUMBER (R_ARM_GLOB_DAT, 21) /* create GOT entry */ + RELOC_NUMBER (R_ARM_JUMP_SLOT, 22) /* create PLT entry */ + RELOC_NUMBER (R_ARM_RELATIVE, 23) /* adjust by program base */ + RELOC_NUMBER (R_ARM_GOTOFF, 24) /* 32 bit offset to GOT */ + RELOC_NUMBER (R_ARM_GOTPC, 25) /* 32 bit PC relative offset to GOT */ + RELOC_NUMBER (R_ARM_GOT32, 26) /* 32 bit GOT entry */ + RELOC_NUMBER (R_ARM_PLT32, 27) /* 32 bit PLT address */ + FAKE_RELOC (FIRST_INVALID_RELOC1, 28) + FAKE_RELOC (LAST_INVALID_RELOC1, 99) + RELOC_NUMBER (R_ARM_GNU_VTENTRY, 100) + RELOC_NUMBER (R_ARM_GNU_VTINHERIT, 101) + RELOC_NUMBER (R_ARM_THM_PC11, 102) /* Cygnus extension to abi: Thumb unconditional branch */ + RELOC_NUMBER (R_ARM_THM_PC9, 103) /* Cygnus extension to abi: Thumb conditional branch */ + FAKE_RELOC (FIRST_INVALID_RELOC2, 104) + FAKE_RELOC (LAST_INVALID_RELOC2, 248) + RELOC_NUMBER (R_ARM_RXPC25, 249) + RELOC_NUMBER (R_ARM_RSBREL32, 250) + RELOC_NUMBER (R_ARM_THM_RPC22, 251) + RELOC_NUMBER (R_ARM_RREL32, 252) + RELOC_NUMBER (R_ARM_RABS32, 253) + RELOC_NUMBER (R_ARM_RPC24, 254) + RELOC_NUMBER (R_ARM_RBASE, 255) +END_RELOC_NUMBERS + +#endif diff --git a/gnu/usr.bin/binutils/include/elf/avr.h b/gnu/usr.bin/binutils/include/elf/avr.h new file mode 100644 index 00000000000..1527455995e --- /dev/null +++ b/gnu/usr.bin/binutils/include/elf/avr.h @@ -0,0 +1,58 @@ +/* AVR ELF support for BFD. + Copyright (C) 1999, 2000 Free Software Foundation, Inc. + Contributed by Denis Chertykov <denisc@overta.ru> + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_AVR_H +#define _ELF_AVR_H + +#include "elf/reloc-macros.h" + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_AVR_MACH 0xf + +#define E_AVR_MACH_AVR1 1 +#define E_AVR_MACH_AVR2 2 +#define E_AVR_MACH_AVR3 3 +#define E_AVR_MACH_AVR4 4 + +/* Relocations. */ +START_RELOC_NUMBERS (elf_avr_reloc_type) + RELOC_NUMBER (R_AVR_NONE, 0) + RELOC_NUMBER (R_AVR_32, 1) + RELOC_NUMBER (R_AVR_7_PCREL, 2) + RELOC_NUMBER (R_AVR_13_PCREL, 3) + RELOC_NUMBER (R_AVR_16, 4) + RELOC_NUMBER (R_AVR_16_PM, 5) + RELOC_NUMBER (R_AVR_LO8_LDI, 6) + RELOC_NUMBER (R_AVR_HI8_LDI, 7) + RELOC_NUMBER (R_AVR_HH8_LDI, 8) + RELOC_NUMBER (R_AVR_LO8_LDI_NEG, 9) + RELOC_NUMBER (R_AVR_HI8_LDI_NEG, 10) + RELOC_NUMBER (R_AVR_HH8_LDI_NEG, 11) + RELOC_NUMBER (R_AVR_LO8_LDI_PM, 12) + RELOC_NUMBER (R_AVR_HI8_LDI_PM, 13) + RELOC_NUMBER (R_AVR_HH8_LDI_PM, 14) + RELOC_NUMBER (R_AVR_LO8_LDI_PM_NEG, 15) + RELOC_NUMBER (R_AVR_HI8_LDI_PM_NEG, 16) + RELOC_NUMBER (R_AVR_HH8_LDI_PM_NEG, 17) + RELOC_NUMBER (R_AVR_CALL, 18) + EMPTY_RELOC (R_AVR_max) +END_RELOC_NUMBERS + +#endif /* _ELF_AVR_H */ diff --git a/gnu/usr.bin/binutils/include/elf/d10v.h b/gnu/usr.bin/binutils/include/elf/d10v.h new file mode 100644 index 00000000000..63b79c801b1 --- /dev/null +++ b/gnu/usr.bin/binutils/include/elf/d10v.h @@ -0,0 +1,38 @@ +/* d10v ELF support for BFD. + Copyright (C) 1998 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_D10V_H +#define _ELF_D10V_H + +#include "elf/reloc-macros.h" + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_d10v_reloc_type) + RELOC_NUMBER (R_D10V_NONE, 0) + RELOC_NUMBER (R_D10V_10_PCREL_R, 1) + RELOC_NUMBER (R_D10V_10_PCREL_L, 2) + RELOC_NUMBER (R_D10V_16, 3) + RELOC_NUMBER (R_D10V_18, 4) + RELOC_NUMBER (R_D10V_18_PCREL, 5) + RELOC_NUMBER (R_D10V_32, 6) + RELOC_NUMBER (R_D10V_GNU_VTINHERIT, 7) + RELOC_NUMBER (R_D10V_GNU_VTENTRY, 8) +END_RELOC_NUMBERS + +#endif diff --git a/gnu/usr.bin/binutils/include/elf/d30v.h b/gnu/usr.bin/binutils/include/elf/d30v.h new file mode 100644 index 00000000000..adbad192325 --- /dev/null +++ b/gnu/usr.bin/binutils/include/elf/d30v.h @@ -0,0 +1,42 @@ +/* d30v ELF support for BFD. + Copyright (C) 1998 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_D30V_H +#define _ELF_D30V_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_d30v_reloc_type) + RELOC_NUMBER (R_D30V_NONE, 0) + RELOC_NUMBER (R_D30V_6, 1) + RELOC_NUMBER (R_D30V_9_PCREL, 2) + RELOC_NUMBER (R_D30V_9_PCREL_R, 3) + RELOC_NUMBER (R_D30V_15, 4) + RELOC_NUMBER (R_D30V_15_PCREL, 5) + RELOC_NUMBER (R_D30V_15_PCREL_R, 6) + RELOC_NUMBER (R_D30V_21, 7) + RELOC_NUMBER (R_D30V_21_PCREL, 8) + RELOC_NUMBER (R_D30V_21_PCREL_R, 9) + RELOC_NUMBER (R_D30V_32, 10) + RELOC_NUMBER (R_D30V_32_PCREL, 11) + RELOC_NUMBER (R_D30V_32_NORMAL, 12) +END_RELOC_NUMBERS + +#endif diff --git a/gnu/usr.bin/binutils/include/elf/dwarf2.h b/gnu/usr.bin/binutils/include/elf/dwarf2.h index f2b2510f152..1bd4fa6cac9 100644 --- a/gnu/usr.bin/binutils/include/elf/dwarf2.h +++ b/gnu/usr.bin/binutils/include/elf/dwarf2.h @@ -1,6 +1,6 @@ /* Declarations and definitions of codes relating to the DWARF symbolic debugging information format. - Copyright (C) 1992, 1993, 1995, 1996 Free Software Foundation, Inc. + Copyright (C) 1992, 1993, 1995, 1996, 1999 Free Software Foundation, Inc. Written by Gary Funck (gary@intrepid.com) The Ada Joint Program Office (AJPO), Florida State Unviversity and Silicon Graphics Inc. @@ -34,6 +34,92 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * #ifndef _ELF_DWARF2_H #define _ELF_DWARF2_H +/* Structure found in the .debug_line section. */ +typedef struct +{ + unsigned char li_length [4]; + unsigned char li_version [2]; + unsigned char li_prologue_length [4]; + unsigned char li_min_insn_length [1]; + unsigned char li_default_is_stmt [1]; + unsigned char li_line_base [1]; + unsigned char li_line_range [1]; + unsigned char li_opcode_base [1]; +} +DWARF2_External_LineInfo; + +typedef struct +{ + unsigned long li_length; + unsigned short li_version; + unsigned int li_prologue_length; + unsigned char li_min_insn_length; + unsigned char li_default_is_stmt; + int li_line_base; + unsigned char li_line_range; + unsigned char li_opcode_base; +} +DWARF2_Internal_LineInfo; + +/* Structure found in .debug_pubnames section. */ +typedef struct +{ + unsigned char pn_length [4]; + unsigned char pn_version [2]; + unsigned char pn_offset [4]; + unsigned char pn_size [4]; +} +DWARF2_External_PubNames; + +typedef struct +{ + unsigned long pn_length; + unsigned short pn_version; + unsigned long pn_offset; + unsigned long pn_size; +} +DWARF2_Internal_PubNames; + +/* Strcuture found in .debug_info section. */ +typedef struct +{ + unsigned char cu_length [4]; + unsigned char cu_version [2]; + unsigned char cu_abbrev_offset [4]; + unsigned char cu_pointer_size [1]; +} +DWARF2_External_CompUnit; + +typedef struct +{ + unsigned long cu_length; + unsigned short cu_version; + unsigned long cu_abbrev_offset; + unsigned char cu_pointer_size; +} +DWARF2_Internal_CompUnit; + +typedef struct +{ + unsigned char ar_length [4]; + unsigned char ar_version [2]; + unsigned char ar_info_offset [4]; + unsigned char ar_pointer_size [1]; + unsigned char ar_segment_size [1]; +} +DWARF2_External_ARange; + +typedef struct +{ + unsigned long ar_length; + unsigned short ar_version; + unsigned long ar_info_offset; + unsigned char ar_pointer_size; + unsigned char ar_segment_size; +} +DWARF2_Internal_ARange; + + /* Tag names and codes. */ enum dwarf_tag @@ -530,6 +616,7 @@ enum dwarf_source_language DW_LANG_Fortran90 = 0x0008, DW_LANG_Pascal83 = 0x0009, DW_LANG_Modula2 = 0x000a, + DW_LANG_Java = 0x9af4, DW_LANG_Mips_Assembler = 0x8001 }; diff --git a/gnu/usr.bin/binutils/include/elf/fr30.h b/gnu/usr.bin/binutils/include/elf/fr30.h new file mode 100644 index 00000000000..223b052973a --- /dev/null +++ b/gnu/usr.bin/binutils/include/elf/fr30.h @@ -0,0 +1,43 @@ +/* FR30 ELF support for BFD. + Copyright (C) 1998 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_FR30_H +#define _ELF_FR30_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_fr30_reloc_type) + RELOC_NUMBER (R_FR30_NONE, 0) + RELOC_NUMBER (R_FR30_8, 1) + RELOC_NUMBER (R_FR30_20, 2) + RELOC_NUMBER (R_FR30_32, 3) + RELOC_NUMBER (R_FR30_48, 4) + RELOC_NUMBER (R_FR30_6_IN_4, 5) + RELOC_NUMBER (R_FR30_8_IN_8, 6) + RELOC_NUMBER (R_FR30_9_IN_8, 7) + RELOC_NUMBER (R_FR30_10_IN_8, 8) + RELOC_NUMBER (R_FR30_9_PCREL, 9) + RELOC_NUMBER (R_FR30_12_PCREL, 10) + RELOC_NUMBER (R_FR30_GNU_VTINHERIT, 11) + RELOC_NUMBER (R_FR30_GNU_VTENTRY, 12) + EMPTY_RELOC (R_FR30_max) +END_RELOC_NUMBERS + +#endif /* _ELF_FR30_H */ diff --git a/gnu/usr.bin/binutils/include/elf/i370.h b/gnu/usr.bin/binutils/include/elf/i370.h new file mode 100644 index 00000000000..9c021f00e89 --- /dev/null +++ b/gnu/usr.bin/binutils/include/elf/i370.h @@ -0,0 +1,46 @@ +/* i370 ELF support for BFD. + Copyright (C) 1995, 2000 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file holds definitions specific to the i370 ELF ABI. Note + that most of this is not actually implemented by BFD. */ + +#ifndef _ELF_I370_H +#define _ELF_I370_H + +/* Processor specific section headers, sh_type field */ + +#define SHT_ORDERED SHT_HIPROC /* Link editor is to sort the \ + entries in this section \ + based on the address \ + specified in the associated \ + symbol table entry. */ + +#define EF_I370_RELOCATABLE 0x00010000 /* i370 -mrelocatable flag */ +#define EF_I370_RELOCATABLE_LIB 0x00008000 /* i370 -mrelocatable-lib flag */ +/* Processor specific section flags, sh_flags field */ + +#define SHF_EXCLUDE 0x80000000 /* Link editor is to exclude \ + this section from executable \ + and shared objects that it \ + builds when those objects \ + are not to be furhter \ + relocated. */ +#endif /* _ELF_I370_H */ + + diff --git a/gnu/usr.bin/binutils/include/elf/i386.h b/gnu/usr.bin/binutils/include/elf/i386.h new file mode 100644 index 00000000000..0586661720e --- /dev/null +++ b/gnu/usr.bin/binutils/include/elf/i386.h @@ -0,0 +1,49 @@ +/* ix86 ELF support for BFD. + Copyright (C) 1998 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_I386_H +#define _ELF_I386_H + +#include "elf/reloc-macros.h" + +START_RELOC_NUMBERS (elf_i386_reloc_type) + RELOC_NUMBER (R_386_NONE, 0) /* No reloc */ + RELOC_NUMBER (R_386_32, 1) /* Direct 32 bit */ + RELOC_NUMBER (R_386_PC32, 2) /* PC relative 32 bit */ + RELOC_NUMBER (R_386_GOT32, 3) /* 32 bit GOT entry */ + RELOC_NUMBER (R_386_PLT32, 4) /* 32 bit PLT address */ + RELOC_NUMBER (R_386_COPY, 5) /* Copy symbol at runtime */ + RELOC_NUMBER (R_386_GLOB_DAT, 6) /* Create GOT entry */ + RELOC_NUMBER (R_386_JUMP_SLOT, 7) /* Create PLT entry */ + RELOC_NUMBER (R_386_RELATIVE, 8) /* Adjust by program base */ + RELOC_NUMBER (R_386_GOTOFF, 9) /* 32 bit offset to GOT */ + RELOC_NUMBER (R_386_GOTPC, 10) /* 32 bit PC relative offset to GOT */ + FAKE_RELOC (FIRST_INVALID_RELOC, 11) + FAKE_RELOC (LAST_INVALID_RELOC, 19) + RELOC_NUMBER (R_386_16, 20) + RELOC_NUMBER (R_386_PC16, 21) + RELOC_NUMBER (R_386_8, 22) + RELOC_NUMBER (R_386_PC8, 23) + RELOC_NUMBER (R_386_max, 24) + /* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_386_GNU_VTINHERIT, 250) + RELOC_NUMBER (R_386_GNU_VTENTRY, 251) +END_RELOC_NUMBERS + +#endif diff --git a/gnu/usr.bin/binutils/include/elf/i960.h b/gnu/usr.bin/binutils/include/elf/i960.h new file mode 100644 index 00000000000..3e60289ea99 --- /dev/null +++ b/gnu/usr.bin/binutils/include/elf/i960.h @@ -0,0 +1,38 @@ +/* Intel 960 ELF support for BFD. + Copyright (C) 1999 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_I960_H +#define _ELF_I960_H + +#include "elf/reloc-macros.h" + + +START_RELOC_NUMBERS (elf_i960_reloc_type) + RELOC_NUMBER (R_960_NONE, 0) + RELOC_NUMBER (R_960_12, 1) + RELOC_NUMBER (R_960_32, 2) + RELOC_NUMBER (R_960_IP24, 3) + RELOC_NUMBER (R_960_SUB, 4) + RELOC_NUMBER (R_960_OPTCALL, 5) + RELOC_NUMBER (R_960_OPTCALLX, 6) + RELOC_NUMBER (R_960_OPTCALLXA, 7) + EMPTY_RELOC (R_960_max) +END_RELOC_NUMBERS + +#endif /* _ELF_I960_H */ diff --git a/gnu/usr.bin/binutils/include/elf/m32r.h b/gnu/usr.bin/binutils/include/elf/m32r.h index 92d9d75c68f..a12ae16aea5 100644 --- a/gnu/usr.bin/binutils/include/elf/m32r.h +++ b/gnu/usr.bin/binutils/include/elf/m32r.h @@ -1,5 +1,5 @@ /* M32R ELF support for BFD. - Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -20,21 +20,25 @@ along with this program; if not, write to the Free Software Foundation, Inc., #ifndef _ELF_M32R_H #define _ELF_M32R_H -enum reloc_type -{ - R_M32R_NONE = 0, - R_M32R_16, - R_M32R_32, - R_M32R_24, - R_M32R_10_PCREL, - R_M32R_18_PCREL, - R_M32R_26_PCREL, - R_M32R_HI16_ULO, - R_M32R_HI16_SLO, - R_M32R_LO16, - R_M32R_SDA16, - R_M32R_max -}; +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_m32r_reloc_type) + RELOC_NUMBER (R_M32R_NONE, 0) + RELOC_NUMBER (R_M32R_16, 1) + RELOC_NUMBER (R_M32R_32, 2) + RELOC_NUMBER (R_M32R_24, 3) + RELOC_NUMBER (R_M32R_10_PCREL, 4) + RELOC_NUMBER (R_M32R_18_PCREL, 5) + RELOC_NUMBER (R_M32R_26_PCREL, 6) + RELOC_NUMBER (R_M32R_HI16_ULO, 7) + RELOC_NUMBER (R_M32R_HI16_SLO, 8) + RELOC_NUMBER (R_M32R_LO16, 9) + RELOC_NUMBER (R_M32R_SDA16, 10) + RELOC_NUMBER (R_M32R_GNU_VTINHERIT, 11) + RELOC_NUMBER (R_M32R_GNU_VTENTRY, 12) + EMPTY_RELOC (R_M32R_max) +END_RELOC_NUMBERS /* Processor specific section indices. These sections do not actually exist. Symbols with a st_shndx field corresponding to one of these @@ -51,4 +55,14 @@ enum reloc_type move. */ #define SHF_M32R_CAN_RELAX 0x10000000 +/* Processor specific flags for the ELF header e_flags field. */ + +/* Two bit m32r architecture field. */ +#define EF_M32R_ARCH 0x30000000 + +/* m32r code. */ +#define E_M32R_ARCH 0x00000000 +/* m32rx code. */ +#define E_M32RX_ARCH 0x10000000 + #endif diff --git a/gnu/usr.bin/binutils/include/elf/m68k.h b/gnu/usr.bin/binutils/include/elf/m68k.h new file mode 100644 index 00000000000..e2d51ef4a90 --- /dev/null +++ b/gnu/usr.bin/binutils/include/elf/m68k.h @@ -0,0 +1,58 @@ +/* MC68k ELF support for BFD. + Copyright (C) 1998 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_M68K_H +#define _ELF_M68K_H + +#include "elf/reloc-macros.h" + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_m68k_reloc_type) + RELOC_NUMBER (R_68K_NONE, 0) /* No reloc */ + RELOC_NUMBER (R_68K_32, 1) /* Direct 32 bit */ + RELOC_NUMBER (R_68K_16, 2) /* Direct 16 bit */ + RELOC_NUMBER (R_68K_8, 3) /* Direct 8 bit */ + RELOC_NUMBER (R_68K_PC32, 4) /* PC relative 32 bit */ + RELOC_NUMBER (R_68K_PC16, 5) /* PC relative 16 bit */ + RELOC_NUMBER (R_68K_PC8, 6) /* PC relative 8 bit */ + RELOC_NUMBER (R_68K_GOT32, 7) /* 32 bit PC relative GOT entry */ + RELOC_NUMBER (R_68K_GOT16, 8) /* 16 bit PC relative GOT entry */ + RELOC_NUMBER (R_68K_GOT8, 9) /* 8 bit PC relative GOT entry */ + RELOC_NUMBER (R_68K_GOT32O, 10) /* 32 bit GOT offset */ + RELOC_NUMBER (R_68K_GOT16O, 11) /* 16 bit GOT offset */ + RELOC_NUMBER (R_68K_GOT8O, 12) /* 8 bit GOT offset */ + RELOC_NUMBER (R_68K_PLT32, 13) /* 32 bit PC relative PLT address */ + RELOC_NUMBER (R_68K_PLT16, 14) /* 16 bit PC relative PLT address */ + RELOC_NUMBER (R_68K_PLT8, 15) /* 8 bit PC relative PLT address */ + RELOC_NUMBER (R_68K_PLT32O, 16) /* 32 bit PLT offset */ + RELOC_NUMBER (R_68K_PLT16O, 17) /* 16 bit PLT offset */ + RELOC_NUMBER (R_68K_PLT8O, 18) /* 8 bit PLT offset */ + RELOC_NUMBER (R_68K_COPY, 19) /* Copy symbol at runtime */ + RELOC_NUMBER (R_68K_GLOB_DAT, 20) /* Create GOT entry */ + RELOC_NUMBER (R_68K_JMP_SLOT, 21) /* Create PLT entry */ + RELOC_NUMBER (R_68K_RELATIVE, 22) /* Adjust by program base */ + /* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_68K_GNU_VTINHERIT, 23) + RELOC_NUMBER (R_68K_GNU_VTENTRY, 24) + EMPTY_RELOC (R_68K_max) +END_RELOC_NUMBERS + +#define EF_CPU32 0x00810000 + +#endif diff --git a/gnu/usr.bin/binutils/include/elf/mcore.h b/gnu/usr.bin/binutils/include/elf/mcore.h new file mode 100644 index 00000000000..62a88c9093e --- /dev/null +++ b/gnu/usr.bin/binutils/include/elf/mcore.h @@ -0,0 +1,47 @@ +/* Motorola MCore support for BFD. + Copyright (C) 1995, 1999 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file holds definitions specific to the MCore ELF ABI. */ +#ifndef _ELF_MORE_H +#define _ELF_MORE_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_mcore_reloc_type) + RELOC_NUMBER (R_MCORE_NONE, 0) + RELOC_NUMBER (R_MCORE_ADDR32, 1) + RELOC_NUMBER (R_MCORE_PCRELIMM8BY4, 2) + RELOC_NUMBER (R_MCORE_PCRELIMM11BY2, 3) + RELOC_NUMBER (R_MCORE_PCRELIMM4BY2, 4) + RELOC_NUMBER (R_MCORE_PCREL32, 5) + RELOC_NUMBER (R_MCORE_PCRELJSR_IMM11BY2, 6) + RELOC_NUMBER (R_MCORE_GNU_VTINHERIT, 7) + RELOC_NUMBER (R_MCORE_GNU_VTENTRY, 8) + RELOC_NUMBER (R_MCORE_RELATIVE, 9) + RELOC_NUMBER (R_MCORE_COPY, 10) + RELOC_NUMBER (R_MCORE_GLOB_DAT, 11) + RELOC_NUMBER (R_MCORE_JUMP_SLOT, 12) + EMPTY_RELOC (R_MCORE_max) +END_RELOC_NUMBERS + +/* Section Attributes. */ +#define SHF_MCORE_NOREAD 0x80000000 + +#endif /* _ELF_MCORE_H */ diff --git a/gnu/usr.bin/binutils/include/elf/mn10200.h b/gnu/usr.bin/binutils/include/elf/mn10200.h new file mode 100644 index 00000000000..5e29e0ad211 --- /dev/null +++ b/gnu/usr.bin/binutils/include/elf/mn10200.h @@ -0,0 +1,39 @@ +/* MN10200 ELF support for BFD. + Copyright (C) 1998 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file holds definitions specific to the MN10200 ELF ABI. */ + +#ifndef _ELF_MN10200_H +#define _ELF_MN10200_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_mn10200_reloc_type) + RELOC_NUMBER (R_MN10200_NONE, 0) + RELOC_NUMBER (R_MN10200_32, 1) + RELOC_NUMBER (R_MN10200_16, 2) + RELOC_NUMBER (R_MN10200_8, 3) + RELOC_NUMBER (R_MN10200_24, 4) + RELOC_NUMBER (R_MN10200_PCREL8, 5) + RELOC_NUMBER (R_MN10200_PCREL16, 6) + RELOC_NUMBER (R_MN10200_PCREL24, 7) +END_RELOC_NUMBERS + +#endif /* _ELF_MN10200_H */ diff --git a/gnu/usr.bin/binutils/include/elf/mn10300.h b/gnu/usr.bin/binutils/include/elf/mn10300.h new file mode 100644 index 00000000000..1b90a137961 --- /dev/null +++ b/gnu/usr.bin/binutils/include/elf/mn10300.h @@ -0,0 +1,54 @@ +/* MN10300 ELF support for BFD. + Copyright (C) 1998 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file holds definitions specific to the MN10300 ELF ABI. */ + +#ifndef _ELF_MN10300_H +#define _ELF_MN10300_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_mn10300_reloc_type) + RELOC_NUMBER (R_MN10300_NONE, 0) + RELOC_NUMBER (R_MN10300_32, 1) + RELOC_NUMBER (R_MN10300_16, 2) + RELOC_NUMBER (R_MN10300_8, 3) + RELOC_NUMBER (R_MN10300_PCREL32, 4) + RELOC_NUMBER (R_MN10300_PCREL16, 5) + RELOC_NUMBER (R_MN10300_PCREL8, 6) + RELOC_NUMBER (R_MN10300_GNU_VTINHERIT, 7) + RELOC_NUMBER (R_MN10300_GNU_VTENTRY, 8) + RELOC_NUMBER (R_MN10300_24, 9) + EMPTY_RELOC (R_MN10300_MAX) +END_RELOC_NUMBERS + +/* Machine variant if we know it. This field was invented at Cygnus, + but it is hoped that other vendors will adopt it. If some standard + is developed, this code should be changed to follow it. */ + +#define EF_MN10300_MACH 0x00FF0000 + +/* Cygnus is choosing values between 80 and 9F; + 00 - 7F should be left for a future standard; + the rest are open. */ + +#define E_MN10300_MACH_MN10300 0x00810000 +#define E_MN10300_MACH_AM33 0x00820000 +#endif /* _ELF_MN10300_H */ diff --git a/gnu/usr.bin/binutils/include/elf/pj.h b/gnu/usr.bin/binutils/include/elf/pj.h new file mode 100644 index 00000000000..6bb8306523e --- /dev/null +++ b/gnu/usr.bin/binutils/include/elf/pj.h @@ -0,0 +1,45 @@ +/* picoJava ELF support for BFD. + Copyright (C) 1999 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_PJ_H +#define _ELF_PJ_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ + +START_RELOC_NUMBERS (elf_pj_reloc_type) + RELOC_NUMBER (R_PJ_NONE, 0) + RELOC_NUMBER (R_PJ_DATA_DIR32, 1) + RELOC_NUMBER (R_PJ_CODE_REL32, 2) + RELOC_NUMBER (R_PJ_CODE_REL16, 3) + RELOC_NUMBER (R_PJ_CODE_DIR32, 6) + RELOC_NUMBER (R_PJ_CODE_DIR16, 7) + RELOC_NUMBER (R_PJ_CODE_LO16, 13) + RELOC_NUMBER (R_PJ_CODE_HI16, 14) + RELOC_NUMBER (R_PJ_GNU_VTINHERIT, 15) + RELOC_NUMBER (R_PJ_GNU_VTENTRY, 16) + EMPTY_RELOC (R_PJ_max) +END_RELOC_NUMBERS + +#define EF_PICOJAVA_ARCH 0x0000000f +#define EF_PICOJAVA_NEWCALLS 0x00000010 +#define EF_PICOJAVA_GNUCALLS 0x00000020 /* The (currently) non standard GNU calling convention */ + +#endif diff --git a/gnu/usr.bin/binutils/include/elf/reloc-macros.h b/gnu/usr.bin/binutils/include/elf/reloc-macros.h new file mode 100644 index 00000000000..42174caeeae --- /dev/null +++ b/gnu/usr.bin/binutils/include/elf/reloc-macros.h @@ -0,0 +1,116 @@ +/* Generic relocation support for BFD. + Copyright (C) 1998 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* These macros are used by the various *.h target specific header + files to either generate an enum containing all the known relocations + for that target, or if RELOC_MACROS_GEN_FUNC is defined, a recognition + function is generated instead. (This is used by binutils/readelf.c) + + Given a header file like this: + + START_RELOC_NUMBERS (foo) + RELOC_NUMBER (R_foo_NONE, 0) + RELOC_NUMBER (R_foo_32, 1) + FAKE_RELOC (R_foo_illegal, 2) + EMPTY_RELOC (R_foo_max) + END_RELOC_NUMBERS + + Then the following will be produced by default (ie if + RELOC_MACROS_GEN_FUNC is *not* defined). + + enum foo + { + foo = -1, + R_foo_NONE = 0, + R_foo_32 = 1, + R_foo_illegal = 2, + R_foo_max + }; + + If RELOC_MACROS_GEN_FUNC *is* defined, then instead the + following function will be generated: + + static const char * foo PARAMS ((unsigned long rtype)); + static const char * + foo (rtype) + unsigned long rtype; + { + switch (rtype) + { + case 0: return "R_foo_NONE"; + case 1: return "R_foo_32"; + default: return NULL; + } + } + */ + +#ifndef _RELOC_MACROS_H +#define _RELOC_MACROS_H + +#ifdef RELOC_MACROS_GEN_FUNC + +/* This function takes the relocation number and returns the + string version name of the name of that relocation. If + the relocation is not recognised, NULL is returned. */ + +#define START_RELOC_NUMBERS(name) \ +static const char * name PARAMS ((unsigned long rtype)); \ +static const char * \ +name (rtype) \ + unsigned long rtype; \ +{ \ + switch (rtype) \ + { + +#ifdef __STDC__ +#define RELOC_NUMBER(name, number) case number : return #name ; +#else +#define RELOC_NUMBER(name, number) case number : return "name" ; +#endif + +#define FAKE_RELOC(name, number) +#define EMPTY_RELOC(name) + +#define END_RELOC_NUMBERS \ + default: return NULL; \ + } \ +} + + +#else /* Default to generating enum. */ + +/* Some compilers cannot cope with an enum that ends with a trailing + comma, so START_RELOC_NUMBERS creates a fake reloc entry, (initialised + to -1 so that the first real entry will still default to 0). Further + entries then prepend a comma to their definitions, creating a list + of enumerator entries that will satisfy these compilers. */ +#ifdef __STDC__ +#define START_RELOC_NUMBERS(name) enum name { _##name = -1 +#else +#define START_RELOC_NUMBERS(name) enum name { name = -1 +#endif + +#define RELOC_NUMBER(name, number) , name = number +#define FAKE_RELOC(name, number) , name = number +#define EMPTY_RELOC(name) , name +#define END_RELOC_NUMBERS }; + +#endif + +#endif /* RELOC_MACROS_H */ diff --git a/gnu/usr.bin/binutils/include/elf/sh.h b/gnu/usr.bin/binutils/include/elf/sh.h new file mode 100644 index 00000000000..faee5099435 --- /dev/null +++ b/gnu/usr.bin/binutils/include/elf/sh.h @@ -0,0 +1,82 @@ +/* SH ELF support for BFD. + Copyright (C) 1998 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_SH_H +#define _ELF_SH_H + +/* Processor specific flags for the ELF header e_flags field. */ + +#define EF_SH_MACH_MASK 0x1f +#define EF_SH_UNKNOWN 0 /* For backwards compatibility. */ +#define EF_SH1 1 +#define EF_SH2 2 +#define EF_SH3 3 +#define EF_SH_HAS_DSP(flags) ((flags) & 4) +#define EF_SH_DSP 4 +#define EF_SH3_DSP 5 +#define EF_SH_HAS_FP(flags) ((flags) & 8) +#define EF_SH3E 8 +#define EF_SH4 9 + +#define EF_SH_MERGE_MACH(mach1, mach2) \ + (((((mach1) == EF_SH3 || (mach1) == EF_SH_UNKNOWN) && (mach2) == EF_SH_DSP) \ + || ((mach1) == EF_SH_DSP \ + && ((mach2) == EF_SH3 || (mach2) == EF_SH_UNKNOWN))) \ + ? EF_SH3_DSP \ + : (((mach1) < EF_SH3 && (mach2) == EF_SH_UNKNOWN) \ + || ((mach2) < EF_SH3 && (mach1) == EF_SH_UNKNOWN)) \ + ? EF_SH3 \ + : (((mach1) == EF_SH3E && (mach2) == EF_SH_UNKNOWN) \ + || ((mach2) == EF_SH3E && (mach1) == EF_SH_UNKNOWN)) \ + ? EF_SH4 \ + : ((mach1) > (mach2) ? (mach1) : (mach2))) + +#include "elf/reloc-macros.h" + +/* Relocations. */ +/* Relocations 25ff are GNU extensions. + 25..33 are used for relaxation and use the same constants as COFF uses. */ +START_RELOC_NUMBERS (elf_sh_reloc_type) + RELOC_NUMBER (R_SH_NONE, 0) + RELOC_NUMBER (R_SH_DIR32, 1) + RELOC_NUMBER (R_SH_REL32, 2) + RELOC_NUMBER (R_SH_DIR8WPN, 3) + RELOC_NUMBER (R_SH_IND12W, 4) + RELOC_NUMBER (R_SH_DIR8WPL, 5) + RELOC_NUMBER (R_SH_DIR8WPZ, 6) + RELOC_NUMBER (R_SH_DIR8BP, 7) + RELOC_NUMBER (R_SH_DIR8W, 8) + RELOC_NUMBER (R_SH_DIR8L, 9) + FAKE_RELOC (R_SH_FIRST_INVALID_RELOC, 10) + FAKE_RELOC (R_SH_LAST_INVALID_RELOC, 24) + RELOC_NUMBER (R_SH_SWITCH16, 25) + RELOC_NUMBER (R_SH_SWITCH32, 26) + RELOC_NUMBER (R_SH_USES, 27) + RELOC_NUMBER (R_SH_COUNT, 28) + RELOC_NUMBER (R_SH_ALIGN, 29) + RELOC_NUMBER (R_SH_CODE, 30) + RELOC_NUMBER (R_SH_DATA, 31) + RELOC_NUMBER (R_SH_LABEL, 32) + RELOC_NUMBER (R_SH_SWITCH8, 33) + RELOC_NUMBER (R_SH_GNU_VTINHERIT, 34) + RELOC_NUMBER (R_SH_GNU_VTENTRY, 35) + EMPTY_RELOC (R_SH_max) +END_RELOC_NUMBERS + +#endif diff --git a/gnu/usr.bin/binutils/include/elf/v850.h b/gnu/usr.bin/binutils/include/elf/v850.h new file mode 100644 index 00000000000..d443b7fdc0d --- /dev/null +++ b/gnu/usr.bin/binutils/include/elf/v850.h @@ -0,0 +1,111 @@ +/* V850 ELF support for BFD. + Copyright (C) 1997 Free Software Foundation, Inc. + Created by Michael Meissner, Cygnus Support <meissner@cygnus.com> + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file holds definitions specific to the MIPS ELF ABI. Note + that most of this is not actually implemented by BFD. */ + +#ifndef _ELF_V850_H +#define _ELF_V850_H + +/* Processor specific flags for the ELF header e_flags field. */ + +/* Four bit V850 architecture field. */ +#define EF_V850_ARCH 0xf0000000 + +/* v850 code. */ +#define E_V850_ARCH 0x00000000 + +/* v850e code. */ +#define E_V850E_ARCH 0x10000000 + +/* v850ea code. */ +#define E_V850EA_ARCH 0x20000000 + + +/* Flags for the st_other field */ +#define V850_OTHER_SDA 0x01 /* symbol had SDA relocations */ +#define V850_OTHER_ZDA 0x02 /* symbol had ZDA relocations */ +#define V850_OTHER_TDA 0x04 /* symbol had TDA relocations */ +#define V850_OTHER_TDA_BYTE 0x08 /* symbol had TDA byte relocations */ +#define V850_OTHER_ERROR 0x80 /* symbol had an error reported */ + +/* V850 relocations */ +#include "elf/reloc-macros.h" + +START_RELOC_NUMBERS (v850_reloc_type) + RELOC_NUMBER (R_V850_NONE, 0) + RELOC_NUMBER (R_V850_9_PCREL, 1) + RELOC_NUMBER (R_V850_22_PCREL, 2) + RELOC_NUMBER (R_V850_HI16_S, 3) + RELOC_NUMBER (R_V850_HI16, 4) + RELOC_NUMBER (R_V850_LO16, 5) + RELOC_NUMBER (R_V850_32, 6) + RELOC_NUMBER (R_V850_16, 7) + RELOC_NUMBER (R_V850_8, 8) + RELOC_NUMBER( R_V850_SDA_16_16_OFFSET, 9) /* For ld.b, st.b, set1, clr1, not1, tst1, movea, movhi */ + RELOC_NUMBER( R_V850_SDA_15_16_OFFSET, 10) /* For ld.w, ld.h, ld.hu, st.w, st.h */ + RELOC_NUMBER( R_V850_ZDA_16_16_OFFSET, 11) /* For ld.b, st.b, set1, clr1, not1, tst1, movea, movhi */ + RELOC_NUMBER( R_V850_ZDA_15_16_OFFSET, 12) /* For ld.w, ld.h, ld.hu, st.w, st.h */ + RELOC_NUMBER( R_V850_TDA_6_8_OFFSET, 13) /* For sst.w, sld.w */ + RELOC_NUMBER( R_V850_TDA_7_8_OFFSET, 14) /* For sst.h, sld.h */ + RELOC_NUMBER( R_V850_TDA_7_7_OFFSET, 15) /* For sst.b, sld.b */ + RELOC_NUMBER( R_V850_TDA_16_16_OFFSET, 16) /* For set1, clr1, not1, tst1, movea, movhi */ +/* CYGNUS LOCAL v850e */ + RELOC_NUMBER( R_V850_TDA_4_5_OFFSET, 17) /* For sld.hu */ + RELOC_NUMBER( R_V850_TDA_4_4_OFFSET, 18) /* For sld.bu */ + RELOC_NUMBER( R_V850_SDA_16_16_SPLIT_OFFSET, 19) /* For ld.bu */ + RELOC_NUMBER( R_V850_ZDA_16_16_SPLIT_OFFSET, 20) /* For ld.bu */ + RELOC_NUMBER( R_V850_CALLT_6_7_OFFSET, 21) /* For callt */ + RELOC_NUMBER( R_V850_CALLT_16_16_OFFSET, 22) /* For callt */ +/* END CYGNUS LOCAL */ + RELOC_NUMBER (R_V850_GNU_VTINHERIT, 23) + RELOC_NUMBER (R_V850_GNU_VTENTRY, 24) + + EMPTY_RELOC (R_V850_max) +END_RELOC_NUMBERS + + +/* Processor specific section indices. These sections do not actually + exist. Symbols with a st_shndx field corresponding to one of these + values have a special meaning. */ + +/* Small data area common symbol. */ +#define SHN_V850_SCOMMON 0xff00 + +/* Tiny data area common symbol. */ +#define SHN_V850_TCOMMON 0xff01 + +/* Zero data area common symbol. */ +#define SHN_V850_ZCOMMON 0xff02 + + +/* Processor specific section types. */ + +/* Section contains the .scommon data. */ +#define SHT_V850_SCOMMON 0x70000000 + +/* Section contains the .scommon data. */ +#define SHT_V850_TCOMMON 0x70000001 + +/* Section contains the .scommon data. */ +#define SHT_V850_ZCOMMON 0x70000002 + + +#endif /* _ELF_V850_H */ diff --git a/gnu/usr.bin/binutils/include/filenames.h b/gnu/usr.bin/binutils/include/filenames.h new file mode 100644 index 00000000000..ba933c8530e --- /dev/null +++ b/gnu/usr.bin/binutils/include/filenames.h @@ -0,0 +1,51 @@ +/* Macros for taking apart, interpreting and processing file names. + + These are here because some non-Posix (a.k.a. DOSish) systems have + drive letter brain-damage at the beginning of an absolute file name, + use forward- and back-slash in path names interchangeably, and + some of them have case-insensitive file names. + + Copyright 2000 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef FILENAMES_H +#define FILENAMES_H + +#if defined(__MSDOS__) || defined(_WIN32) || defined(__OS2__) + +#ifndef HAVE_DOS_BASED_FILE_SYSTEM +#define HAVE_DOS_BASED_FILE_SYSTEM 1 +#endif + +#define IS_DIR_SEPARATOR(c) ((c) == '/' || (c) == '\\') +/* Note that IS_ABSOLUTE_PATH accepts d:foo as well, although it is + only semi-absolute. This is because the users of IS_ABSOLUTE_PATH + want to know whether to prepend the current working directory to + a file name, which should not be done with a name like d:foo. */ +#define IS_ABSOLUTE_PATH(f) (IS_DIR_SEPARATOR((f)[0]) || (((f)[0]) && ((f)[1] == ':'))) +#define FILENAME_CMP(s1, s2) strcasecmp(s1, s2) + +#else /* not DOSish */ + +#define IS_DIR_SEPARATOR(c) ((c) == '/') +#define IS_ABSOLUTE_PATH(f) (IS_DIR_SEPARATOR((f)[0])) +#define FILENAME_CMP(s1, s2) strcmp(s1, s2) + +#endif /* not DOSish */ + +#endif /* FILENAMES_H */ diff --git a/gnu/usr.bin/binutils/include/hashtab.h b/gnu/usr.bin/binutils/include/hashtab.h new file mode 100644 index 00000000000..5fe239391ff --- /dev/null +++ b/gnu/usr.bin/binutils/include/hashtab.h @@ -0,0 +1,128 @@ +/* An expandable hash tables datatype. + Copyright (C) 1999 Free Software Foundation, Inc. + Contributed by Vladimir Makarov (vmakarov@cygnus.com). + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This package implements basic hash table functionality. It is possible + to search for an entry, create an entry and destroy an entry. + + Elements in the table are generic pointers. + + The size of the table is not fixed; if the occupancy of the table + grows too high the hash table will be expanded. + + The abstract data implementation is based on generalized Algorithm D + from Knuth's book "The art of computer programming". Hash table is + expanded by creation of new hash table and transferring elements from + the old table to the new table. */ + +#ifndef __HASHTAB_H__ +#define __HASHTAB_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include <ansidecl.h> + +/* Callback function pointer types. */ + +/* Calculate hash of a table entry. */ +typedef unsigned int (*htab_hash) PARAMS ((const void *)); + +/* Compare a table entry with a possible entry. The entry already in + the table always comes first, so the second element can be of a + different type (but in this case htab_find and htab_find_slot + cannot be used; instead the variants that accept a hash value + must be used). */ +typedef int (*htab_eq) PARAMS ((const void *, const void *)); + +/* Cleanup function called whenever a live element is removed from + the hash table. */ +typedef void (*htab_del) PARAMS ((void *)); + +/* Function called by htab_traverse for each live element. The first + arg is the slot of the element (which can be passed to htab_clear_slot + if desired), the second arg is the auxiliary pointer handed to + htab_traverse. Return 1 to continue scan, 0 to stop. */ +typedef int (*htab_trav) PARAMS ((void **, void *)); + +/* Hash tables are of the following type. The structure + (implementation) of this type is not needed for using the hash + tables. All work with hash table should be executed only through + functions mentioned below. */ + +struct htab +{ + /* Pointer to hash function. */ + htab_hash hash_f; + + /* Pointer to comparison function. */ + htab_eq eq_f; + + /* Pointer to cleanup function. */ + htab_del del_f; + + /* Table itself. */ + void **entries; + + /* Current size (in entries) of the hash table */ + size_t size; + + /* Current number of elements including also deleted elements */ + size_t n_elements; + + /* Current number of deleted elements in the table */ + size_t n_deleted; + + /* The following member is used for debugging. Its value is number + of all calls of `htab_find_slot' for the hash table. */ + unsigned int searches; + + /* The following member is used for debugging. Its value is number + of collisions fixed for time of work with the hash table. */ + unsigned int collisions; +}; + +typedef struct htab *htab_t; + +/* The prototypes of the package functions. */ + +extern htab_t htab_create PARAMS ((size_t, htab_hash, + htab_eq, htab_del)); +extern void htab_delete PARAMS ((htab_t)); +extern void htab_empty PARAMS ((htab_t)); + +extern void *htab_find PARAMS ((htab_t, const void *)); +extern void **htab_find_slot PARAMS ((htab_t, const void *, int)); +extern void *htab_find_with_hash PARAMS ((htab_t, const void *, + unsigned int)); +extern void **htab_find_slot_with_hash PARAMS ((htab_t, const void *, + unsigned int, int)); +extern void htab_clear_slot PARAMS ((htab_t, void **)); +extern void htab_remove_elt PARAMS ((htab_t, void *)); + +extern void htab_traverse PARAMS ((htab_t, htab_trav, void *)); + +extern size_t htab_size PARAMS ((htab_t)); +extern size_t htab_elements PARAMS ((htab_t)); +extern double htab_collisions PARAMS ((htab_t)); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __HASHTAB_H */ diff --git a/gnu/usr.bin/binutils/include/objalloc.h b/gnu/usr.bin/binutils/include/objalloc.h index 24f87f8749d..0b451cdc295 100644 --- a/gnu/usr.bin/binutils/include/objalloc.h +++ b/gnu/usr.bin/binutils/include/objalloc.h @@ -14,7 +14,8 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software -Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ +Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ #ifndef OBJALLOC_H #define OBJALLOC_H diff --git a/gnu/usr.bin/binutils/include/opcode/alpha.h b/gnu/usr.bin/binutils/include/opcode/alpha.h index c3babc9f370..6f31e9ae09c 100644 --- a/gnu/usr.bin/binutils/include/opcode/alpha.h +++ b/gnu/usr.bin/binutils/include/opcode/alpha.h @@ -1,5 +1,5 @@ /* alpha.h -- Header file for Alpha opcode table - Copyright 1996 Free Software Foundation, Inc. + Copyright 1996, 1999 Free Software Foundation, Inc. Contributed by Richard Henderson <rth@tamu.edu>, patterned after the PPC opcode table written by Ian Lance Taylor. @@ -54,7 +54,7 @@ struct alpha_opcode in the order in which the disassembler should consider instructions. */ extern const struct alpha_opcode alpha_opcodes[]; -extern const int alpha_num_opcodes; +extern const unsigned alpha_num_opcodes; /* Values defined for the flags field of a struct alpha_opcode. */ @@ -62,11 +62,12 @@ extern const int alpha_num_opcodes; #define AXP_OPCODE_BASE 0x0001 /* Base architecture -- all cpus. */ #define AXP_OPCODE_EV4 0x0002 /* EV4 specific PALcode insns. */ #define AXP_OPCODE_EV5 0x0004 /* EV5 specific PALcode insns. */ +#define AXP_OPCODE_EV6 0x0008 /* EV6 specific PALcode insns. */ #define AXP_OPCODE_BWX 0x0100 /* Byte/word extension (amask bit 0). */ #define AXP_OPCODE_CIX 0x0200 /* "Count" extension (amask bit 1). */ #define AXP_OPCODE_MAX 0x0400 /* Multimedia extension (amask bit 8). */ -#define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5)) +#define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6)) /* A macro to extract the major opcode from an instruction. */ #define AXP_OP(i) (((i) >> 26) & 0x3F) @@ -134,7 +135,7 @@ struct alpha_operand the operands field of the alpha_opcodes table. */ extern const struct alpha_operand alpha_operands[]; -extern const int alpha_num_operands; +extern const unsigned alpha_num_operands; /* Values defined for the flags field of a struct alpha_operand. */ diff --git a/gnu/usr.bin/binutils/include/opcode/arc.h b/gnu/usr.bin/binutils/include/opcode/arc.h new file mode 100644 index 00000000000..a1e0ca15263 --- /dev/null +++ b/gnu/usr.bin/binutils/include/opcode/arc.h @@ -0,0 +1,274 @@ +/* Opcode table for the ARC. + Copyright 1994, 1995, 1997 Free Software Foundation, Inc. + Contributed by Doug Evans (dje@cygnus.com). + +This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and +the GNU Binutils. + +GAS/GDB is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GAS/GDB is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GAS or GDB; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* List of the various cpu types. + The tables currently use bit masks to say whether the instruction or + whatever is supported by a particular cpu. This lets us have one entry + apply to several cpus. + + This duplicates bfd_mach_arc_xxx. For now I wish to isolate this from bfd + and bfd from this. Also note that these numbers are bit values as we want + to allow for things available on more than one ARC (but not necessarily all + ARCs). */ + +/* The `base' cpu must be 0 (table entries are omitted for the base cpu). + The cpu type is treated independently of endianness. + The complete `mach' number includes endianness. + These values are internal to opcodes/bfd/binutils/gas. */ +#define ARC_MACH_BASE 0 +#define ARC_MACH_UNUSED1 1 +#define ARC_MACH_UNUSED2 2 +#define ARC_MACH_UNUSED4 4 +/* Additional cpu values can be inserted here and ARC_MACH_BIG moved down. */ +#define ARC_MACH_BIG 8 + +/* Mask of number of bits necessary to record cpu type. */ +#define ARC_MACH_CPU_MASK 7 +/* Mask of number of bits necessary to record cpu type + endianness. */ +#define ARC_MACH_MASK 15 + +/* Type to denote an ARC instruction (at least a 32 bit unsigned int). */ +typedef unsigned int arc_insn; + +struct arc_opcode { + char *syntax; /* syntax of insn */ + unsigned long mask, value; /* recognize insn if (op&mask)==value */ + int flags; /* various flag bits */ + +/* Values for `flags'. */ + +/* Return CPU number, given flag bits. */ +#define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) +/* Return MACH number, given flag bits. */ +#define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK) +/* First opcode flag bit available after machine mask. */ +#define ARC_OPCODE_FLAG_START ((ARC_MACH_MASK + 1) << 0) +/* This insn is a conditional branch. */ +#define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START) + + /* These values are used to optimize assembly and disassembly. Each insn is + on a list of related insns (same first letter for assembly, same insn code + for disassembly). */ + struct arc_opcode *next_asm; /* Next instruction to try during assembly. */ + struct arc_opcode *next_dis; /* Next instruction to try during disassembly. */ + + /* Macros to create the hash values for the lists. */ +#define ARC_HASH_OPCODE(string) \ + ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26) +#define ARC_HASH_ICODE(insn) \ + ((unsigned int) (insn) >> 27) + + /* Macros to access `next_asm', `next_dis' so users needn't care about the + underlying mechanism. */ +#define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm) +#define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis) +}; + +struct arc_operand_value { + char *name; /* eg: "eq" */ + short value; /* eg: 1 */ + unsigned char type; /* index into `arc_operands' */ + unsigned char flags; /* various flag bits */ + +/* Values for `flags'. */ + +/* Return CPU number, given flag bits. */ +#define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) +/* Return MACH number, given flag bits. */ +#define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK) +}; + +struct arc_operand { + /* One of the insn format chars. */ + unsigned char fmt; + + /* The number of bits in the operand (may be unused for a modifier). */ + unsigned char bits; + + /* How far the operand is left shifted in the instruction, or + the modifier's flag bit (may be unused for a modifier. */ + unsigned char shift; + + /* Various flag bits. */ + int flags; + +/* Values for `flags'. */ + +/* This operand is a suffix to the opcode. */ +#define ARC_OPERAND_SUFFIX 1 + +/* This operand is a relative branch displacement. The disassembler + prints these symbolically if possible. */ +#define ARC_OPERAND_RELATIVE_BRANCH 2 + +/* This operand is an absolute branch address. The disassembler + prints these symbolically if possible. */ +#define ARC_OPERAND_ABSOLUTE_BRANCH 4 + +/* This operand is an address. The disassembler + prints these symbolically if possible. */ +#define ARC_OPERAND_ADDRESS 8 + +/* This operand is a long immediate value. */ +#define ARC_OPERAND_LIMM 0x10 + +/* This operand takes signed values. */ +#define ARC_OPERAND_SIGNED 0x20 + +/* This operand takes signed values, but also accepts a full positive + range of values. That is, if bits is 16, it takes any value from + -0x8000 to 0xffff. */ +#define ARC_OPERAND_SIGNOPT 0x40 + +/* This operand should be regarded as a negative number for the + purposes of overflow checking (i.e., the normal most negative + number is disallowed and one more than the normal most positive + number is allowed). This flag will only be set for a signed + operand. */ +#define ARC_OPERAND_NEGATIVE 0x80 + +/* This operand doesn't really exist. The program uses these operands + in special ways. */ +#define ARC_OPERAND_FAKE 0x100 + +/* Modifier values. */ +/* A dot is required before a suffix. Eg: .le */ +#define ARC_MOD_DOT 0x1000 + +/* A normal register is allowed (not used, but here for completeness). */ +#define ARC_MOD_REG 0x2000 + +/* An auxiliary register name is expected. */ +#define ARC_MOD_AUXREG 0x4000 + +/* Sum of all ARC_MOD_XXX bits. */ +#define ARC_MOD_BITS 0x7000 + +/* Non-zero if the operand type is really a modifier. */ +#define ARC_MOD_P(X) ((X) & ARC_MOD_BITS) + + /* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (p & ((1 << o->bits) - 1)) << o->shift; + (I is the instruction which we are filling in, O is a pointer to + this structure, and OP is the opcode value; this assumes twos + complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged. + + REG is non-NULL when inserting a register value. */ + + arc_insn (*insert) PARAMS ((arc_insn insn, + const struct arc_operand *operand, int mods, + const struct arc_operand_value *reg, long value, + const char **errmsg)); + + /* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = ((i) >> o->shift) & ((1 << o->bits) - 1); + if ((o->flags & ARC_OPERAND_SIGNED) != 0 + && (op & (1 << (o->bits - 1))) != 0) + op -= 1 << o->bits; + (I is the instruction, O is a pointer to this structure, and OP + is the result; this assumes twos complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. + + INSN is a pointer to an array of two `arc_insn's. The first element is + the insn, the second is the limm if present. + + Operands that have a printable form like registers and suffixes have + their struct arc_operand_value pointer stored in OPVAL. */ + + long (*extract) PARAMS ((arc_insn *insn, + const struct arc_operand *operand, + int mods, const struct arc_operand_value **opval, + int *invalid)); +}; + +/* Bits that say what version of cpu we have. + These should be passed to arc_init_opcode_tables. + At present, all there is is the cpu type. */ + +/* CPU number, given value passed to `arc_init_opcode_tables'. */ +#define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) +/* MACH number, given value passed to `arc_init_opcode_tables'. */ +#define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK) + +/* Special register values: */ +#define ARC_REG_SHIMM_UPDATE 61 +#define ARC_REG_SHIMM 63 +#define ARC_REG_LIMM 62 + +/* Non-zero if REG is a constant marker. */ +#define ARC_REG_CONSTANT_P(REG) ((REG) >= 61) + +/* Positions and masks of various fields: */ +#define ARC_SHIFT_REGA 21 +#define ARC_SHIFT_REGB 15 +#define ARC_SHIFT_REGC 9 +#define ARC_MASK_REG 63 + +/* Delay slot types. */ +#define ARC_DELAY_NONE 0 /* no delay slot */ +#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */ +#define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */ + +/* Non-zero if X will fit in a signed 9 bit field. */ +#define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255) + +extern const struct arc_operand arc_operands[]; +extern const int arc_operand_count; +extern /*const*/ struct arc_opcode arc_opcodes[]; +extern const int arc_opcodes_count; +extern const struct arc_operand_value arc_suffixes[]; +extern const int arc_suffixes_count; +extern const struct arc_operand_value arc_reg_names[]; +extern const int arc_reg_names_count; +extern unsigned char arc_operand_map[]; + +/* Utility fns in arc-opc.c. */ +int arc_get_opcode_mach PARAMS ((int, int)); +/* `arc_opcode_init_tables' must be called before `arc_xxx_supported'. */ +void arc_opcode_init_tables PARAMS ((int)); +void arc_opcode_init_insert PARAMS ((void)); +void arc_opcode_init_extract PARAMS ((void)); +const struct arc_opcode *arc_opcode_lookup_asm PARAMS ((const char *)); +const struct arc_opcode *arc_opcode_lookup_dis PARAMS ((unsigned int)); +int arc_opcode_limm_p PARAMS ((long *)); +const struct arc_operand_value *arc_opcode_lookup_suffix PARAMS ((const struct arc_operand *type, int value)); +int arc_opcode_supported PARAMS ((const struct arc_opcode *)); +int arc_opval_supported PARAMS ((const struct arc_operand_value *)); diff --git a/gnu/usr.bin/binutils/include/opcode/cgen.h b/gnu/usr.bin/binutils/include/opcode/cgen.h index cda3373fd33..0cff7c82682 100644 --- a/gnu/usr.bin/binutils/include/opcode/cgen.h +++ b/gnu/usr.bin/binutils/include/opcode/cgen.h @@ -1,6 +1,6 @@ /* Header file for targets using CGEN: Cpu tools GENerator. -Copyright (C) 1996, 1997 Free Software Foundation, Inc. +Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. This file is part of GDB, the GNU debugger, and the GNU Binutils. @@ -14,30 +14,34 @@ but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef CGEN_H #define CGEN_H -#ifndef CGEN_CAT3 -#if defined(__STDC__) || defined(ALMOST_STDC) -#define CGEN_XCAT3(a,b,c) a ## b ## c -#define CGEN_CAT3(a,b,c) CGEN_XCAT3 (a, b, c) -#else -#define CGEN_CAT3(a,b,c) a/**/b/**/c -#endif -#endif +/* ??? This file requires bfd.h but only to get bfd_vma. + Seems like an awful lot to require just to get such a fundamental type. + Perhaps the definition of bfd_vma can be moved outside of bfd.h. + Or perhaps one could duplicate its definition in another file. + Until such time, this file conditionally compiles definitions that require + bfd_vma using BFD_VERSION. */ -/* Prepend the cpu name, defined in cpu-opc.h, and _cgen_ to symbol S. +/* Enums must be defined before they can be used. + Allow them to be used in struct definitions, even though the enum must + be defined elsewhere. + If CGEN_ARCH isn't defined, this file is being included by something other + than <arch>-desc.h. */ + +/* Prepend the arch name, defined in <arch>-desc.h, and _cgen_ to symbol S. The lack of spaces in the arg list is important for non-stdc systems. - This file is included by <cpu>-opc.h. - It can be included independently of cpu-opc.h, in which case the cpu + This file is included by <arch>-desc.h. + It can be included independently of <arch>-desc.h, in which case the arch dependent portions will be declared as "unknown_cgen_foo". */ #ifndef CGEN_SYM -#define CGEN_SYM(s) CGEN_CAT3 (unknown,_cgen_,s) +#define CGEN_SYM(s) CONCAT3 (unknown,_cgen_,s) #endif /* This file contains the static (unchanging) pieces and as much other stuff @@ -47,67 +51,155 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* The assembler syntax is made up of expressions (duh...). At the lowest level the values are mnemonics, register names, numbers, etc. Above that are subexpressions, if any (an example might be the - "effective address" in m68k cpus). At the second highest level are the - insns themselves. Above that are pseudo-insns, synthetic insns, and macros, - if any. -*/ + "effective address" in m68k cpus). Subexpressions are wip. + At the second highest level are the insns themselves. Above that are + pseudo-insns, synthetic insns, and macros, if any. */ /* Lots of cpu's have a fixed insn size, or one which rarely changes, and it's generally easier to handle these by treating the insn as an integer type, rather than an array of characters. So we allow targets - to control this. */ + to control this. When an integer type the value is in host byte order, + when an array of characters the value is in target byte order. */ -#ifdef CGEN_INT_INSN -typedef unsigned int cgen_insn_t; +typedef unsigned int CGEN_INSN_INT; +#if CGEN_INT_INSN_P +typedef CGEN_INSN_INT CGEN_INSN_BYTES; +typedef CGEN_INSN_INT *CGEN_INSN_BYTES_PTR; #else -typedef char *cgen_insn_t; +typedef unsigned char *CGEN_INSN_BYTES; +typedef unsigned char *CGEN_INSN_BYTES_PTR; #endif #ifdef __GNUC__ -#define CGEN_INLINE inline +#define CGEN_INLINE __inline__ #else #define CGEN_INLINE #endif -/* Perhaps we should just use bfd.h, but it's not clear - one would want to require that yet. */ -enum cgen_endian { +enum cgen_endian +{ CGEN_ENDIAN_UNKNOWN, CGEN_ENDIAN_LITTLE, CGEN_ENDIAN_BIG }; + +/* Forward decl. */ + +typedef struct cgen_insn CGEN_INSN; + +/* Opaque pointer version for use by external world. */ + +typedef struct cgen_cpu_desc *CGEN_CPU_DESC; /* Attributes. - Attributes are used to describe various random things. */ + Attributes are used to describe various random things associated with + an object (ifield, hardware, operand, insn, whatever) and are specified + as name/value pairs. + Integer attributes computed at compile time are currently all that's + supported, though adding string attributes and run-time computation is + straightforward. Integer attribute values are always host int's + (signed or unsigned). For portability, this means 32 bits. + Integer attributes are further categorized as boolean, bitset, integer, + and enum types. Boolean attributes appear frequently enough that they're + recorded in one host int. This limits the maximum number of boolean + attributes to 32, though that's a *lot* of attributes. */ + +/* Type of attribute values. */ + +typedef int CGEN_ATTR_VALUE_TYPE; /* Struct to record attribute information. */ -typedef struct { - unsigned int num_nonbools; + +typedef struct +{ + /* Boolean attributes. */ unsigned int bool; - unsigned int nonbool[1]; + /* Non-boolean integer attributes. */ + CGEN_ATTR_VALUE_TYPE nonbool[1]; } CGEN_ATTR; /* Define a structure member for attributes with N non-boolean entries. - The attributes are sorted so that the non-boolean ones come first. - num_nonbools: count of nonboolean attributes - bool: values of boolean attributes - nonbool: values of non-boolean attributes - There is a maximum of 32 attributes total. */ + There is no maximum number of non-boolean attributes. + There is a maximum of 32 boolean attributes (since they are all recorded + in one host int). */ + #define CGEN_ATTR_TYPE(n) \ -const struct { unsigned int num_nonbools; \ - unsigned int bool; \ - unsigned int nonbool[(n) ? (n) : 1]; } +struct { unsigned int bool; \ + CGEN_ATTR_VALUE_TYPE nonbool[(n) ? (n) : 1]; } + +/* Return the boolean attributes. */ + +#define CGEN_ATTR_BOOLS(a) ((a)->bool) + +/* Non-boolean attribute numbers are offset by this much. */ + +#define CGEN_ATTR_NBOOL_OFFSET 32 + +/* Given a boolean attribute number, return its mask. */ -/* Given an attribute number, return its mask. */ #define CGEN_ATTR_MASK(attr) (1 << (attr)) +/* Return the value of boolean attribute ATTR in ATTRS. */ + +#define CGEN_BOOL_ATTR(attrs, attr) ((CGEN_ATTR_MASK (attr) & (attrs)) != 0) + /* Return value of attribute ATTR in ATTR_TABLE for OBJ. - OBJ is a pointer to the entity that has the attributes. - It's not used at present but is reserved for future purposes. */ + OBJ is a pointer to the entity that has the attributes + (??? not used at present but is reserved for future purposes - eventually + the goal is to allow recording attributes in source form and computing + them lazily at runtime, not sure of the details yet). */ + #define CGEN_ATTR_VALUE(obj, attr_table, attr) \ -((unsigned int) (attr) < (attr_table)->num_nonbools \ - ? ((attr_table)->nonbool[attr]) \ - : (((attr_table)->bool & (1 << (attr))) != 0)) +((unsigned int) (attr) < CGEN_ATTR_NBOOL_OFFSET \ + ? ((CGEN_ATTR_BOOLS (attr_table) & CGEN_ATTR_MASK (attr)) != 0) \ + : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET])) + +/* Attribute name/value tables. + These are used to assist parsing of descriptions at run-time. */ + +typedef struct +{ + const char * name; + CGEN_ATTR_VALUE_TYPE value; +} CGEN_ATTR_ENTRY; + +/* For each domain (ifld,hw,operand,insn), list of attributes. */ + +typedef struct +{ + const char * name; + const CGEN_ATTR_ENTRY * dfault; + const CGEN_ATTR_ENTRY * vals; +} CGEN_ATTR_TABLE; + +/* Instruction set variants. */ + +typedef struct { + const char *name; + + /* Default instruction size (in bits). + This is used by the assembler when it encounters an unknown insn. */ + unsigned int default_insn_bitsize; + + /* Base instruction size (in bits). + For non-LIW cpus this is generally the length of the smallest insn. + For LIW cpus its wip (work-in-progress). For the m32r its 32. */ + unsigned int base_insn_bitsize; + + /* Minimum/maximum instruction size (in bits). */ + unsigned int min_insn_bitsize; + unsigned int max_insn_bitsize; +} CGEN_ISA; + +/* Machine variants. */ + +typedef struct { + const char *name; + /* The argument to bfd_arch_info->scan. */ + const char *bfd_name; + /* one of enum mach_attr */ + int num; +} CGEN_MACH; /* Parse result (also extraction result). @@ -125,210 +217,272 @@ const struct { unsigned int num_nonbools; \ where it varies. */ -struct cgen_fields; +typedef struct cgen_fields CGEN_FIELDS; /* Total length of the insn, as recorded in the `fields' struct. */ /* ??? The field insert handler has lots of opportunities for optimization if it ever gets inlined. On architectures where insns all have the same size, may wish to detect that and make this macro a constant - to allow further optimizations. */ + #define CGEN_FIELDS_BITSIZE(fields) ((fields)->length) -/* Associated with each insn or expression is a set of "handlers" for - performing operations like parsing, printing, etc. */ +/* Extraction support for variable length insn sets. */ -/* Forward decl. */ -typedef struct cgen_insn CGEN_INSN; +/* When disassembling we don't know the number of bytes to read at the start. + So the first CGEN_BASE_INSN_SIZE bytes are read at the start and the rest + are read when needed. This struct controls this. It is basically the + disassemble_info stuff, except that we provide a cache for values already + read (since bytes can typically be read several times to fetch multiple + operands that may be in them), and that extraction of fields is needed + in contexts other than disassembly. */ + +typedef struct { + /* A pointer to the disassemble_info struct. + We don't require dis-asm.h so we use PTR for the type here. + If NULL, BYTES is full of valid data (VALID == -1). */ + PTR dis_info; + /* Points to a working buffer of sufficient size. */ + unsigned char *insn_bytes; + /* Mask of bytes that are valid in INSN_BYTES. */ + unsigned int valid; +} CGEN_EXTRACT_INFO; + +/* Associated with each insn or expression is a set of "handlers" for + performing operations like parsing, printing, etc. These require a bfd_vma + value to be passed around but we don't want all applications to need bfd.h. + So this stuff is only provided if bfd.h has been included. */ /* Parse handler. - The first argument is a pointer to a struct describing the insn being - parsed. - The second argument is a pointer to a pointer to the text being parsed. - The third argument is a pointer to a cgen_fields struct - in which the results are placed. - If the expression is successfully parsed, the pointer to the text is - updated. If not it is left alone. + CD is a cpu table descriptor. + INSN is a pointer to a struct describing the insn being parsed. + STRP is a pointer to a pointer to the text being parsed. + FIELDS is a pointer to a cgen_fields struct in which the results are placed. + If the expression is successfully parsed, *STRP is updated. + If not it is left alone. The result is NULL if success or an error message. */ -typedef const char * (cgen_parse_fn) PARAMS ((const struct cgen_insn *, - const char **, - struct cgen_fields *)); +typedef const char * (cgen_parse_fn) + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *insn_, + const char **strp_, CGEN_FIELDS *fields_)); + +/* Insert handler. + CD is a cpu table descriptor. + INSN is a pointer to a struct describing the insn being parsed. + FIELDS is a pointer to a cgen_fields struct from which the values + are fetched. + INSNP is a pointer to a buffer in which to place the insn. + PC is the pc value of the insn. + The result is an error message or NULL if success. */ -/* Print handler. - The first argument is a pointer to the disassembly info. - Eg: disassemble_info. It's defined as `PTR' so this file can be included - without dis-asm.h. - The second argument is a pointer to a struct describing the insn being - printed. - The third argument is a pointer to a cgen_fields struct. - The fourth argument is the pc value of the insn. - The fifth argument is the length of the insn, in bytes. */ -/* Don't require bfd.h unnecessarily. */ #ifdef BFD_VERSION -typedef void (cgen_print_fn) PARAMS ((PTR, const struct cgen_insn *, - struct cgen_fields *, bfd_vma, int)); +typedef const char * (cgen_insert_fn) + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *insn_, + CGEN_FIELDS *fields_, CGEN_INSN_BYTES_PTR insnp_, + bfd_vma pc_)); #else -typedef void (cgen_print_fn) (); +typedef const char * (cgen_insert_fn) (); #endif -/* Insert handler. - The first argument is a pointer to a struct describing the insn being - parsed. - The second argument is a pointer to a cgen_fields struct - from which the values are fetched. - The third argument is a pointer to a buffer in which to place the insn. */ -typedef void (cgen_insert_fn) PARAMS ((const struct cgen_insn *, - struct cgen_fields *, cgen_insn_t *)); - /* Extract handler. - The first argument is a pointer to a struct describing the insn being - parsed. + CD is a cpu table descriptor. + INSN is a pointer to a struct describing the insn being parsed. The second argument is a pointer to a struct controlling extraction (only used for variable length insns). - The third argument is the first CGEN_BASE_INSN_SIZE bytes. - The fourth argument is a pointer to a cgen_fields struct - in which the results are placed. - The result is the length of the insn or zero if not recognized. */ -typedef int (cgen_extract_fn) PARAMS ((const struct cgen_insn *, - void *, cgen_insn_t, - struct cgen_fields *)); - -/* The `parse' and `insert' fields are indices into these tables. - The elements are pointer to specialized handler functions. - Element 0 is special, it means use the default handler. */ -extern cgen_parse_fn * CGEN_SYM (parse_handlers) []; -#define CGEN_PARSE_FN(x) (CGEN_SYM (parse_handlers)[(x)->base.parse]) -extern cgen_insert_fn * CGEN_SYM (insert_handlers) []; -#define CGEN_INSERT_FN(x) (CGEN_SYM (insert_handlers)[(x)->base.insert]) - -/* Likewise for the `extract' and `print' fields. */ -extern cgen_extract_fn * CGEN_SYM (extract_handlers) []; -#define CGEN_EXTRACT_FN(x) (CGEN_SYM (extract_handlers)[(x)->base.extract]) -extern cgen_print_fn * CGEN_SYM (print_handlers) []; -#define CGEN_PRINT_FN(x) (CGEN_SYM (print_handlers)[(x)->base.print]) - -/* Base class of parser/printer. - (Don't read too much into the use of the phrase "base class"). + EX_INFO is a pointer to a struct for controlling reading of further + bytes for the insn. + BASE_INSN is the first CGEN_BASE_INSN_SIZE bytes (host order). + FIELDS is a pointer to a cgen_fields struct in which the results are placed. + PC is the pc value of the insn. + The result is the length of the insn in bits or zero if not recognized. */ - Instructions and expressions all share this data in common. - It's a collection of the common elements needed to parse and print - each of them. */ +#ifdef BFD_VERSION +typedef int (cgen_extract_fn) + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *insn_, + CGEN_EXTRACT_INFO *ex_info_, CGEN_INSN_INT base_insn_, + CGEN_FIELDS *fields_, bfd_vma pc_)); +#else +typedef int (cgen_extract_fn) (); +#endif -#ifndef CGEN_MAX_INSN_ATTRS -#define CGEN_MAX_INSN_ATTRS 1 +/* Print handler. + CD is a cpu table descriptor. + INFO is a pointer to the disassembly info. + Eg: disassemble_info. It's defined as `PTR' so this file can be included + without dis-asm.h. + INSN is a pointer to a struct describing the insn being printed. + FIELDS is a pointer to a cgen_fields struct. + PC is the pc value of the insn. + LEN is the length of the insn, in bits. */ + +#ifdef BFD_VERSION +typedef void (cgen_print_fn) + PARAMS ((CGEN_CPU_DESC, PTR info_, const CGEN_INSN *insn_, + CGEN_FIELDS *fields_, bfd_vma pc_, int len_)); +#else +typedef void (cgen_print_fn) (); #endif -struct cgen_base { - /* Indices into the handler tables. - We could use pointers here instead, but in the case of the insn table, - 90% of them would be identical and that's a lot of redundant data. - 0 means use the default (what the default is is up to the code). */ - unsigned char parse, insert, extract, print; +/* Parse/insert/extract/print handlers. - /* Attributes. */ - CGEN_ATTR_TYPE (CGEN_MAX_INSN_ATTRS) attrs; + Indices into the handler tables. + We could use pointers here instead, but 90% of them are generally identical + and that's a lot of redundant data. Making these unsigned char indices + into tables of pointers saves a bit of space. + Using indices also keeps assembler code out of the disassembler and + vice versa. */ + +struct cgen_opcode_handler +{ + unsigned char parse, insert, extract, print; }; -/* Syntax table. +/* Assembler interface. - Each insn and subexpression has one of these. + The interface to the assembler is intended to be clean in the sense that + libopcodes.a is a standalone entity and could be used with any assembler. + Not that one would necessarily want to do that but rather that it helps + keep a clean interface. The interface will obviously be slanted towards + GAS, but at least it's a start. + ??? Note that one possible user of the assembler besides GAS is GDB. - The syntax "string" consists of characters (n > 0 && n < 128), and operand - values (n >= 128), and is terminated by 0. Operand values are 128 + index - into the operand table. The operand table doesn't exist in C, per se, as - the data is recorded in the parse/insert/extract/print switch statements. + Parsing is controlled by the assembler which calls + CGEN_SYM (assemble_insn). If it can parse and build the entire insn + it doesn't call back to the assembler. If it needs/wants to call back + to the assembler, cgen_parse_operand_fn is called which can either - ??? Whether we want to use yacc instead is unclear, but we do make an - effort to not make doing that difficult. At least that's the intent. -*/ + - return a number to be inserted in the insn + - return a "register" value to be inserted + (the register might not be a register per pe) + - queue the argument and return a marker saying the expression has been + queued (eg: a fix-up) + - return an error message indicating the expression wasn't recognizable -struct cgen_syntax { - /* Original syntax string, for debugging purposes. */ - char *orig; + The result is an error message or NULL for success. + The parsed value is stored in the bfd_vma *. */ - /* Name of entry (that distinguishes it from all other entries). - This is used, for example, in simulator profiling results. */ - char *name; +/* Values for indicating what the caller wants. */ -#if 0 /* not needed yet */ - /* Format of this insn. - This doesn't closely follow the notion of instruction formats for more - complex instruction sets. This is the value computed at runtime. */ - enum cgen_fmt_type fmt; -#endif +enum cgen_parse_operand_type +{ + CGEN_PARSE_OPERAND_INIT, + CGEN_PARSE_OPERAND_INTEGER, + CGEN_PARSE_OPERAND_ADDRESS +}; - /* Mnemonic (or name if expression). */ - char *mnemonic; +/* Values for indicating what was parsed. */ - /* Syntax string. */ - /* FIXME: If each insn's mnemonic is constant, do we want to record just - the arguments here? */ -#ifndef CGEN_MAX_SYNTAX_BYTES -#define CGEN_MAX_SYNTAX_BYTES 16 +enum cgen_parse_operand_result +{ + CGEN_PARSE_OPERAND_RESULT_NUMBER, + CGEN_PARSE_OPERAND_RESULT_REGISTER, + CGEN_PARSE_OPERAND_RESULT_QUEUED, + CGEN_PARSE_OPERAND_RESULT_ERROR +}; + +#ifdef BFD_VERSION /* Don't require bfd.h unnecessarily. */ +typedef const char * (cgen_parse_operand_fn) + PARAMS ((CGEN_CPU_DESC, + enum cgen_parse_operand_type, const char **, int, int, + enum cgen_parse_operand_result *, bfd_vma *)); +#else +typedef const char * (cgen_parse_operand_fn) (); #endif - unsigned char syntax[CGEN_MAX_SYNTAX_BYTES]; -#define CGEN_SYNTAX_CHAR_P(c) ((c) < 128) -#define CGEN_SYNTAX_CHAR(c) (c) -#define CGEN_SYNTAX_FIELD(c) ((c) - 128) +/* Set the cgen_parse_operand_fn callback. */ - /* recognize insn if (op & mask) == value - For architectures with variable length insns, this is just a preliminary - test. */ - /* FIXME: Might want a selectable type (rather than always - unsigned long). */ - unsigned long mask, value; - - /* length, in bits - This is the size that `mask' and `value' have been calculated to. - Normally it is CGEN_BASE_INSN_BITSIZE. On vliw architectures where - the base insn size may be larger than the size of an insn, this field is - less than CGEN_BASE_INSN_BITSIZE. - On architectures like the 386 and m68k the real size of the insn may - be computed while parsing. */ - /* FIXME: wip, of course */ - int length; -}; +extern void cgen_set_parse_operand_fn + PARAMS ((CGEN_CPU_DESC, cgen_parse_operand_fn)); + +/* Called before trying to match a table entry with the insn. */ + +extern void cgen_init_parse_operand PARAMS ((CGEN_CPU_DESC)); /* Operand values (keywords, integers, symbols, etc.) */ /* Types of assembler elements. */ -enum cgen_asm_type { - CGEN_ASM_KEYWORD, CGEN_ASM_MAX +enum cgen_asm_type +{ + CGEN_ASM_NONE, CGEN_ASM_KEYWORD, CGEN_ASM_MAX }; +#ifndef CGEN_ARCH +enum cgen_hw_type { CGEN_HW_MAX }; +#endif + /* List of hardware elements. */ -typedef struct cgen_hw_entry { - struct cgen_hw_entry *next; +typedef struct +{ char *name; + enum cgen_hw_type type; + /* There is currently no example where both index specs and value specs + are required, so for now both are clumped under "asm_data". */ enum cgen_asm_type asm_type; PTR asm_data; +#ifndef CGEN_HW_NBOOL_ATTRS +#define CGEN_HW_NBOOL_ATTRS 1 +#endif + CGEN_ATTR_TYPE (CGEN_HW_NBOOL_ATTRS) attrs; +#define CGEN_HW_ATTRS(hw) (&(hw)->attrs) } CGEN_HW_ENTRY; -extern CGEN_HW_ENTRY *CGEN_SYM (hw_list); +/* Return value of attribute ATTR in HW. */ -CGEN_HW_ENTRY *cgen_hw_lookup PARAMS ((const char *)); +#define CGEN_HW_ATTR_VALUE(hw, attr) \ +CGEN_ATTR_VALUE ((hw), CGEN_HW_ATTRS (hw), (attr)) -#ifndef CGEN_MAX_KEYWORD_ATTRS -#define CGEN_MAX_KEYWORD_ATTRS 1 -#endif +/* Table of hardware elements for selected mach, computed at runtime. + enum cgen_hw_type is an index into this table (specifically `entries'). */ + +typedef struct { + /* Pointer to null terminated table of all compiled in entries. */ + const CGEN_HW_ENTRY *init_entries; + unsigned int entry_size; /* since the attribute member is variable sized */ + /* Array of all entries, initial and run-time added. */ + const CGEN_HW_ENTRY **entries; + /* Number of elements in `entries'. */ + unsigned int num_entries; + /* For now, xrealloc is called each time a new entry is added at runtime. + ??? May wish to keep track of some slop to reduce the number of calls to + xrealloc, except that there's unlikely to be many and not expected to be + in speed critical code. */ +} CGEN_HW_TABLE; + +extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_name + PARAMS ((CGEN_CPU_DESC, const char *)); +extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_num + PARAMS ((CGEN_CPU_DESC, int)); /* This struct is used to describe things like register names, etc. */ -typedef struct cgen_keyword_entry { +typedef struct cgen_keyword_entry +{ /* Name (as in register name). */ - char *name; + char * name; /* Value (as in register number). The value cannot be -1 as that is used to indicate "not found". IDEA: Have "FUNCTION" attribute? [function is called to fetch value]. */ int value; - /* Attributes. */ + /* Attributes. + This should, but technically needn't, appear last. It is a variable sized + array in that one architecture may have 1 nonbool attribute and another + may have more. Having this last means the non-architecture specific code + needn't care. The goal is to eventually record + attributes in their raw form, evaluate them at run-time, and cache the + values, so this worry will go away anyway. */ + /* ??? Moving this last should be done by treating keywords like insn lists + and moving the `next' fields into a CGEN_KEYWORD_LIST struct. */ /* FIXME: Not used yet. */ - CGEN_ATTR_TYPE (CGEN_MAX_KEYWORD_ATTRS) attrs; +#ifndef CGEN_KEYWORD_NBOOL_ATTRS +#define CGEN_KEYWORD_NBOOL_ATTRS 1 +#endif + CGEN_ATTR_TYPE (CGEN_KEYWORD_NBOOL_ATTRS) attrs; + /* ??? Putting these here means compiled in entries can't be const. + Not a really big deal, but something to consider. */ /* Next name hash table entry. */ struct cgen_keyword_entry *next_name; /* Next value hash table entry. */ @@ -338,349 +492,908 @@ typedef struct cgen_keyword_entry { /* Top level struct for describing a set of related keywords (e.g. register names). - This struct supports runtime entry of new values, and hashed lookups. */ + This struct supports run-time entry of new values, and hashed lookups. */ -typedef struct cgen_keyword { +typedef struct cgen_keyword +{ /* Pointer to initial [compiled in] values. */ - struct cgen_keyword_entry *init_entries; + CGEN_KEYWORD_ENTRY *init_entries; + /* Number of entries in `init_entries'. */ unsigned int num_init_entries; + /* Hash table used for name lookup. */ - struct cgen_keyword_entry **name_hash_table; + CGEN_KEYWORD_ENTRY **name_hash_table; + /* Hash table used for value lookup. */ - struct cgen_keyword_entry **value_hash_table; + CGEN_KEYWORD_ENTRY **value_hash_table; + /* Number of entries in the hash_tables. */ unsigned int hash_table_size; + + /* Pointer to null keyword "" entry if present. */ + const CGEN_KEYWORD_ENTRY *null_entry; } CGEN_KEYWORD; /* Structure used for searching. */ -typedef struct cgen_keyword_search { +typedef struct +{ /* Table being searched. */ - const struct cgen_keyword *table; + const CGEN_KEYWORD *table; + /* Specification of what is being searched for. */ const char *spec; + /* Current index in hash table. */ unsigned int current_hash; + /* Current element in current hash chain. */ - struct cgen_keyword_entry *current_entry; + CGEN_KEYWORD_ENTRY *current_entry; } CGEN_KEYWORD_SEARCH; /* Lookup a keyword from its name. */ -const struct cgen_keyword_entry * cgen_keyword_lookup_name - PARAMS ((struct cgen_keyword *, const char *)); + +const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_name + PARAMS ((CGEN_KEYWORD *, const char *)); + /* Lookup a keyword from its value. */ -const struct cgen_keyword_entry * cgen_keyword_lookup_value - PARAMS ((struct cgen_keyword *, int)); + +const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_value + PARAMS ((CGEN_KEYWORD *, int)); + /* Add a keyword. */ -void cgen_keyword_add PARAMS ((struct cgen_keyword *, - struct cgen_keyword_entry *)); + +void cgen_keyword_add PARAMS ((CGEN_KEYWORD *, CGEN_KEYWORD_ENTRY *)); + /* Keyword searching. This can be used to retrieve every keyword, or a subset. */ -struct cgen_keyword_search cgen_keyword_search_init - PARAMS ((struct cgen_keyword *, const char *)); -const struct cgen_keyword_entry *cgen_keyword_search_next - PARAMS ((struct cgen_keyword_search *)); + +CGEN_KEYWORD_SEARCH cgen_keyword_search_init + PARAMS ((CGEN_KEYWORD *, const char *)); +const CGEN_KEYWORD_ENTRY *cgen_keyword_search_next + PARAMS ((CGEN_KEYWORD_SEARCH *)); /* Operand value support routines. */ -/* FIXME: some of the long's here will need to be bfd_vma or some such. */ - -const char * cgen_parse_keyword PARAMS ((const char **, - struct cgen_keyword *, - long *)); -const char * cgen_parse_signed_integer PARAMS ((const char **, int, - long, long, long *)); -const char * cgen_parse_unsigned_integer PARAMS ((const char **, int, - unsigned long, unsigned long, - unsigned long *)); -const char * cgen_parse_address PARAMS ((const char **, int, - int, long *)); -const char * cgen_validate_signed_integer PARAMS ((long, long, long)); -const char * cgen_validate_unsigned_integer PARAMS ((unsigned long, - unsigned long, - unsigned long)); + +extern const char *cgen_parse_keyword + PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *)); +#ifdef BFD_VERSION /* Don't require bfd.h unnecessarily. */ +extern const char *cgen_parse_signed_integer + PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); +extern const char *cgen_parse_unsigned_integer + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +extern const char *cgen_parse_address + PARAMS ((CGEN_CPU_DESC, const char **, int, int, + enum cgen_parse_operand_result *, bfd_vma *)); +extern const char *cgen_validate_signed_integer + PARAMS ((long, long, long)); +extern const char *cgen_validate_unsigned_integer + PARAMS ((unsigned long, unsigned long, unsigned long)); +#endif -/* This struct defines each entry in the operand table. */ +/* Operand modes. */ + +/* ??? This duplicates the values in arch.h. Revisit. + These however need the CGEN_ prefix [as does everything in this file]. */ +/* ??? Targets may need to add their own modes so we may wish to move this + to <arch>-opc.h, or add a hook. */ + +enum cgen_mode { + CGEN_MODE_VOID, /* ??? rename simulator's VM to VOID? */ + CGEN_MODE_BI, CGEN_MODE_QI, CGEN_MODE_HI, CGEN_MODE_SI, CGEN_MODE_DI, + CGEN_MODE_UBI, CGEN_MODE_UQI, CGEN_MODE_UHI, CGEN_MODE_USI, CGEN_MODE_UDI, + CGEN_MODE_SF, CGEN_MODE_DF, CGEN_MODE_XF, CGEN_MODE_TF, + CGEN_MODE_TARGET_MAX, + CGEN_MODE_INT, CGEN_MODE_UINT, + CGEN_MODE_MAX +}; + +/* FIXME: Until simulator is updated. */ + +#define CGEN_MODE_VM CGEN_MODE_VOID + +/* Operands. */ -#ifndef CGEN_MAX_OPERAND_ATTRS -#define CGEN_MAX_OPERAND_ATTRS 1 +#ifndef CGEN_ARCH +enum cgen_operand_type { CGEN_OPERAND_MAX }; #endif -typedef struct cgen_operand { - /* For debugging. */ +/* "nil" indicator for the operand instance table */ +#define CGEN_OPERAND_NIL CGEN_OPERAND_MAX + +/* This struct defines each entry in the operand table. */ + +typedef struct +{ + /* Name as it appears in the syntax string. */ char *name; - /* Bit position (msb of first byte = bit 0). + /* Operand type. */ + enum cgen_operand_type type; + + /* The hardware element associated with this operand. */ + enum cgen_hw_type hw_type; + + /* FIXME: We don't yet record ifield definitions, which we should. + When we do it might make sense to delete start/length (since they will + be duplicated in the ifield's definition) and replace them with a + pointer to the ifield entry. */ + + /* Bit position. + This is just a hint, and may be unused in more complex operands. May be unused for a modifier. */ unsigned char start; /* The number of bits in the operand. + This is just a hint, and may be unused in more complex operands. May be unused for a modifier. */ unsigned char length; - /* Attributes. */ - CGEN_ATTR_TYPE (CGEN_MAX_OPERAND_ATTRS) attrs; -#define CGEN_OPERAND_ATTRS(operand) (&(operand)->attrs) - -#if 0 /* ??? Interesting idea but relocs tend to get too complicated for - simple table lookups to work. */ +#if 0 /* ??? Interesting idea but relocs tend to get too complicated, + and ABI dependent, for simple table lookups to work. */ /* Ideally this would be the internal (external?) reloc type. */ int reloc_type; #endif + + /* Attributes. + This should, but technically needn't, appear last. It is a variable sized + array in that one architecture may have 1 nonbool attribute and another + may have more. Having this last means the non-architecture specific code + needn't care, now or tomorrow. The goal is to eventually record + attributes in their raw form, evaluate them at run-time, and cache the + values, so this worry will go away anyway. */ +#ifndef CGEN_OPERAND_NBOOL_ATTRS +#define CGEN_OPERAND_NBOOL_ATTRS 1 +#endif + CGEN_ATTR_TYPE (CGEN_OPERAND_NBOOL_ATTRS) attrs; +#define CGEN_OPERAND_ATTRS(operand) (&(operand)->attrs) } CGEN_OPERAND; /* Return value of attribute ATTR in OPERAND. */ -#define CGEN_OPERAND_ATTR(operand, attr) \ -CGEN_ATTR_VALUE (operand, CGEN_OPERAND_ATTRS (operand), attr) -/* The operand table is currently a very static entity. */ -extern const CGEN_OPERAND CGEN_SYM (operand_table)[]; +#define CGEN_OPERAND_ATTR_VALUE(operand, attr) \ +CGEN_ATTR_VALUE ((operand), CGEN_OPERAND_ATTRS (operand), (attr)) -enum cgen_operand_type; +/* Table of operands for selected mach/isa, computed at runtime. + enum cgen_operand_type is an index into this table (specifically + `entries'). */ -#define CGEN_OPERAND_INDEX(operand) ((int) ((operand) - CGEN_SYM (operand_table))) -/* FIXME: Rename, cpu-opc.h defines this as the typedef of the enum. */ -#define CGEN_OPERAND_TYPE(operand) ((enum cgen_operand_type) CGEN_OPERAND_INDEX (operand)) -#define CGEN_OPERAND_ENTRY(n) (& CGEN_SYM (operand_table) [n]) +typedef struct { + /* Pointer to null terminated table of all compiled in entries. */ + const CGEN_OPERAND *init_entries; + unsigned int entry_size; /* since the attribute member is variable sized */ + /* Array of all entries, initial and run-time added. */ + const CGEN_OPERAND **entries; + /* Number of elements in `entries'. */ + unsigned int num_entries; + /* For now, xrealloc is called each time a new entry is added at runtime. + ??? May wish to keep track of some slop to reduce the number of calls to + xrealloc, except that there's unlikely to be many and not expected to be + in speed critical code. */ +} CGEN_OPERAND_TABLE; + +extern const CGEN_OPERAND * cgen_operand_lookup_by_name + PARAMS ((CGEN_CPU_DESC, const char *)); +extern const CGEN_OPERAND * cgen_operand_lookup_by_num + PARAMS ((CGEN_CPU_DESC, int)); -/* This struct defines each entry in the instruction table. */ +/* Instruction operand instances. + + For each instruction, a list of the hardware elements that are read and + written are recorded. */ -struct cgen_insn { - struct cgen_base base; -/* Given a pointer to a cgen_insn struct, return a pointer to `base'. */ -#define CGEN_INSN_BASE(insn) (&(insn)->base) -#define CGEN_INSN_ATTRS(insn) (&(insn)->base.attrs) +/* The type of the instance. */ - struct cgen_syntax syntax; -#define CGEN_INSN_SYNTAX(insn) (&(insn)->syntax) -#define CGEN_INSN_FMT(insn) ((insn)->syntax.fmt) -#define CGEN_INSN_BITSIZE(insn) ((insn)->syntax.length) +enum cgen_opinst_type { + /* End of table marker. */ + CGEN_OPINST_END = 0, + CGEN_OPINST_INPUT, CGEN_OPINST_OUTPUT }; +typedef struct +{ + /* Input or output indicator. */ + enum cgen_opinst_type type; + + /* Name of operand. */ + const char *name; + + /* The hardware element referenced. */ + enum cgen_hw_type hw_type; + + /* The mode in which the operand is being used. */ + enum cgen_mode mode; + + /* The operand table entry CGEN_OPERAND_NIL if there is none + (i.e. an explicit hardware reference). */ + enum cgen_operand_type op_type; + + /* If `operand' is "nil", the index (e.g. into array of registers). */ + int index; + + /* Attributes. + ??? This perhaps should be a real attribute struct but there's + no current need, so we save a bit of space and just have a set of + flags. The interface is such that this can easily be made attributes + should it prove useful. */ + unsigned int attrs; +#define CGEN_OPINST_ATTRS(opinst) ((opinst)->attrs) +/* Return value of attribute ATTR in OPINST. */ +#define CGEN_OPINST_ATTR(opinst, attr) \ +((CGEN_OPINST_ATTRS (opinst) & (attr)) != 0) +/* Operand is conditionally referenced (read/written). */ +#define CGEN_OPINST_COND_REF 1 +} CGEN_OPINST; + +/* Syntax string. + + Each insn format and subexpression has one of these. + + The syntax "string" consists of characters (n > 0 && n < 128), and operand + values (n >= 128), and is terminated by 0. Operand values are 128 + index + into the operand table. The operand table doesn't exist in C, per se, as + the data is recorded in the parse/insert/extract/print switch statements. */ + +#ifndef CGEN_MAX_SYNTAX_BYTES +#define CGEN_MAX_SYNTAX_BYTES 16 +#endif + +typedef struct +{ + unsigned char syntax[CGEN_MAX_SYNTAX_BYTES]; +} CGEN_SYNTAX; + +#define CGEN_SYNTAX_STRING(syn) (syn->syntax) +#define CGEN_SYNTAX_CHAR_P(c) ((c) < 128) +#define CGEN_SYNTAX_CHAR(c) (c) +#define CGEN_SYNTAX_FIELD(c) ((c) - 128) +#define CGEN_SYNTAX_MAKE_FIELD(c) ((c) + 128) + +/* ??? I can't currently think of any case where the mnemonic doesn't come + first [and if one ever doesn't building the hash tables will be tricky]. + However, we treat mnemonics as just another operand of the instruction. + A value of 1 means "this is where the mnemonic appears". 1 isn't + special other than it's a non-printable ASCII char. */ + +#define CGEN_SYNTAX_MNEMONIC 1 +#define CGEN_SYNTAX_MNEMONIC_P(ch) ((ch) == CGEN_SYNTAX_MNEMONIC) + +/* Instruction fields. + + ??? We currently don't allow adding fields at run-time. + Easy to fix when needed. */ + +typedef struct cgen_ifld { + /* Enum of ifield. */ + int num; +#define CGEN_IFLD_NUM(f) ((f)->num) + + /* Name of the field, distinguishes it from all other fields. */ + const char *name; +#define CGEN_IFLD_NAME(f) ((f)->name) + + /* Default offset, in bits, from the start of the insn to the word + containing the field. */ + int word_offset; +#define CGEN_IFLD_WORD_OFFSET(f) ((f)->word_offset) + + /* Default length of the word containing the field. */ + int word_size; +#define CGEN_IFLD_WORD_SIZE(f) ((f)->word_size) + + /* Default starting bit number. + Whether lsb=0 or msb=0 is determined by CGEN_INSN_LSB0_P. */ + int start; +#define CGEN_IFLD_START(f) ((f)->start) + + /* Length of the field, in bits. */ + int length; +#define CGEN_IFLD_LENGTH(f) ((f)->length) + +#ifndef CGEN_IFLD_NBOOL_ATTRS +#define CGEN_IFLD_NBOOL_ATTRS 1 +#endif + CGEN_ATTR_TYPE (CGEN_IFLD_NBOOL_ATTRS) attrs; +#define CGEN_IFLD_ATTRS(f) (&(f)->attrs) +} CGEN_IFLD; + +/* Return value of attribute ATTR in IFLD. */ +#define CGEN_IFLD_ATTR_VALUE(ifld, attr) \ +CGEN_ATTR_VALUE ((ifld), CGEN_IFLD_ATTRS (ifld), (attr)) + +/* Instruction data. */ + +/* Instruction formats. + + Instructions are grouped by format. Associated with an instruction is its + format. Each insn's opcode table entry contains a format table entry. + ??? There is usually very few formats compared with the number of insns, + so one can reduce the size of the opcode table by recording the format table + as a separate entity. Given that we currently don't, format table entries + are also distinguished by their operands. This increases the size of the + table, but reduces the number of tables. It's all minutiae anyway so it + doesn't really matter [at this point in time]. + + ??? Support for variable length ISA's is wip. */ + +/* Accompanying each iformat description is a list of its fields. */ + +typedef struct { + const CGEN_IFLD *ifld; +#define CGEN_IFMT_IFLD_IFLD(ii) ((ii)->ifld) +} CGEN_IFMT_IFLD; + +#ifndef CGEN_MAX_IFMT_OPERANDS +#define CGEN_MAX_IFMT_OPERANDS 1 +#endif + +typedef struct +{ + /* Length that MASK and VALUE have been calculated to + [VALUE is recorded elsewhere]. + Normally it is base_insn_bitsize. On [V]LIW architectures where the base + insn size may be larger than the size of an insn, this field is less than + base_insn_bitsize. */ + unsigned char mask_length; +#define CGEN_IFMT_MASK_LENGTH(ifmt) ((ifmt)->mask_length) + + /* Total length of instruction, in bits. */ + unsigned char length; +#define CGEN_IFMT_LENGTH(ifmt) ((ifmt)->length) + + /* Mask to apply to the first MASK_LENGTH bits. + Each insn's value is stored with the insn. + The first step in recognizing an insn for disassembly is + (opcode & mask) == value. */ + CGEN_INSN_INT mask; +#define CGEN_IFMT_MASK(ifmt) ((ifmt)->mask) + + /* Instruction fields. + +1 for trailing NULL. */ + CGEN_IFMT_IFLD iflds[CGEN_MAX_IFMT_OPERANDS + 1]; +#define CGEN_IFMT_IFLDS(ifmt) ((ifmt)->iflds) +} CGEN_IFMT; + +/* Instruction values. */ + +typedef struct +{ + /* The opcode portion of the base insn. */ + CGEN_INSN_INT base_value; + +#ifdef CGEN_MAX_EXTRA_OPCODE_OPERANDS + /* Extra opcode values beyond base_value. */ + unsigned long ifield_values[CGEN_MAX_EXTRA_OPCODE_OPERANDS]; +#endif +} CGEN_IVALUE; + +/* Instruction opcode table. + This contains the syntax and format data of an instruction. */ + +/* ??? Some ports already have an opcode table yet still need to use the rest + of what cgen_insn has. Plus keeping the opcode data with the operand + instance data can create a pretty big file. So we keep them separately. + Not sure this is a good idea in the long run. */ + +typedef struct +{ + /* Indices into parse/insert/extract/print handler tables. */ + struct cgen_opcode_handler handlers; +#define CGEN_OPCODE_HANDLERS(opc) (& (opc)->handlers) + + /* Syntax string. */ + CGEN_SYNTAX syntax; +#define CGEN_OPCODE_SYNTAX(opc) (& (opc)->syntax) + + /* Format entry. */ + const CGEN_IFMT *format; +#define CGEN_OPCODE_FORMAT(opc) ((opc)->format) +#define CGEN_OPCODE_MASK_BITSIZE(opc) CGEN_IFMT_MASK_LENGTH (CGEN_OPCODE_FORMAT (opc)) +#define CGEN_OPCODE_BITSIZE(opc) CGEN_IFMT_LENGTH (CGEN_OPCODE_FORMAT (opc)) +#define CGEN_OPCODE_IFLDS(opc) CGEN_IFMT_IFLDS (CGEN_OPCODE_FORMAT (opc)) + + /* Instruction opcode value. */ + CGEN_IVALUE value; +#define CGEN_OPCODE_VALUE(opc) (& (opc)->value) +#define CGEN_OPCODE_BASE_VALUE(opc) (CGEN_OPCODE_VALUE (opc)->base_value) +#define CGEN_OPCODE_BASE_MASK(opc) CGEN_IFMT_MASK (CGEN_OPCODE_FORMAT (opc)) +} CGEN_OPCODE; + +/* Instruction attributes. + This is made a published type as applications can cache a pointer to + the attributes for speed. */ + +#ifndef CGEN_INSN_NBOOL_ATTRS +#define CGEN_INSN_NBOOL_ATTRS 1 +#endif +typedef CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) CGEN_INSN_ATTR_TYPE; + +/* Enum of architecture independent attributes. */ + +#ifndef CGEN_ARCH +/* ??? Numbers here are recorded in two places. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS = 0 +} CGEN_INSN_ATTR; +#endif + +/* This struct defines each entry in the instruction table. */ + +typedef struct +{ + /* Each real instruction is enumerated. */ + /* ??? This may go away in time. */ + int num; +#define CGEN_INSN_NUM(insn) ((insn)->base->num) + + /* Name of entry (that distinguishes it from all other entries). */ + /* ??? If mnemonics have operands, try to print full mnemonic. */ + const char *name; +#define CGEN_INSN_NAME(insn) ((insn)->base->name) + + /* Mnemonic. This is used when parsing and printing the insn. + In the case of insns that have operands on the mnemonics, this is + only the constant part. E.g. for conditional execution of an `add' insn, + where the full mnemonic is addeq, addne, etc., and the condition is + treated as an operand, this is only "add". */ + const char *mnemonic; +#define CGEN_INSN_MNEMONIC(insn) ((insn)->base->mnemonic) + + /* Total length of instruction, in bits. */ + int bitsize; +#define CGEN_INSN_BITSIZE(insn) ((insn)->base->bitsize) + +#if 0 /* ??? Disabled for now as there is a problem with embedded newlines + and the table is already pretty big. Should perhaps be moved + to a file of its own. */ + /* Semantics, as RTL. */ + /* ??? Plain text or bytecodes? */ + /* ??? Note that the operand instance table could be computed at run-time + if we parse this and cache the results. Something to eventually do. */ + const char *rtx; +#define CGEN_INSN_RTX(insn) ((insn)->base->rtx) +#endif + + /* Attributes. + This must appear last. It is a variable sized array in that one + architecture may have 1 nonbool attribute and another may have more. + Having this last means the non-architecture specific code needn't + care. The goal is to eventually record attributes in their raw form, + evaluate them at run-time, and cache the values, so this worry will go + away anyway. */ + CGEN_INSN_ATTR_TYPE attrs; +#define CGEN_INSN_ATTRS(insn) (&(insn)->base->attrs) /* Return value of attribute ATTR in INSN. */ -#define CGEN_INSN_ATTR(insn, attr) \ -CGEN_ATTR_VALUE (insn, CGEN_INSN_ATTRS (insn), attr) +#define CGEN_INSN_ATTR_VALUE(insn, attr) \ +CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr)) +} CGEN_IBASE; + +/* Return non-zero if INSN is the "invalid" insn marker. */ + +#define CGEN_INSN_INVALID_P(insn) (CGEN_INSN_MNEMONIC (insn) == 0) + +/* Main struct contain instruction information. + BASE is always present, the rest is present only if asked for. */ + +struct cgen_insn +{ + /* ??? May be of use to put a type indicator here. + Then this struct could different info for different classes of insns. */ + /* ??? A speedup can be had by moving `base' into this struct. + Maybe later. */ + const CGEN_IBASE *base; + const CGEN_OPCODE *opcode; + const CGEN_OPINST *opinst; +}; /* Instruction lists. This is used for adding new entries and for creating the hash lists. */ -typedef struct cgen_insn_list { +typedef struct cgen_insn_list +{ struct cgen_insn_list *next; - const struct cgen_insn *insn; + const CGEN_INSN *insn; } CGEN_INSN_LIST; -/* The table of instructions. */ +/* Table of instructions. */ -typedef struct cgen_insn_table { - /* Pointer to initial [compiled in] entries. */ - const struct cgen_insn *init_entries; - /* Number of entries in `init_entries', including trailing NULL entry. */ +typedef struct +{ + const CGEN_INSN *init_entries; + unsigned int entry_size; /* since the attribute member is variable sized */ unsigned int num_init_entries; - /* Values added at runtime. */ - struct cgen_insn_list *new_entries; - /* Assembler hash function. */ - unsigned int (*asm_hash) PARAMS ((const char *)); - /* Number of entries in assembler hash table. */ - unsigned int asm_hash_table_size; - /* Disassembler hash function. */ - unsigned int (*dis_hash) PARAMS ((const char *, unsigned long)); - /* Number of entries in disassembler hash table. */ - unsigned int dis_hash_table_size; + CGEN_INSN_LIST *new_entries; } CGEN_INSN_TABLE; -/* ??? This is currently used by the simulator. - We want this to be fast and the simulator currently doesn't handle - runtime added instructions so this is ok. An alternative would be to - store the index in the table. */ -extern const CGEN_INSN CGEN_SYM (insn_table_entries)[]; -#define CGEN_INSN_INDEX(insn) ((int) ((insn) - CGEN_SYM (insn_table_entries))) -#define CGEN_INSN_ENTRY(n) (& CGEN_SYM (insn_table_entries) [n]) +/* Return number of instructions. This includes any added at run-time. */ + +extern int cgen_insn_count PARAMS ((CGEN_CPU_DESC)); +extern int cgen_macro_insn_count PARAMS ((CGEN_CPU_DESC)); + +/* Macros to access the other insn elements not recorded in CGEN_IBASE. */ + +/* Fetch INSN's operand instance table. */ +/* ??? Doesn't handle insns added at runtime. */ +#define CGEN_INSN_OPERANDS(insn) ((insn)->opinst) + +/* Return INSN's opcode table entry. */ +#define CGEN_INSN_OPCODE(insn) ((insn)->opcode) -/* Return number of instructions. This includes any added at runtime. */ +/* Return INSN's handler data. */ +#define CGEN_INSN_HANDLERS(insn) CGEN_OPCODE_HANDLERS (CGEN_INSN_OPCODE (insn)) -int cgen_insn_count PARAMS (()); +/* Return INSN's syntax. */ +#define CGEN_INSN_SYNTAX(insn) CGEN_OPCODE_SYNTAX (CGEN_INSN_OPCODE (insn)) +/* Return size of base mask in bits. */ +#define CGEN_INSN_MASK_BITSIZE(insn) \ + CGEN_OPCODE_MASK_BITSIZE (CGEN_INSN_OPCODE (insn)) + +/* Return mask of base part of INSN. */ +#define CGEN_INSN_BASE_MASK(insn) \ + CGEN_OPCODE_BASE_MASK (CGEN_INSN_OPCODE (insn)) + +/* Return value of base part of INSN. */ +#define CGEN_INSN_BASE_VALUE(insn) \ + CGEN_OPCODE_BASE_VALUE (CGEN_INSN_OPCODE (insn)) + +/* Standard way to test whether INSN is supported by MACH. + MACH is one of enum mach_attr. + The "|1" is because the base mach is always selected. */ +#define CGEN_INSN_MACH_HAS_P(insn, mach) \ +((CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_MACH) & ((1 << (mach)) | 1)) != 0) + +/* Macro instructions. + Macro insns aren't real insns, they map to one or more real insns. + E.g. An architecture's "nop" insn may actually be an "mv r0,r0" or + some such. + + Macro insns can expand to nothing (e.g. a nop that is optimized away). + This is useful in multi-insn macros that build a constant in a register. + Of course this isn't the default behaviour and must be explicitly enabled. + + Assembly of macro-insns is relatively straightforward. Disassembly isn't. + However, disassembly of at least some kinds of macro insns is important + in order that the disassembled code preserve the readability of the original + insn. What is attempted here is to disassemble all "simple" macro-insns, + where "simple" is currently defined to mean "expands to one real insn". + + Simple macro-insns are handled specially. They are emitted as ALIAS's + of real insns. This simplifies their handling since there's usually more + of them than any other kind of macro-insn, and proper disassembly of them + falls out for free. */ + +/* For each macro-insn there may be multiple expansion possibilities, + depending on the arguments. This structure is accessed via the `data' + member of CGEN_INSN. */ + +typedef struct cgen_minsn_expansion { + /* Function to do the expansion. + If the expansion fails (e.g. "no match") NULL is returned. + Space for the expansion is obtained with malloc. + It is up to the caller to free it. */ + const char * (* fn) PARAMS ((const struct cgen_minsn_expansion *, + const char *, const char **, int *, + CGEN_OPERAND **)); +#define CGEN_MIEXPN_FN(ex) ((ex)->fn) + + /* Instruction(s) the macro expands to. + The format of STR is defined by FN. + It is typically the assembly code of the real insn, but it could also be + the original Scheme expression or a tokenized form of it (with FN being + an appropriate interpreter). */ + const char * str; +#define CGEN_MIEXPN_STR(ex) ((ex)->str) +} CGEN_MINSN_EXPANSION; + +/* Normal expander. + When supported, this function will convert the input string to another + string and the parser will be invoked recursively. The output string + may contain further macro invocations. */ + +extern const char * cgen_expand_macro_insn + PARAMS ((CGEN_CPU_DESC, const struct cgen_minsn_expansion *, + const char *, const char **, int *, CGEN_OPERAND **)); + /* The assembler insn table is hashed based on some function of the mnemonic (the actually hashing done is up to the target, but we provide a few - examples like the first letter or a function of the entire mnemonic). - The index of each entry is the index of the corresponding table entry. - The value of each entry is the index of the next entry, with a 0 - terminating (thus the first entry is reserved). */ - -#ifndef CGEN_ASM_HASH -#ifdef CGEN_MNEMONIC_OPERANDS -#define CGEN_ASM_HASH_SIZE 127 -#define CGEN_ASM_HASH(string) (*(unsigned char *) (string) % CGEN_ASM_HASH_SIZE) -#else -#define CGEN_ASM_HASH_SIZE 128 -#define CGEN_ASM_HASH(string) (*(unsigned char *) (string) % CGEN_ASM_HASH_SIZE) /*FIXME*/ -#endif -#endif + examples like the first letter or a function of the entire mnemonic). */ -unsigned int CGEN_SYM (asm_hash_insn) PARAMS ((const char *)); -CGEN_INSN_LIST * cgen_asm_lookup_insn PARAMS ((const char *)); -#define CGEN_ASM_LOOKUP_INSN(insn) cgen_asm_lookup_insn (insn) +extern CGEN_INSN_LIST * cgen_asm_lookup_insn + PARAMS ((CGEN_CPU_DESC, const char *)); +#define CGEN_ASM_LOOKUP_INSN(cd, string) cgen_asm_lookup_insn ((cd), (string)) #define CGEN_ASM_NEXT_INSN(insn) ((insn)->next) /* The disassembler insn table is hashed based on some function of machine instruction (the actually hashing done is up to the target). */ -/* It doesn't make much sense to provide a default here, - but while this is under development we do. - BUFFER is a pointer to the bytes of the insn. - INSN is the first CGEN_BASE_INSN_SIZE bytes as an int in host order. */ -#ifndef CGEN_DIS_HASH -#define CGEN_DIS_HASH_SIZE 256 -#define CGEN_DIS_HASH(buffer, insn) (*(unsigned char *) (buffer)) -#endif - -unsigned int CGEN_SYM (dis_hash_insn) PARAMS ((const char *, unsigned long)); -CGEN_INSN_LIST * cgen_dis_lookup_insn PARAMS ((const char *, unsigned long)); -#define CGEN_DIS_LOOKUP_INSN(buf, insn) cgen_dis_lookup_insn (buf, insn) +extern CGEN_INSN_LIST * cgen_dis_lookup_insn + PARAMS ((CGEN_CPU_DESC, const char *, CGEN_INSN_INT)); +/* FIXME: delete these two */ +#define CGEN_DIS_LOOKUP_INSN(cd, buf, value) cgen_dis_lookup_insn ((cd), (buf), (value)) #define CGEN_DIS_NEXT_INSN(insn) ((insn)->next) -/* Top level structures and functions. */ +/* The CPU description. + A copy of this is created when the cpu table is "opened". + All global state information is recorded here. + Access macros are provided for "public" members. */ + +typedef struct cgen_cpu_desc +{ + /* Bitmap of selected machine(s) (a la BFD machine number). */ + int machs; + + /* Bitmap of selected isa(s). + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. */ + int isas; + + /* Current endian. */ + enum cgen_endian endian; +#define CGEN_CPU_ENDIAN(cd) ((cd)->endian) + + /* Current insn endian. */ + enum cgen_endian insn_endian; +#define CGEN_CPU_INSN_ENDIAN(cd) ((cd)->insn_endian) + + /* Word size (in bits). */ + /* ??? Or maybe maximum word size - might we ever need to allow a cpu table + to be opened for both sparc32/sparc64? + ??? Another alternative is to create a table of selected machs and + lazily fetch the data from there. */ + unsigned int word_bitsize; + + /* Indicator if sizes are unknown. + This is used by default_insn_bitsize,base_insn_bitsize if there is a + difference between the selected isa's. */ +#define CGEN_SIZE_UNKNOWN 65535 + + /* Default instruction size (in bits). + This is used by the assembler when it encounters an unknown insn. */ + unsigned int default_insn_bitsize; + + /* Base instruction size (in bits). + For non-LIW cpus this is generally the length of the smallest insn. + For LIW cpus its wip (work-in-progress). For the m32r its 32. */ + unsigned int base_insn_bitsize; + + /* Minimum/maximum instruction size (in bits). */ + unsigned int min_insn_bitsize; + unsigned int max_insn_bitsize; + + /* Instruction set variants. */ + const CGEN_ISA *isa_table; + + /* Machine variants. */ + const CGEN_MACH *mach_table; + + /* Hardware elements. */ + CGEN_HW_TABLE hw_table; + + /* Instruction fields. */ + const CGEN_IFLD *ifld_table; + + /* Operands. */ + CGEN_OPERAND_TABLE operand_table; + + /* Main instruction table. */ + CGEN_INSN_TABLE insn_table; +#define CGEN_CPU_INSN_TABLE(cd) (& (cd)->insn_table) + + /* Macro instructions are defined separately and are combined with real + insns during hash table computation. */ + CGEN_INSN_TABLE macro_insn_table; + + /* Copy of CGEN_INT_INSN_P. */ + int int_insn_p; + + /* Called to rebuild the tables after something has changed. */ + void (*rebuild_tables) PARAMS ((CGEN_CPU_DESC)); + + /* Operand parser callback. */ + cgen_parse_operand_fn * parse_operand_fn; + + /* Parse/insert/extract/print cover fns for operands. */ + const char * (*parse_operand) + PARAMS ((CGEN_CPU_DESC, int opindex_, const char **, + CGEN_FIELDS *fields_)); +#ifdef BFD_VERSION + const char * (*insert_operand) + PARAMS ((CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, + CGEN_INSN_BYTES_PTR, bfd_vma pc_)); + int (*extract_operand) + PARAMS ((CGEN_CPU_DESC, int opindex_, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + CGEN_FIELDS *fields_, bfd_vma pc_)); + void (*print_operand) + PARAMS ((CGEN_CPU_DESC, int opindex_, PTR info_, CGEN_FIELDS * fields_, + void const *attrs_, bfd_vma pc_, int length_)); +#else + const char * (*insert_operand) (); + int (*extract_operand) (); + void (*print_operand) (); +#endif +#define CGEN_CPU_PARSE_OPERAND(cd) ((cd)->parse_operand) +#define CGEN_CPU_INSERT_OPERAND(cd) ((cd)->insert_operand) +#define CGEN_CPU_EXTRACT_OPERAND(cd) ((cd)->extract_operand) +#define CGEN_CPU_PRINT_OPERAND(cd) ((cd)->print_operand) + + /* Size of CGEN_FIELDS struct. */ + unsigned int sizeof_fields; +#define CGEN_CPU_SIZEOF_FIELDS(cd) ((cd)->sizeof_fields) + + /* Set the bitsize field. */ + void (*set_fields_bitsize) PARAMS ((CGEN_FIELDS *fields_, int size_)); +#define CGEN_CPU_SET_FIELDS_BITSIZE(cd) ((cd)->set_fields_bitsize) + + /* CGEN_FIELDS accessors. */ + int (*get_int_operand) + PARAMS ((CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_)); + void (*set_int_operand) + PARAMS ((CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, int value_)); +#ifdef BFD_VERSION + bfd_vma (*get_vma_operand) + PARAMS ((CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_)); + void (*set_vma_operand) + PARAMS ((CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, bfd_vma value_)); +#else + long (*get_vma_operand) (); + void (*set_vma_operand) (); +#endif +#define CGEN_CPU_GET_INT_OPERAND(cd) ((cd)->get_int_operand) +#define CGEN_CPU_SET_INT_OPERAND(cd) ((cd)->set_int_operand) +#define CGEN_CPU_GET_VMA_OPERAND(cd) ((cd)->get_vma_operand) +#define CGEN_CPU_SET_VMA_OPERAND(cd) ((cd)->set_vma_operand) + + /* Instruction parse/insert/extract/print handlers. */ + /* FIXME: make these types uppercase. */ + cgen_parse_fn * const *parse_handlers; + cgen_insert_fn * const *insert_handlers; + cgen_extract_fn * const *extract_handlers; + cgen_print_fn * const *print_handlers; +#define CGEN_PARSE_FN(cd, insn) (cd->parse_handlers[(insn)->opcode->handlers.parse]) +#define CGEN_INSERT_FN(cd, insn) (cd->insert_handlers[(insn)->opcode->handlers.insert]) +#define CGEN_EXTRACT_FN(cd, insn) (cd->extract_handlers[(insn)->opcode->handlers.extract]) +#define CGEN_PRINT_FN(cd, insn) (cd->print_handlers[(insn)->opcode->handlers.print]) + + /* Return non-zero if insn should be added to hash table. */ + int (* asm_hash_p) PARAMS ((const CGEN_INSN *)); + + /* Assembler hash function. */ + unsigned int (* asm_hash) PARAMS ((const char *)); + + /* Number of entries in assembler hash table. */ + unsigned int asm_hash_size; -typedef struct cgen_opcode_data { - CGEN_HW_ENTRY *hw_list; - /*CGEN_OPERAND_TABLE *operand_table; - FIXME:wip */ - CGEN_INSN_TABLE *insn_table; -} CGEN_OPCODE_DATA; + /* Return non-zero if insn should be added to hash table. */ + int (* dis_hash_p) PARAMS ((const CGEN_INSN *)); -/* Each CPU has one of these. */ -extern CGEN_OPCODE_DATA CGEN_SYM (opcode_data); + /* Disassembler hash function. */ + unsigned int (* dis_hash) PARAMS ((const char *, CGEN_INSN_INT)); -/* Global state access macros. - Some of these are tucked away and accessed with cover fns. - Simpler things like the current machine and endian are not. */ + /* Number of entries in disassembler hash table. */ + unsigned int dis_hash_size; -extern int cgen_current_machine; -#define CGEN_CURRENT_MACHINE cgen_current_machine + /* Assembler instruction hash table. */ + CGEN_INSN_LIST **asm_hash_table; + CGEN_INSN_LIST *asm_hash_table_entries; -extern enum cgen_endian cgen_current_endian; -#define CGEN_CURRENT_ENDIAN cgen_current_endian + /* Disassembler instruction hash table. */ + CGEN_INSN_LIST **dis_hash_table; + CGEN_INSN_LIST *dis_hash_table_entries; -/* Prototypes of major functions. */ + /* This field could be turned into a bitfield if room for other flags is needed. */ + unsigned int signed_overflow_ok_p; + +} CGEN_CPU_TABLE; -/* Set the current cpu (+ mach number, endian, etc.). *? -void cgen_set_cpu PARAMS ((CGEN_OPCODE_DATA *, int, enum cgen_endian)); - -/* Initialize the assembler, disassembler. */ -void cgen_asm_init PARAMS ((void)); -void cgen_dis_init PARAMS ((void)); - -/* `init_tables' must be called before `xxx_supported'. */ -void CGEN_SYM (init_tables) PARAMS ((int)); -void CGEN_SYM (init_asm) PARAMS ((int, enum cgen_endian)); -void CGEN_SYM (init_dis) PARAMS ((int, enum cgen_endian)); -void CGEN_SYM (init_parse) PARAMS ((void)); -void CGEN_SYM (init_print) PARAMS ((void)); -void CGEN_SYM (init_insert) PARAMS ((void)); -void CGEN_SYM (init_extract) PARAMS ((void)); -const struct cgen_insn * -CGEN_SYM (assemble_insn) PARAMS ((const char *, struct cgen_fields *, - cgen_insn_t *, char **)); -int CGEN_SYM (insn_supported) PARAMS ((const struct cgen_syntax *)); -#if 0 /* old */ -int CGEN_SYM (opval_supported) PARAMS ((const struct cgen_opval *)); +/* wip */ +#ifndef CGEN_WORD_ENDIAN +#define CGEN_WORD_ENDIAN(cd) CGEN_CPU_ENDIAN (cd) +#endif +#ifndef CGEN_INSN_WORD_ENDIAN +#define CGEN_INSN_WORD_ENDIAN(cd) CGEN_CPU_INSN_ENDIAN (cd) #endif + +/* Prototypes of major functions. */ +/* FIXME: Move more CGEN_SYM-defined functions into CGEN_CPU_DESC. + Not the init fns though, as that would drag in things that mightn't be + used and might not even exist. */ + +/* Argument types to cpu_open. */ + +enum cgen_cpu_open_arg { + CGEN_CPU_OPEN_END, + /* Select instruction set(s), arg is bitmap or 0 meaning "unspecified". */ + CGEN_CPU_OPEN_ISAS, + /* Select machine(s), arg is bitmap or 0 meaning "unspecified". */ + CGEN_CPU_OPEN_MACHS, + /* Select machine, arg is mach's bfd name. + Multiple machines can be specified by repeated use. */ + CGEN_CPU_OPEN_BFDMACH, + /* Select endian, arg is CGEN_ENDIAN_*. */ + CGEN_CPU_OPEN_ENDIAN +}; -extern const struct cgen_keyword CGEN_SYM (operand_mach); -int CGEN_SYM (get_mach) PARAMS ((const char *)); +/* Open a cpu descriptor table for use. + ??? We only support ISO C stdargs here, not K&R. + Laziness, plus experiment to see if anything requires K&R - eventually + K&R will no longer be supported - e.g. GDB is currently trying this. */ -CGEN_INLINE void -CGEN_SYM (put_operand) PARAMS ((int, const long *, - struct cgen_fields *)); -CGEN_INLINE long -CGEN_SYM (get_operand) PARAMS ((int, const struct cgen_fields *)); +extern CGEN_CPU_DESC CGEN_SYM (cpu_open) (enum cgen_cpu_open_arg, ...); -CGEN_INLINE const char * -CGEN_SYM (parse_operand) PARAMS ((int, const char **, struct cgen_fields *)); +/* Cover fn to handle simple case. */ -CGEN_INLINE const char * -CGEN_SYM (validate_operand) PARAMS ((int, const struct cgen_fields *)); +extern CGEN_CPU_DESC CGEN_SYM (cpu_open_1) PARAMS ((const char *mach_name_, + enum cgen_endian endian_)); -/* Default insn parser, printer. */ -extern cgen_parse_fn CGEN_SYM (parse_insn); -extern cgen_insert_fn CGEN_SYM (insert_insn); -extern cgen_extract_fn CGEN_SYM (extract_insn); -extern cgen_print_fn CGEN_SYM (print_insn); +/* Close it. */ -/* Read in a cpu description file. */ -const char * cgen_read_cpu_file PARAMS ((const char *)); - -/* Assembler interface. +extern void CGEN_SYM (cpu_close) PARAMS ((CGEN_CPU_DESC)); - The interface to the assembler is intended to be clean in the sense that - libopcodes.a is a standalone entity and could be used with any assembler. - Not that one would necessarily want to do that but rather that it helps - keep a clean interface. The interface will obviously be slanted towards - GAS, but at least it's a start. +/* Initialize the opcode table for use. + Called by init_asm/init_dis. */ - Parsing is controlled by the assembler which calls - CGEN_SYM (assemble_insn). If it can parse and build the entire insn - it doesn't call back to the assembler. If it needs/wants to call back - to the assembler, (*cgen_parse_operand_fn) is called which can either +extern void CGEN_SYM (init_opcode_table) PARAMS ((CGEN_CPU_DESC cd_)); - - return a number to be inserted in the insn - - return a "register" value to be inserted - (the register might not be a register per pe) - - queue the argument and return a marker saying the expression has been - queued (eg: a fix-up) - - return an error message indicating the expression wasn't recognizable +/* Initialize the ibld table for use. + Called by init_asm/init_dis. */ - The result is an error message or NULL for success. - The parsed value is stored in the bfd_vma *. */ +extern void CGEN_SYM (init_ibld_table) PARAMS ((CGEN_CPU_DESC cd_)); -/* Values for indicating what the caller wants. */ -enum cgen_parse_operand_type { - CGEN_PARSE_OPERAND_INIT, CGEN_PARSE_OPERAND_INTEGER, - CGEN_PARSE_OPERAND_ADDRESS -}; +/* Initialize an cpu table for assembler or disassembler use. + These must be called immediately after cpu_open. */ -/* Values for indicating what was parsed. - ??? Not too useful at present but in time. */ -enum cgen_parse_operand_result { - CGEN_PARSE_OPERAND_RESULT_NUMBER, CGEN_PARSE_OPERAND_RESULT_REGISTER, - CGEN_PARSE_OPERAND_RESULT_QUEUED, CGEN_PARSE_OPERAND_RESULT_ERROR -}; +extern void CGEN_SYM (init_asm) PARAMS ((CGEN_CPU_DESC)); +extern void CGEN_SYM (init_dis) PARAMS ((CGEN_CPU_DESC)); -/* Don't require bfd.h unnecessarily. */ -#ifdef BFD_VERSION -extern const char * (*cgen_parse_operand_fn) - PARAMS ((enum cgen_parse_operand_type, const char **, int, int, - enum cgen_parse_operand_result *, bfd_vma *)); -#endif +/* Initialize the operand instance table for use. */ -/* Called before trying to match a table entry with the insn. */ -void cgen_init_parse_operand PARAMS ((void)); +extern void CGEN_SYM (init_opinst_table) PARAMS ((CGEN_CPU_DESC cd_)); -/* Called from <cpu>-asm.c to initialize operand parsing. */ +/* Assemble an instruction. */ -/* These are GAS specific. They're not here as part of the interface, - but rather that we need to put them somewhere. */ +extern const CGEN_INSN * CGEN_SYM (assemble_insn) + PARAMS ((CGEN_CPU_DESC, const char *, CGEN_FIELDS *, + CGEN_INSN_BYTES_PTR, char **)); -/* Call this from md_assemble to initialize the assembler callback. */ -void cgen_asm_init_parse PARAMS ((void)); +extern const CGEN_KEYWORD CGEN_SYM (operand_mach); +extern int CGEN_SYM (get_mach) PARAMS ((const char *)); -/* Don't require bfd.h unnecessarily. */ -#ifdef BFD_VERSION -/* The result is an error message or NULL for success. - The parsed value is stored in the bfd_vma *. */ -const char *cgen_parse_operand PARAMS ((enum cgen_parse_operand_type, - const char **, int, int, - enum cgen_parse_operand_result *, - bfd_vma *)); -#endif +/* Operand index computation. */ +extern const CGEN_INSN * cgen_lookup_insn + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN * insn_, + CGEN_INSN_INT int_value_, unsigned char *bytes_value_, + int length_, CGEN_FIELDS *fields_, int alias_p_)); +extern void cgen_get_insn_operands + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN * insn_, + const CGEN_FIELDS *fields_, int *indices_)); +extern const CGEN_INSN * cgen_lookup_get_insn_operands + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *insn_, + CGEN_INSN_INT int_value_, unsigned char *bytes_value_, + int length_, int *indices_, CGEN_FIELDS *fields_)); + +/* Cover fns to bfd_get/set. */ + +extern CGEN_INSN_INT cgen_get_insn_value + PARAMS ((CGEN_CPU_DESC, unsigned char *, int)); +extern void cgen_put_insn_value + PARAMS ((CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT)); + +/* Read in a cpu description file. + ??? For future concerns, including adding instructions to the assembler/ + disassembler at run-time. */ + +extern const char * cgen_read_cpu_file + PARAMS ((CGEN_CPU_DESC, const char * filename_)); + +/* Allow signed overflow of instruction fields. */ +extern void cgen_set_signed_overflow_ok PARAMS ((CGEN_CPU_DESC)); -/* Add a register to the assembler's hash table. - This makes lets GAS parse registers for us. - ??? This isn't currently used, but it could be in the future. */ -void cgen_asm_record_register PARAMS ((char *, int)); +/* Generate an error message if a signed field in an instruction overflows. */ +extern void cgen_clear_signed_overflow_ok PARAMS ((CGEN_CPU_DESC)); -/* After CGEN_SYM (assemble_insn) is done, this is called to - output the insn and record any fixups. */ -void cgen_asm_finish_insn PARAMS ((const struct cgen_insn *, cgen_insn_t *, - unsigned int)); +/* Will an error message be generated if a signed field in an instruction overflows ? */ +extern unsigned int cgen_signed_overflow_ok_p PARAMS ((CGEN_CPU_DESC)); #endif /* CGEN_H */ diff --git a/gnu/usr.bin/binutils/include/opcode/d10v.h b/gnu/usr.bin/binutils/include/opcode/d10v.h index 33d1af40c84..7c6d32ddffa 100644 --- a/gnu/usr.bin/binutils/include/opcode/d10v.h +++ b/gnu/usr.bin/binutils/include/opcode/d10v.h @@ -1,5 +1,5 @@ /* d10v.h -- Header file for D10V opcode table - Copyright 1996 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998 Free Software Foundation, Inc. Written by Martin Hunt (hunt@cygnus.com), Cygnus Support This file is part of GDB, GAS, and the GNU binutils. @@ -148,24 +148,37 @@ extern const struct d10v_operand d10v_operands[]; /* @( */ #define OPERAND_ATPAR (0x200) -/* accumulator */ -#define OPERAND_ACC (0x400) +/* accumulator 0 */ +#define OPERAND_ACC0 (0x400) -/* flag register */ -#define OPERAND_FLAG (0x800) +/* accumulator 1 */ +#define OPERAND_ACC1 (0x800) + +/* f0 / f1 flag register */ +#define OPERAND_FFLAG (0x1000) + +/* c flag register */ +#define OPERAND_CFLAG (0x2000) /* control register */ -#define OPERAND_CONTROL (0x1000) +#define OPERAND_CONTROL (0x4000) /* predecrement mode '@-sp' */ -#define OPERAND_ATMINUS (0x2000) +#define OPERAND_ATMINUS (0x8000) /* signed number */ -#define OPERAND_SIGNED (0x4000) +#define OPERAND_SIGNED (0x10000) /* special accumulator shifts need a 4-bit number */ /* 1 <= x <= 16 */ -#define OPERAND_SHIFT (0x8000) +#define OPERAND_SHIFT (0x20000) + +/* general purpose register */ +#define OPERAND_GPR (0x40000) + +/* special imm3 values with range restricted to -2 <= imm3 <= 3 */ +/* needed for rac/rachi */ +#define RESTRICTED_NUM3 (0x80000) /* Structure to hold information about predefined registers. */ struct pd_reg diff --git a/gnu/usr.bin/binutils/include/opcode/d30v.h b/gnu/usr.bin/binutils/include/opcode/d30v.h new file mode 100644 index 00000000000..f90b7a420ce --- /dev/null +++ b/gnu/usr.bin/binutils/include/opcode/d30v.h @@ -0,0 +1,286 @@ +/* d30v.h -- Header file for D30V opcode table + Copyright (C) 1997, 2000 Free Software Foundation, Inc. + Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef D30V_H +#define D30V_H + +#define NOP 0x00F00000 + +/* Structure to hold information about predefined registers. */ +struct pd_reg +{ + char *name; /* name to recognize */ + char *pname; /* name to print for this register */ + int value; +}; + +extern const struct pd_reg pre_defined_registers[]; +int reg_name_cnt(); + +/* the number of control registers */ +#define MAX_CONTROL_REG 64 + +/* define the format specifiers */ +#define FM00 0 +#define FM01 0x80000000 +#define FM10 0x8000000000000000LL +#define FM11 0x8000000080000000LL + +/* define the opcode classes */ +#define BRA 0 +#define LOGIC 1 +#define IMEM 2 +#define IALU1 4 +#define IALU2 5 + +/* define the execution condition codes */ +#define ECC_AL 0 /* ALways (default) */ +#define ECC_TX 1 /* F0=True, F1=Don't care */ +#define ECC_FX 2 /* F0=False, F1=Don't care */ +#define ECC_XT 3 /* F0=Don't care, F1=True */ +#define ECC_XF 4 /* F0=Don't care, F1=False */ +#define ECC_TT 5 /* F0=True, F1=True */ +#define ECC_TF 6 /* F0=True, F1=False */ +#define ECC_RESERVED 7 /* reserved */ +#define ECC_MAX ECC_RESERVED + +extern const char *d30v_ecc_names[]; + +/* condition code table for CMP and CMPU */ +extern const char *d30v_cc_names[]; + +/* The opcode table is an array of struct d30v_opcode. */ +struct d30v_opcode +{ + /* The opcode name. */ + const char *name; + + /* the opcode */ + int op1; /* first part, "IALU1" for example */ + int op2; /* the rest of the opcode */ + + /* opcode format(s). These numbers correspond to entries */ + /* in the d30v_format_table */ + unsigned char format[4]; + +#define SHORT_M 1 +#define SHORT_M2 5 /* for ld2w and st2w */ +#define SHORT_A 9 +#define SHORT_B1 11 +#define SHORT_B2 12 +#define SHORT_B2r 13 +#define SHORT_B3 14 +#define SHORT_B3r 16 +#define SHORT_B3b 18 +#define SHORT_B3br 20 +#define SHORT_D1r 22 +#define SHORT_D2 24 +#define SHORT_D2r 26 +#define SHORT_D2Br 28 +#define SHORT_U 30 /* unary SHORT_A. ABS for example */ +#define SHORT_F 31 /* SHORT_A with flag registers */ +#define SHORT_AF 33 /* SHORT_A with only the first register a flag register */ +#define SHORT_T 35 /* for trap instruction */ +#define SHORT_A5 36 /* SHORT_A with a 5-bit immediate instead of 6 */ +#define SHORT_CMP 38 /* special form for CMPcc */ +#define SHORT_CMPU 40 /* special form for CMPUcc */ +#define SHORT_A1 42 /* special form of SHORT_A for MACa opcodes where a=1 */ +#define SHORT_AA 44 /* SHORT_A with the first register an accumulator */ +#define SHORT_RA 46 /* SHORT_A with the second register an accumulator */ +#define SHORT_MODINC 48 +#define SHORT_MODDEC 49 +#define SHORT_C1 50 +#define SHORT_C2 51 +#define SHORT_UF 52 +#define SHORT_A2 53 +#define SHORT_NONE 55 /* no operands */ +#define SHORT_AR 56 /* like SHORT_AA but only accept register as third parameter */ +#define LONG 57 +#define LONG_U 58 /* unary LONG */ +#define LONG_Ur 59 /* LONG pc-relative */ +#define LONG_CMP 60 /* special form for CMPcc and CMPUcc */ +#define LONG_M 61 /* Memory long for ldb, stb */ +#define LONG_M2 62 /* Memory long for ld2w, st2w */ +#define LONG_2 63 /* LONG with 2 operands; jmptnz */ +#define LONG_2r 64 /* LONG with 2 operands; bratnz */ +#define LONG_2b 65 /* LONG_2 with modifier of 3 */ +#define LONG_2br 66 /* LONG_2r with modifier of 3 */ +#define LONG_D 67 /* for DJMPI */ +#define LONG_Dr 68 /* for DBRAI */ +#define LONG_Dbr 69 /* for repeati */ + + /* the execution unit(s) used */ + int unit; +#define EITHER 0 +#define IU 1 +#define MU 2 +#define EITHER_BUT_PREFER_MU 3 + + /* this field is used to decide if two instructions */ + /* can be executed in parallel */ + long flags_used; + long flags_set; +#define FLAG_0 (1L<<0) +#define FLAG_1 (1L<<1) +#define FLAG_2 (1L<<2) +#define FLAG_3 (1L<<3) +#define FLAG_4 (1L<<4) /* S (saturation) */ +#define FLAG_5 (1L<<5) /* V (overflow) */ +#define FLAG_6 (1L<<6) /* VA (accumulated overflow) */ +#define FLAG_7 (1L<<7) /* C (carry/borrow) */ +#define FLAG_SM (1L<<8) /* SM (stack mode) */ +#define FLAG_RP (1L<<9) /* RP (repeat enable) */ +#define FLAG_CONTROL (1L<<10) /* control registers */ +#define FLAG_A0 (1L<<11) /* A0 */ +#define FLAG_A1 (1L<<12) /* A1 */ +#define FLAG_JMP (1L<<13) /* instruction is a branch */ +#define FLAG_JSR (1L<<14) /* subroutine call. must be aligned */ +#define FLAG_MEM (1L<<15) /* reads/writes memory */ +#define FLAG_NOT_WITH_ADDSUBppp (1L<<16) /* Old meaning: a 2 word 4 byter operation + New meaning: operation cannot be + combined in parallel with ADD/SUBppp. */ +#define FLAG_MUL16 (1L<<17) /* 16 bit multiply */ +#define FLAG_MUL32 (1L<<18) /* 32 bit multiply */ +#define FLAG_ADDSUBppp (1L<<19) /* ADDppp or SUBppp */ +#define FLAG_DELAY (1L<<20) /* This is a delayed branch or jump */ +#define FLAG_LKR (1L<<21) /* insn in left slot kills right slot */ +#define FLAG_CVVA (FLAG_5|FLAG_6|FLAG_7) +#define FLAG_C FLAG_7 +#define FLAG_ALL (FLAG_0 | \ + FLAG_1 | \ + FLAG_2 | \ + FLAG_3 | \ + FLAG_4 | \ + FLAG_5 | \ + FLAG_6 | \ + FLAG_7 | \ + FLAG_SM | \ + FLAG_RP | \ + FLAG_CONTROL) + + int reloc_flag; +#define RELOC_PCREL 1 +#define RELOC_ABS 2 +}; + +extern const struct d30v_opcode d30v_opcode_table[]; +extern const int d30v_num_opcodes; + +/* The operands table is an array of struct d30v_operand. */ +struct d30v_operand +{ + /* the length of the field */ + int length; + + /* The number of significant bits in the operand. */ + int bits; + + /* position relative to Ra */ + int position; + + /* syntax flags. */ + long flags; +}; +extern const struct d30v_operand d30v_operand_table[]; + +/* Values defined for the flags field of a struct d30v_operand. */ + +/* this is the destination register; it will be modified */ +/* this is used by the optimizer */ +#define OPERAND_DEST (1) + +/* number or symbol */ +#define OPERAND_NUM (2) + +/* address or label */ +#define OPERAND_ADDR (4) + +/* register */ +#define OPERAND_REG (8) + +/* postincrement + */ +#define OPERAND_PLUS (0x10) + +/* postdecrement - */ +#define OPERAND_MINUS (0x20) + +/* signed number */ +#define OPERAND_SIGNED (0x40) + +/* this operand must be shifted left by 3 */ +#define OPERAND_SHIFT (0x80) + +/* flag register */ +#define OPERAND_FLAG (0x100) + +/* control register */ +#define OPERAND_CONTROL (0x200) + +/* accumulator */ +#define OPERAND_ACC (0x400) + +/* @ */ +#define OPERAND_ATSIGN (0x800) + +/* @( */ +#define OPERAND_ATPAR (0x1000) + +/* predecrement mode '@-sp' */ +#define OPERAND_ATMINUS (0x2000) + +/* this operand changes the instruction name */ +/* for example, CPMcc, CMPUcc */ +#define OPERAND_NAME (0x4000) + +/* fake operand for mvtsys and mvfsys */ +#define OPERAND_SPECIAL (0x8000) + +/* let the optimizer know that two registers are affected */ +#define OPERAND_2REG (0x10000) + +/* This operand is pc-relative. Note that repeati can have two immediate + operands, one of which is pcrel, the other (the IMM6U one) is not. */ +#define OPERAND_PCREL (0x20000) + +/* The format table is an array of struct d30v_format. */ +struct d30v_format +{ + int form; /* SHORT_A, LONG, etc */ + int modifier; /* two bit modifier following opcode */ + unsigned char operands[5]; +}; +extern const struct d30v_format d30v_format_table[]; + + +/* an instruction is defined by an opcode and a format */ +/* for example, "add" has one opcode, but three different */ +/* formats, 2 SHORT_A forms and a LONG form. */ +struct d30v_insn +{ + struct d30v_opcode *op; /* pointer to an entry in the opcode table */ + struct d30v_format *form; /* pointer to an entry in the format table */ + int ecc; /* execution condition code */ +}; + +/* an expressionS only has one register type, so we fake it */ +/* by setting high bits to indicate type */ +#define REGISTER_MASK 0xFF + +#endif /* D30V_H */ diff --git a/gnu/usr.bin/binutils/include/opcode/i370.h b/gnu/usr.bin/binutils/include/opcode/i370.h new file mode 100644 index 00000000000..f2049e741d1 --- /dev/null +++ b/gnu/usr.bin/binutils/include/opcode/i370.h @@ -0,0 +1,265 @@ +/* i370.h -- Header file for S/390 opcode table + Copyright 1994, 95, 98, 99, 2000 Free Software Foundation, Inc. + PowerPC version written by Ian Lance Taylor, Cygnus Support + Rewritten for i370 ESA/390 support, Linas Vepstas <linas@linas.org> + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef I370_H +#define I370_H + +/* The opcode table is an array of struct i370_opcode. */ +typedef union +{ + unsigned int i[2]; + unsigned short s[4]; + unsigned char b[8]; +} i370_insn_t; + +struct i370_opcode +{ + /* The opcode name. */ + const char *name; + + /* the length of the instruction */ + char len; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + i370_insn_t opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + i370_insn_t mask; + + /* One bit flags for the opcode. These are used to indicate which + specific processors support the instructions. The defined values + are listed below. */ + unsigned long flags; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[8]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct i370_opcode i370_opcodes[]; +extern const int i370_num_opcodes; + +/* Values defined for the flags field of a struct i370_opcode. */ + +/* Opcode is defined for the original 360 architecture. */ +#define I370_OPCODE_360 (0x01) + +/* Opcode is defined for the 370 architecture. */ +#define I370_OPCODE_370 (0x02) + +/* Opcode is defined for the 370-XA architecture. */ +#define I370_OPCODE_370_XA (0x04) + +/* Opcode is defined for the ESA/370 architecture. */ +#define I370_OPCODE_ESA370 (0x08) + +/* Opcode is defined for the ESA/390 architecture. */ +#define I370_OPCODE_ESA390 (0x10) + +/* Opcode is defined for the ESA/390 w/ BFP facility. */ +#define I370_OPCODE_ESA390_BF (0x20) + +/* Opcode is defined for the ESA/390 w/ branch & set authority facility. */ +#define I370_OPCODE_ESA390_BS (0x40) + +/* Opcode is defined for the ESA/390 w/ checksum facility. */ +#define I370_OPCODE_ESA390_CK (0x80) + +/* Opcode is defined for the ESA/390 w/ compare & move extended facility. */ +#define I370_OPCODE_ESA390_CM (0x100) + +/* Opcode is defined for the ESA/390 w/ flt.pt. support extensions facility. */ +#define I370_OPCODE_ESA390_FX (0x200) + +/* Opcode is defined for the ESA/390 w/ HFP facility. */ +#define I370_OPCODE_ESA390_HX (0x400) + +/* Opcode is defined for the ESA/390 w/ immediate & relative facility. */ +#define I370_OPCODE_ESA390_IR (0x800) + +/* Opcode is defined for the ESA/390 w/ move-inverse facility. */ +#define I370_OPCODE_ESA390_MI (0x1000) + +/* Opcode is defined for the ESA/390 w/ program-call-fast facility. */ +#define I370_OPCODE_ESA390_PC (0x2000) + +/* Opcode is defined for the ESA/390 w/ perform-locked-op facility. */ +#define I370_OPCODE_ESA390_PL (0x4000) + +/* Opcode is defined for the ESA/390 w/ square-root facility. */ +#define I370_OPCODE_ESA390_QR (0x8000) + +/* Opcode is defined for the ESA/390 w/ resume-program facility. */ +#define I370_OPCODE_ESA390_RP (0x10000) + +/* Opcode is defined for the ESA/390 w/ set-address-space-fast facility. */ +#define I370_OPCODE_ESA390_SA (0x20000) + +/* Opcode is defined for the ESA/390 w/ subspace group facility. */ +#define I370_OPCODE_ESA390_SG (0x40000) + +/* Opcode is defined for the ESA/390 w/ string facility. */ +#define I370_OPCODE_ESA390_SR (0x80000) + +/* Opcode is defined for the ESA/390 w/ trap facility. */ +#define I370_OPCODE_ESA390_TR (0x100000) + +#define I370_OPCODE_ESA390_SUPERSET (0x1fffff) + + +/* The operands table is an array of struct i370_operand. */ + +struct i370_operand +{ + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + + /* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (op & ((1 << o->bits) - 1)) << o->shift; + (i is the instruction which we are filling in, o is a pointer to + this structure, and op is the opcode value; this assumes twos + complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged (most operands + can accept any value). */ + i370_insn_t (*insert) PARAMS ((i370_insn_t instruction, long op, + const char **errmsg)); + + /* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = ((i) >> o->shift) & ((1 << o->bits) - 1); + if ((o->flags & I370_OPERAND_SIGNED) != 0 + && (op & (1 << (o->bits - 1))) != 0) + op -= 1 << o->bits; + (i is the instruction, o is a pointer to this structure, and op + is the result; this assumes twos complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. */ + long (*extract) PARAMS ((i370_insn_t instruction, int *invalid)); + + /* One bit syntax flags. */ + unsigned long flags; + + /* name -- handy for debugging, otherwise pointless */ + char * name; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the i370_opcodes table. */ + +extern const struct i370_operand i370_operands[]; + +/* Values defined for the flags field of a struct i370_operand. */ + +/* This operand should be wrapped in parentheses rather than + separated from the previous by a comma. This is used for S, RS and + SS form instructions which want their operands to look like + reg,displacement(basereg) */ +#define I370_OPERAND_SBASE (0x01) + +/* This operand is a base register. It may or may not appear next + to an index register, i.e. either of the two forms + reg,displacement(basereg) + reg,displacement(index,basereg) */ +#define I370_OPERAND_BASE (0x02) + +/* This pair of operands should be wrapped in parentheses rather than + separated from the last by a comma. This is used for the RX form + instructions which want their operands to look like + reg,displacement(index,basereg) */ +#define I370_OPERAND_INDEX (0x04) + +/* This operand names a register. The disassembler uses this to print + register names with a leading 'r'. */ +#define I370_OPERAND_GPR (0x08) + +/* This operand names a floating point register. The disassembler + prints these with a leading 'f'. */ +#define I370_OPERAND_FPR (0x10) + +/* This operand is a displacement. */ +#define I370_OPERAND_RELATIVE (0x20) + +/* This operand is a length, such as that in SS form instructions. */ +#define I370_OPERAND_LENGTH (0x40) + +/* This operand is optional, and is zero if omitted. This is used for + the optional B2 field in the shift-left, shift-right instructions. The + assembler must count the number of operands remaining on the line, + and the number of operands remaining for the opcode, and decide + whether this operand is present or not. The disassembler should + print this operand out only if it is not zero. */ +#define I370_OPERAND_OPTIONAL (0x80) + + +/* Define some misc macros. We keep them with the operands table + for simplicity. The macro table is an array of struct i370_macro. */ + +struct i370_macro +{ + /* The macro name. */ + const char *name; + + /* The number of operands the macro takes. */ + unsigned int operands; + + /* One bit flags for the opcode. These are used to indicate which + specific processors support the instructions. The values are the + same as those for the struct i370_opcode flags field. */ + unsigned long flags; + + /* A format string to turn the macro into a normal instruction. + Each %N in the string is replaced with operand number N (zero + based). */ + const char *format; +}; + +extern const struct i370_macro i370_macros[]; +extern const int i370_num_macros; + + +#endif /* I370_H */ diff --git a/gnu/usr.bin/binutils/include/opcode/pj.h b/gnu/usr.bin/binutils/include/opcode/pj.h new file mode 100644 index 00000000000..8759b627e3d --- /dev/null +++ b/gnu/usr.bin/binutils/include/opcode/pj.h @@ -0,0 +1,46 @@ +/* Definitions for decoding the picoJava opcode table. + Copyright (C) 1999 Free Software Foundation, Inc. + Contributed by Steve Chamberlain of Transmeta (sac@pobox.com). + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +/* Names used to describe the type of instruction arguments, used by + the assembler and disassembler. Attributes are encoded in various fields. */ + +/* reloc size pcrel uns */ +#define O_N 0 +#define O_16 (1<<4 | 2 | (0<<6) | (0<<3)) +#define O_U16 (1<<4 | 2 | (0<<6) | (1<<3)) +#define O_R16 (2<<4 | 2 | (1<<6) | (0<<3)) +#define O_8 (3<<4 | 1 | (0<<6) | (0<<3)) +#define O_U8 (3<<4 | 1 | (0<<6) | (1<<3)) +#define O_R8 (4<<4 | 1 | (0<<6) | (0<<3)) +#define O_R32 (5<<4 | 4 | (1<<6) | (0<<3)) +#define O_32 (6<<4 | 4 | (0<<6) | (0<<3)) + +#define ASIZE(x) ((x) & 0x7) +#define PCREL(x) (!!((x) & (1<<6))) +#define UNS(x) (!!((x) & (1<<3))) + + +typedef struct +{ + short opcode; + short opcode_next; + char len; + unsigned char arg[2]; + const char *name; +} pj_opc_info_t; diff --git a/gnu/usr.bin/binutils/include/opcode/tic30.h b/gnu/usr.bin/binutils/include/opcode/tic30.h new file mode 100644 index 00000000000..a7002759118 --- /dev/null +++ b/gnu/usr.bin/binutils/include/opcode/tic30.h @@ -0,0 +1,691 @@ +/* tic30.h -- Header file for TI TMS320C30 opcode table + Copyright 1998 Free Software Foundation, Inc. + Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ + +/* FIXME: The opcode table should be in opcodes/tic30-opc.c, not in a + header file. */ + +#ifndef _TMS320_H_ +#define _TMS320_H_ + +struct _register +{ + char *name; + unsigned char opcode; + unsigned char regtype; +}; + +typedef struct _register reg; + +#define REG_Rn 0x01 +#define REG_ARn 0x02 +#define REG_DP 0x03 +#define REG_OTHER 0x04 + +static const reg tic30_regtab[] = { + { "r0", 0x00, REG_Rn }, + { "r1", 0x01, REG_Rn }, + { "r2", 0x02, REG_Rn }, + { "r3", 0x03, REG_Rn }, + { "r4", 0x04, REG_Rn }, + { "r5", 0x05, REG_Rn }, + { "r6", 0x06, REG_Rn }, + { "r7", 0x07, REG_Rn }, + { "ar0",0x08, REG_ARn }, + { "ar1",0x09, REG_ARn }, + { "ar2",0x0A, REG_ARn }, + { "ar3",0x0B, REG_ARn }, + { "ar4",0x0C, REG_ARn }, + { "ar5",0x0D, REG_ARn }, + { "ar6",0x0E, REG_ARn }, + { "ar7",0x0F, REG_ARn }, + { "dp", 0x10, REG_DP }, + { "ir0",0x11, REG_OTHER }, + { "ir1",0x12, REG_OTHER }, + { "bk", 0x13, REG_OTHER }, + { "sp", 0x14, REG_OTHER }, + { "st", 0x15, REG_OTHER }, + { "ie", 0x16, REG_OTHER }, + { "if", 0x17, REG_OTHER }, + { "iof",0x18, REG_OTHER }, + { "rs", 0x19, REG_OTHER }, + { "re", 0x1A, REG_OTHER }, + { "rc", 0x1B, REG_OTHER }, + { "R0", 0x00, REG_Rn }, + { "R1", 0x01, REG_Rn }, + { "R2", 0x02, REG_Rn }, + { "R3", 0x03, REG_Rn }, + { "R4", 0x04, REG_Rn }, + { "R5", 0x05, REG_Rn }, + { "R6", 0x06, REG_Rn }, + { "R7", 0x07, REG_Rn }, + { "AR0",0x08, REG_ARn }, + { "AR1",0x09, REG_ARn }, + { "AR2",0x0A, REG_ARn }, + { "AR3",0x0B, REG_ARn }, + { "AR4",0x0C, REG_ARn }, + { "AR5",0x0D, REG_ARn }, + { "AR6",0x0E, REG_ARn }, + { "AR7",0x0F, REG_ARn }, + { "DP", 0x10, REG_DP }, + { "IR0",0x11, REG_OTHER }, + { "IR1",0x12, REG_OTHER }, + { "BK", 0x13, REG_OTHER }, + { "SP", 0x14, REG_OTHER }, + { "ST", 0x15, REG_OTHER }, + { "IE", 0x16, REG_OTHER }, + { "IF", 0x17, REG_OTHER }, + { "IOF",0x18, REG_OTHER }, + { "RS", 0x19, REG_OTHER }, + { "RE", 0x1A, REG_OTHER }, + { "RC", 0x1B, REG_OTHER }, + { "", 0, 0 } +}; + +static const reg *const tic30_regtab_end + = tic30_regtab + sizeof(tic30_regtab)/sizeof(tic30_regtab[0]); + +/* Indirect Addressing Modes Modification Fields */ +/* Indirect Addressing with Displacement */ +#define PreDisp_Add 0x00 +#define PreDisp_Sub 0x01 +#define PreDisp_Add_Mod 0x02 +#define PreDisp_Sub_Mod 0x03 +#define PostDisp_Add_Mod 0x04 +#define PostDisp_Sub_Mod 0x05 +#define PostDisp_Add_Circ 0x06 +#define PostDisp_Sub_Circ 0x07 +/* Indirect Addressing with Index Register IR0 */ +#define PreIR0_Add 0x08 +#define PreIR0_Sub 0x09 +#define PreIR0_Add_Mod 0x0A +#define PreIR0_Sub_Mod 0x0B +#define PostIR0_Add_Mod 0x0C +#define PostIR0_Sub_Mod 0x0D +#define PostIR0_Add_Circ 0x0E +#define PostIR0_Sub_Circ 0x0F +/* Indirect Addressing with Index Register IR1 */ +#define PreIR1_Add 0x10 +#define PreIR1_Sub 0x11 +#define PreIR1_Add_Mod 0x12 +#define PreIR1_Sub_Mod 0x13 +#define PostIR1_Add_Mod 0x14 +#define PostIR1_Sub_Mod 0x15 +#define PostIR1_Add_Circ 0x16 +#define PostIR1_Sub_Circ 0x17 +/* Indirect Addressing (Special Cases) */ +#define IndirectOnly 0x18 +#define PostIR0_Add_BitRev 0x19 + +typedef struct { + char *syntax; + unsigned char modfield; + unsigned char displacement; +} ind_addr_type; + +#define IMPLIED_DISP 0x01 +#define DISP_REQUIRED 0x02 +#define NO_DISP 0x03 + +static const ind_addr_type tic30_indaddr_tab[] = { + { "*+ar", PreDisp_Add, IMPLIED_DISP }, + { "*-ar", PreDisp_Sub, IMPLIED_DISP }, + { "*++ar", PreDisp_Add_Mod, IMPLIED_DISP }, + { "*--ar", PreDisp_Sub_Mod, IMPLIED_DISP }, + { "*ar++", PostDisp_Add_Mod, IMPLIED_DISP }, + { "*ar--", PostDisp_Sub_Mod, IMPLIED_DISP }, + { "*ar++%", PostDisp_Add_Circ, IMPLIED_DISP }, + { "*ar--%", PostDisp_Sub_Circ, IMPLIED_DISP }, + { "*+ar()", PreDisp_Add, DISP_REQUIRED }, + { "*-ar()", PreDisp_Sub, DISP_REQUIRED }, + { "*++ar()", PreDisp_Add_Mod, DISP_REQUIRED }, + { "*--ar()", PreDisp_Sub_Mod, DISP_REQUIRED }, + { "*ar++()", PostDisp_Add_Mod, DISP_REQUIRED }, + { "*ar--()", PostDisp_Sub_Mod, DISP_REQUIRED }, + { "*ar++()%", PostDisp_Add_Circ, DISP_REQUIRED }, + { "*ar--()%", PostDisp_Sub_Circ, DISP_REQUIRED }, + { "*+ar(ir0)", PreIR0_Add, NO_DISP }, + { "*-ar(ir0)", PreIR0_Sub, NO_DISP }, + { "*++ar(ir0)", PreIR0_Add_Mod, NO_DISP }, + { "*--ar(ir0)", PreIR0_Sub_Mod, NO_DISP }, + { "*ar++(ir0)", PostIR0_Add_Mod, NO_DISP }, + { "*ar--(ir0)", PostIR0_Sub_Mod, NO_DISP }, + { "*ar++(ir0)%",PostIR0_Add_Circ, NO_DISP }, + { "*ar--(ir0)%",PostIR0_Sub_Circ, NO_DISP }, + { "*+ar(ir1)", PreIR1_Add, NO_DISP }, + { "*-ar(ir1)", PreIR1_Sub, NO_DISP }, + { "*++ar(ir1)", PreIR1_Add_Mod, NO_DISP }, + { "*--ar(ir1)", PreIR1_Sub_Mod, NO_DISP }, + { "*ar++(ir1)", PostIR1_Add_Mod, NO_DISP }, + { "*ar--(ir1)", PostIR1_Sub_Mod, NO_DISP }, + { "*ar++(ir1)%",PostIR1_Add_Circ, NO_DISP }, + { "*ar--(ir1)%",PostIR1_Sub_Circ, NO_DISP }, + { "*ar", IndirectOnly, NO_DISP }, + { "*ar++(ir0)b",PostIR0_Add_BitRev, NO_DISP }, + { "", 0,0 } +}; + +static const ind_addr_type *const tic30_indaddrtab_end + = tic30_indaddr_tab + sizeof(tic30_indaddr_tab)/sizeof(tic30_indaddr_tab[0]); + +/* Possible operand types */ +/* Register types */ +#define Rn 0x0001 +#define ARn 0x0002 +#define DPReg 0x0004 +#define OtherReg 0x0008 +/* Addressing mode types */ +#define Direct 0x0010 +#define Indirect 0x0020 +#define Imm16 0x0040 +#define Disp 0x0080 +#define Imm24 0x0100 +#define Abs24 0x0200 +/* 3 operand addressing mode types */ +#define op3T1 0x0400 +#define op3T2 0x0800 +/* Interrupt vector */ +#define IVector 0x1000 +/* Not required */ +#define NotReq 0x2000 + +#define GAddr1 Rn | Direct | Indirect | Imm16 +#define GAddr2 GAddr1 | AllReg +#define TAddr1 op3T1 | Rn | Indirect +#define TAddr2 op3T2 | Rn | Indirect +#define Reg Rn | ARn +#define AllReg Reg | DPReg | OtherReg + +typedef struct _template +{ + char *name; + unsigned int operands; /* how many operands */ + unsigned int base_opcode; /* base_opcode is the fundamental opcode byte */ + /* the bits in opcode_modifier are used to generate the final opcode from + the base_opcode. These bits also are used to detect alternate forms of + the same instruction */ + unsigned int opcode_modifier; + + /* opcode_modifier bits: */ +#define AddressMode 0x00600000 +#define PCRel 0x02000000 +#define StackOp 0x001F0000 +#define Rotate StackOp + + /* operand_types[i] describes the type of operand i. This is made + by OR'ing together all of the possible type masks. (e.g. + 'operand_types[i] = Reg|Imm' specifies that operand i can be + either a register or an immediate operand */ + unsigned int operand_types[3]; + /* This defines the number type of an immediate argument to an instruction. */ + int imm_arg_type; +#define Imm_None 0 +#define Imm_Float 1 +#define Imm_SInt 2 +#define Imm_UInt 3 +} +template; + +static const template tic30_optab[] = { + { "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "absi" ,2,0x00800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "addc" ,2,0x01000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "addc3" ,3,0x20000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "addf" ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, + { "addi" ,2,0x02000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "addi3" ,3,0x21000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "and" ,2,0x02800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "and3" ,3,0x21800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "andn" ,2,0x03000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "andn3" ,3,0x22000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "ash" ,2,0x03800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ash3" ,3,0x22800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bls" ,1,0x68020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bhi" ,1,0x68030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bhs" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "beq" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bne" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blt" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "ble" ,1,0x68080000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bgt" ,1,0x68090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bge" ,1,0x680A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bz" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnz" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bp" ,1,0x68090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bn" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnn" ,1,0x680A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnv" ,1,0x680C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bv" ,1,0x680D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnuf" ,1,0x680E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "buf" ,1,0x680F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnc" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bc" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnlv" ,1,0x68100000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blv" ,1,0x68110000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnluf" ,1,0x68120000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bluf" ,1,0x68130000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bzuf" ,1,0x68140000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bd" ,1,0x68200000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bud" ,1,0x68200000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blod" ,1,0x68210000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blsd" ,1,0x68220000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bhid" ,1,0x68230000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bhsd" ,1,0x68240000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "beqd" ,1,0x68250000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bned" ,1,0x68260000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bltd" ,1,0x68270000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bled" ,1,0x68280000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bgtd" ,1,0x68290000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bged" ,1,0x682A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bzd" ,1,0x68250000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnzd" ,1,0x68260000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bpd" ,1,0x68290000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnd" ,1,0x68270000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnnd" ,1,0x682A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnvd" ,1,0x682C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bvd" ,1,0x682D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnufd" ,1,0x682E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bufd" ,1,0x682F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bncd" ,1,0x68240000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bcd" ,1,0x68210000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnlvd" ,1,0x68300000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blvd" ,1,0x68310000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnlufd" ,1,0x68320000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blufd" ,1,0x68330000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bzufd" ,1,0x68340000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "br" ,1,0x60000000,0, { Imm24, 0, 0 }, Imm_UInt }, + { "brd" ,1,0x61000000,0, { Imm24, 0, 0 }, Imm_UInt }, + { "call" ,1,0x62000000,0, { Imm24, 0, 0 }, Imm_UInt }, + { "callu" ,1,0x70000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calllo" ,1,0x70010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callls" ,1,0x70020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callhi" ,1,0x70030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callhs" ,1,0x70040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calleq" ,1,0x70050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callne" ,1,0x70060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calllt" ,1,0x70070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callle" ,1,0x70080000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callgt" ,1,0x70090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callge" ,1,0x700A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callz" ,1,0x70050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnz" ,1,0x70060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callp" ,1,0x70090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calln" ,1,0x70070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnn" ,1,0x700A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnv" ,1,0x700C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callv" ,1,0x700D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnuf",1,0x700E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calluf" ,1,0x700F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnc" ,1,0x70040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callc" ,1,0x70010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnlv",1,0x70100000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calllv" ,1,0x70110000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnluf",1,0x70120000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callluf",1,0x70130000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callzuf",1,0x70140000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "cmpf" ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "cmpf3" ,2,0x23000000,AddressMode, { TAddr1, TAddr2, 0 }, Imm_None }, + { "cmpi" ,2,0x04800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "cmpi3" ,2,0x23800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None }, + { "db" ,2,0x6C000000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbu" ,2,0x6C000000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblo" ,2,0x6C010000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbls" ,2,0x6C020000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbhi" ,2,0x6C030000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbhs" ,2,0x6C040000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbeq" ,2,0x6C050000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbne" ,2,0x6C060000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblt" ,2,0x6C070000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dble" ,2,0x6C080000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbgt" ,2,0x6C090000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbge" ,2,0x6C0A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbz" ,2,0x6C050000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnz" ,2,0x6C060000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbp" ,2,0x6C090000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbn" ,2,0x6C070000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnn" ,2,0x6C0A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnv" ,2,0x6C0C0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbv" ,2,0x6C0D0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnuf" ,2,0x6C0E0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbuf" ,2,0x6C0F0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnc" ,2,0x6C040000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbc" ,2,0x6C010000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnlv" ,2,0x6C100000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblv" ,2,0x6C110000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnluf" ,2,0x6C120000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbluf" ,2,0x6C130000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbzuf" ,2,0x6C140000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbd" ,2,0x6C200000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbud" ,2,0x6C200000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblod" ,2,0x6C210000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblsd" ,2,0x6C220000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbhid" ,2,0x6C230000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbhsd" ,2,0x6C240000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbeqd" ,2,0x6C250000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbned" ,2,0x6C260000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbltd" ,2,0x6C270000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbled" ,2,0x6C280000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbgtd" ,2,0x6C290000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbged" ,2,0x6C2A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbzd" ,2,0x6C250000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnzd" ,2,0x6C260000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbpd" ,2,0x6C290000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnd" ,2,0x6C270000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnnd" ,2,0x6C2A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnvd" ,2,0x6C2C0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbvd" ,2,0x6C2D0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnufd" ,2,0x6C2E0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbufd" ,2,0x6C2F0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbncd" ,2,0x6C240000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbcd" ,2,0x6C210000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnlvd" ,2,0x6C300000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblvd" ,2,0x6C310000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnlufd",2,0x6C320000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblufd" ,2,0x6C330000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbzufd" ,2,0x6C340000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "fix" ,2,0x05000000,AddressMode, { GAddr1, AllReg, 0 }, Imm_Float }, + { "float" ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt }, + { "iack" ,1,0x1B000000,AddressMode, { Direct|Indirect, 0, 0 }, Imm_None }, + { "idle" ,0,0x06000000,0, { 0, 0, 0 }, Imm_None }, + { "idle2" ,0,0x06000001,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ + { "lde" ,2,0x06800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldf" ,2,0x07000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfu" ,2,0x40000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldflo" ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfls" ,2,0x41000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfhi" ,2,0x41800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfhs" ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfeq" ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfne" ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldflt" ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfle" ,2,0x44000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfgt" ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfge" ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfz" ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnz" ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfp" ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfn" ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnn" ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnv" ,2,0x46000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfv" ,2,0x46800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnuf" ,2,0x47000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfuf" ,2,0x47800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnc" ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfc" ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnlv" ,2,0x48000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldflv" ,2,0x48800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnluf",2,0x49000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfluf" ,2,0x49800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfzuf" ,2,0x4A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfi" ,2,0x07800000,AddressMode, { Direct|Indirect, Rn, 0 }, Imm_None }, + { "ldi" ,2,0x08000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiu" ,2,0x50000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldilo" ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldils" ,2,0x51000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldihi" ,2,0x51800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldihs" ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldieq" ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldine" ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldilt" ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldile" ,2,0x54000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldigt" ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldige" ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiz" ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinz" ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldip" ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldin" ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinn" ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinv" ,2,0x56000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiv" ,2,0x56800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinuf" ,2,0x57000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiuf" ,2,0x57800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinc" ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldic" ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinlv" ,2,0x58000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldilv" ,2,0x58800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinluf",2,0x59000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiluf" ,2,0x59800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldizuf" ,2,0x5A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldii" ,2,0x08800000,AddressMode, { Direct|Indirect, AllReg, 0 }, Imm_None }, + { "ldm" ,2,0x09000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldp" ,2,0x08700000,0, { Abs24|Direct, DPReg|NotReq, 0 }, Imm_UInt }, + { "lopower",0,0x10800001,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ + { "lsh" ,2,0x09800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "lsh3" ,3,0x24000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "maxspeed",0,0x10800000,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ + { "mpyf" ,2,0x0A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "mpyf3" ,3,0x24800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, + { "mpyi" ,2,0x0A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "mpyi3" ,3,0x25000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "negb" ,2,0x0B000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "negf" ,2,0x0B800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "negi" ,2,0x0C000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "nop" ,1,0x0C800000,AddressMode, { AllReg|Indirect|NotReq, 0, 0 }, Imm_None }, + { "norm" ,2,0x0D000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, /*Check another source*/ + { "not" ,2,0x0D800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "or" ,2,0x10000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "or3" ,3,0x25800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "pop" ,1,0x0E200000,StackOp, { AllReg, 0, 0 }, Imm_None }, + { "popf" ,1,0x0EA00000,StackOp, { Rn, 0, 0 }, Imm_None }, + { "push" ,1,0x0F200000,StackOp, { AllReg, 0, 0 }, Imm_None }, + { "pushf" ,1,0x0FA00000,StackOp, { Rn, 0, 0 }, Imm_None }, + { "reti" ,0,0x78000000,0, { 0, 0, 0 }, Imm_None }, + { "retiu" ,0,0x78000000,0, { 0, 0, 0 }, Imm_None }, + { "retilo" ,0,0x78010000,0, { 0, 0, 0 }, Imm_None }, + { "retils" ,0,0x78020000,0, { 0, 0, 0 }, Imm_None }, + { "retihi" ,0,0x78030000,0, { 0, 0, 0 }, Imm_None }, + { "retihs" ,0,0x78040000,0, { 0, 0, 0 }, Imm_None }, + { "retieq" ,0,0x78050000,0, { 0, 0, 0 }, Imm_None }, + { "retine" ,0,0x78060000,0, { 0, 0, 0 }, Imm_None }, + { "retilt" ,0,0x78070000,0, { 0, 0, 0 }, Imm_None }, + { "retile" ,0,0x78080000,0, { 0, 0, 0 }, Imm_None }, + { "retigt" ,0,0x78090000,0, { 0, 0, 0 }, Imm_None }, + { "retige" ,0,0x780A0000,0, { 0, 0, 0 }, Imm_None }, + { "retiz" ,0,0x78050000,0, { 0, 0, 0 }, Imm_None }, + { "retinz" ,0,0x78060000,0, { 0, 0, 0 }, Imm_None }, + { "retip" ,0,0x78090000,0, { 0, 0, 0 }, Imm_None }, + { "retin" ,0,0x78070000,0, { 0, 0, 0 }, Imm_None }, + { "retinn" ,0,0x780A0000,0, { 0, 0, 0 }, Imm_None }, + { "retinv" ,0,0x780C0000,0, { 0, 0, 0 }, Imm_None }, + { "retiv" ,0,0x780D0000,0, { 0, 0, 0 }, Imm_None }, + { "retinuf",0,0x780E0000,0, { 0, 0, 0 }, Imm_None }, + { "retiuf" ,0,0x780F0000,0, { 0, 0, 0 }, Imm_None }, + { "retinc" ,0,0x78040000,0, { 0, 0, 0 }, Imm_None }, + { "retic" ,0,0x78010000,0, { 0, 0, 0 }, Imm_None }, + { "retinlv",0,0x78100000,0, { 0, 0, 0 }, Imm_None }, + { "retilv" ,0,0x78110000,0, { 0, 0, 0 }, Imm_None }, + { "retinluf",0,0x78120000,0, { 0, 0, 0 }, Imm_None }, + { "retiluf",0,0x78130000,0, { 0, 0, 0 }, Imm_None }, + { "retizuf",0,0x78140000,0, { 0, 0, 0 }, Imm_None }, + { "rets" ,0,0x78800000,0, { 0, 0, 0 }, Imm_None }, + { "retsu" ,0,0x78800000,0, { 0, 0, 0 }, Imm_None }, + { "retslo" ,0,0x78810000,0, { 0, 0, 0 }, Imm_None }, + { "retsls" ,0,0x78820000,0, { 0, 0, 0 }, Imm_None }, + { "retshi" ,0,0x78830000,0, { 0, 0, 0 }, Imm_None }, + { "retshs" ,0,0x78840000,0, { 0, 0, 0 }, Imm_None }, + { "retseq" ,0,0x78850000,0, { 0, 0, 0 }, Imm_None }, + { "retsne" ,0,0x78860000,0, { 0, 0, 0 }, Imm_None }, + { "retslt" ,0,0x78870000,0, { 0, 0, 0 }, Imm_None }, + { "retsle" ,0,0x78880000,0, { 0, 0, 0 }, Imm_None }, + { "retsgt" ,0,0x78890000,0, { 0, 0, 0 }, Imm_None }, + { "retsge" ,0,0x788A0000,0, { 0, 0, 0 }, Imm_None }, + { "retsz" ,0,0x78850000,0, { 0, 0, 0 }, Imm_None }, + { "retsnz" ,0,0x78860000,0, { 0, 0, 0 }, Imm_None }, + { "retsp" ,0,0x78890000,0, { 0, 0, 0 }, Imm_None }, + { "retsn" ,0,0x78870000,0, { 0, 0, 0 }, Imm_None }, + { "retsnn" ,0,0x788A0000,0, { 0, 0, 0 }, Imm_None }, + { "retsnv" ,0,0x788C0000,0, { 0, 0, 0 }, Imm_None }, + { "retsv" ,0,0x788D0000,0, { 0, 0, 0 }, Imm_None }, + { "retsnuf",0,0x788E0000,0, { 0, 0, 0 }, Imm_None }, + { "retsuf" ,0,0x788F0000,0, { 0, 0, 0 }, Imm_None }, + { "retsnc" ,0,0x78840000,0, { 0, 0, 0 }, Imm_None }, + { "retsc" ,0,0x78810000,0, { 0, 0, 0 }, Imm_None }, + { "retsnlv",0,0x78900000,0, { 0, 0, 0 }, Imm_None }, + { "retslv" ,0,0x78910000,0, { 0, 0, 0 }, Imm_None }, + { "retsnluf",0,0x78920000,0, { 0, 0, 0 }, Imm_None }, + { "retsluf",0,0x78930000,0, { 0, 0, 0 }, Imm_None }, + { "retszuf",0,0x78940000,0, { 0, 0, 0 }, Imm_None }, + { "rnd" ,2,0x11000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "rol" ,1,0x11E00001,Rotate, { AllReg, 0, 0 }, Imm_None }, + { "rolc" ,1,0x12600001,Rotate, { AllReg, 0, 0 }, Imm_None }, + { "ror" ,1,0x12E0FFFF,Rotate, { AllReg, 0, 0 }, Imm_None }, + { "rorc" ,1,0x1360FFFF,Rotate, { AllReg, 0, 0 }, Imm_None }, + { "rptb" ,1,0x64000000,0, { Imm24, 0, 0 }, Imm_UInt }, + { "rpts" ,1,0x139B0000,AddressMode, { GAddr2, 0, 0 }, Imm_UInt }, + { "sigi" ,0,0x16000000,0, { 0, 0, 0 }, Imm_None }, + { "stf" ,2,0x14000000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float }, + { "stfi" ,2,0x14800000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float }, + { "sti" ,2,0x15000000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt }, + { "stii" ,2,0x15800000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt }, + { "subb" ,2,0x16800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "subb3" ,3,0x26000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "subc" ,2,0x17000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "subf" ,2,0x17800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "subf3" ,3,0x26800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, + { "subi" ,2,0x18000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "subi3" ,3,0x27000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "subrb" ,2,0x18800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "subrf" ,2,0x19000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "subri" ,2,0x19800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "swi" ,0,0x66000000,0, { 0, 0, 0 }, Imm_None }, + { "trap" ,1,0x74800020,0, { IVector, 0, 0 }, Imm_None }, + { "trapu" ,1,0x74800020,0, { IVector, 0, 0 }, Imm_None }, + { "traplo" ,1,0x74810020,0, { IVector, 0, 0 }, Imm_None }, + { "trapls" ,1,0x74820020,0, { IVector, 0, 0 }, Imm_None }, + { "traphi" ,1,0x74830020,0, { IVector, 0, 0 }, Imm_None }, + { "traphs" ,1,0x74840020,0, { IVector, 0, 0 }, Imm_None }, + { "trapeq" ,1,0x74850020,0, { IVector, 0, 0 }, Imm_None }, + { "trapne" ,1,0x74860020,0, { IVector, 0, 0 }, Imm_None }, + { "traplt" ,1,0x74870020,0, { IVector, 0, 0 }, Imm_None }, + { "traple" ,1,0x74880020,0, { IVector, 0, 0 }, Imm_None }, + { "trapgt" ,1,0x74890020,0, { IVector, 0, 0 }, Imm_None }, + { "trapge" ,1,0x748A0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapz" ,1,0x74850020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnz" ,1,0x74860020,0, { IVector, 0, 0 }, Imm_None }, + { "trapp" ,1,0x74890020,0, { IVector, 0, 0 }, Imm_None }, + { "trapn" ,1,0x74870020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnn" ,1,0x748A0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnv" ,1,0x748C0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapv" ,1,0x748D0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnuf",1,0x748E0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapuf" ,1,0x748F0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnc" ,1,0x74840020,0, { IVector, 0, 0 }, Imm_None }, + { "trapc" ,1,0x74810020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnlv",1,0x74900020,0, { IVector, 0, 0 }, Imm_None }, + { "traplv" ,1,0x74910020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnluf",1,0x74920020,0, { IVector, 0, 0 }, Imm_None }, + { "trapluf",1,0x74930020,0, { IVector, 0, 0 }, Imm_None }, + { "trapzuf",1,0x74940020,0, { IVector, 0, 0 }, Imm_None }, + { "tstb" ,2,0x1A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "tstb3" ,2,0x27800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None }, + { "xor" ,2,0x1A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "xor3" ,3,0x28000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "" ,0,0x00000000,0, { 0, 0, 0 }, 0 } +}; + +static const template *const tic30_optab_end = + tic30_optab + sizeof(tic30_optab)/sizeof(tic30_optab[0]); + +typedef struct { + char *name; + unsigned int operands_1; + unsigned int operands_2; + unsigned int base_opcode; + unsigned int operand_types[2][3]; + /* Which operand fits into which part of the final opcode word. */ + int oporder; +} partemplate; + +/* oporder defines - not very descriptive. */ +#define OO_4op1 0 +#define OO_4op2 1 +#define OO_4op3 2 +#define OO_5op1 3 +#define OO_5op2 4 +#define OO_PField 5 + +static const partemplate tic30_paroptab[] = { + { "q_absf_stf", 2,2,0xC8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_absi_sti", 2,2,0xCA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_addf3_stf", 3,2,0xCC000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_addi3_sti", 3,2,0xCE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_and3_sti", 3,2,0xD0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_ash3_sti", 3,2,0xD2000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, + OO_5op2 }, + { "q_fix_sti", 2,2,0xD4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_float_stf", 2,2,0xD6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_ldf_ldf", 2,2,0xC4000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } }, + OO_4op2 }, + { "q_ldf_stf", 2,2,0xD8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_ldi_ldi", 2,2,0xC6000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } }, + OO_4op2 }, + { "q_ldi_sti", 2,2,0xDA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_lsh3_sti", 3,2,0xDC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, + OO_5op2 }, + { "q_mpyf3_addf3",3,3,0x80000000, { { Rn | Indirect, Rn | Indirect, Rn }, + { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, + { "q_mpyf3_stf", 3,2,0xDE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_mpyf3_subf3",3,3,0x84000000, { { Rn | Indirect, Rn | Indirect, Rn }, + { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, + { "q_mpyi3_addi3",3,3,0x88000000, { { Rn | Indirect, Rn | Indirect, Rn }, + { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, + { "q_mpyi3_sti", 3,2,0xE0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_mpyi3_subi3",3,3,0x8C000000, { { Rn | Indirect, Rn | Indirect, Rn }, + { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, + { "q_negf_stf", 2,2,0xE2000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_negi_sti", 2,2,0xE4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_not_sti", 2,2,0xE6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_or3_sti", 3,2,0xE8000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_stf_stf", 2,2,0xC0000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } }, + OO_4op3 }, + { "q_sti_sti", 2,2,0xC2000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } }, + OO_4op3 }, + { "q_subf3_stf", 3,2,0xEA000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, + OO_5op2 }, + { "q_subi3_sti", 3,2,0xEC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, + OO_5op2 }, + { "q_xor3_sti", 3,2,0xEE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "", 0,0,0x00000000, { { 0, 0, 0 }, { 0, 0, 0 } }, 0 } +}; + +static const partemplate *const tic30_paroptab_end = + tic30_paroptab + sizeof(tic30_paroptab)/sizeof(tic30_paroptab[0]); + +#endif diff --git a/gnu/usr.bin/binutils/include/opcode/tic80.h b/gnu/usr.bin/binutils/include/opcode/tic80.h new file mode 100644 index 00000000000..b99bc30b818 --- /dev/null +++ b/gnu/usr.bin/binutils/include/opcode/tic80.h @@ -0,0 +1,277 @@ +/* tic80.h -- Header file for TI TMS320C80 (MV) opcode table + Copyright 1996, 1997, 1999 Free Software Foundation, Inc. + Written by Fred Fish (fnf@cygnus.com), Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef TIC80_H +#define TIC80_H + +/* The opcode table is an array of struct tic80_opcode. */ + +struct tic80_opcode +{ + /* The opcode name. */ + + const char *name; + + /* The opcode itself. Those bits which will be filled in with operands + are zeroes. */ + + unsigned long opcode; + + /* The opcode mask. This is used by the disassembler. This is a mask + containing ones indicating those bits which must match the opcode + field, and zeroes indicating those bits which need not match (and are + presumably filled in by operands). */ + + unsigned long mask; + + /* Special purpose flags for this opcode. */ + + unsigned char flags; + + /* An array of operand codes. Each code is an index into the operand + table. They appear in the order which the operands must appear in + assembly code, and are terminated by a zero. FIXME: Adjust size to + match actual requirements when TIc80 support is complete */ + + unsigned char operands[8]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise in + the order in which the disassembler should consider instructions. + FIXME: This isn't currently true. */ + +extern const struct tic80_opcode tic80_opcodes[]; +extern const int tic80_num_opcodes; + + +/* The operands table is an array of struct tic80_operand. */ + +struct tic80_operand +{ + /* The number of bits in the operand. */ + + int bits; + + /* How far the operand is left shifted in the instruction. */ + + int shift; + + /* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (op & ((1 << o->bits) - 1)) << o->shift; + (i is the instruction which we are filling in, o is a pointer to + this structure, and op is the opcode value; this assumes twos + complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged (most operands + can accept any value). */ + + unsigned long (*insert) PARAMS ((unsigned long instruction, long op, + const char **errmsg)); + + /* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = ((i) >> o->shift) & ((1 << o->bits) - 1); + if ((o->flags & TIC80_OPERAND_SIGNED) != 0 + && (op & (1 << (o->bits - 1))) != 0) + op -= 1 << o->bits; + (i is the instruction, o is a pointer to this structure, and op + is the result; this assumes twos complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. */ + + long (*extract) PARAMS ((unsigned long instruction, int *invalid)); + + /* One bit syntax flags. */ + + unsigned long flags; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the tic80_opcodes table. */ + +extern const struct tic80_operand tic80_operands[]; + + +/* Values defined for the flags field of a struct tic80_operand. + + Note that flags for all predefined symbols, such as the general purpose + registers (ex: r10), control registers (ex: FPST), condition codes (ex: + eq0.b), bit numbers (ex: gt.b), etc are large enough that they can be + or'd into an int where the lower bits contain the actual numeric value + that correponds to this predefined symbol. This way a single int can + contain both the value of the symbol and it's type. + */ + +/* This operand must be an even register number. Floating point numbers + for example are stored in even/odd register pairs. */ + +#define TIC80_OPERAND_EVEN (1 << 0) + +/* This operand must be an odd register number and must be one greater than + the register number of the previous operand. I.E. the second register in + an even/odd register pair. */ + +#define TIC80_OPERAND_ODD (1 << 1) + +/* This operand takes signed values. */ + +#define TIC80_OPERAND_SIGNED (1 << 2) + +/* This operand may be either a predefined constant name or a numeric value. + An example would be a condition code like "eq0.b" which has the numeric + value 0x2. */ + +#define TIC80_OPERAND_NUM (1 << 3) + +/* This operand should be wrapped in parentheses rather than separated + from the previous one by a comma. This is used for various + instructions, like the load and store instructions, which want + their operands to look like "displacement(reg)" */ + +#define TIC80_OPERAND_PARENS (1 << 4) + +/* This operand is a PC relative branch offset. The disassembler prints + these symbolically if possible. Note that the offsets are taken as word + offsets. */ + +#define TIC80_OPERAND_PCREL (1 << 5) + +/* This flag is a hint to the disassembler for using hex as the prefered + printing format, even for small positive or negative immediate values. + Normally values in the range -999 to 999 are printed as signed decimal + values and other values are printed in hex. */ + +#define TIC80_OPERAND_BITFIELD (1 << 6) + +/* This operand may have a ":m" modifier specified by bit 17 in a short + immediate form instruction. */ + +#define TIC80_OPERAND_M_SI (1 << 7) + +/* This operand may have a ":m" modifier specified by bit 15 in a long + immediate or register form instruction. */ + +#define TIC80_OPERAND_M_LI (1 << 8) + +/* This operand may have a ":s" modifier specified in bit 11 in a long + immediate or register form instruction. */ + +#define TIC80_OPERAND_SCALED (1 << 9) + +/* This operand is a floating point value */ + +#define TIC80_OPERAND_FLOAT (1 << 10) + +/* This operand is an byte offset from a base relocation. The lower + two bits of the final relocated address are ignored when the value is + written to the program counter. */ + +#define TIC80_OPERAND_BASEREL (1 << 11) + +/* This operand is an "endmask" field for a shift instruction. + It is treated special in that it can have values of 0-32, + where 0 and 32 result in the same instruction. The assembler + must be able to accept both endmask values. This disassembler + has no way of knowing from the instruction which value was + given at assembly time, so it just uses '0'. */ + +#define TIC80_OPERAND_ENDMASK (1 << 12) + +/* This operand is one of the 32 general purpose registers. + The disassembler prints these with a leading 'r'. */ + +#define TIC80_OPERAND_GPR (1 << 27) + +/* This operand is a floating point accumulator register. + The disassembler prints these with a leading 'a'. */ + +#define TIC80_OPERAND_FPA ( 1 << 28) + +/* This operand is a control register number, either numeric or + symbolic (like "EIF", "EPC", etc). + The disassembler prints these symbolically. */ + +#define TIC80_OPERAND_CR (1 << 29) + +/* This operand is a condition code, either numeric or + symbolic (like "eq0.b", "ne0.w", etc). + The disassembler prints these symbolically. */ + +#define TIC80_OPERAND_CC (1 << 30) + +/* This operand is a bit number, either numeric or + symbolic (like "eq.b", "or.f", etc). + The disassembler prints these symbolically. + Note that they appear in the instruction in 1's complement relative + to the values given in the manual. */ + +#define TIC80_OPERAND_BITNUM (1 << 31) + +/* This mask is used to strip operand bits from an int that contains + both operand bits and a numeric value in the lsbs. */ + +#define TIC80_OPERAND_MASK (TIC80_OPERAND_GPR | TIC80_OPERAND_FPA | TIC80_OPERAND_CR | TIC80_OPERAND_CC | TIC80_OPERAND_BITNUM) + + +/* Flag bits for the struct tic80_opcode flags field. */ + +#define TIC80_VECTOR 01 /* Is a vector instruction */ +#define TIC80_NO_R0_DEST 02 /* Register r0 cannot be a destination register */ + + +/* The opcodes library contains a table that allows translation from predefined + symbol names to numeric values, and vice versa. */ + +/* Structure to hold information about predefined symbols. */ + +struct predefined_symbol +{ + char *name; /* name to recognize */ + int value; +}; + +#define PDS_NAME(pdsp) ((pdsp) -> name) +#define PDS_VALUE(pdsp) ((pdsp) -> value) + +extern const struct predefined_symbol tic80_predefined_symbols[]; /* Translation array */ +extern const int tic80_num_predefined_symbols; /* How many members in the array */ + +const char *tic80_value_to_symbol PARAMS ((int val, int class)); /* Translate value to symbolic name */ +int tic80_symbol_to_value PARAMS ((char *name, int class)); /* Translate symbolic name to value */ + +const struct predefined_symbol * +tic80_next_predefined_symbol PARAMS ((const struct predefined_symbol *)); + +#endif /* TIC80_H */ diff --git a/gnu/usr.bin/binutils/include/opcode/v850.h b/gnu/usr.bin/binutils/include/opcode/v850.h new file mode 100644 index 00000000000..88916f1b848 --- /dev/null +++ b/gnu/usr.bin/binutils/include/opcode/v850.h @@ -0,0 +1,166 @@ +/* v850.h -- Header file for NEC V850 opcode table + Copyright 1996 Free Software Foundation, Inc. + Written by J.T. Conklin, Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef V850_H +#define V850_H + +/* The opcode table is an array of struct v850_opcode. */ + +struct v850_opcode +{ + /* The opcode name. */ + const char *name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + unsigned long opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + unsigned long mask; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[8]; + + /* Which (if any) operand is a memory operand. */ + unsigned int memop; + + /* Target processor(s). A bit field of processors which support + this instruction. Note a bit field is used as some instructions + are available on multiple, different processor types, whereas + other instructions are only available on one specific type. */ + unsigned int processors; +}; + +/* Values for the processors field in the v850_opcode structure. */ +#define PROCESSOR_V850 (1 << 0) /* Just the V850. */ +#define PROCESSOR_ALL -1 /* Any processor. */ +#define PROCESSOR_V850E (1 << 1) /* Just the V850E. */ +#define PROCESSOR_NOT_V850 (~ PROCESSOR_V850) /* Any processor except the V850. */ +#define PROCESSOR_V850EA (1 << 2) /* Just the V850EA. */ + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct v850_opcode v850_opcodes[]; +extern const int v850_num_opcodes; + + +/* The operands table is an array of struct v850_operand. */ + +struct v850_operand +{ + /* The number of bits in the operand. */ + /* If this value is -1 then the operand's bits are in a discontinous distribution in the instruction. */ + int bits; + + /* (bits >= 0): How far the operand is left shifted in the instruction. */ + /* (bits == -1): Bit mask of the bits in the operand. */ + int shift; + + /* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (op & ((1 << o->bits) - 1)) << o->shift; + (i is the instruction which we are filling in, o is a pointer to + this structure, and op is the opcode value; this assumes twos + complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged (most operands + can accept any value). */ + unsigned long (* insert) PARAMS ((unsigned long instruction, long op, + const char ** errmsg)); + + /* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = o->bits == -1 ? ((i) & o->shift) : ((i) >> o->shift) & ((1 << o->bits) - 1); + if (o->flags & V850_OPERAND_SIGNED) + op = (op << (32 - o->bits)) >> (32 - o->bits); + (i is the instruction, o is a pointer to this structure, and op + is the result; this assumes twos complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. */ + unsigned long (* extract) PARAMS ((unsigned long instruction, int * invalid)); + + /* One bit syntax flags. */ + int flags; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the v850_opcodes table. */ + +extern const struct v850_operand v850_operands[]; + +/* Values defined for the flags field of a struct v850_operand. */ + +/* This operand names a general purpose register */ +#define V850_OPERAND_REG 0x01 + +/* This operand names a system register */ +#define V850_OPERAND_SRG 0x02 + +/* This operand names a condition code used in the setf instruction */ +#define V850_OPERAND_CC 0x04 + +/* This operand takes signed values */ +#define V850_OPERAND_SIGNED 0x08 + +/* This operand is the ep register. */ +#define V850_OPERAND_EP 0x10 + +/* This operand is a PC displacement */ +#define V850_OPERAND_DISP 0x20 + +/* This is a relaxable operand. Only used for D9->D22 branch relaxing + right now. We may need others in the future (or maybe handle them like + promoted operands on the mn10300?) */ +#define V850_OPERAND_RELAX 0x40 + +/* The register specified must not be r0 */ +#define V850_NOT_R0 0x80 + +/* CYGNUS LOCAL v850e */ +/* push/pop type instruction, V850E specific. */ +#define V850E_PUSH_POP 0x100 + +/* 16 bit immediate follows instruction, V850E specific. */ +#define V850E_IMMEDIATE16 0x200 + +/* 32 bit immediate follows instruction, V850E specific. */ +#define V850E_IMMEDIATE32 0x400 + +#endif /* V850_H */ diff --git a/gnu/usr.bin/binutils/include/partition.h b/gnu/usr.bin/binutils/include/partition.h new file mode 100644 index 00000000000..f49d67a8cad --- /dev/null +++ b/gnu/usr.bin/binutils/include/partition.h @@ -0,0 +1,81 @@ +/* List implentation of a partition of consecutive integers. + Copyright (C) 2000 Free Software Foundation, Inc. + Contributed by CodeSourcery, LLC. + + This file is part of GNU CC. + + GNU CC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GNU CC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GNU CC; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +/* This package implements a partition of consecutive integers. The + elements are partitioned into classes. Each class is represented + by one of its elements, the canonical element, which is chosen + arbitrarily from elements in the class. The principal operations + on a partition are FIND, which takes an element, determines its + class, and returns the canonical element for that class, and UNION, + which unites the two classes that contain two given elements into a + single class. + + The list implementation used here provides constant-time finds. By + storing the size of each class with the class's canonical element, + it is able to perform unions over all the classes in the partition + in O (N log N) time. */ + +#ifndef _PARTITION_H +#define _PARTITION_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include <ansidecl.h> +#include <stdio.h> + +struct partition_elem +{ + /* The canonical element that represents the class containing this + element. */ + int class_element; + /* The next element in this class. Elements in each class form a + circular list. */ + struct partition_elem* next; + /* The number of elements in this class. Valid only if this is the + canonical element for its class. */ + unsigned class_count; +}; + +typedef struct partition_def +{ + /* The number of elements in this partition. */ + int num_elements; + /* The elements in the partition. */ + struct partition_elem elements[1]; +} *partition; + +extern partition partition_new PARAMS((int)); +extern void partition_delete PARAMS((partition)); +extern int partition_union PARAMS((partition, + int, + int)); +extern void partition_print PARAMS((partition, + FILE*)); + +/* Returns the canonical element corresponding to the class containing + ELEMENT__ in PARTITION__. */ + +#define partition_find(partition__, element__) \ + ((partition__)->elements[(element__)].class_element) + +#endif /* _PARTITION_H */ diff --git a/gnu/usr.bin/binutils/include/regs/ChangeLog b/gnu/usr.bin/binutils/include/regs/ChangeLog new file mode 100644 index 00000000000..e69de29bb2d --- /dev/null +++ b/gnu/usr.bin/binutils/include/regs/ChangeLog diff --git a/gnu/usr.bin/binutils/include/sim-d10v.h b/gnu/usr.bin/binutils/include/sim-d10v.h new file mode 100644 index 00000000000..84eab2a1a5e --- /dev/null +++ b/gnu/usr.bin/binutils/include/sim-d10v.h @@ -0,0 +1,103 @@ +/* This file defines the interface between the d10v simulator and gdb. + Copyright (C) 1999 Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#if !defined (SIM_D10V_H) +#define SIM_D10V_H + +#ifdef __cplusplus +extern "C" { // } +#endif + +/* GDB interprets addresses as: + + 0x00xxxxxx: Physical unified memory segment (Unified memory) + 0x01xxxxxx: Physical instruction memory segment (On-chip insn memory) + 0x02xxxxxx: Physical data memory segment (On-chip data memory) + 0x10xxxxxx: Logical data address segment (DMAP translated memory) + 0x11xxxxxx: Logical instruction address segment (IMAP translated memory) + + The remote d10v board interprets addresses as: + + 0x00xxxxxx: Physical unified memory segment (Unified memory) + 0x01xxxxxx: Physical instruction memory segment (On-chip insn memory) + 0x02xxxxxx: Physical data memory segment (On-chip data memory) + + The following translate a virtual DMAP/IMAP offset into a physical + memory segment assigning the translated address to PHYS. Since a + memory access may cross a page boundrary the number of bytes for + which the translation is applicable (or 0 for an invalid virtual + offset) is returned. */ + +enum + { + SIM_D10V_MEMORY_UNIFIED = 0x00000000, + SIM_D10V_MEMORY_INSN = 0x01000000, + SIM_D10V_MEMORY_DATA = 0x02000000, + SIM_D10V_MEMORY_DMAP = 0x10000000, + SIM_D10V_MEMORY_IMAP = 0x11000000 + }; + +extern unsigned long sim_d10v_translate_dmap_addr + (unsigned long offset, + int nr_bytes, + unsigned long *phys, + unsigned long (*dmap_register) (int reg_nr)); + +extern unsigned long sim_d10v_translate_imap_addr + (unsigned long offset, + int nr_bytes, + unsigned long *phys, + unsigned long (*imap_register) (int reg_nr)); + +extern unsigned long sim_d10v_translate_addr + (unsigned long vaddr, + int nr_bytes, + unsigned long *phys, + unsigned long (*dmap_register) (int reg_nr), + unsigned long (*imap_register) (int reg_nr)); + + +/* The simulator makes use of the following register information. */ + +enum + { + SIM_D10V_R0_REGNUM = 0, + SIM_D10V_CR0_REGNUM = 16, + SIM_D10V_A0_REGNUM = 32, + SIM_D10V_SPI_REGNUM = 34, + SIM_D10V_SPU_REGNUM = 35, + SIM_D10V_IMAP0_REGNUM = 36, + SIM_D10V_DMAP0_REGNUM = 38, + SIM_D10V_TS2_DMAP_REGNUM = 40 + }; + +enum + { + SIM_D10V_NR_R_REGS = 16, + SIM_D10V_NR_A_REGS = 2, + SIM_D10V_NR_IMAP_REGS = 2, + SIM_D10V_NR_DMAP_REGS = 4, + SIM_D10V_NR_CR_REGS = 16 + }; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/gnu/usr.bin/binutils/include/splay-tree.h b/gnu/usr.bin/binutils/include/splay-tree.h new file mode 100644 index 00000000000..6d70c8d9075 --- /dev/null +++ b/gnu/usr.bin/binutils/include/splay-tree.h @@ -0,0 +1,117 @@ +/* A splay-tree datatype. + Copyright (C) 1998 Free Software Foundation, Inc. + Contributed by Mark Mitchell (mark@markmitchell.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* For an easily readable description of splay-trees, see: + + Lewis, Harry R. and Denenberg, Larry. Data Structures and Their + Algorithms. Harper-Collins, Inc. 1991. + + The major feature of splay trees is that all basic tree operations + are amortized O(log n) time for a tree with n nodes. */ + +#ifndef _SPLAY_TREE_H +#define _SPLAY_TREE_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include <ansidecl.h> + +/* Use typedefs for the key and data types to facilitate changing + these types, if necessary. These types should be sufficiently wide + that any pointer or scalar can be cast to these types, and then + cast back, without loss of precision. */ +typedef unsigned long int splay_tree_key; +typedef unsigned long int splay_tree_value; + +/* Forward declaration for a node in the tree. */ +typedef struct splay_tree_node_s *splay_tree_node; + +/* The type of a function which compares two splay-tree keys. The + function should return values as for qsort. */ +typedef int (*splay_tree_compare_fn) PARAMS((splay_tree_key, splay_tree_key)); + +/* The type of a function used to deallocate any resources associated + with the key. */ +typedef void (*splay_tree_delete_key_fn) PARAMS((splay_tree_key)); + +/* The type of a function used to deallocate any resources associated + with the value. */ +typedef void (*splay_tree_delete_value_fn) PARAMS((splay_tree_value)); + +/* The type of a function used to iterate over the tree. */ +typedef int (*splay_tree_foreach_fn) PARAMS((splay_tree_node, void*)); + +/* The nodes in the splay tree. */ +struct splay_tree_node_s +{ + /* The key. */ + splay_tree_key key; + + /* The value. */ + splay_tree_value value; + + /* The left and right children, respectively. */ + splay_tree_node left; + splay_tree_node right; +}; + +/* The splay tree itself. */ +typedef struct splay_tree_s +{ + /* The root of the tree. */ + splay_tree_node root; + + /* The comparision function. */ + splay_tree_compare_fn comp; + + /* The deallocate-key function. NULL if no cleanup is necessary. */ + splay_tree_delete_key_fn delete_key; + + /* The deallocate-value function. NULL if no cleanup is necessary. */ + splay_tree_delete_value_fn delete_value; +} *splay_tree; + +extern splay_tree splay_tree_new PARAMS((splay_tree_compare_fn, + splay_tree_delete_key_fn, + splay_tree_delete_value_fn)); +extern void splay_tree_delete PARAMS((splay_tree)); +extern splay_tree_node splay_tree_insert + PARAMS((splay_tree, + splay_tree_key, + splay_tree_value)); +extern splay_tree_node splay_tree_lookup + PARAMS((splay_tree, + splay_tree_key)); +extern int splay_tree_foreach PARAMS((splay_tree, + splay_tree_foreach_fn, + void*)); +extern int splay_tree_compare_ints PARAMS((splay_tree_key, + splay_tree_key)); +extern int splay_tree_compare_pointers PARAMS((splay_tree_key, + splay_tree_key)); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _SPLAY_TREE_H */ diff --git a/gnu/usr.bin/binutils/include/symcat.h b/gnu/usr.bin/binutils/include/symcat.h new file mode 100644 index 00000000000..3e27162b264 --- /dev/null +++ b/gnu/usr.bin/binutils/include/symcat.h @@ -0,0 +1,40 @@ +/* Symbol concatenation utilities. + + Copyright (C) 1998, 2000 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef SYM_CAT_H +#define SYM_CAT_H + +#if defined (__STDC__) || defined (ALMOST_STDC) +#define CONCAT2(a,b) a##b +#define CONCAT3(a,b,c) a##b##c +#define CONCAT4(a,b,c,d) a##b##c##d +#define STRINGX(s) #s +#else +#define CONCAT2(a,b) a/**/b +#define CONCAT3(a,b,c) a/**/b/**/c +#define CONCAT4(a,b,c,d) a/**/b/**/c/**/d +#define STRINGX(s) "s" +#endif + +#define XCONCAT2(a,b) CONCAT2(a,b) +#define XCONCAT3(a,b,c) CONCAT3(a,b,c) +#define XCONCAT4(a,b,c,d) CONCAT4(a,b,c,d) + +#define XSTRING(s) STRINGX(s) + +#endif SYM_CAT_H |