diff options
Diffstat (limited to 'gnu/usr.bin/binutils/opcodes')
| -rw-r--r-- | gnu/usr.bin/binutils/opcodes/ChangeLog | 198 | ||||
| -rw-r--r-- | gnu/usr.bin/binutils/opcodes/Makefile.in | 24 | ||||
| -rw-r--r-- | gnu/usr.bin/binutils/opcodes/alpha-dis.c | 482 | ||||
| -rw-r--r-- | gnu/usr.bin/binutils/opcodes/arm-dis.c | 71 | ||||
| -rw-r--r-- | gnu/usr.bin/binutils/opcodes/arm-opc.h | 5 | ||||
| -rw-r--r-- | gnu/usr.bin/binutils/opcodes/configure | 32 | ||||
| -rw-r--r-- | gnu/usr.bin/binutils/opcodes/configure.in | 5 | ||||
| -rw-r--r-- | gnu/usr.bin/binutils/opcodes/disassemble.c | 2 | ||||
| -rw-r--r-- | gnu/usr.bin/binutils/opcodes/h8300-dis.c | 71 | ||||
| -rw-r--r-- | gnu/usr.bin/binutils/opcodes/i386-dis.c | 227 | ||||
| -rw-r--r-- | gnu/usr.bin/binutils/opcodes/m68k-opc.c | 928 | ||||
| -rw-r--r-- | gnu/usr.bin/binutils/opcodes/mpw-make.sed | 6 | ||||
| -rw-r--r-- | gnu/usr.bin/binutils/opcodes/ppc-opc.c | 2 | ||||
| -rw-r--r-- | gnu/usr.bin/binutils/opcodes/sparc-dis.c | 23 | ||||
| -rw-r--r-- | gnu/usr.bin/binutils/opcodes/sparc-opc.c | 34 |
15 files changed, 1210 insertions, 900 deletions
diff --git a/gnu/usr.bin/binutils/opcodes/ChangeLog b/gnu/usr.bin/binutils/opcodes/ChangeLog index fc76a05b172..9ebbd26fca0 100644 --- a/gnu/usr.bin/binutils/opcodes/ChangeLog +++ b/gnu/usr.bin/binutils/opcodes/ChangeLog @@ -1,3 +1,201 @@ +Tue Sep 3 12:09:46 1996 Doug Evans <dje@canuck.cygnus.com> + + * sparc-opc.c (sparc_opcodes): Add setuw, setsw, setx. + +Mon Aug 19 15:21:38 1996 Doug Evans <dje@canuck.cygnus.com> + + * sparc-dis.c (print_insn_sparc): Handle little endian sparcs. + +Thu Aug 15 13:11:13 1996 Stan Shebs <shebs@andros.cygnus.com> + + * mpw-make.sed: Update editing of include pathnames to be + more general. + +Thu Aug 15 16:28:41 1996 James G. Smith <jsmith@cygnus.co.uk> + + * arm-opc.h: Added "bx" instruction definition. + +Wed Aug 14 17:00:04 1996 Richard Henderson <rth@tamu.edu> + + * alpha-opc.c (EV4EXTHWINDEX): Field width should be 8 not 5. + +Thu Aug 8 12:43:52 1996 Klaus Kaempf <kkaempf@progis.de> + + * makefile.vms: Update for alpha-opc changes. + +Wed Aug 7 11:55:10 1996 Ian Lance Taylor <ian@cygnus.com> + + * i386-dis.c (print_insn_i386): Actually return the correct value. + (ONE, OP_ONE): #ifdef out; not used. + +Wed Jul 31 16:21:41 1996 Ian Lance Taylor <ian@cygnus.com> + + * m68k-opc.c: Add cpushl for the mcf5200. From Ken Rose + <rose@netcom.com>. + +Wed Jul 31 14:39:27 1996 James G. Smith <jsmith@cygnus.co.uk> + + * arm-opc.h: (arm_opcodes): Added halfword and sign-extension + memory transfer instructions. Add new format string entries %h and %s. + * arm-dis.c: (print_insn_arm): Provide decoding of the new + formats %h and %s. + +Fri Jul 26 14:01:43 1996 Ian Lance Taylor <ian@cygnus.com> + + * alpha-dis.c (print_insn_alpha_osf): Remove. + (print_insn_alpha_vms): Remove. + (print_insn_alpha): Make globally visible. Chose the register + names based on info->flavour. + * disassemble.c: Always return print_insn_alpha for the alpha. + +Mon Jul 22 15:38:53 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> + + * m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire + move ccr/sr insns more strict so that the disassembler only + selects them when the addressing mode is data register. + +Mon Jul 22 13:47:23 1996 Ian Lance Taylor <ian@cygnus.com> + + * sparc-opc.c: Fix opcode values for fpack16, and fpackfix. Fix + operands for fexpand and fpmerge. From Christian Kuehnke + <Christian.Kuehnke@arbi.informatik.uni-oldenburg.de>. + +Mon Jul 22 13:17:06 1996 Richard Henderson <rth@tamu.edu> + + * alpha-dis.c (print_insn_alpha): No longer the user-visible + print routine. Take new regnames and cpumask arguments. + Kill the environment variable nonsense. + (print_insn_alpha_osf): New function. Do OSF/1 style regnames. + (print_insn_alpha_vms): New function. Do VMS style regnames. + * disassemble.c (disassembler): Test bfd flavour to pick + between OSF and VMS routines. Default to OSF. + +Thu Jul 18 17:19:34 1996 Ian Lance Taylor <ian@cygnus.com> + + * configure.in: Call AC_SUBST (INSTALL_SHLIB). + * configure: Rebuild. + * Makefile.in (install): Use @INSTALL_SHLIB@. + +Wed Jul 17 10:12:05 1996 J.T. Conklin <jtc@rtl.cygnus.com> + + * m68k-opc.c (m68k_opcodes): Fix bugs in coldfire insns relating + to bcc, trapfl, subxl, and wddata discovered by Andreas Schwab. + +Mon Jul 15 16:59:55 1996 Stu Grossman (grossman@critters.cygnus.com) + + * i386-dis.c: Get rid of print_insn_i8086. Use info.mach to + distinguish between variants of the instruction set. + * sparc-dis.c: Get rid of print_insn_sparclite. Use info.mach to + distinguish between variants of the instruction set. + +Fri Jul 12 10:12:01 1996 Stu Grossman (grossman@critters.cygnus.com) + + * i386-dis.c (print_insn_i8086): New routine to disassemble using + the 8086 instruction set. + * i386-dis.c: General cleanups. Make most things static. Add + prototypes. Get rid of static variables aflags and dflags. Pass + them as args (to almost everything). + +Thu Jul 11 11:58:44 1996 Jeffrey A Law (law@cygnus.com) + + * h8300-dis.c (bfd_h8_disassemble): Handle macregs in ldmac insns. + + * h8300-dis.c (bfd_h8_disassemble): Handle "ldm.l" and "stm.l". + + * h8300-dis.c (bfd_h8_disassemble): "abs" is implicitly two + if the next arg is marked with SRC_IN_DST. Gross. + + * h8300-dis.c (bfd_h8_disassemble): Print "exr" when + we're looking for and find EXR. + + * h8300-dis.c (bfd_h8_disassemble): We don't have a match + if we're looking for KBIT and we don't find it. + + * h8300-dis.c (bfd_h8_disassemble): Mask off unwanted bits + for L_3 and L_2. + + * h8300-dis.c (bfd_h8_disassemble): Don't set plen for + 3bit immediate operands. + +Tue Jul 9 10:55:20 1996 Ian Lance Taylor <ian@cygnus.com> + + * Released binutils 2.7. + + * alpha-opc.c: Add new case of "mov". From Klaus Kaempf + <kkaempf@progis.ac-net.de>. + +Thu Jul 4 11:42:51 1996 Ian Lance Taylor <ian@cygnus.com> + + * alpha-opc.c: Correct second case of "mov" to use OPRL. + +Wed Jul 3 16:03:47 1996 Stu Grossman (grossman@critters.cygnus.com) + + * sparc-dis.c (print_insn_sparclite): New routine to print + sparclite instructions. + +Wed Jul 3 14:21:18 1996 J.T. Conklin <jtc@rtl.cygnus.com> + + * m68k-opc.c (m68k_opcodes): Add coldfire support. + +Fri Jun 28 15:53:51 1996 Doug Evans <dje@canuck.cygnus.com> + + * sparc-opc.c (asi_table): Add #ASI_N, #ASI_N_L, #ASI_NUCLEUS, + #ASI_NUCLEUS_LITTLE. Rename #ASI_AS_IF_USER_{PRIMARY,SECONDARY}_L + to #ASI_AS_IF_USER_{PRIMARY,SECONDARY}_LITTLE. + +Tue Jun 25 22:58:31 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) + + * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir): + Use autoconf-set values. + (docdir, oldincludedir): Removed. + * configure.in (AC_PREREQ): autoconf 2.5 or higher. + +Fri Jun 21 13:53:36 1996 Richard Henderson <rth@tamu.edu> + + * alpha-opc.c: New file. + * alpha-opc.h: Remove. + * alpha-dis.c: Complete rewrite to use new opcode table. + * configure.in: For bfd_alpha_arch, use alpha-opc.o. + * configure: Rebuild with autoconf 2.10. + * Makefile.in (ALL_MACHINES): Add alpha-opc.o. + (alpha-dis.o): Depend upon $(INCDIR)/opcode/alpha.h, not + alpha-opc.h. + (alpha-opc.o): New target. + +Wed Jun 19 15:55:12 1996 Ian Lance Taylor <ian@cygnus.com> + + * sparc-dis.c (print_insn_sparc): Remove unused local variable i. + Set imm_added_to_rs1 even if the source and destination register + are not the same. + + * sparc-opc.c: Add some two operand forms of the wr instruction. + +Tue Jun 18 15:58:27 1996 Jeffrey A. Law <law@rtl.cygnus.com> + + * h8300-dis.c (bfd_h8_disassemble): Rename "hmode" argument + to just "mode". + + * disassemble.c (disassembler): Handle H8/S. + * h8300-dis.c (print_insn_h8300s): New function for H8/S. + +Tue Jun 18 18:06:50 1996 Ian Lance Taylor <ian@cygnus.com> + + * sparc-opc.c: Add beq/teq as aliases for be/te. + + * ppc-opc.c: Fix fcmpo opcode. From Sergei Steshenko + <sergei@msil.sps.mot.com>. + +Tue Jun 18 15:08:54 1996 Klaus Kaempf <kkaempf@progis.de> + + * makefile.vms: New file. + + * alpha-dis.c (print_insn_alpha): Print lda ra,lit(rz) as mov. + +Mon Jun 10 18:50:38 1996 Ian Lance Taylor <ian@cygnus.com> + + * h8300-dis.c (bfd_h8_disassemble): Always print ABS8MEM with :8, + regardless of plen. + Tue Jun 4 09:15:53 1996 Doug Evans <dje@canuck.cygnus.com> * i386-dis.c (OP_OFF): Call append_prefix. diff --git a/gnu/usr.bin/binutils/opcodes/Makefile.in b/gnu/usr.bin/binutils/opcodes/Makefile.in index 74fbaa7c215..cda3d4c66dd 100644 --- a/gnu/usr.bin/binutils/opcodes/Makefile.in +++ b/gnu/usr.bin/binutils/opcodes/Makefile.in @@ -1,5 +1,6 @@ # Makefile template for Configure for the opcodes library. -# Copyright (C) 1990, 1991, 1992, 1995 Free Software Foundation, Inc. +# Copyright (C) 1990, 91, 92, 93, 94, 95, 1996 +# Free Software Foundation, Inc. # Written by Cygnus Support. # # This program is free software; you can redistribute it and/or modify @@ -23,11 +24,11 @@ prefix = @prefix@ program_transform_name = @program_transform_name@ exec_prefix = @exec_prefix@ -bindir = $(exec_prefix)/bin -libdir = $(exec_prefix)/lib +bindir = @bindir@ +libdir = @libdir@ -datadir = $(prefix)/lib -mandir = $(prefix)/man +datadir = @datadir@ +mandir = @mandir@ man1dir = $(mandir)/man1 man2dir = $(mandir)/man2 man3dir = $(mandir)/man3 @@ -37,10 +38,8 @@ man6dir = $(mandir)/man6 man7dir = $(mandir)/man7 man8dir = $(mandir)/man8 man9dir = $(mandir)/man9 -infodir = $(prefix)/info -includedir = $(prefix)/include -oldincludedir = -docdir = $(srcdir)/doc +infodir = @infodir@ +includedir = @includedir@ SHELL = /bin/sh @@ -77,7 +76,7 @@ TARGETLIB = libopcodes.a # To circumvent a Sun make VPATH bug, each file listed here # should also have a foo.o: foo.c line further along in this file. -ALL_MACHINES = a29k-dis.o alpha-dis.o h8300-dis.o h8500-dis.o \ +ALL_MACHINES = a29k-dis.o alpha-dis.o alpha-opc.o h8300-dis.o h8500-dis.o \ hppa-dis.o i386-dis.o i960-dis.o m68k-dis.o m68k-opc.o \ m88k-dis.o mips-dis.o mips-opc.o sh-dis.o sparc-dis.o \ sparc-opc.o z8k-dis.o ns32k-dis.o ppc-dis.o ppc-opc.o \ @@ -214,7 +213,8 @@ sparc-opc.o: sparc-opc.c $(INCDIR)/opcode/sparc.h z8k-dis.o: z8k-dis.c z8k-opc.h $(INCDIR)/dis-asm.h ns32k-dis.o: ns32k-dis.c $(INCDIR)/dis-asm.h $(INCDIR)/opcode/ns32k.h sh-dis.o: sh-dis.c sh-opc.h $(INCDIR)/dis-asm.h -alpha-dis.o: alpha-dis.c alpha-opc.h $(INCDIR)/dis-asm.h +alpha-dis.o: alpha-dis.c $(INCDIR)/dis-asm.h $(INCDIR)/opcode/alpha.h +alpha-opc.o: alpha-opc.c $(INCDIR)/dis-asm.h $(INCDIR)/opcode/alpha.h hppa-dis.o: hppa-dis.c $(INCDIR)/dis-asm.h $(INCDIR)/opcode/hppa.h m88k-dis.o: m88k-dis.c $(INCDIR)/dis-asm.h $(INCDIR)/opcode/m88k.h arm-dis.o: arm-dis.c arm-opc.h $(INCDIR)/dis-asm.h @@ -268,7 +268,7 @@ install: $(ALLLIBS) ts=lib`echo $(SHLIB) | sed -e 's,^\.\./bfd/,,' -e 's/^lib//' | sed '$(program_transform_name)'`; \ ln -sf $$ts $(libdir)/$$tf; \ elif [ "$$f" = "$(SHLIB)" ]; then \ - $(INSTALL_PROGRAM) $$f $(libdir)/$$tf; \ + @INSTALL_SHLIB@ \ else \ $(INSTALL_DATA) $$f $(libdir)/$$tf; \ $(RANLIB) $(libdir)/$$tf; \ diff --git a/gnu/usr.bin/binutils/opcodes/alpha-dis.c b/gnu/usr.bin/binutils/opcodes/alpha-dis.c index c0ed843f55e..3515bc1bd00 100644 --- a/gnu/usr.bin/binutils/opcodes/alpha-dis.c +++ b/gnu/usr.bin/binutils/opcodes/alpha-dis.c @@ -1,335 +1,199 @@ -/* Instruction printing code for the Alpha - Copyright (C) 1993, 1995 Free Software Foundation, Inc. - Contributed by Cygnus Support. - -Written by Steve Chamberlain (sac@cygnus.com) - -This file is part of libopcodes. - -This program is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 2 of the License, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, but WITHOUT -ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -more details. - -You should have received a copy of the GNU General Public License along with -This program; if not, write to the Free Software Foundation, Inc., 675 - Mass Ave, Boston, MA 02111-1307, USA. -*/ - +/* alpha-dis.c -- Disassemble Alpha AXP instructions + Copyright 1996 Free Software Foundation, Inc. + Contributed by Richard Henderson <rth@tamu.edu>, + patterned after the PPC opcode handling written by Ian Lance Taylor. + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +2, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ + +#include <stdlib.h> +#include <stdio.h> +#include "ansidecl.h" +#include "sysdep.h" #include "dis-asm.h" -#define DEFINE_TABLE -#include "alpha-opc.h" +#include "opcode/alpha.h" +/* OSF register names. */ -/* Print one instruction from PC on INFO->STREAM. - Return the size of the instruction (always 4 on alpha). */ +static const char * const osf_regnames[64] = +{ + "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", + "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", + "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", + "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero", + "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", + "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", + "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", + "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" +}; + +/* VMS register names. */ + +static const char * const vms_regnames[64] = +{ + "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", + "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", + "R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23", + "R24", "AI", "RA", "PV", "AT", "FP", "SP", "RZ", + "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7", + "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15", + "F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23", + "F24", "F25", "F26", "F27", "F28", "F29", "F30", "FZ" +}; + +/* Disassemble Alpha instructions. */ int -print_insn_alpha(pc, info) - bfd_vma pc; +print_insn_alpha (memaddr, info) + bfd_vma memaddr; struct disassemble_info *info; { - alpha_insn *insn; - unsigned char b[4]; - void *stream = info->stream; - fprintf_ftype func = info->fprintf_func; - unsigned long given; - int status ; - int found = 0; - - status = (*info->read_memory_func) (pc, (bfd_byte *) &b[0], 4, info); - if (status != 0) { - (*info->memory_error_func) (status, pc, info); - return -1; - } - given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); - - func (stream, "\t%08x\t", given); - - for (insn = alpha_insn_set; - insn->name && !found; - insn++) + static const struct alpha_opcode *opcode_index[AXP_NOPS+1]; + const char * const * regnames; + const struct alpha_opcode *opcode, *opcode_end; + const unsigned char *opindex; + unsigned insn, op; + int need_comma; + + /* Initialize the majorop table the first time through */ + if (!opcode_index[0]) { - switch (insn->type) - { - case MEMORY_FORMAT_CODE: - if ((insn->i & MEMORY_FORMAT_MASK) - ==(given & MEMORY_FORMAT_MASK)) - { - func (stream, "%s\t%s, %d(%s)", - insn->name, - alpha_regs[RA(given)], - OPCODE (given) == 9 ? DISP(given) * 65536 : DISP(given), - alpha_regs[RB(given)]); - found = 1; - } - break; - - - case MEMORY_FUNCTION_FORMAT_CODE: - if ((insn->i & MEMORY_FUNCTION_FORMAT_MASK) - ==(given & MEMORY_FUNCTION_FORMAT_MASK)) - { - switch (given & 0xffff) - { - case 0x8000: /* fetch */ - case 0xa000: /* fetch_m */ - func (stream, "%s\t(%s)", insn->name, alpha_regs[RB(given)]); - break; - - case 0xc000: /* rpcc */ - func (stream, "%s\t%s", insn->name, alpha_regs[RA(given)]); - break; - - default: - func (stream, "%s", insn->name); - break; - } - found = 1; - } - break; - - case BRANCH_FORMAT_CODE: - if ((insn->i & BRANCH_FORMAT_MASK) - == (given & BRANCH_FORMAT_MASK)) - { - if (RA(given) == 31) - func (stream, "%s\t ", insn->name); - else - func (stream, "%s\t%s, ", insn->name, - alpha_regs[RA(given)]); - (*info->print_address_func) (BDISP(given) * 4 + pc + 4, info); - found = 1; - } - break; - - case MEMORY_BRANCH_FORMAT_CODE: - if ((insn->i & MEMORY_BRANCH_FORMAT_MASK) - == (given & MEMORY_BRANCH_FORMAT_MASK)) - { - if (given & (1<<15)) - { - func (stream, "%s\t%s, (%s), %d", insn->name, - alpha_regs[RA(given)], - alpha_regs[RB(given)], - JUMP_HINT(given)); - } - else - { - /* The displacement is a hint only, do not put out - a symbolic address. */ - func (stream, "%s\t%s, (%s), 0x%lx", insn->name, - alpha_regs[RA(given)], - alpha_regs[RB(given)], - JDISP(given) * 4 + pc + 4); - } - found = 1; - } - break; + opcode = alpha_opcodes; + opcode_end = opcode + alpha_num_opcodes; + + for (op = 0; op < AXP_NOPS; ++op) + { + opcode_index[op] = opcode; + while (opcode < opcode_end && op == AXP_OP (opcode->opcode)) + ++opcode; + } + opcode_index[op] = opcode; + } - case OPERATE_FORMAT_CODE: - if ((insn->i & OPERATE_FORMAT_MASK) - == (given & OPERATE_FORMAT_MASK)) - { - int opcode = OPCODE(given); - int optype = OP_OPTYPE(given); - if (OP_OPTYPE(insn->i) == optype) - { - int ra; - ra = RA(given); + if (info->flavour == bfd_target_evax_flavour) + regnames = vms_regnames; + else + regnames = osf_regnames; - if (OP_IS_CONSTANT(given)) - { - if ((opcode == 0x11) && (optype == 0x20) - && (ra == 31)) /* bis R31, lit, Ry */ - { - func (stream, "mov\t0x%x, %s", - LITERAL(given), alpha_regs[RC(given)] ); - } - else - { -#if GNU_ASMCODE - func (stream, "%s\t%s, 0x%x, %s", insn->name, - alpha_regs[RA(given)], - LITERAL(given), - alpha_regs[RC(given)]); -#else - func (stream, "%s\t%s, #%d, %s", insn->name, - alpha_regs[RA(given)], - LITERAL(given), - alpha_regs[RC(given)]); - } -#endif - } else { /* not constant */ - int rb, rc; - rb = RB(given); rc = RC(given); - switch ((opcode << 8) | optype) - { - case 0x1009: /* subl */ - if (ra == 31) - { - func (stream, "negl\t%s, %s", - alpha_regs[rb], alpha_regs[rc]); - found = 1; - } - break; - case 0x1029: /* subq */ - if (ra == 31) - { - func (stream, "negq\t%s, %s", - alpha_regs[rb], alpha_regs[rc]); - found = 1; - } - break; - case 0x1120: /* bis */ - if (ra == 31) - { - if (ra == rb) /* ra=R31, rb=R31 */ - { - if (rc == 31) - func (stream, "nop"); - else - func (stream, "clr\t%s", alpha_regs[rc]); - } - else - func (stream, "mov\t%s, %s", - alpha_regs[rb], alpha_regs[rc]); - } - else - func (stream, "or\t%s, %s, %s", - alpha_regs[ra], alpha_regs[rb], - alpha_regs[rc]); - found = 1; - break; + /* Read the insn into a host word */ + { + bfd_byte buffer[4]; + int status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getl32 (buffer); + } - default: - break; + /* Get the major opcode of the instruction. */ + op = AXP_OP (insn); - } + /* Find the first match in the opcode table. */ + opcode_end = opcode_index[op+1]; + for (opcode = opcode_index[op]; opcode < opcode_end; ++opcode) + { + if ((insn & opcode->mask) != opcode->opcode) + continue; - if (!found) - func (stream, "%s\t%s, %s, %s", insn->name, - alpha_regs[ra], alpha_regs[rb], alpha_regs[rc]); - } - found = 1; - } - } + if (!(opcode->flags & AXP_OPCODE_ALL)) + continue; - break; + /* Make two passes over the operands. First see if any of them + have extraction functions, and, if they do, make sure the + instruction is valid. */ + { + int invalid = 0; + for (opindex = opcode->operands; *opindex != 0; opindex++) + { + const struct alpha_operand *operand = alpha_operands + *opindex; + if (operand->extract) + (*operand->extract) (insn, &invalid); + } + if (invalid) + continue; + } - case FLOAT_FORMAT_CODE: - if ((insn->i & FLOAT_FORMAT_MASK) - == (given & FLOAT_FORMAT_MASK)) - { - int ra, rb, rc; - ra = RA(given); rb = RB(given); rc = RC(given); - switch (OP_OPTYPE(given)) - { - case 0x20: /* cpys */ - if (ra == 31) - { - if (rb == 31) - { - if (rc == 31) - func (stream, "fnop"); - else - func (stream, "fclr\tf%d", rc); - } - else - func (stream, "fabs\tf%d, f%d", rb, rc); - found = 1; - } - else if (ra == rb) - { - func (stream, "fmov\tf%d, f%d", rb, rc); - found = 1; - } - break; - case 0x21: /* cpysn */ - if (ra == rb) - { - func (stream, "fneg\tf%d, f%d", rb, rc); - found = 1; - } - default: - ; - } + /* The instruction is valid. */ + goto found; + } - if (!found) - func (stream, "%s\tf%d, f%d, f%d", insn->name, ra, rb, rc); + /* No instruction found */ + (*info->fprintf_func) (info->stream, ".long %#08x", insn); + + return 4; - found = 1; - } +found: + (*info->fprintf_func) (info->stream, "%s", opcode->name); + if (opcode->operands[0] != 0) + (*info->fprintf_func) (info->stream, "\t"); - break; - case PAL_FORMAT_CODE: - if (insn->i == given) + /* Now extract and print the operands. */ + need_comma = 0; + for (opindex = opcode->operands; *opindex != 0; opindex++) + { + const struct alpha_operand *operand = alpha_operands + *opindex; + int value; + + /* Operands that are marked FAKE are simply ignored. We + already made sure that the extract function considered + the instruction to be valid. */ + if ((operand->flags & AXP_OPERAND_FAKE) != 0) + continue; + + /* Extract the value from the instruction. */ + if (operand->extract) + value = (*operand->extract) (insn, (int *) NULL); + else + { + value = (insn >> operand->shift) & ((1 << operand->bits) - 1); + if (operand->flags & AXP_OPERAND_SIGNED) { - func (stream, "call_pal %s", insn->name); - found = 1; + int signbit = 1 << (operand->bits - 1); + value = (value ^ signbit) - signbit; } + } - break; - case FLOAT_MEMORY_FORMAT_CODE: - if ((insn->i & MEMORY_FORMAT_MASK) - ==(given & MEMORY_FORMAT_MASK)) - { - func (stream, "%s\tf%d, %d(%s)", - insn->name, - RA(given), - OPCODE (given) == 9 ? DISP(given) * 65536 : DISP(given), - alpha_regs[RB(given)]); - found = 1; - } - break; - case FLOAT_BRANCH_FORMAT_CODE: - if ((insn->i & BRANCH_FORMAT_MASK) - == (given & BRANCH_FORMAT_MASK)) - { - func (stream, "%s\tf%d, ", - insn->name, - RA(given)); - (*info->print_address_func) (BDISP(given) * 4 + pc + 4, info); - found = 1; - } - break; + if (need_comma && + ((operand->flags & (AXP_OPERAND_PARENS|AXP_OPERAND_COMMA)) + != AXP_OPERAND_PARENS)) + { + (*info->fprintf_func) (info->stream, ","); } + if (operand->flags & AXP_OPERAND_PARENS) + (*info->fprintf_func) (info->stream, "("); + + /* Print the operand as directed by the flags. */ + if (operand->flags & AXP_OPERAND_IR) + (*info->fprintf_func) (info->stream, "%s", regnames[value]); + else if (operand->flags & AXP_OPERAND_FPR) + (*info->fprintf_func) (info->stream, "%s", regnames[value+32]); + else if (operand->flags & AXP_OPERAND_RELATIVE) + (*info->print_address_func) (memaddr + 4 + value, info); + else if (operand->flags & AXP_OPERAND_SIGNED) + (*info->fprintf_func) (info->stream, "%d", value); + else + (*info->fprintf_func) (info->stream, "%#x", value); + + if (operand->flags & AXP_OPERAND_PARENS) + (*info->fprintf_func) (info->stream, ")"); + need_comma = 1; } - if (!found) - switch (OPCODE (given)) - { - case 0x00: - func (stream, "call_pal 0x%x", given); - break; - case 0x19: - case 0x1b: - case 0x1d: - case 0x1e: - case 0x1f: - func (stream, "PAL%X 0x%x", OPCODE (given), given & 0x3ffffff); - break; - case 0x01: - case 0x02: - case 0x03: - case 0x04: - case 0x05: - case 0x06: - case 0x07: - case 0x0a: - case 0x0c: - case 0x0d: - case 0x0e: - case 0x14: - case 0x1c: - func (stream, "OPC%02X 0x%x", OPCODE (given), given & 0x3ffffff); - break; - } - return 4; } diff --git a/gnu/usr.bin/binutils/opcodes/arm-dis.c b/gnu/usr.bin/binutils/opcodes/arm-dis.c index 32c7f8122f4..deeef731ddc 100644 --- a/gnu/usr.bin/binutils/opcodes/arm-dis.c +++ b/gnu/usr.bin/binutils/opcodes/arm-dis.c @@ -155,6 +155,70 @@ print_insn_arm (pc, info, given) } } break; + + case 's': + if ((given & 0x004f0000) == 0x004f0000) + { + /* PC relative with immediate offset */ + int offset = ((given & 0xf00) >> 4) | (given & 0xf); + if ((given & 0x00800000) == 0) + offset = -offset; + (*info->print_address_func) + (offset + pc + 8, info); + } + else + { + func (stream, "[%s", + arm_regnames[(given >> 16) & 0xf]); + if ((given & 0x01000000) != 0) + { + /* pre-indexed */ + if ((given & 0x00400000) == 0x00400000) + { + /* immediate */ + int offset = ((given & 0xf00) >> 4) | (given & 0xf); + if (offset) + func (stream, ", %s#%x", + (((given & 0x00800000) == 0) + ? "-" : ""), offset); + } + else + { + /* register */ + func (stream, ", %s%s", + (((given & 0x00800000) == 0) + ? "-" : ""), + arm_regnames[given & 0xf]); + } + + func (stream, "]%s", + ((given & 0x00200000) != 0) ? "!" : ""); + } + else + { + /* post-indexed */ + if ((given & 0x00400000) == 0x00400000) + { + /* immediate */ + int offset = ((given & 0xf00) >> 4) | (given & 0xf); + if (offset) + func (stream, "], %s#%x", + (((given & 0x00800000) == 0) + ? "-" : ""), offset); + else + func (stream, "]"); + } + else + { + /* register */ + func (stream, "], %s%s", + (((given & 0x00800000) == 0) + ? "-" : ""), + arm_regnames[given & 0xf]); + } + } + } + break; case 'b': (*info->print_address_func) @@ -207,6 +271,13 @@ print_insn_arm (pc, info, given) func (stream, "t"); break; + case 'h': + if ((given & 0x00000020) == 0x00000020) + func (stream, "h"); + else + func (stream, "b"); + break; + case 'A': func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); if ((given & 0x01000000) != 0) diff --git a/gnu/usr.bin/binutils/opcodes/arm-opc.h b/gnu/usr.bin/binutils/opcodes/arm-opc.h index 33f5daa90d2..c1f544374b1 100644 --- a/gnu/usr.bin/binutils/opcodes/arm-opc.h +++ b/gnu/usr.bin/binutils/opcodes/arm-opc.h @@ -39,8 +39,10 @@ struct arm_opcode { %<bitnum>?ab print a if bit is one else print b %p print 'p' iff bits 12-15 are 15 %t print 't' iff bit 21 set and bit 24 clear + %h print 'h' iff bit 5 set, else print 'b' %o print operand2 (immediate or register + shift) %a print address for ldr/str instruction + %s print address for ldr/str halfword/signextend instruction %b print branch destination %A print address for ldc/stc/ldf/stf instruction %m print register mask for ldm/stm instruction @@ -53,11 +55,14 @@ struct arm_opcode { static struct arm_opcode arm_opcodes[] = { /* ARM instructions */ + {0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, {0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"}, {0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"}, {0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"}, {0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, {0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {0x00000090, 0x0e100090, "str%c%6's%h\t%12-15r, %s"}, + {0x00100090, 0x0e100090, "ldr%c%6's%h\t%12-15r, %s"}, {0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"}, {0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"}, {0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"}, diff --git a/gnu/usr.bin/binutils/opcodes/configure b/gnu/usr.bin/binutils/opcodes/configure index adfbe7d8497..8bd16a4b0b4 100644 --- a/gnu/usr.bin/binutils/opcodes/configure +++ b/gnu/usr.bin/binutils/opcodes/configure @@ -1,8 +1,8 @@ #! /bin/sh # Guess values for system-dependent variables and create Makefiles. -# Generated automatically using autoconf version 2.8 -# Copyright (C) 1992, 1993, 1994 Free Software Foundation, Inc. +# Generated automatically using autoconf version 2.10 +# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc. # # This configure script is free software; the Free Software Foundation # gives unlimited permission to copy, distribute and modify it. @@ -336,7 +336,7 @@ EOF verbose=yes ;; -version | --version | --versio | --versi | --vers) - echo "configure generated by autoconf version 2.8" + echo "configure generated by autoconf version 2.10" exit 0 ;; -with-* | --with-*) @@ -1030,6 +1030,7 @@ fi + echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6 # On Suns, sometimes $CPP names a directory. if test -n "$CPP" && test -d "$CPP"; then @@ -1045,13 +1046,13 @@ else # On the NeXT, cc -E runs the code through the compiler's parser, # not just through cpp. cat > conftest.$ac_ext <<EOF -#line 1049 "configure" +#line 1050 "configure" #include "confdefs.h" #include <assert.h> Syntax Error EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:1055: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:1056: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out` if test -z "$ac_err"; then : @@ -1060,13 +1061,13 @@ else rm -rf conftest* CPP="${CC-cc} -E -traditional-cpp" cat > conftest.$ac_ext <<EOF -#line 1064 "configure" +#line 1065 "configure" #include "confdefs.h" #include <assert.h> Syntax Error EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:1070: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:1071: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out` if test -z "$ac_err"; then : @@ -1094,12 +1095,12 @@ if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 1098 "configure" +#line 1099 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:1103: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:1104: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out` if test -z "$ac_err"; then rm -rf conftest* @@ -1166,7 +1167,7 @@ if test x${all_targets} = xfalse ; then case "$arch" in bfd_a29k_arch) ta="$ta a29k-dis.o" ;; bfd_alliant_arch) ;; - bfd_alpha_arch) ta="$ta alpha-dis.o" ;; + bfd_alpha_arch) ta="$ta alpha-dis.o alpha-opc.o" ;; bfd_arm_arch) ta="$ta arm-dis.o" ;; bfd_convex_arch) ;; bfd_h8300_arch) ta="$ta h8300-dis.o" ;; @@ -1302,7 +1303,7 @@ do echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion" exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;; -version | --version | --versio | --versi | --vers | --ver | --ve | --v) - echo "$CONFIG_STATUS generated by autoconf version 2.8" + echo "$CONFIG_STATUS generated by autoconf version 2.10" exit 0 ;; -help | --help | --hel | --he | --h) echo "\$ac_cs_usage"; exit 0 ;; @@ -1373,6 +1374,7 @@ s%@COMMON_SHLIB@%$COMMON_SHLIB%g s%@SHLIB_DEP@%$SHLIB_DEP%g s%@BFD_PICLIST@%$BFD_PICLIST%g s%@SHLINK@%$SHLINK%g +s%@INSTALL_SHLIB@%$INSTALL_SHLIB%g s%@CPP@%$CPP%g s%@archdefs@%$archdefs%g s%@BFD_MACHINES@%$BFD_MACHINES%g @@ -1480,7 +1482,7 @@ rm -f conftest.vals cat > conftest.hdr <<\EOF s/[\\&%]/\\&/g s%[\\$`]%\\&%g -s%#define \([A-Za-z_][A-Za-z0-9_]*\) \(.*\)%${ac_dA}\1${ac_dB}\1${ac_dC}\2${ac_dD}%gp +s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%${ac_dA}\1${ac_dB}\1${ac_dC}\2${ac_dD}%gp s%ac_d%ac_u%gp s%ac_u%ac_e%gp EOF @@ -1528,6 +1530,12 @@ cat >> $CONFIG_STATUS <<\EOF echo "$ac_file is unchanged" rm -f conftest.h else + # Remove last slash and all that follows it. Not all systems have dirname. + ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'` + if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then + # The file is in a subdirectory. + test ! -d "$ac_dir" && mkdir "$ac_dir" + fi rm -f $ac_file mv conftest.h $ac_file fi diff --git a/gnu/usr.bin/binutils/opcodes/configure.in b/gnu/usr.bin/binutils/opcodes/configure.in index 947a3ffbc3f..2ca6dd98b24 100644 --- a/gnu/usr.bin/binutils/opcodes/configure.in +++ b/gnu/usr.bin/binutils/opcodes/configure.in @@ -1,4 +1,4 @@ -AC_PREREQ(2.0) +AC_PREREQ(2.5) AC_INIT(z8k-dis.c) # configure.in script for the opcodes library. # Copyright (C) 1995, 1996 Free Software Foundation, Inc. @@ -111,6 +111,7 @@ AC_SUBST(COMMON_SHLIB) AC_SUBST(SHLIB_DEP) AC_SUBST(BFD_PICLIST) AC_SUBST(SHLINK) +AC_SUBST(INSTALL_SHLIB) AC_CHECK_HEADERS(string.h strings.h) @@ -156,7 +157,7 @@ if test x${all_targets} = xfalse ; then case "$arch" in bfd_a29k_arch) ta="$ta a29k-dis.o" ;; bfd_alliant_arch) ;; - bfd_alpha_arch) ta="$ta alpha-dis.o" ;; + bfd_alpha_arch) ta="$ta alpha-dis.o alpha-opc.o" ;; bfd_arm_arch) ta="$ta arm-dis.o" ;; bfd_convex_arch) ;; bfd_h8300_arch) ta="$ta h8300-dis.o" ;; diff --git a/gnu/usr.bin/binutils/opcodes/disassemble.c b/gnu/usr.bin/binutils/opcodes/disassemble.c index b5d37aed476..02adfe6a209 100644 --- a/gnu/usr.bin/binutils/opcodes/disassemble.c +++ b/gnu/usr.bin/binutils/opcodes/disassemble.c @@ -73,6 +73,8 @@ disassembler (abfd) case bfd_arch_h8300: if (bfd_get_mach(abfd) == bfd_mach_h8300h) disassemble = print_insn_h8300h; + else if (bfd_get_mach(abfd) == bfd_mach_h8300s) + disassemble = print_insn_h8300s; else disassemble = print_insn_h8300; break; diff --git a/gnu/usr.bin/binutils/opcodes/h8300-dis.c b/gnu/usr.bin/binutils/opcodes/h8300-dis.c index a25aa31d428..31f5edf3444 100644 --- a/gnu/usr.bin/binutils/opcodes/h8300-dis.c +++ b/gnu/usr.bin/binutils/opcodes/h8300-dis.c @@ -64,10 +64,10 @@ bfd_h8_disassemble_init () unsigned int -bfd_h8_disassemble (addr, info, hmode) +bfd_h8_disassemble (addr, info, mode) bfd_vma addr; disassemble_info *info; - int hmode; + int mode; { /* Find the first entry in the table for this opcode */ static CONST char *regnames[] = @@ -96,7 +96,7 @@ bfd_h8_disassemble (addr, info, hmode) int plen = 0; static boolean init = 0; struct h8_opcode *q = h8_opcodes; - char CONST **pregnames = hmode ? lregnames : wregnames; + char CONST **pregnames = mode != 0 ? lregnames : wregnames; int status; int l; @@ -234,6 +234,8 @@ bfd_h8_disassemble (addr, info, hmode) case 0: abs = 1; break; + default: + goto fail; } } else if (looking_for & L_8) @@ -243,13 +245,16 @@ bfd_h8_disassemble (addr, info, hmode) } else if (looking_for & L_3) { - plen = 3; - bit = thisnib; + bit = thisnib & 0x7; } else if (looking_for & L_2) { plen = 2; - abs = thisnib; + abs = thisnib & 0x3; + } + else if (looking_for & MACREG) + { + abs = (thisnib == 3); } else if (looking_for == E) { @@ -267,6 +272,30 @@ bfd_h8_disassemble (addr, info, hmode) } } fprintf (stream, "%s\t", q->name); + + /* Gross. Disgusting. */ + if (strcmp (q->name, "ldm.l") == 0) + { + int count, high; + + count = (data[1] >> 4) & 0x3; + high = data[3] & 0x7; + + fprintf (stream, "@sp+,er%d-er%d", high - count, high); + return q->length; + } + + if (strcmp (q->name, "stm.l") == 0) + { + int count, low; + + count = (data[1] >> 4) & 0x3; + low = data[3] & 0x7; + + fprintf (stream, "er%d-er%d,@-sp", low, low + count); + return q->length; + } + /* Fill in the args */ { op_type *args = q->args.nib; @@ -286,6 +315,10 @@ bfd_h8_disassemble (addr, info, hmode) } else if (x & (IMM|KBIT|DBIT)) { + /* Bletch. For shal #2,er0 and friends. */ + if (*(args+1) & SRC_IN_DST) + abs = 2; + fprintf (stream, "#0x%x", (unsigned) abs); } else if (x & REG) @@ -306,7 +339,10 @@ bfd_h8_disassemble (addr, info, hmode) } } - + else if (x & MACREG) + { + fprintf (stream, "mac%c", abs ? 'l' : 'h'); + } else if (x & INC) { fprintf (stream, "@%s+", pregnames[rs]); @@ -322,7 +358,12 @@ bfd_h8_disassemble (addr, info, hmode) fprintf (stream, "@%s", pregnames[rn]); } - else if (x & (ABS|ABSJMP|ABS8MEM)) + else if (x & ABS8MEM) + { + fprintf (stream, "@0x%x:8", (unsigned) abs); + } + + else if (x & (ABS|ABSJMP)) { fprintf (stream, "@0x%x:%d", (unsigned) abs, plen); } @@ -352,9 +393,12 @@ bfd_h8_disassemble (addr, info, hmode) else if (x & CCR) { - fprintf (stream, "ccr"); } + else if (x & EXR) + { + fprintf (stream, "exr"); + } else fprintf (stream, "Hmmmm %x", x); @@ -395,7 +439,7 @@ disassemble_info *info; return bfd_h8_disassemble (addr, info , 0); } - int +int print_insn_h8300h (addr, info) bfd_vma addr; disassemble_info *info; @@ -403,3 +447,10 @@ disassemble_info *info; return bfd_h8_disassemble (addr, info , 1); } +int +print_insn_h8300s (addr, info) +bfd_vma addr; +disassemble_info *info; +{ + return bfd_h8_disassemble (addr, info , 2); +} diff --git a/gnu/usr.bin/binutils/opcodes/i386-dis.c b/gnu/usr.bin/binutils/opcodes/i386-dis.c index b8c11cf887a..4e1024d6270 100644 --- a/gnu/usr.bin/binutils/opcodes/i386-dis.c +++ b/gnu/usr.bin/binutils/opcodes/i386-dis.c @@ -97,7 +97,9 @@ fetch_data (info, addr) #define Iw OP_I, w_mode #define Jb OP_J, b_mode #define Jv OP_J, v_mode +#if 0 #define ONE OP_ONE, 0 +#endif #define Cd OP_C, d_mode #define Dd OP_D, d_mode #define Td OP_T, d_mode @@ -139,13 +141,22 @@ fetch_data (info, addr) #define fs OP_REG, fs_reg #define gs OP_REG, gs_reg -int OP_E(), OP_indirE(), OP_G(), OP_I(), OP_sI(), OP_REG(); -int OP_J(), OP_SEG(); -int OP_DIR(), OP_OFF(), OP_DSSI(), OP_ESDI(), OP_ONE(), OP_C(); -int OP_D(), OP_T(), OP_rm(); +typedef int op_rtn PARAMS ((int bytemode, int aflag, int dflag)); -static void dofloat (), putop (), append_prefix (), set_op (); -static int get16 (), get32 (); +static op_rtn OP_E, OP_G, OP_I, OP_indirE, OP_sI, OP_REG, OP_J, OP_DIR, OP_OFF; +static op_rtn OP_ESDI, OP_DSSI, OP_SEG, OP_C, OP_D, OP_T, OP_rm, OP_ST; +static op_rtn OP_STi; +#if 0 +static op_rtn OP_ONE; +#endif + +static void append_prefix PARAMS ((void)); +static void set_op PARAMS ((int op)); +static void putop PARAMS ((char *template, int aflag, int dflag)); +static void dofloat PARAMS ((int aflag, int dflag)); +static int get16 PARAMS ((void)); +static int get32 PARAMS ((void)); +static void ckprefix PARAMS ((void)); #define b_mode 1 #define v_mode 2 @@ -212,15 +223,15 @@ static int get16 (), get32 (); struct dis386 { char *name; - int (*op1)(); + op_rtn *op1; int bytemode1; - int (*op2)(); + op_rtn *op2; int bytemode2; - int (*op3)(); + op_rtn *op3; int bytemode3; }; -struct dis386 dis386[] = { +static struct dis386 dis386[] = { /* 00 */ { "addb", Eb, Gb }, { "addS", Ev, Gv }, @@ -511,7 +522,7 @@ struct dis386 dis386[] = { { GRP5 }, }; -struct dis386 dis386_twobyte[] = { +static struct dis386 dis386_twobyte[] = { /* 00 */ { GRP6 }, { GRP7 }, @@ -732,7 +743,7 @@ static disassemble_info *the_info; static int mod; static int rm; static int reg; -static void oappend (); +static void oappend PARAMS ((char *s)); static char *names32[]={ "%eax","%ecx","%edx","%ebx", "%esp","%ebp","%esi","%edi", @@ -750,7 +761,7 @@ static char *index16[] = { "bx+si","bx+di","bp+si","bp+di","si","di","bp","bx" }; -struct dis386 grps[][8] = { +static struct dis386 grps[][8] = { /* GRP1b */ { { "addb", Eb, Ib }, @@ -1007,9 +1018,6 @@ ckprefix () } } -static int dflag; -static int aflag; - static char op1out[100], op2out[100], op3out[100]; static int op_address[3], op_ad, op_index[3]; static int start_pc; @@ -1024,11 +1032,26 @@ static int start_pc; * The function returns the length of this instruction in bytes. */ +int print_insn_x86 PARAMS ((bfd_vma pc, disassemble_info *info, int aflag, + int dflag)); int print_insn_i386 (pc, info) bfd_vma pc; disassemble_info *info; { + if (info->mach == bfd_mach_i386_i386) + return print_insn_x86 (pc, info, 1, 1); + else if (info->mach == bfd_mach_i386_i8086) + return print_insn_x86 (pc, info, 0, 0); + else + abort (); +} + +int +print_insn_x86 (pc, info, aflag, dflag) + bfd_vma pc; + disassemble_info *info; +{ struct dis386 *dp; int i; int enter_instruction; @@ -1083,10 +1106,6 @@ print_insn_i386 (pc, info) return (1); } - /* these would be initialized to 0 if disassembling for 8086 or 286 */ - dflag = 1; - aflag = 1; - if (prefixes & PREFIX_DATA) dflag ^= 1; @@ -1119,29 +1138,29 @@ print_insn_i386 (pc, info) if (dp->name == NULL && dp->bytemode1 == FLOATCODE) { - dofloat (); + dofloat (aflag, dflag); } else { if (dp->name == NULL) dp = &grps[dp->bytemode1][reg]; - putop (dp->name); + putop (dp->name, aflag, dflag); obufp = op1out; op_ad = 2; if (dp->op1) - (*dp->op1)(dp->bytemode1); + (*dp->op1)(dp->bytemode1, aflag, dflag); obufp = op2out; op_ad = 1; if (dp->op2) - (*dp->op2)(dp->bytemode2); + (*dp->op2)(dp->bytemode2, aflag, dflag); obufp = op3out; op_ad = 0; if (dp->op3) - (*dp->op3)(dp->bytemode3); + (*dp->op3)(dp->bytemode3, aflag, dflag); } obufp = obuf + strlen (obuf); @@ -1200,7 +1219,7 @@ print_insn_i386 (pc, info) return (codep - inbuf); } -char *float_mem[] = { +static char *float_mem[] = { /* d8 */ "fadds", "fmuls", @@ -1277,7 +1296,6 @@ char *float_mem[] = { #define ST OP_ST, 0 #define STi OP_STi, 0 -int OP_ST(), OP_STi(); #define FGRPd9_2 NULL, NULL, 0 #define FGRPd9_4 NULL, NULL, 1 @@ -1289,7 +1307,7 @@ int OP_ST(), OP_STi(); #define FGRPde_3 NULL, NULL, 7 #define FGRPdf_4 NULL, NULL, 8 -struct dis386 float_reg[][8] = { +static struct dis386 float_reg[][8] = { /* d8 */ { { "fadd", ST, STi }, @@ -1381,7 +1399,7 @@ struct dis386 float_reg[][8] = { }; -char *fgrps[][8] = { +static char *fgrps[][8] = { /* d9_2 0 */ { "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", @@ -1430,7 +1448,9 @@ char *fgrps[][8] = { }; static void -dofloat () +dofloat (aflag, dflag) + int aflag; + int dflag; { struct dis386 *dp; unsigned char floatop; @@ -1439,9 +1459,9 @@ dofloat () if (mod != 3) { - putop (float_mem[(floatop - 0xd8) * 8 + reg]); + putop (float_mem[(floatop - 0xd8) * 8 + reg], aflag, dflag); obufp = op1out; - OP_E (v_mode); + OP_E (v_mode, aflag, dflag); return; } codep++; @@ -1449,7 +1469,7 @@ dofloat () dp = &float_reg[floatop - 0xd8][reg]; if (dp->name == NULL) { - putop (fgrps[dp->bytemode1][rm]); + putop (fgrps[dp->bytemode1][rm], aflag, dflag); /* instruction fnstsw is only one with strange arg */ if (floatop == 0xdf && FETCH_DATA (the_info, codep + 1) @@ -1458,29 +1478,33 @@ dofloat () } else { - putop (dp->name); + putop (dp->name, aflag, dflag); obufp = op1out; if (dp->op1) - (*dp->op1)(dp->bytemode1); + (*dp->op1)(dp->bytemode1, aflag, dflag); obufp = op2out; if (dp->op2) - (*dp->op2)(dp->bytemode2); + (*dp->op2)(dp->bytemode2, aflag, dflag); } } /* ARGSUSED */ -int -OP_ST (ignore) +static int +OP_ST (ignore, aflag, dflag) int ignore; + int aflag; + int dflag; { oappend ("%st"); return (0); } /* ARGSUSED */ -int -OP_STi (ignore) +static int +OP_STi (ignore, aflag, dflag) int ignore; + int aflag; + int dflag; { sprintf (scratchbuf, "%%st(%d)", rm); oappend (scratchbuf); @@ -1490,8 +1514,10 @@ OP_STi (ignore) /* capital letters in template are macros */ static void -putop (template) +putop (template, aflag, dflag) char *template; + int aflag; + int dflag; { char *p; @@ -1548,17 +1574,21 @@ append_prefix () oappend ("%gs:"); } -int -OP_indirE (bytemode) +static int +OP_indirE (bytemode, aflag, dflag) int bytemode; + int aflag; + int dflag; { oappend ("*"); - return OP_E (bytemode); + return OP_E (bytemode, aflag, dflag); } -int -OP_E (bytemode) +static int +OP_E (bytemode, aflag, dflag) int bytemode; + int aflag; + int dflag; { int disp; @@ -1688,9 +1718,11 @@ OP_E (bytemode) return 0; } -int -OP_G (bytemode) +static int +OP_G (bytemode, aflag, dflag) int bytemode; + int aflag; + int dflag; { switch (bytemode) { @@ -1748,9 +1780,11 @@ set_op (op) op_address[op_ad] = op; } -int -OP_REG (code) +static int +OP_REG (code, aflag, dflag) int code; + int aflag; + int dflag; { char *s; @@ -1784,9 +1818,11 @@ OP_REG (code) return (0); } -int -OP_I (bytemode) +static int +OP_I (bytemode, aflag, dflag) int bytemode; + int aflag; + int dflag; { int op; @@ -1814,9 +1850,11 @@ OP_I (bytemode) return (0); } -int -OP_sI (bytemode) +static int +OP_sI (bytemode, aflag, dflag) int bytemode; + int aflag; + int dflag; { int op; @@ -1844,9 +1882,11 @@ OP_sI (bytemode) return (0); } -int -OP_J (bytemode) +static int +OP_J (bytemode, aflag, dflag) int bytemode; + int aflag; + int dflag; { int disp; int mask = -1; @@ -1881,9 +1921,11 @@ OP_J (bytemode) } /* ARGSUSED */ -int -OP_SEG (dummy) +static int +OP_SEG (dummy, aflag, dflag) int dummy; + int aflag; + int dflag; { static char *sreg[] = { "%es","%cs","%ss","%ds","%fs","%gs","%?","%?", @@ -1893,9 +1935,11 @@ OP_SEG (dummy) return (0); } -int -OP_DIR (size) +static int +OP_DIR (size, aflag, dflag) int size; + int aflag; + int dflag; { int seg, offset; @@ -1934,9 +1978,11 @@ OP_DIR (size) } /* ARGSUSED */ -int -OP_OFF (bytemode) +static int +OP_OFF (bytemode, aflag, dflag) int bytemode; + int aflag; + int dflag; { int off; @@ -1953,9 +1999,11 @@ OP_OFF (bytemode) } /* ARGSUSED */ -int -OP_ESDI (dummy) - int dummy; +static int +OP_ESDI (dummy, aflag, dflag) + int dummy; + int aflag; + int dflag; { oappend ("%es:("); oappend (aflag ? "%edi" : "%di"); @@ -1964,9 +2012,11 @@ OP_ESDI (dummy) } /* ARGSUSED */ -int -OP_DSSI (dummy) - int dummy; +static int +OP_DSSI (dummy, aflag, dflag) + int dummy; + int aflag; + int dflag; { oappend ("%ds:("); oappend (aflag ? "%esi" : "%si"); @@ -1974,19 +2024,28 @@ OP_DSSI (dummy) return (0); } +#if 0 +/* Not used. */ + /* ARGSUSED */ -int -OP_ONE (dummy) - int dummy; +static int +OP_ONE (dummy, aflag, dflag) + int dummy; + int aflag; + int dflag; { oappend ("1"); return (0); } +#endif + /* ARGSUSED */ -int -OP_C (dummy) - int dummy; +static int +OP_C (dummy, aflag, dflag) + int dummy; + int aflag; + int dflag; { codep++; /* skip mod/rm */ sprintf (scratchbuf, "%%cr%d", reg); @@ -1995,9 +2054,11 @@ OP_C (dummy) } /* ARGSUSED */ -int -OP_D (dummy) - int dummy; +static int +OP_D (dummy, aflag, dflag) + int dummy; + int aflag; + int dflag; { codep++; /* skip mod/rm */ sprintf (scratchbuf, "%%db%d", reg); @@ -2006,9 +2067,11 @@ OP_D (dummy) } /* ARGSUSED */ -int -OP_T (dummy) +static int +OP_T (dummy, aflag, dflag) int dummy; + int aflag; + int dflag; { codep++; /* skip mod/rm */ sprintf (scratchbuf, "%%tr%d", reg); @@ -2016,9 +2079,11 @@ OP_T (dummy) return (0); } -int -OP_rm (bytemode) +static int +OP_rm (bytemode, aflag, dflag) int bytemode; + int aflag; + int dflag; { switch (bytemode) { diff --git a/gnu/usr.bin/binutils/opcodes/m68k-opc.c b/gnu/usr.bin/binutils/opcodes/m68k-opc.c index 5e46578714f..819de45b604 100644 --- a/gnu/usr.bin/binutils/opcodes/m68k-opc.c +++ b/gnu/usr.bin/binutils/opcodes/m68k-opc.c @@ -30,151 +30,151 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA const struct m68k_opcode m68k_opcodes[] = { -{"abcd", one(0140400), one(0170770), "DsDd", m68000up }, -{"abcd", one(0140410), one(0170770), "-s-d", m68000up }, +{"abcd", one(0140400), one(0170770), "DsDd", m68000up }, +{"abcd", one(0140410), one(0170770), "-s-d", m68000up }, -{"addaw", one(0150300), one(0170700), "*wAd", m68000up }, -{"addal", one(0150700), one(0170700), "*lAd", m68000up }, +{"addaw", one(0150300), one(0170700), "*wAd", m68000up }, +{"addal", one(0150700), one(0170700), "*lAd", m68000up | mcf5200 }, -{"addib", one(0003000), one(0177700), "#b$b", m68000up }, -{"addiw", one(0003100), one(0177700), "#w$w", m68000up }, -{"addil", one(0003200), one(0177700), "#l$l", m68000up }, +{"addib", one(0003000), one(0177700), "#b$b", m68000up }, +{"addiw", one(0003100), one(0177700), "#w$w", m68000up }, +{"addil", one(0003200), one(0177700), "#l$l", m68000up | mcf5200 }, -{"addqb", one(0050000), one(0170700), "Qd$b", m68000up }, -{"addqw", one(0050100), one(0170700), "Qd%w", m68000up }, -{"addql", one(0050200), one(0170700), "Qd%l", m68000up }, +{"addqb", one(0050000), one(0170700), "Qd$b", m68000up }, +{"addqw", one(0050100), one(0170700), "Qd%w", m68000up }, +{"addql", one(0050200), one(0170700), "Qd%l", m68000up | mcf5200 }, /* The add opcode can generate the adda, addi, and addq instructions. */ -{"addb", one(0050000), one(0170700), "Qd$b", m68000up }, -{"addb", one(0003000), one(0177700), "#b$b", m68000up }, -{"addb", one(0150000), one(0170700), ";bDd", m68000up }, -{"addb", one(0150400), one(0170700), "Dd~b", m68000up }, -{"addw", one(0050100), one(0170700), "Qd%w", m68000up }, -{"addw", one(0150300), one(0170700), "*wAd", m68000up }, -{"addw", one(0003100), one(0177700), "#w$w", m68000up }, -{"addw", one(0150100), one(0170700), "*wDd", m68000up }, -{"addw", one(0150500), one(0170700), "Dd~w", m68000up }, -{"addl", one(0050200), one(0170700), "Qd%l", m68000up }, -{"addl", one(0003200), one(0177700), "#l$l", m68000up }, -{"addl", one(0150700), one(0170700), "*lAd", m68000up }, -{"addl", one(0150200), one(0170700), "*lDd", m68000up }, -{"addl", one(0150600), one(0170700), "Dd~l", m68000up }, - -{"addxb", one(0150400), one(0170770), "DsDd", m68000up }, -{"addxb", one(0150410), one(0170770), "-s-d", m68000up }, -{"addxw", one(0150500), one(0170770), "DsDd", m68000up }, -{"addxw", one(0150510), one(0170770), "-s-d", m68000up }, -{"addxl", one(0150600), one(0170770), "DsDd", m68000up }, -{"addxl", one(0150610), one(0170770), "-s-d", m68000up }, - -{"andib", one(0001000), one(0177700), "#b$b", m68000up }, -{"andib", one(0001074), one(0177777), "#bCb", m68000up }, -{"andiw", one(0001100), one(0177700), "#w$w", m68000up }, -{"andiw", one(0001174), one(0177777), "#wSw", m68000up }, -{"andil", one(0001200), one(0177700), "#l$l", m68000up }, -{"andi", one(0001100), one(0177700), "#w$w", m68000up }, -{"andi", one(0001074), one(0177777), "#bCb", m68000up }, -{"andi", one(0001174), one(0177777), "#wSw", m68000up }, +{"addb", one(0050000), one(0170700), "Qd$b", m68000up }, +{"addb", one(0003000), one(0177700), "#b$b", m68000up }, +{"addb", one(0150000), one(0170700), ";bDd", m68000up }, +{"addb", one(0150400), one(0170700), "Dd~b", m68000up }, +{"addw", one(0050100), one(0170700), "Qd%w", m68000up }, +{"addw", one(0150300), one(0170700), "*wAd", m68000up }, +{"addw", one(0003100), one(0177700), "#w$w", m68000up }, +{"addw", one(0150100), one(0170700), "*wDd", m68000up }, +{"addw", one(0150500), one(0170700), "Dd~w", m68000up }, +{"addl", one(0050200), one(0170700), "Qd%l", m68000up | mcf5200 }, +{"addl", one(0003200), one(0177700), "#l$l", m68000up | mcf5200 }, +{"addl", one(0150700), one(0170700), "*lAd", m68000up | mcf5200 }, +{"addl", one(0150200), one(0170700), "*lDd", m68000up | mcf5200 }, +{"addl", one(0150600), one(0170700), "Dd~l", m68000up | mcf5200 }, + +{"addxb", one(0150400), one(0170770), "DsDd", m68000up }, +{"addxb", one(0150410), one(0170770), "-s-d", m68000up }, +{"addxw", one(0150500), one(0170770), "DsDd", m68000up }, +{"addxw", one(0150510), one(0170770), "-s-d", m68000up }, +{"addxl", one(0150600), one(0170770), "DsDd", m68000up | mcf5200 }, +{"addxl", one(0150610), one(0170770), "-s-d", m68000up }, + +{"andib", one(0001000), one(0177700), "#b$b", m68000up }, +{"andib", one(0001074), one(0177777), "#bCb", m68000up }, +{"andiw", one(0001100), one(0177700), "#w$w", m68000up }, +{"andiw", one(0001174), one(0177777), "#wSw", m68000up }, +{"andil", one(0001200), one(0177700), "#l$l", m68000up | mcf5200 }, +{"andi", one(0001100), one(0177700), "#w$w", m68000up }, +{"andi", one(0001074), one(0177777), "#bCb", m68000up }, +{"andi", one(0001174), one(0177777), "#wSw", m68000up }, /* The and opcode can generate the andi instruction. */ -{"andb", one(0001000), one(0177700), "#b$b", m68000up }, -{"andb", one(0001074), one(0177777), "#bCb", m68000up }, -{"andb", one(0140000), one(0170700), ";bDd", m68000up }, -{"andb", one(0140400), one(0170700), "Dd~b", m68000up }, -{"andw", one(0001100), one(0177700), "#w$w", m68000up }, -{"andw", one(0001174), one(0177777), "#wSw", m68000up }, -{"andw", one(0140100), one(0170700), ";wDd", m68000up }, -{"andw", one(0140500), one(0170700), "Dd~w", m68000up }, -{"andl", one(0001200), one(0177700), "#l$l", m68000up }, -{"andl", one(0140200), one(0170700), ";lDd", m68000up }, -{"andl", one(0140600), one(0170700), "Dd~l", m68000up }, -{"and", one(0001100), one(0177700), "#w$w", m68000up }, -{"and", one(0001074), one(0177777), "#bCb", m68000up }, -{"and", one(0001174), one(0177777), "#wSw", m68000up }, -{"and", one(0140100), one(0170700), ";wDd", m68000up }, -{"and", one(0140500), one(0170700), "Dd~w", m68000up }, - -{"aslb", one(0160400), one(0170770), "QdDs", m68000up }, -{"aslb", one(0160440), one(0170770), "DdDs", m68000up }, -{"aslw", one(0160500), one(0170770), "QdDs", m68000up }, -{"aslw", one(0160540), one(0170770), "DdDs", m68000up }, -{"aslw", one(0160700), one(0177700), "~s", m68000up }, -{"asll", one(0160600), one(0170770), "QdDs", m68000up }, -{"asll", one(0160640), one(0170770), "DdDs", m68000up }, - -{"asrb", one(0160000), one(0170770), "QdDs", m68000up }, -{"asrb", one(0160040), one(0170770), "DdDs", m68000up }, -{"asrw", one(0160100), one(0170770), "QdDs", m68000up }, -{"asrw", one(0160140), one(0170770), "DdDs", m68000up }, -{"asrw", one(0160300), one(0177700), "~s", m68000up }, -{"asrl", one(0160200), one(0170770), "QdDs", m68000up }, -{"asrl", one(0160240), one(0170770), "DdDs", m68000up }, - -{"bhiw", one(0061000), one(0177777), "BW", m68000up }, -{"blsw", one(0061400), one(0177777), "BW", m68000up }, -{"bccw", one(0062000), one(0177777), "BW", m68000up }, -{"bcsw", one(0062400), one(0177777), "BW", m68000up }, -{"bnew", one(0063000), one(0177777), "BW", m68000up }, -{"beqw", one(0063400), one(0177777), "BW", m68000up }, -{"bvcw", one(0064000), one(0177777), "BW", m68000up }, -{"bvsw", one(0064400), one(0177777), "BW", m68000up }, -{"bplw", one(0065000), one(0177777), "BW", m68000up }, -{"bmiw", one(0065400), one(0177777), "BW", m68000up }, -{"bgew", one(0066000), one(0177777), "BW", m68000up }, -{"bltw", one(0066400), one(0177777), "BW", m68000up }, -{"bgtw", one(0067000), one(0177777), "BW", m68000up }, -{"blew", one(0067400), one(0177777), "BW", m68000up }, - -{"bhil", one(0061377), one(0177777), "BL", m68020up | cpu32 }, -{"blsl", one(0061777), one(0177777), "BL", m68020up | cpu32 }, -{"bccl", one(0062377), one(0177777), "BL", m68020up | cpu32 }, -{"bcsl", one(0062777), one(0177777), "BL", m68020up | cpu32 }, -{"bnel", one(0063377), one(0177777), "BL", m68020up | cpu32 }, -{"beql", one(0063777), one(0177777), "BL", m68020up | cpu32 }, -{"bvcl", one(0064377), one(0177777), "BL", m68020up | cpu32 }, -{"bvsl", one(0064777), one(0177777), "BL", m68020up | cpu32 }, -{"bpll", one(0065377), one(0177777), "BL", m68020up | cpu32 }, -{"bmil", one(0065777), one(0177777), "BL", m68020up | cpu32 }, -{"bgel", one(0066377), one(0177777), "BL", m68020up | cpu32 }, -{"bltl", one(0066777), one(0177777), "BL", m68020up | cpu32 }, -{"bgtl", one(0067377), one(0177777), "BL", m68020up | cpu32 }, -{"blel", one(0067777), one(0177777), "BL", m68020up | cpu32 }, - -{"bhis", one(0061000), one(0177400), "BB", m68000up }, -{"blss", one(0061400), one(0177400), "BB", m68000up }, -{"bccs", one(0062000), one(0177400), "BB", m68000up }, -{"bcss", one(0062400), one(0177400), "BB", m68000up }, -{"bnes", one(0063000), one(0177400), "BB", m68000up }, -{"beqs", one(0063400), one(0177400), "BB", m68000up }, -{"bvcs", one(0064000), one(0177400), "BB", m68000up }, -{"bvss", one(0064400), one(0177400), "BB", m68000up }, -{"bpls", one(0065000), one(0177400), "BB", m68000up }, -{"bmis", one(0065400), one(0177400), "BB", m68000up }, -{"bges", one(0066000), one(0177400), "BB", m68000up }, -{"blts", one(0066400), one(0177400), "BB", m68000up }, -{"bgts", one(0067000), one(0177400), "BB", m68000up }, -{"bles", one(0067400), one(0177400), "BB", m68000up }, - -{"jhi", one(0061000), one(0177400), "Bg", m68000up }, -{"jls", one(0061400), one(0177400), "Bg", m68000up }, -{"jcc", one(0062000), one(0177400), "Bg", m68000up }, -{"jcs", one(0062400), one(0177400), "Bg", m68000up }, -{"jne", one(0063000), one(0177400), "Bg", m68000up }, -{"jeq", one(0063400), one(0177400), "Bg", m68000up }, -{"jvc", one(0064000), one(0177400), "Bg", m68000up }, -{"jvs", one(0064400), one(0177400), "Bg", m68000up }, -{"jpl", one(0065000), one(0177400), "Bg", m68000up }, -{"jmi", one(0065400), one(0177400), "Bg", m68000up }, -{"jge", one(0066000), one(0177400), "Bg", m68000up }, -{"jlt", one(0066400), one(0177400), "Bg", m68000up }, -{"jgt", one(0067000), one(0177400), "Bg", m68000up }, -{"jle", one(0067400), one(0177400), "Bg", m68000up }, - -{"bchg", one(0000500), one(0170700), "Dd$s", m68000up }, -{"bchg", one(0004100), one(0177700), "#b$s", m68000up }, - -{"bclr", one(0000600), one(0170700), "Dd$s", m68000up }, -{"bclr", one(0004200), one(0177700), "#b$s", m68000up }, +{"andb", one(0001000), one(0177700), "#b$b", m68000up }, +{"andb", one(0001074), one(0177777), "#bCb", m68000up }, +{"andb", one(0140000), one(0170700), ";bDd", m68000up }, +{"andb", one(0140400), one(0170700), "Dd~b", m68000up }, +{"andw", one(0001100), one(0177700), "#w$w", m68000up }, +{"andw", one(0001174), one(0177777), "#wSw", m68000up }, +{"andw", one(0140100), one(0170700), ";wDd", m68000up }, +{"andw", one(0140500), one(0170700), "Dd~w", m68000up }, +{"andl", one(0001200), one(0177700), "#l$l", m68000up | mcf5200 }, +{"andl", one(0140200), one(0170700), ";lDd", m68000up | mcf5200 }, +{"andl", one(0140600), one(0170700), "Dd~l", m68000up | mcf5200 }, +{"and", one(0001100), one(0177700), "#w$w", m68000up }, +{"and", one(0001074), one(0177777), "#bCb", m68000up }, +{"and", one(0001174), one(0177777), "#wSw", m68000up }, +{"and", one(0140100), one(0170700), ";wDd", m68000up }, +{"and", one(0140500), one(0170700), "Dd~w", m68000up }, + +{"aslb", one(0160400), one(0170770), "QdDs", m68000up }, +{"aslb", one(0160440), one(0170770), "DdDs", m68000up }, +{"aslw", one(0160500), one(0170770), "QdDs", m68000up }, +{"aslw", one(0160540), one(0170770), "DdDs", m68000up }, +{"aslw", one(0160700), one(0177700), "~s", m68000up }, +{"asll", one(0160600), one(0170770), "QdDs", m68000up | mcf5200 }, +{"asll", one(0160640), one(0170770), "DdDs", m68000up | mcf5200 }, + +{"asrb", one(0160000), one(0170770), "QdDs", m68000up }, +{"asrb", one(0160040), one(0170770), "DdDs", m68000up }, +{"asrw", one(0160100), one(0170770), "QdDs", m68000up }, +{"asrw", one(0160140), one(0170770), "DdDs", m68000up }, +{"asrw", one(0160300), one(0177700), "~s", m68000up }, +{"asrl", one(0160200), one(0170770), "QdDs", m68000up | mcf5200 }, +{"asrl", one(0160240), one(0170770), "DdDs", m68000up | mcf5200 }, + +{"bhiw", one(0061000), one(0177777), "BW", m68000up | mcf5200 }, +{"blsw", one(0061400), one(0177777), "BW", m68000up | mcf5200 }, +{"bccw", one(0062000), one(0177777), "BW", m68000up | mcf5200 }, +{"bcsw", one(0062400), one(0177777), "BW", m68000up | mcf5200 }, +{"bnew", one(0063000), one(0177777), "BW", m68000up | mcf5200 }, +{"beqw", one(0063400), one(0177777), "BW", m68000up | mcf5200 }, +{"bvcw", one(0064000), one(0177777), "BW", m68000up | mcf5200 }, +{"bvsw", one(0064400), one(0177777), "BW", m68000up | mcf5200 }, +{"bplw", one(0065000), one(0177777), "BW", m68000up | mcf5200 }, +{"bmiw", one(0065400), one(0177777), "BW", m68000up | mcf5200 }, +{"bgew", one(0066000), one(0177777), "BW", m68000up | mcf5200 }, +{"bltw", one(0066400), one(0177777), "BW", m68000up | mcf5200 }, +{"bgtw", one(0067000), one(0177777), "BW", m68000up | mcf5200 }, +{"blew", one(0067400), one(0177777), "BW", m68000up | mcf5200 }, + +{"bhil", one(0061377), one(0177777), "BL", m68020up | cpu32 }, +{"blsl", one(0061777), one(0177777), "BL", m68020up | cpu32 }, +{"bccl", one(0062377), one(0177777), "BL", m68020up | cpu32 }, +{"bcsl", one(0062777), one(0177777), "BL", m68020up | cpu32 }, +{"bnel", one(0063377), one(0177777), "BL", m68020up | cpu32 }, +{"beql", one(0063777), one(0177777), "BL", m68020up | cpu32 }, +{"bvcl", one(0064377), one(0177777), "BL", m68020up | cpu32 }, +{"bvsl", one(0064777), one(0177777), "BL", m68020up | cpu32 }, +{"bpll", one(0065377), one(0177777), "BL", m68020up | cpu32 }, +{"bmil", one(0065777), one(0177777), "BL", m68020up | cpu32 }, +{"bgel", one(0066377), one(0177777), "BL", m68020up | cpu32 }, +{"bltl", one(0066777), one(0177777), "BL", m68020up | cpu32 }, +{"bgtl", one(0067377), one(0177777), "BL", m68020up | cpu32 }, +{"blel", one(0067777), one(0177777), "BL", m68020up | cpu32 }, + +{"bhis", one(0061000), one(0177400), "BB", m68000up | mcf5200 }, +{"blss", one(0061400), one(0177400), "BB", m68000up | mcf5200 }, +{"bccs", one(0062000), one(0177400), "BB", m68000up | mcf5200 }, +{"bcss", one(0062400), one(0177400), "BB", m68000up | mcf5200 }, +{"bnes", one(0063000), one(0177400), "BB", m68000up | mcf5200 }, +{"beqs", one(0063400), one(0177400), "BB", m68000up | mcf5200 }, +{"bvcs", one(0064000), one(0177400), "BB", m68000up | mcf5200 }, +{"bvss", one(0064400), one(0177400), "BB", m68000up | mcf5200 }, +{"bpls", one(0065000), one(0177400), "BB", m68000up | mcf5200 }, +{"bmis", one(0065400), one(0177400), "BB", m68000up | mcf5200 }, +{"bges", one(0066000), one(0177400), "BB", m68000up | mcf5200 }, +{"blts", one(0066400), one(0177400), "BB", m68000up | mcf5200 }, +{"bgts", one(0067000), one(0177400), "BB", m68000up | mcf5200 }, +{"bles", one(0067400), one(0177400), "BB", m68000up | mcf5200 }, + +{"jhi", one(0061000), one(0177400), "Bg", m68000up | mcf5200 }, +{"jls", one(0061400), one(0177400), "Bg", m68000up | mcf5200 }, +{"jcc", one(0062000), one(0177400), "Bg", m68000up | mcf5200 }, +{"jcs", one(0062400), one(0177400), "Bg", m68000up | mcf5200 }, +{"jne", one(0063000), one(0177400), "Bg", m68000up | mcf5200 }, +{"jeq", one(0063400), one(0177400), "Bg", m68000up | mcf5200 }, +{"jvc", one(0064000), one(0177400), "Bg", m68000up | mcf5200 }, +{"jvs", one(0064400), one(0177400), "Bg", m68000up | mcf5200 }, +{"jpl", one(0065000), one(0177400), "Bg", m68000up | mcf5200 }, +{"jmi", one(0065400), one(0177400), "Bg", m68000up | mcf5200 }, +{"jge", one(0066000), one(0177400), "Bg", m68000up | mcf5200 }, +{"jlt", one(0066400), one(0177400), "Bg", m68000up | mcf5200 }, +{"jgt", one(0067000), one(0177400), "Bg", m68000up | mcf5200 }, +{"jle", one(0067400), one(0177400), "Bg", m68000up | mcf5200 }, + +{"bchg", one(0000500), one(0170700), "Dd$s", m68000up | mcf5200 }, +{"bchg", one(0004100), one(0177700), "#b$s", m68000up | mcf5200 }, + +{"bclr", one(0000600), one(0170700), "Dd$s", m68000up | mcf5200 }, +{"bclr", one(0004200), one(0177700), "#b$s", m68000up | mcf5200 }, {"bfchg", two(0165300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, {"bfclr", two(0166300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, @@ -189,19 +189,19 @@ const struct m68k_opcode m68k_opcodes[] = {"bkpt", one(0044110), one(0177770), "ts", m68010up }, -{"braw", one(0060000), one(0177777), "BW", m68000up }, -{"bral", one(0060377), one(0177777), "BL", m68020up | cpu32 }, -{"bras", one(0060000), one(0177400), "BB", m68000up }, +{"braw", one(0060000), one(0177777), "BW", m68000up | mcf5200 }, +{"bral", one(0060377), one(0177777), "BL", m68020up | cpu32 }, +{"bras", one(0060000), one(0177400), "BB", m68000up | mcf5200 }, -{"bset", one(0000700), one(0170700), "Dd$s", m68000up }, -{"bset", one(0004300), one(0177700), "#b$s", m68000up }, +{"bset", one(0000700), one(0170700), "Dd$s", m68000up | mcf5200 }, +{"bset", one(0004300), one(0177700), "#b$s", m68000up | mcf5200 }, -{"bsrw", one(0060400), one(0177777), "BW", m68000up }, -{"bsrl", one(0060777), one(0177777), "BL", m68020up | cpu32 }, -{"bsrs", one(0060400), one(0177400), "BB", m68000up }, +{"bsrw", one(0060400), one(0177777), "BW", m68000up | mcf5200 }, +{"bsrl", one(0060777), one(0177777), "BL", m68020up | cpu32 }, +{"bsrs", one(0060400), one(0177400), "BB", m68000up | mcf5200 }, -{"btst", one(0000400), one(0170700), "Dd@s", m68000up }, -{"btst", one(0004000), one(0177700), "#b@s", m68000up }, +{"btst", one(0000400), one(0170700), "Dd@s", m68000up | mcf5200 }, +{"btst", one(0004000), one(0177700), "#b@s", m68000up | mcf5200 }, {"callm", one(0003300), one(0177700), "#b!s", m68020 }, @@ -231,60 +231,61 @@ const struct m68k_opcode m68k_opcodes[] = {"cpusha", one(0xf420|SCOPE_ALL), one(0xff38), "ce", m68040up }, {"cpushl", one(0xf420|SCOPE_LINE), one(0xff38), "ceas", m68040up }, +{"cpushl", one(0x04e8), one(0xfff8), "as", mcf5200 }, {"cpushp", one(0xf420|SCOPE_PAGE), one(0xff38), "ceas", m68040up }, #undef SCOPE_LINE #undef SCOPE_PAGE #undef SCOPE_ALL -{"clrb", one(0041000), one(0177700), "$s", m68000up }, -{"clrw", one(0041100), one(0177700), "$s", m68000up }, -{"clrl", one(0041200), one(0177700), "$s", m68000up }, +{"clrb", one(0041000), one(0177700), "$s", m68000up | mcf5200 }, +{"clrw", one(0041100), one(0177700), "$s", m68000up | mcf5200 }, +{"clrl", one(0041200), one(0177700), "$s", m68000up | mcf5200 }, {"cmp2b", two(0000300,0), two(0177700,07777), "!sR1", m68020up | cpu32 }, {"cmp2w", two(0001300,0), two(0177700,07777), "!sR1", m68020up | cpu32 }, {"cmp2l", two(0002300,0), two(0177700,07777), "!sR1", m68020up | cpu32 }, -{"cmpaw", one(0130300), one(0170700), "*wAd", m68000up }, -{"cmpal", one(0130700), one(0170700), "*lAd", m68000up }, +{"cmpaw", one(0130300), one(0170700), "*wAd", m68000up }, +{"cmpal", one(0130700), one(0170700), "*lAd", m68000up | mcf5200 }, -{"cmpib", one(0006000), one(0177700), "#b;b", m68000up }, -{"cmpiw", one(0006100), one(0177700), "#w;w", m68000up }, -{"cmpil", one(0006200), one(0177700), "#l;l", m68000up }, +{"cmpib", one(0006000), one(0177700), "#b;b", m68000up }, +{"cmpiw", one(0006100), one(0177700), "#w;w", m68000up }, +{"cmpil", one(0006200), one(0177700), "#l;l", m68000up | mcf5200 }, -{"cmpmb", one(0130410), one(0170770), "+s+d", m68000up }, -{"cmpmw", one(0130510), one(0170770), "+s+d", m68000up }, -{"cmpml", one(0130610), one(0170770), "+s+d", m68000up }, +{"cmpmb", one(0130410), one(0170770), "+s+d", m68000up }, +{"cmpmw", one(0130510), one(0170770), "+s+d", m68000up }, +{"cmpml", one(0130610), one(0170770), "+s+d", m68000up | mcf5200 }, /* The cmp opcode can generate the cmpa, cmpm, and cmpi instructions. */ -{"cmpb", one(0006000), one(0177700), "#b;b", m68000up }, -{"cmpb", one(0130410), one(0170770), "+s+d", m68000up }, -{"cmpb", one(0130000), one(0170700), ";bDd", m68000up }, -{"cmpw", one(0130300), one(0170700), "*wAd", m68000up }, -{"cmpw", one(0006100), one(0177700), "#w;w", m68000up }, -{"cmpw", one(0130510), one(0170770), "+s+d", m68000up }, -{"cmpw", one(0130100), one(0170700), "*wDd", m68000up }, -{"cmpl", one(0130700), one(0170700), "*lAd", m68000up }, -{"cmpl", one(0006200), one(0177700), "#l;l", m68000up }, -{"cmpl", one(0130610), one(0170770), "+s+d", m68000up }, -{"cmpl", one(0130200), one(0170700), "*lDd", m68000up }, - -{"dbcc", one(0052310), one(0177770), "DsBw", m68000up }, -{"dbcs", one(0052710), one(0177770), "DsBw", m68000up }, -{"dbeq", one(0053710), one(0177770), "DsBw", m68000up }, -{"dbf", one(0050710), one(0177770), "DsBw", m68000up }, -{"dbge", one(0056310), one(0177770), "DsBw", m68000up }, -{"dbgt", one(0057310), one(0177770), "DsBw", m68000up }, -{"dbhi", one(0051310), one(0177770), "DsBw", m68000up }, -{"dble", one(0057710), one(0177770), "DsBw", m68000up }, -{"dbls", one(0051710), one(0177770), "DsBw", m68000up }, -{"dblt", one(0056710), one(0177770), "DsBw", m68000up }, -{"dbmi", one(0055710), one(0177770), "DsBw", m68000up }, -{"dbne", one(0053310), one(0177770), "DsBw", m68000up }, -{"dbpl", one(0055310), one(0177770), "DsBw", m68000up }, -{"dbt", one(0050310), one(0177770), "DsBw", m68000up }, -{"dbvc", one(0054310), one(0177770), "DsBw", m68000up }, -{"dbvs", one(0054710), one(0177770), "DsBw", m68000up }, +{"cmpb", one(0006000), one(0177700), "#b;b", m68000up }, +{"cmpb", one(0130410), one(0170770), "+s+d", m68000up }, +{"cmpb", one(0130000), one(0170700), ";bDd", m68000up }, +{"cmpw", one(0130300), one(0170700), "*wAd", m68000up }, +{"cmpw", one(0006100), one(0177700), "#w;w", m68000up }, +{"cmpw", one(0130510), one(0170770), "+s+d", m68000up }, +{"cmpw", one(0130100), one(0170700), "*wDd", m68000up }, +{"cmpl", one(0130700), one(0170700), "*lAd", m68000up | mcf5200 }, +{"cmpl", one(0006200), one(0177700), "#l;l", m68000up | mcf5200 }, +{"cmpl", one(0130610), one(0170770), "+s+d", m68000up | mcf5200 }, +{"cmpl", one(0130200), one(0170700), "*lDd", m68000up | mcf5200 }, + +{"dbcc", one(0052310), one(0177770), "DsBw", m68000up }, +{"dbcs", one(0052710), one(0177770), "DsBw", m68000up }, +{"dbeq", one(0053710), one(0177770), "DsBw", m68000up }, +{"dbf", one(0050710), one(0177770), "DsBw", m68000up }, +{"dbge", one(0056310), one(0177770), "DsBw", m68000up }, +{"dbgt", one(0057310), one(0177770), "DsBw", m68000up }, +{"dbhi", one(0051310), one(0177770), "DsBw", m68000up }, +{"dble", one(0057710), one(0177770), "DsBw", m68000up }, +{"dbls", one(0051710), one(0177770), "DsBw", m68000up }, +{"dblt", one(0056710), one(0177770), "DsBw", m68000up }, +{"dbmi", one(0055710), one(0177770), "DsBw", m68000up }, +{"dbne", one(0053310), one(0177770), "DsBw", m68000up }, +{"dbpl", one(0055310), one(0177770), "DsBw", m68000up }, +{"dbt", one(0050310), one(0177770), "DsBw", m68000up }, +{"dbvc", one(0054310), one(0177770), "DsBw", m68000up }, +{"dbvs", one(0054710), one(0177770), "DsBw", m68000up }, {"divsw", one(0100700), one(0170700), ";wDd", m68000up }, @@ -302,37 +303,37 @@ const struct m68k_opcode m68k_opcodes[] = {"divull", two(0046100,0000000),two(0177700,0107770),";lD3D1",m68020up|cpu32 }, {"divull", two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 }, -{"eorib", one(0005000), one(0177700), "#b$s", m68000up }, -{"eorib", one(0005074), one(0177777), "#bCs", m68000up }, -{"eoriw", one(0005100), one(0177700), "#w$s", m68000up }, -{"eoriw", one(0005174), one(0177777), "#wSs", m68000up }, -{"eoril", one(0005200), one(0177700), "#l$s", m68000up }, -{"eori", one(0005074), one(0177777), "#bCs", m68000up }, -{"eori", one(0005174), one(0177777), "#wSs", m68000up }, -{"eori", one(0005100), one(0177700), "#w$s", m68000up }, +{"eorib", one(0005000), one(0177700), "#b$s", m68000up }, +{"eorib", one(0005074), one(0177777), "#bCs", m68000up }, +{"eoriw", one(0005100), one(0177700), "#w$s", m68000up }, +{"eoriw", one(0005174), one(0177777), "#wSs", m68000up }, +{"eoril", one(0005200), one(0177700), "#l$s", m68000up | mcf5200 }, +{"eori", one(0005074), one(0177777), "#bCs", m68000up }, +{"eori", one(0005174), one(0177777), "#wSs", m68000up }, +{"eori", one(0005100), one(0177700), "#w$s", m68000up }, /* The eor opcode can generate the eori instruction. */ -{"eorb", one(0005000), one(0177700), "#b$s", m68000up }, -{"eorb", one(0005074), one(0177777), "#bCs", m68000up }, -{"eorb", one(0130400), one(0170700), "Dd$s", m68000up }, -{"eorw", one(0005100), one(0177700), "#w$s", m68000up }, -{"eorw", one(0005174), one(0177777), "#wSs", m68000up }, -{"eorw", one(0130500), one(0170700), "Dd$s", m68000up }, -{"eorl", one(0005200), one(0177700), "#l$s", m68000up }, -{"eorl", one(0130600), one(0170700), "Dd$s", m68000up }, -{"eor", one(0005074), one(0177777), "#bCs", m68000up }, -{"eor", one(0005174), one(0177777), "#wSs", m68000up }, -{"eor", one(0005100), one(0177700), "#w$s", m68000up }, -{"eor", one(0130500), one(0170700), "Dd$s", m68000up }, - -{"exg", one(0140500), one(0170770), "DdDs", m68000up }, -{"exg", one(0140510), one(0170770), "AdAs", m68000up }, -{"exg", one(0140610), one(0170770), "DdAs", m68000up }, -{"exg", one(0140610), one(0170770), "AsDd", m68000up }, - -{"extw", one(0044200), one(0177770), "Ds", m68000up }, -{"extl", one(0044300), one(0177770), "Ds", m68000up }, -{"extbl", one(0044700), one(0177770), "Ds", m68020up | cpu32 }, +{"eorb", one(0005000), one(0177700), "#b$s", m68000up }, +{"eorb", one(0005074), one(0177777), "#bCs", m68000up }, +{"eorb", one(0130400), one(0170700), "Dd$s", m68000up }, +{"eorw", one(0005100), one(0177700), "#w$s", m68000up }, +{"eorw", one(0005174), one(0177777), "#wSs", m68000up }, +{"eorw", one(0130500), one(0170700), "Dd$s", m68000up }, +{"eorl", one(0005200), one(0177700), "#l$s", m68000up | mcf5200 }, +{"eorl", one(0130600), one(0170700), "Dd$s", m68000up | mcf5200 }, +{"eor", one(0005074), one(0177777), "#bCs", m68000up }, +{"eor", one(0005174), one(0177777), "#wSs", m68000up }, +{"eor", one(0005100), one(0177700), "#w$s", m68000up }, +{"eor", one(0130500), one(0170700), "Dd$s", m68000up }, + +{"exg", one(0140500), one(0170770), "DdDs", m68000up }, +{"exg", one(0140510), one(0170770), "AdAs", m68000up }, +{"exg", one(0140610), one(0170770), "DdAs", m68000up }, +{"exg", one(0140610), one(0170770), "AsDd", m68000up }, + +{"extw", one(0044200), one(0177770), "Ds", m68000up|mcf5200 }, +{"extl", one(0044300), one(0177770), "Ds", m68000up|mcf5200 }, +{"extbl", one(0044700), one(0177770), "Ds", m68020up|cpu32|mcf5200 }, /* float stuff starts here */ @@ -1184,96 +1185,106 @@ const struct m68k_opcode m68k_opcodes[] = {"ftwotoxx", two(0xF000, 0x4811), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"ftwotoxx", two(0xF000, 0x0011), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"illegal", one(0045374), one(0177777), "", m68000up }, +{"halt", one(0045310), one(0177777), "", mcf5200 }, -{"jmp", one(0047300), one(0177700), "!s", m68000up }, +{"illegal", one(0045374), one(0177777), "", m68000up }, -{"jra", one(0060000), one(0177400), "Bg", m68000up }, -{"jra", one(0047300), one(0177700), "!s", m68000up }, +{"jmp", one(0047300), one(0177700), "!s", m68000up | mcf5200 }, -{"jsr", one(0047200), one(0177700), "!s", m68000up }, +{"jra", one(0060000), one(0177400), "Bg", m68000up | mcf5200 }, +{"jra", one(0047300), one(0177700), "!s", m68000up | mcf5200 }, -{"jbsr", one(0060400), one(0177400), "Bg", m68000up }, -{"jbsr", one(0047200), one(0177700), "!s", m68000up }, +{"jsr", one(0047200), one(0177700), "!s", m68000up | mcf5200 }, -{"lea", one(0040700), one(0170700), "!sAd", m68000up }, +{"jbsr", one(0060400), one(0177400), "Bg", m68000up | mcf5200 }, +{"jbsr", one(0047200), one(0177700), "!s", m68000up | mcf5200 }, + +{"lea", one(0040700), one(0170700), "!sAd", m68000up | mcf5200 }, {"lpstop", two(0174000,0000700), two(0177777,0177777), "", cpu32|m68060 }, -{"linkw", one(0047120), one(0177770), "As#w", m68000up }, +{"linkw", one(0047120), one(0177770), "As#w", m68000up | mcf5200 }, {"linkl", one(0044010), one(0177770), "As#l", m68020up | cpu32 }, -{"link", one(0047120), one(0177770), "As#W", m68000up }, +{"link", one(0047120), one(0177770), "As#W", m68000up | mcf5200 }, {"link", one(0044010), one(0177770), "As#l", m68020up | cpu32 }, -{"lslb", one(0160410), one(0170770), "QdDs", m68000up }, -{"lslb", one(0160450), one(0170770), "DdDs", m68000up }, -{"lslw", one(0160510), one(0170770), "QdDs", m68000up }, -{"lslw", one(0160550), one(0170770), "DdDs", m68000up }, -{"lslw", one(0161700), one(0177700), "~s", m68000up }, -{"lsll", one(0160610), one(0170770), "QdDs", m68000up }, -{"lsll", one(0160650), one(0170770), "DdDs", m68000up }, - -{"lsrb", one(0160010), one(0170770), "QdDs", m68000up }, -{"lsrb", one(0160050), one(0170770), "DdDs", m68000up }, -{"lsrw", one(0160110), one(0170770), "QdDs", m68000up }, -{"lsrw", one(0160150), one(0170770), "DdDs", m68000up }, -{"lsrw", one(0161300), one(0177700), "~s", m68000up }, -{"lsrl", one(0160210), one(0170770), "QdDs", m68000up }, -{"lsrl", one(0160250), one(0170770), "DdDs", m68000up }, - -{"moveal", one(0020100), one(0170700), "*lAd", m68000up }, -{"moveaw", one(0030100), one(0170700), "*wAd", m68000up }, - -{"movec", one(0047173), one(0177777), "R1Jj", m68010up }, -{"movec", one(0047173), one(0177777), "R1#j", m68010up }, -{"movec", one(0047172), one(0177777), "JjR1", m68010up }, -{"movec", one(0047172), one(0177777), "#jR1", m68010up }, - -{"movemw", one(0044200), one(0177700), "Lw&s", m68000up }, -{"movemw", one(0044240), one(0177770), "lw-s", m68000up }, -{"movemw", one(0046200), one(0177700), "!sLw", m68000up }, -{"movemw", one(0046230), one(0177770), "+sLw", m68000up }, -{"movemw", one(0044200), one(0177700), "#w&s", m68000up }, -{"movemw", one(0044240), one(0177770), "#w-s", m68000up }, -{"movemw", one(0046200), one(0177700), "!s#w", m68000up }, -{"movemw", one(0046230), one(0177770), "+s#w", m68000up }, -{"moveml", one(0044300), one(0177700), "Lw&s", m68000up }, -{"moveml", one(0044340), one(0177770), "lw-s", m68000up }, -{"moveml", one(0046300), one(0177700), "!sLw", m68000up }, -{"moveml", one(0046330), one(0177770), "+sLw", m68000up }, -{"moveml", one(0044300), one(0177700), "#w&s", m68000up }, -{"moveml", one(0044340), one(0177770), "#w-s", m68000up }, -{"moveml", one(0046300), one(0177700), "!s#w", m68000up }, -{"moveml", one(0046330), one(0177770), "+s#w", m68000up }, - -{"movepw", one(0000410), one(0170770), "dsDd", m68000up }, -{"movepw", one(0000610), one(0170770), "Ddds", m68000up }, -{"movepl", one(0000510), one(0170770), "dsDd", m68000up }, -{"movepl", one(0000710), one(0170770), "Ddds", m68000up }, - -{"moveq", one(0070000), one(0170400), "MsDd", m68000up }, +{"lslb", one(0160410), one(0170770), "QdDs", m68000up }, +{"lslb", one(0160450), one(0170770), "DdDs", m68000up }, +{"lslw", one(0160510), one(0170770), "QdDs", m68000up }, +{"lslw", one(0160550), one(0170770), "DdDs", m68000up }, +{"lslw", one(0161700), one(0177700), "~s", m68000up }, +{"lsll", one(0160610), one(0170770), "QdDs", m68000up | mcf5200 }, +{"lsll", one(0160650), one(0170770), "DdDs", m68000up | mcf5200 }, + +{"lsrb", one(0160010), one(0170770), "QdDs", m68000up }, +{"lsrb", one(0160050), one(0170770), "DdDs", m68000up }, +{"lsrw", one(0160110), one(0170770), "QdDs", m68000up }, +{"lsrw", one(0160150), one(0170770), "DdDs", m68000up }, +{"lsrw", one(0161300), one(0177700), "~s", m68000up }, +{"lsrl", one(0160210), one(0170770), "QdDs", m68000up | mcf5200 }, +{"lsrl", one(0160250), one(0170770), "DdDs", m68000up | mcf5200 }, + +{"moveal", one(0020100), one(0170700), "*lAd", m68000up | mcf5200 }, +{"moveaw", one(0030100), one(0170700), "*wAd", m68000up | mcf5200 }, + +{"movec", one(0047173), one(0177777), "R1Jj", m68010up | mcf5200 }, +{"movec", one(0047173), one(0177777), "R1#j", m68010up | mcf5200 }, +{"movec", one(0047172), one(0177777), "JjR1", m68010up }, +{"movec", one(0047172), one(0177777), "#jR1", m68010up }, + +{"movemw", one(0044200), one(0177700), "Lw&s", m68000up }, +{"movemw", one(0044240), one(0177770), "lw-s", m68000up }, +{"movemw", one(0046200), one(0177700), "!sLw", m68000up }, +{"movemw", one(0046230), one(0177770), "+sLw", m68000up }, +{"movemw", one(0044200), one(0177700), "#w&s", m68000up }, +{"movemw", one(0044240), one(0177770), "#w-s", m68000up }, +{"movemw", one(0046200), one(0177700), "!s#w", m68000up }, +{"movemw", one(0046230), one(0177770), "+s#w", m68000up }, +{"moveml", one(0044300), one(0177700), "Lw&s", m68000up | mcf5200 }, +{"moveml", one(0044340), one(0177770), "lw-s", m68000up | mcf5200 }, +{"moveml", one(0046300), one(0177700), "!sLw", m68000up | mcf5200 }, +{"moveml", one(0046330), one(0177770), "+sLw", m68000up | mcf5200 }, +{"moveml", one(0044300), one(0177700), "#w&s", m68000up | mcf5200 }, +{"moveml", one(0044340), one(0177770), "#w-s", m68000up | mcf5200 }, +{"moveml", one(0046300), one(0177700), "!s#w", m68000up | mcf5200 }, +{"moveml", one(0046330), one(0177770), "+s#w", m68000up | mcf5200 }, + +{"movepw", one(0000410), one(0170770), "dsDd", m68000up }, +{"movepw", one(0000610), one(0170770), "Ddds", m68000up }, +{"movepl", one(0000510), one(0170770), "dsDd", m68000up }, +{"movepl", one(0000710), one(0170770), "Ddds", m68000up }, + +{"moveq", one(0070000), one(0170400), "MsDd", m68000up | mcf5200 }, /* The move opcode can generate the movea and moveq instructions. */ -{"moveb", one(0010000), one(0170000), ";b$d", m68000up }, -{"movew", one(0030000), one(0170000), "*w$d", m68000up }, -{"movew", one(0030100), one(0170700), "*wAd", m68000up }, -{"movew", one(0040300), one(0177700), "Ss$s", m68000up }, -{"movew", one(0041300), one(0177700), "Cs$s", m68010up }, -{"movew", one(0042300), one(0177700), ";wCd", m68000up }, -{"movew", one(0043300), one(0177700), ";wSd", m68000up }, -{"movel", one(0070000), one(0170400), "MsDd", m68000up }, -{"movel", one(0020000), one(0170000), "*l$d", m68000up }, -{"movel", one(0020100), one(0170700), "*lAd", m68000up }, -{"movel", one(0047140), one(0177770), "AsUd", m68000up }, -{"movel", one(0047150), one(0177770), "UdAs", m68000up }, -{"move", one(0030000), one(0170000), "*w$d", m68000up }, -{"move", one(0030100), one(0170700), "*wAd", m68000up }, -{"move", one(0040300), one(0177700), "Ss$s", m68000up }, -{"move", one(0041300), one(0177700), "Cs$s", m68010up }, -{"move", one(0042300), one(0177700), ";wCd", m68000up }, -{"move", one(0043300), one(0177700), ";wSd", m68000up }, -{"move", one(0047140), one(0177770), "AsUd", m68000up }, -{"move", one(0047150), one(0177770), "UdAs", m68000up }, +{"moveb", one(0010000), one(0170000), ";b$d", m68000up | mcf5200 }, +{"movew", one(0030000), one(0170000), "*w$d", m68000up | mcf5200 }, +{"movew", one(0030100), one(0170700), "*wAd", m68000up | mcf5200 }, + +{"movew", one(0040300), one(0177770), "SsDs", mcf5200 }, +{"movew", one(0041300), one(0177770), "CsDs", mcf5200 }, +{"movew", one(0040300), one(0177700), "Ss$s", m68000up }, +{"movew", one(0041300), one(0177700), "Cs$s", m68010up }, +{"movew", one(0042300), one(0177700), ";wCd", m68000up | mcf5200 }, +{"movew", one(0043300), one(0177700), ";wSd", m68000up | mcf5200 }, + +{"movel", one(0070000), one(0170400), "MsDd", m68000up | mcf5200 }, +{"movel", one(0020000), one(0170000), "*l$d", m68000up | mcf5200 }, +{"movel", one(0020100), one(0170700), "*lAd", m68000up | mcf5200 }, +{"movel", one(0047140), one(0177770), "AsUd", m68000up | mcf5200 }, +{"movel", one(0047150), one(0177770), "UdAs", m68000up | mcf5200 }, +{"move", one(0030000), one(0170000), "*w$d", m68000up | mcf5200 }, +{"move", one(0030100), one(0170700), "*wAd", m68000up | mcf5200 }, + +{"move", one(0040300), one(0177770), "SsDs", mcf5200 }, +{"move", one(0041300), one(0177770), "CsDs", mcf5200 }, +{"move", one(0040300), one(0177700), "Ss$s", m68000up }, +{"move", one(0041300), one(0177700), "Cs$s", m68010up }, +{"move", one(0042300), one(0177700), ";wCd", m68000up | mcf5200 }, +{"move", one(0043300), one(0177700), ";wSd", m68000up | mcf5200 }, + +{"move", one(0047140), one(0177770), "AsUd", m68000up | mcf5200 }, +{"move", one(0047150), one(0177770), "UdAs", m68000up | mcf5200 }, {"movesb", two(0007000, 0), two(0177700, 07777), "~sR1", m68010up }, {"movesb", two(0007000, 04000), two(0177700, 07777), "R1~s", m68010up }, @@ -1288,59 +1299,59 @@ const struct m68k_opcode m68k_opcodes[] = {"move16", one(0xf610), one(0xfff8), "as_L", m68040up }, {"move16", one(0xf618), one(0xfff8), "_Las", m68040up }, -{"mulsw", one(0140700), one(0170700), ";wDd", m68000up }, -{"mulsl", two(0046000,004000), two(0177700,0107770), ";lD1", m68020up|cpu32 }, -{"mulsl", two(0046000,006000), two(0177700,0107770), ";lD3D1",m68020up|cpu32 }, +{"mulsw", one(0140700), one(0170700), ";wDd", m68000up|mcf5200 }, +{"mulsl", two(0046000,004000), two(0177700,0107770), ";lD1", m68020up|cpu32|mcf5200 }, +{"mulsl", two(0046000,006000), two(0177700,0107770), ";lD3D1",m68020up|cpu32 }, -{"muluw", one(0140300), one(0170700), ";wDd", m68000up }, -{"mulul", two(0046000,000000), two(0177700,0107770), ";lD1", m68020up|cpu32 }, -{"mulul", two(0046000,002000), two(0177700,0107770), ";lD3D1",m68020up|cpu32 }, +{"muluw", one(0140300), one(0170700), ";wDd", m68000up|mcf5200 }, +{"mulul", two(0046000,000000), two(0177700,0107770), ";lD1", m68020up|cpu32|mcf5200 }, +{"mulul", two(0046000,002000), two(0177700,0107770), ";lD3D1",m68020up|cpu32 }, -{"nbcd", one(0044000), one(0177700), "$s", m68000up }, +{"nbcd", one(0044000), one(0177700), "$s", m68000up }, -{"negb", one(0042000), one(0177700), "$s", m68000up }, -{"negw", one(0042100), one(0177700), "$s", m68000up }, -{"negl", one(0042200), one(0177700), "$s", m68000up }, +{"negb", one(0042000), one(0177700), "$s", m68000up }, +{"negw", one(0042100), one(0177700), "$s", m68000up }, +{"negl", one(0042200), one(0177700), "$s", m68000up | mcf5200}, -{"negxb", one(0040000), one(0177700), "$s", m68000up }, -{"negxw", one(0040100), one(0177700), "$s", m68000up }, -{"negxl", one(0040200), one(0177700), "$s", m68000up }, +{"negxb", one(0040000), one(0177700), "$s", m68000up }, +{"negxw", one(0040100), one(0177700), "$s", m68000up }, +{"negxl", one(0040200), one(0177700), "$s", m68000up | mcf5200}, -{"nop", one(0047161), one(0177777), "", m68000up }, +{"nop", one(0047161), one(0177777), "", m68000up | mcf5200}, -{"notb", one(0043000), one(0177700), "$s", m68000up }, -{"notw", one(0043100), one(0177700), "$s", m68000up }, -{"notl", one(0043200), one(0177700), "$s", m68000up }, +{"notb", one(0043000), one(0177700), "$s", m68000up }, +{"notw", one(0043100), one(0177700), "$s", m68000up }, +{"notl", one(0043200), one(0177700), "$s", m68000up | mcf5200}, -{"orib", one(0000000), one(0177700), "#b$s", m68000up }, -{"orib", one(0000074), one(0177777), "#bCs", m68000up }, -{"oriw", one(0000100), one(0177700), "#w$s", m68000up }, -{"oriw", one(0000174), one(0177777), "#wSs", m68000up }, -{"oril", one(0000200), one(0177700), "#l$s", m68000up }, -{"ori", one(0000074), one(0177777), "#bCs", m68000up }, -{"ori", one(0000100), one(0177700), "#w$s", m68000up }, -{"ori", one(0000174), one(0177777), "#wSs", m68000up }, +{"orib", one(0000000), one(0177700), "#b$s", m68000up }, +{"orib", one(0000074), one(0177777), "#bCs", m68000up }, +{"oriw", one(0000100), one(0177700), "#w$s", m68000up }, +{"oriw", one(0000174), one(0177777), "#wSs", m68000up }, +{"oril", one(0000200), one(0177700), "#l$s", m68000up | mcf5200 }, +{"ori", one(0000074), one(0177777), "#bCs", m68000up }, +{"ori", one(0000100), one(0177700), "#w$s", m68000up }, +{"ori", one(0000174), one(0177777), "#wSs", m68000up }, /* The or opcode can generate the ori instruction. */ -{"orb", one(0000000), one(0177700), "#b$s", m68000up }, -{"orb", one(0000074), one(0177777), "#bCs", m68000up }, -{"orb", one(0100000), one(0170700), ";bDd", m68000up }, -{"orb", one(0100400), one(0170700), "Dd~s", m68000up }, -{"orw", one(0000100), one(0177700), "#w$s", m68000up }, -{"orw", one(0000174), one(0177777), "#wSs", m68000up }, -{"orw", one(0100100), one(0170700), ";wDd", m68000up }, -{"orw", one(0100500), one(0170700), "Dd~s", m68000up }, -{"orl", one(0000200), one(0177700), "#l$s", m68000up }, -{"orl", one(0100200), one(0170700), ";lDd", m68000up }, -{"orl", one(0100600), one(0170700), "Dd~s", m68000up }, -{"or", one(0000074), one(0177777), "#bCs", m68000up }, -{"or", one(0000100), one(0177700), "#w$s", m68000up }, -{"or", one(0000174), one(0177777), "#wSs", m68000up }, -{"or", one(0100100), one(0170700), ";wDd", m68000up }, -{"or", one(0100500), one(0170700), "Dd~s", m68000up }, - -{"pack", one(0100500), one(0170770), "DsDd#w", m68020up }, -{"pack", one(0100510), one(0170770), "-s-d#w", m68020up }, +{"orb", one(0000000), one(0177700), "#b$s", m68000up }, +{"orb", one(0000074), one(0177777), "#bCs", m68000up }, +{"orb", one(0100000), one(0170700), ";bDd", m68000up }, +{"orb", one(0100400), one(0170700), "Dd~s", m68000up }, +{"orw", one(0000100), one(0177700), "#w$s", m68000up }, +{"orw", one(0000174), one(0177777), "#wSs", m68000up }, +{"orw", one(0100100), one(0170700), ";wDd", m68000up }, +{"orw", one(0100500), one(0170700), "Dd~s", m68000up }, +{"orl", one(0000200), one(0177700), "#l$s", m68000up | mcf5200 }, +{"orl", one(0100200), one(0170700), ";lDd", m68000up | mcf5200 }, +{"orl", one(0100600), one(0170700), "Dd~s", m68000up | mcf5200 }, +{"or", one(0000074), one(0177777), "#bCs", m68000up }, +{"or", one(0000100), one(0177700), "#w$s", m68000up }, +{"or", one(0000174), one(0177777), "#wSs", m68000up }, +{"or", one(0100100), one(0170700), ";wDd", m68000up }, +{"or", one(0100500), one(0170700), "Dd~s", m68000up }, + +{"pack", one(0100500), one(0170770), "DsDd#w", m68020up }, +{"pack", one(0100510), one(0170770), "-s-d#w", m68020up }, {"pbac", one(0xf087), one(0xffbf), "Bc", m68851 }, {"pbacw", one(0xf087), one(0xffff), "BW", m68851 }, @@ -1392,7 +1403,7 @@ const struct m68k_opcode m68k_opcodes[] = {"pdbwc", two(0xf048, 0x0009), two(0xfff8, 0xffff), "DsBw", m68851 }, {"pdbws", two(0xf048, 0x0008), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pea", one(0044100), one(0177700), "!s", m68000up }, +{"pea", one(0044100), one(0177700), "!s", m68000up|mcf5200 }, {"pflusha", two(0xf000,0x2400), two(0xffff,0xffff), "", m68030 | m68851 }, {"pflusha", one(0xf518), one(0xfff8), "", m68040up }, @@ -1552,6 +1563,8 @@ const struct m68k_opcode m68k_opcodes[] = {"ptrapwsl", two(0xf07b, 0x0008), two(0xffff, 0xffff), "#l", m68851 }, {"ptrapws", two(0xf07c, 0x0008), two(0xffff, 0xffff), "", m68851 }, +{"pulse", one(0045314), one(0177777), "", mcf5200 }, + {"pvalid", two(0xf000, 0x2800), two(0xffc0, 0xffff), "Vs&s", m68851 }, {"pvalid", two(0xf000, 0x2c00), two(0xffc0, 0xfff8), "A3&s", m68851 }, @@ -1591,71 +1604,71 @@ const struct m68k_opcode m68k_opcodes[] = {"rtd", one(0047164), one(0177777), "#w", m68010up }, -{"rte", one(0047163), one(0177777), "", m68000up }, +{"rte", one(0047163), one(0177777), "", m68000up|mcf5200 }, {"rtm", one(0003300), one(0177760), "Rs", m68020 }, {"rtr", one(0047167), one(0177777), "", m68000up }, -{"rts", one(0047165), one(0177777), "", m68000up }, +{"rts", one(0047165), one(0177777), "", m68000up|mcf5200 }, {"sbcd", one(0100400), one(0170770), "DsDd", m68000up }, {"sbcd", one(0100410), one(0170770), "-s-d", m68000up }, -{"scc", one(0052300), one(0177700), "$s", m68000up }, -{"scs", one(0052700), one(0177700), "$s", m68000up }, -{"seq", one(0053700), one(0177700), "$s", m68000up }, -{"sf", one(0050700), one(0177700), "$s", m68000up }, -{"sge", one(0056300), one(0177700), "$s", m68000up }, -{"sgt", one(0057300), one(0177700), "$s", m68000up }, -{"shi", one(0051300), one(0177700), "$s", m68000up }, -{"sle", one(0057700), one(0177700), "$s", m68000up }, -{"sls", one(0051700), one(0177700), "$s", m68000up }, -{"slt", one(0056700), one(0177700), "$s", m68000up }, -{"smi", one(0055700), one(0177700), "$s", m68000up }, -{"sne", one(0053300), one(0177700), "$s", m68000up }, -{"spl", one(0055300), one(0177700), "$s", m68000up }, -{"st", one(0050300), one(0177700), "$s", m68000up }, -{"svc", one(0054300), one(0177700), "$s", m68000up }, -{"svs", one(0054700), one(0177700), "$s", m68000up }, - -{"stop", one(0047162), one(0177777), "#w", m68000up }, - -{"subal", one(0110700), one(0170700), "*lAd", m68000up }, -{"subaw", one(0110300), one(0170700), "*wAd", m68000up }, - -{"subib", one(0002000), one(0177700), "#b$s", m68000up }, -{"subiw", one(0002100), one(0177700), "#w$s", m68000up }, -{"subil", one(0002200), one(0177700), "#l$s", m68000up }, - -{"subqb", one(0050400), one(0170700), "Qd%s", m68000up }, -{"subqw", one(0050500), one(0170700), "Qd%s", m68000up }, -{"subql", one(0050600), one(0170700), "Qd%s", m68000up }, +{"scc", one(0052300), one(0177700), "$s", m68000up | mcf5200 }, +{"scs", one(0052700), one(0177700), "$s", m68000up | mcf5200 }, +{"seq", one(0053700), one(0177700), "$s", m68000up | mcf5200 }, +{"sf", one(0050700), one(0177700), "$s", m68000up | mcf5200 }, +{"sge", one(0056300), one(0177700), "$s", m68000up | mcf5200 }, +{"sgt", one(0057300), one(0177700), "$s", m68000up | mcf5200 }, +{"shi", one(0051300), one(0177700), "$s", m68000up | mcf5200 }, +{"sle", one(0057700), one(0177700), "$s", m68000up | mcf5200 }, +{"sls", one(0051700), one(0177700), "$s", m68000up | mcf5200 }, +{"slt", one(0056700), one(0177700), "$s", m68000up | mcf5200 }, +{"smi", one(0055700), one(0177700), "$s", m68000up | mcf5200 }, +{"sne", one(0053300), one(0177700), "$s", m68000up | mcf5200 }, +{"spl", one(0055300), one(0177700), "$s", m68000up | mcf5200 }, +{"st", one(0050300), one(0177700), "$s", m68000up | mcf5200 }, +{"svc", one(0054300), one(0177700), "$s", m68000up | mcf5200 }, +{"svs", one(0054700), one(0177700), "$s", m68000up | mcf5200 }, + +{"stop", one(0047162), one(0177777), "#w", m68000up | mcf5200 }, + +{"subal", one(0110700), one(0170700), "*lAd", m68000up | mcf5200 }, +{"subaw", one(0110300), one(0170700), "*wAd", m68000up }, + +{"subib", one(0002000), one(0177700), "#b$s", m68000up }, +{"subiw", one(0002100), one(0177700), "#w$s", m68000up }, +{"subil", one(0002200), one(0177700), "#l$s", m68000up | mcf5200 }, + +{"subqb", one(0050400), one(0170700), "Qd%s", m68000up }, +{"subqw", one(0050500), one(0170700), "Qd%s", m68000up }, +{"subql", one(0050600), one(0170700), "Qd%s", m68000up | mcf5200 }, /* The sub opcode can generate the suba, subi, and subq instructions. */ -{"subb", one(0050400), one(0170700), "Qd%s", m68000up }, -{"subb", one(0002000), one(0177700), "#b$s", m68000up }, -{"subb", one(0110000), one(0170700), ";bDd", m68000up }, -{"subb", one(0110400), one(0170700), "Dd~s", m68000up }, -{"subw", one(0050500), one(0170700), "Qd%s", m68000up }, -{"subw", one(0002100), one(0177700), "#w$s", m68000up }, -{"subw", one(0110300), one(0170700), "*wAd", m68000up }, -{"subw", one(0110100), one(0170700), "*wDd", m68000up }, -{"subw", one(0110500), one(0170700), "Dd~s", m68000up }, -{"subl", one(0050600), one(0170700), "Qd%s", m68000up }, -{"subl", one(0002200), one(0177700), "#l$s", m68000up }, -{"subl", one(0110700), one(0170700), "*lAd", m68000up }, -{"subl", one(0110200), one(0170700), "*lDd", m68000up }, -{"subl", one(0110600), one(0170700), "Dd~s", m68000up }, - -{"subxb", one(0110400), one(0170770), "DsDd", m68000up }, -{"subxb", one(0110410), one(0170770), "-s-d", m68000up }, -{"subxw", one(0110500), one(0170770), "DsDd", m68000up }, -{"subxw", one(0110510), one(0170770), "-s-d", m68000up }, -{"subxl", one(0110600), one(0170770), "DsDd", m68000up }, -{"subxl", one(0110610), one(0170770), "-s-d", m68000up }, - -{"swap", one(0044100), one(0177770), "Ds", m68000up }, +{"subb", one(0050400), one(0170700), "Qd%s", m68000up }, +{"subb", one(0002000), one(0177700), "#b$s", m68000up }, +{"subb", one(0110000), one(0170700), ";bDd", m68000up }, +{"subb", one(0110400), one(0170700), "Dd~s", m68000up }, +{"subw", one(0050500), one(0170700), "Qd%s", m68000up }, +{"subw", one(0002100), one(0177700), "#w$s", m68000up }, +{"subw", one(0110300), one(0170700), "*wAd", m68000up }, +{"subw", one(0110100), one(0170700), "*wDd", m68000up }, +{"subw", one(0110500), one(0170700), "Dd~s", m68000up }, +{"subl", one(0050600), one(0170700), "Qd%s", m68000up | mcf5200 }, +{"subl", one(0002200), one(0177700), "#l$s", m68000up | mcf5200 }, +{"subl", one(0110700), one(0170700), "*lAd", m68000up | mcf5200 }, +{"subl", one(0110200), one(0170700), "*lDd", m68000up | mcf5200 }, +{"subl", one(0110600), one(0170700), "Dd~s", m68000up | mcf5200 }, + +{"subxb", one(0110400), one(0170770), "DsDd", m68000up }, +{"subxb", one(0110410), one(0170770), "-s-d", m68000up }, +{"subxw", one(0110500), one(0170770), "DsDd", m68000up }, +{"subxw", one(0110510), one(0170770), "-s-d", m68000up }, +{"subxl", one(0110600), one(0170770), "DsDd", m68000up | mcf5200 }, +{"subxl", one(0110610), one(0170770), "-s-d", m68000up }, + +{"swap", one(0044100), one(0177770), "Ds", m68000up | mcf5200 }, {"tas", one(0045300), one(0177700), "$s", m68000up }, @@ -1671,69 +1684,74 @@ TBL("tblsnb", "tblsnw", "tblsnl", 1, 0), TBL("tblub", "tbluw", "tblul", 0, 1), TBL("tblunb", "tblunw", "tblunl", 0, 0), -{"trap", one(0047100), one(0177760), "Ts", m68000up }, - -{"trapcc", one(0052374), one(0177777), "", m68020up | cpu32 }, -{"trapcs", one(0052774), one(0177777), "", m68020up | cpu32 }, -{"trapeq", one(0053774), one(0177777), "", m68020up | cpu32 }, -{"trapf", one(0050774), one(0177777), "", m68020up | cpu32 }, -{"trapge", one(0056374), one(0177777), "", m68020up | cpu32 }, -{"trapgt", one(0057374), one(0177777), "", m68020up | cpu32 }, -{"traphi", one(0051374), one(0177777), "", m68020up | cpu32 }, -{"traple", one(0057774), one(0177777), "", m68020up | cpu32 }, -{"trapls", one(0051774), one(0177777), "", m68020up | cpu32 }, -{"traplt", one(0056774), one(0177777), "", m68020up | cpu32 }, -{"trapmi", one(0055774), one(0177777), "", m68020up | cpu32 }, -{"trapne", one(0053374), one(0177777), "", m68020up | cpu32 }, -{"trappl", one(0055374), one(0177777), "", m68020up | cpu32 }, -{"trapt", one(0050374), one(0177777), "", m68020up | cpu32 }, -{"trapvc", one(0054374), one(0177777), "", m68020up | cpu32 }, -{"trapvs", one(0054774), one(0177777), "", m68020up | cpu32 }, - -{"trapccw", one(0052372), one(0177777), "#w", m68020up | cpu32 }, -{"trapcsw", one(0052772), one(0177777), "#w", m68020up | cpu32 }, -{"trapeqw", one(0053772), one(0177777), "#w", m68020up | cpu32 }, -{"trapfw", one(0050772), one(0177777), "#w", m68020up | cpu32 }, -{"trapgew", one(0056372), one(0177777), "#w", m68020up | cpu32 }, -{"trapgtw", one(0057372), one(0177777), "#w", m68020up | cpu32 }, -{"traphiw", one(0051372), one(0177777), "#w", m68020up | cpu32 }, -{"traplew", one(0057772), one(0177777), "#w", m68020up | cpu32 }, -{"traplsw", one(0051772), one(0177777), "#w", m68020up | cpu32 }, -{"trapltw", one(0056772), one(0177777), "#w", m68020up | cpu32 }, -{"trapmiw", one(0055772), one(0177777), "#w", m68020up | cpu32 }, -{"trapnew", one(0053372), one(0177777), "#w", m68020up | cpu32 }, -{"trapplw", one(0055372), one(0177777), "#w", m68020up | cpu32 }, -{"traptw", one(0050372), one(0177777), "#w", m68020up | cpu32 }, -{"trapvcw", one(0054372), one(0177777), "#w", m68020up | cpu32 }, -{"trapvsw", one(0054772), one(0177777), "#w", m68020up | cpu32 }, - -{"trapccl", one(0052373), one(0177777), "#l", m68020up | cpu32 }, -{"trapcsl", one(0052773), one(0177777), "#l", m68020up | cpu32 }, -{"trapeql", one(0053773), one(0177777), "#l", m68020up | cpu32 }, -{"trapfl", one(0050773), one(0177777), "#l", m68020up | cpu32 }, -{"trapgel", one(0056373), one(0177777), "#l", m68020up | cpu32 }, -{"trapgtl", one(0057373), one(0177777), "#l", m68020up | cpu32 }, -{"traphil", one(0051373), one(0177777), "#l", m68020up | cpu32 }, -{"traplel", one(0057773), one(0177777), "#l", m68020up | cpu32 }, -{"traplsl", one(0051773), one(0177777), "#l", m68020up | cpu32 }, -{"trapltl", one(0056773), one(0177777), "#l", m68020up | cpu32 }, -{"trapmil", one(0055773), one(0177777), "#l", m68020up | cpu32 }, -{"trapnel", one(0053373), one(0177777), "#l", m68020up | cpu32 }, -{"trappll", one(0055373), one(0177777), "#l", m68020up | cpu32 }, -{"traptl", one(0050373), one(0177777), "#l", m68020up | cpu32 }, -{"trapvcl", one(0054373), one(0177777), "#l", m68020up | cpu32 }, -{"trapvsl", one(0054773), one(0177777), "#l", m68020up | cpu32 }, - -{"trapv", one(0047166), one(0177777), "", m68000up }, - -{"tstb", one(0045000), one(0177700), ";b", m68000up }, -{"tstw", one(0045100), one(0177700), "*w", m68000up }, -{"tstl", one(0045200), one(0177700), "*l", m68000up }, - -{"unlk", one(0047130), one(0177770), "As", m68000up }, - -{"unpk", one(0100600), one(0170770), "DsDd#w", m68020up }, -{"unpk", one(0100610), one(0170770), "-s-d#w", m68020up }, +{"trap", one(0047100), one(0177760), "Ts", m68000up | mcf5200 }, + +{"trapcc", one(0052374), one(0177777), "", m68020up | cpu32 }, +{"trapcs", one(0052774), one(0177777), "", m68020up | cpu32 }, +{"trapeq", one(0053774), one(0177777), "", m68020up | cpu32 }, +{"trapf", one(0050774), one(0177777), "", m68020up | cpu32 | mcf5200 }, +{"trapge", one(0056374), one(0177777), "", m68020up | cpu32 }, +{"trapgt", one(0057374), one(0177777), "", m68020up | cpu32 }, +{"traphi", one(0051374), one(0177777), "", m68020up | cpu32 }, +{"traple", one(0057774), one(0177777), "", m68020up | cpu32 }, +{"trapls", one(0051774), one(0177777), "", m68020up | cpu32 }, +{"traplt", one(0056774), one(0177777), "", m68020up | cpu32 }, +{"trapmi", one(0055774), one(0177777), "", m68020up | cpu32 }, +{"trapne", one(0053374), one(0177777), "", m68020up | cpu32 }, +{"trappl", one(0055374), one(0177777), "", m68020up | cpu32 }, +{"trapt", one(0050374), one(0177777), "", m68020up | cpu32 }, +{"trapvc", one(0054374), one(0177777), "", m68020up | cpu32 }, +{"trapvs", one(0054774), one(0177777), "", m68020up | cpu32 }, + +{"trapccw", one(0052372), one(0177777), "#w", m68020up|cpu32 }, +{"trapcsw", one(0052772), one(0177777), "#w", m68020up|cpu32 }, +{"trapeqw", one(0053772), one(0177777), "#w", m68020up|cpu32 }, +{"trapfw", one(0050772), one(0177777), "#w", m68020up|cpu32|mcf5200}, +{"trapgew", one(0056372), one(0177777), "#w", m68020up|cpu32 }, +{"trapgtw", one(0057372), one(0177777), "#w", m68020up|cpu32 }, +{"traphiw", one(0051372), one(0177777), "#w", m68020up|cpu32 }, +{"traplew", one(0057772), one(0177777), "#w", m68020up|cpu32 }, +{"traplsw", one(0051772), one(0177777), "#w", m68020up|cpu32 }, +{"trapltw", one(0056772), one(0177777), "#w", m68020up|cpu32 }, +{"trapmiw", one(0055772), one(0177777), "#w", m68020up|cpu32 }, +{"trapnew", one(0053372), one(0177777), "#w", m68020up|cpu32 }, +{"trapplw", one(0055372), one(0177777), "#w", m68020up|cpu32 }, +{"traptw", one(0050372), one(0177777), "#w", m68020up|cpu32 }, +{"trapvcw", one(0054372), one(0177777), "#w", m68020up|cpu32 }, +{"trapvsw", one(0054772), one(0177777), "#w", m68020up|cpu32 }, + +{"trapccl", one(0052373), one(0177777), "#l", m68020up|cpu32 }, +{"trapcsl", one(0052773), one(0177777), "#l", m68020up|cpu32 }, +{"trapeql", one(0053773), one(0177777), "#l", m68020up|cpu32 }, +{"trapfl", one(0050773), one(0177777), "#l", m68020up|cpu32|mcf5200}, +{"trapgel", one(0056373), one(0177777), "#l", m68020up|cpu32 }, +{"trapgtl", one(0057373), one(0177777), "#l", m68020up|cpu32 }, +{"traphil", one(0051373), one(0177777), "#l", m68020up|cpu32 }, +{"traplel", one(0057773), one(0177777), "#l", m68020up|cpu32 }, +{"traplsl", one(0051773), one(0177777), "#l", m68020up|cpu32 }, +{"trapltl", one(0056773), one(0177777), "#l", m68020up|cpu32 }, +{"trapmil", one(0055773), one(0177777), "#l", m68020up|cpu32 }, +{"trapnel", one(0053373), one(0177777), "#l", m68020up|cpu32 }, +{"trappll", one(0055373), one(0177777), "#l", m68020up|cpu32 }, +{"traptl", one(0050373), one(0177777), "#l", m68020up|cpu32 }, +{"trapvcl", one(0054373), one(0177777), "#l", m68020up|cpu32 }, +{"trapvsl", one(0054773), one(0177777), "#l", m68020up|cpu32 }, + +{"trapv", one(0047166), one(0177777), "", m68000up }, + +{"tstb", one(0045000), one(0177700), ";b", m68000up | mcf5200 }, +{"tstw", one(0045100), one(0177700), "*w", m68000up | mcf5200 }, +{"tstl", one(0045200), one(0177700), "*l", m68000up | mcf5200 }, + +{"unlk", one(0047130), one(0177770), "As", m68000up | mcf5200 }, + +{"unpk", one(0100600), one(0170770), "DsDd#w", m68020up }, +{"unpk", one(0100610), one(0170770), "-s-d#w", m68020up }, + +{"wddatab", one(0172000), one(0177700), "~s", mcf5200 }, +{"wddataw", one(0172100), one(0177700), "~s", mcf5200 }, +{"wddatal", one(0172200), one(0177700), "~s", mcf5200 }, + }; const int m68k_numopcodes = sizeof m68k_opcodes / sizeof m68k_opcodes[0]; diff --git a/gnu/usr.bin/binutils/opcodes/mpw-make.sed b/gnu/usr.bin/binutils/opcodes/mpw-make.sed index 5faa927d919..ee604862de6 100644 --- a/gnu/usr.bin/binutils/opcodes/mpw-make.sed +++ b/gnu/usr.bin/binutils/opcodes/mpw-make.sed @@ -3,8 +3,10 @@ # Empty HDEFINES. /HDEFINES/s/@HDEFINES@// -/INCDIR=/s/"{srcdir}":/"{topsrcdir}"/ -/^CSEARCH = .*$/s/$/ -i "{INCDIR}":mpw: -i ::extra-include:/ +# Fix pathnames to include directories. +/^INCDIR = /s/^INCDIR = .*$/INCDIR = "{topsrcdir}"include/ +/^CSEARCH = /s/$/ -i "{INCDIR}":mpw: -i ::extra-include:/ + /BFD_MACHINES/s/@BFD_MACHINES@/{BFD_MACHINES}/ /archdefs/s/@archdefs@/{ARCHDEFS}/ diff --git a/gnu/usr.bin/binutils/opcodes/ppc-opc.c b/gnu/usr.bin/binutils/opcodes/ppc-opc.c index 2572318ce01..c3b6de573ae 100644 --- a/gnu/usr.bin/binutils/opcodes/ppc-opc.c +++ b/gnu/usr.bin/binutils/opcodes/ppc-opc.c @@ -2797,7 +2797,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, { "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, -{ "fcmpo", X(63,30), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, +{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, { "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } }, { "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } }, diff --git a/gnu/usr.bin/binutils/opcodes/sparc-dis.c b/gnu/usr.bin/binutils/opcodes/sparc-dis.c index 3b56385a736..90338dd2194 100644 --- a/gnu/usr.bin/binutils/opcodes/sparc-dis.c +++ b/gnu/usr.bin/binutils/opcodes/sparc-dis.c @@ -200,7 +200,6 @@ print_insn_sparc (memaddr, info) FILE *stream = info->stream; bfd_byte buffer[4]; unsigned long insn; - register unsigned int i; register struct opcode_hash *op; /* Nonzero of opcode table has been initialized. */ static int opcodes_initialized = 0; @@ -228,7 +227,10 @@ print_insn_sparc (memaddr, info) } } - insn = bfd_getb32 (buffer); + if (info->endian == BFD_ENDIAN_BIG) + insn = bfd_getb32 (buffer); + else + insn = bfd_getl32 (buffer); info->insn_info_valid = 1; /* We do return this info */ info->insn_type = dis_nonbranch; /* Assume non branch insn */ @@ -257,11 +259,10 @@ print_insn_sparc (memaddr, info) /* Nonzero means we have an annulled branch. */ int is_annulled = 0; - /* Do we have an `add' or `or' instruction where rs1 is the same - as rsd, and which has the i bit set? */ - if ((opcode->match == 0x80102000 || opcode->match == 0x80002000) + /* Do we have an `add' or `or' instruction combining an + immediate with rs1? */ + if (opcode->match == 0x80102000 || opcode->match == 0x80002000) /* (or) (add) */ - && X_RS1 (insn) == X_RD (insn)) imm_added_to_rs1 = 1; if (X_RS1 (insn) != X_RD (insn) @@ -629,7 +630,10 @@ print_insn_sparc (memaddr, info) errcode = (*info->read_memory_func) (memaddr - 4, buffer, sizeof (buffer), info); - prev_insn = bfd_getb32 (buffer); + if (info->endian == BFD_ENDIAN_BIG) + prev_insn = bfd_getb32 (buffer); + else + prev_insn = bfd_getl32 (buffer); if (errcode == 0) { @@ -646,7 +650,10 @@ print_insn_sparc (memaddr, info) { errcode = (*info->read_memory_func) (memaddr - 8, buffer, sizeof (buffer), info); - prev_insn = bfd_getb32 (buffer); + if (info->endian == BFD_ENDIAN_BIG) + prev_insn = bfd_getb32 (buffer); + else + prev_insn = bfd_getl32 (buffer); } } diff --git a/gnu/usr.bin/binutils/opcodes/sparc-opc.c b/gnu/usr.bin/binutils/opcodes/sparc-opc.c index 81905a3ddf3..718177e4f0e 100644 --- a/gnu/usr.bin/binutils/opcodes/sparc-opc.c +++ b/gnu/usr.bin/binutils/opcodes/sparc-opc.c @@ -22,8 +22,6 @@ Boston, MA 02111-1307, USA. */ instruction's name rather than the args. This would make gas faster, pinsn slower, but would mess up some macros a bit. xoxorich. */ -/* v9 FIXME: Doesn't accept `setsw', `setx' synthetic instructions for v9. */ - #include <stdio.h> #include "ansidecl.h" #include "opcode/sparc.h" @@ -716,14 +714,19 @@ struct sparc_opcode sparc_opcodes[] = { { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, v8 }, /* wr r,r,%asrX */ { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, v8 }, /* wr r,i,%asrX */ +{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */ { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, v6 }, /* wr r,r,%y */ { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, v6 }, /* wr r,i,%y */ +{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */ { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, v6notv9 }, /* wr r,r,%psr */ { "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, v6notv9 }, /* wr r,i,%psr */ +{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */ { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, v6notv9 }, /* wr r,r,%wim */ { "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, v6notv9 }, /* wr r,i,%wim */ +{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */ { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, v6notv9 }, /* wr r,r,%tbr */ { "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, v6notv9 }, /* wr r,i,%tbr */ +{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */ { "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, v9 }, /* wr r,r,%ccr */ { "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, v9 }, /* wr r,i,%ccr */ @@ -981,6 +984,7 @@ cond ("ba", "t", CONDA, F_UNBR|F_ALIAS), cond ("bcc", "tcc", CONDCC, F_CONDBR), cond ("bcs", "tcs", CONDCS, F_CONDBR), cond ("be", "te", CONDE, F_CONDBR), +cond ("beq", "teq", CONDE, F_CONDBR|F_ALIAS), cond ("bg", "tg", CONDG, F_CONDBR), cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS), cond ("bge", "tge", CONDGE, F_CONDBR), @@ -1345,6 +1349,9 @@ CONDFC ("fbule", "cb013", 0xe, 0), { "nop", F2(0, 4), 0xfeffffff, "", 0, v6 }, /* sethi 0, %g0 */ { "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "Sh,d", F_ALIAS, v6 }, +{ "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "Sh,d", F_ALIAS, v9 }, +{ "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "Sh,d", F_ALIAS, v9 }, +{ "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, v9 }, { "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 }, @@ -1610,11 +1617,11 @@ IMPDEP ("impdep2", 0x37), { "fsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, v9a }, { "fsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, v9a }, -{ "fpack16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039)|RS1_G0, "B,H", 0, v9a }, { "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, v9a }, -{ "fpackfix", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,H", 0, v9a }, -{ "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "B,H", 0, v9a }, -{ "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "v,B,H", 0, v9a }, +{ "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, v9a }, +{ "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, v9a }, +{ "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, v9a }, +{ "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, v9a }, /* Note that the mixing of 32/64 bit regs is intentional. FIXME: Should these be commutative? */ @@ -1734,6 +1741,12 @@ lookup_value (table, value) static arg asi_table[] = { + /* These are in the v9 architecture manual. */ + /* The shorter versions appear first, they're here because Sun's as has them. + Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the + UltraSPARC architecture manual). */ + { 0x04, "#ASI_N" }, + { 0x0c, "#ASI_N_L" }, { 0x10, "#ASI_AIUP" }, { 0x11, "#ASI_AIUS" }, { 0x18, "#ASI_AIUP_L" }, @@ -1746,10 +1759,12 @@ static arg asi_table[] = { 0x89, "#ASI_S_L" }, { 0x8a, "#ASI_PNF_L" }, { 0x8b, "#ASI_SNF_L" }, + { 0x04, "#ASI_NUCLEUS" }, + { 0x0c, "#ASI_NUCLEUS_LITTLE" }, { 0x10, "#ASI_AS_IF_USER_PRIMARY" }, { 0x11, "#ASI_AS_IF_USER_SECONDARY" }, - { 0x18, "#ASI_AS_IF_USER_PRIMARY_L" }, - { 0x19, "#ASI_AS_IF_USER_SECONDARY_L" }, + { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" }, + { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" }, { 0x80, "#ASI_PRIMARY" }, { 0x81, "#ASI_SECONDARY" }, { 0x82, "#ASI_PRIMARY_NOFAULT" }, @@ -1758,6 +1773,9 @@ static arg asi_table[] = { 0x89, "#ASI_SECONDARY_LITTLE" }, { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" }, { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" }, + /* These are UltraSPARC extensions. */ + /* FIXME: There are dozens of them. Not sure we want them all. + Most are for kernel building but some are for vis type stuff. */ { 0, 0 } }; |