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-rw-r--r--gnu/usr.bin/gcc/config/alpha/alpha.c7
-rw-r--r--gnu/usr.bin/gcc/config/alpha/alpha.h3
-rw-r--r--gnu/usr.bin/gcc/config/arm/arm.md50
-rw-r--r--gnu/usr.bin/gcc/config/i386/freebsd.h6
-rw-r--r--gnu/usr.bin/gcc/config/mips/mips.c2
-rw-r--r--gnu/usr.bin/gcc/config/msdos/top.sed4
-rw-r--r--gnu/usr.bin/gcc/config/pa/pa.h2
-rw-r--r--gnu/usr.bin/gcc/config/rs6000/rs6000.c182
-rw-r--r--gnu/usr.bin/gcc/config/rs6000/rs6000.md88
-rw-r--r--gnu/usr.bin/gcc/config/sparc/sparc.h16
-rw-r--r--gnu/usr.bin/gcc/config/svr4.h14
-rw-r--r--gnu/usr.bin/gcc/config/vax/vax.h3
-rw-r--r--gnu/usr.bin/gcc/config/vax/vax.md1
-rw-r--r--gnu/usr.bin/gcc/config/winnt/config-nt.sed2
14 files changed, 234 insertions, 146 deletions
diff --git a/gnu/usr.bin/gcc/config/alpha/alpha.c b/gnu/usr.bin/gcc/config/alpha/alpha.c
index b80717d41c1..0efe27ca733 100644
--- a/gnu/usr.bin/gcc/config/alpha/alpha.c
+++ b/gnu/usr.bin/gcc/config/alpha/alpha.c
@@ -1247,12 +1247,7 @@ alpha_write_verstamp (file)
FILE *file;
{
#ifdef MS_STAMP
- char *p;
-
- fprintf (file, "\t.verstamp %d %d ", MS_STAMP, LS_STAMP);
- for (p = version_string; *p != ' ' && *p != 0; p++)
- fprintf (file, "%c", *p == '.' ? ' ' : *p);
- fprintf (file, "\n");
+ fprintf (file, "\t.verstamp %d %d\n", MS_STAMP, LS_STAMP);
#endif
}
diff --git a/gnu/usr.bin/gcc/config/alpha/alpha.h b/gnu/usr.bin/gcc/config/alpha/alpha.h
index b179f1445a0..a4ff2e31272 100644
--- a/gnu/usr.bin/gcc/config/alpha/alpha.h
+++ b/gnu/usr.bin/gcc/config/alpha/alpha.h
@@ -2094,6 +2094,9 @@ do { \
/* The system headers under OSF/1 are C++-aware. */
#define NO_IMPLICIT_EXTERN_C
+/* Also define __LANGUAGE_C__ when running fix-header. */
+#define FIXPROTO_INIT(CPPFILE) cpp_define (CPPFILE, "__LANGUAGE_C__")
+
/* The linker will stick __main into the .init section. */
#define HAS_INIT_SECTION
#define LD_INIT_SWITCH "-init"
diff --git a/gnu/usr.bin/gcc/config/arm/arm.md b/gnu/usr.bin/gcc/config/arm/arm.md
index 461aeada97a..5e60f2d227b 100644
--- a/gnu/usr.bin/gcc/config/arm/arm.md
+++ b/gnu/usr.bin/gcc/config/arm/arm.md
@@ -3316,9 +3316,9 @@
(define_expand "movsicc"
[(set (match_operand:SI 0 "register_operand" "")
- (if_then_else (match_operand 1 "comparison_operator" "")
- (match_operand:SI 2 "arm_not_operand" "")
- (match_operand:SI 3 "register_operand" "")))]
+ (if_then_else:SI (match_operand 1 "comparison_operator" "")
+ (match_operand:SI 2 "arm_not_operand" "")
+ (match_operand:SI 3 "register_operand" "")))]
""
"
{
@@ -3331,9 +3331,9 @@
(define_expand "movsfcc"
[(set (match_operand:SF 0 "register_operand" "")
- (if_then_else (match_operand 1 "comparison_operator" "")
- (match_operand:SF 2 "nonmemory_operand" "")
- (match_operand:SF 3 "register_operand" "")))]
+ (if_then_else:SF (match_operand 1 "comparison_operator" "")
+ (match_operand:SF 2 "nonmemory_operand" "")
+ (match_operand:SF 3 "register_operand" "")))]
""
"
{
@@ -3346,9 +3346,9 @@
(define_expand "movdfcc"
[(set (match_operand:DF 0 "register_operand" "")
- (if_then_else (match_operand 1 "comparison_operator" "")
- (match_operand:DF 2 "nonmemory_operand" "")
- (match_operand:DF 3 "register_operand" "")))]
+ (if_then_else:DF (match_operand 1 "comparison_operator" "")
+ (match_operand:DF 2 "nonmemory_operand" "")
+ (match_operand:DF 3 "register_operand" "")))]
"TARGET_HARD_FLOAT"
"
{
@@ -3361,10 +3361,10 @@
(define_insn "*movsicc_insn"
[(set (match_operand:SI 0 "register_operand" "=r,r")
- (if_then_else (match_operator 1 "comparison_operator"
- [(reg 24) (const_int 0)])
- (match_operand:SI 2 "arm_not_operand" "rI,K")
- (match_operand:SI 3 "register_operand" "0,0")))]
+ (if_then_else:SI (match_operator 1 "comparison_operator"
+ [(reg 24) (const_int 0)])
+ (match_operand:SI 2 "arm_not_operand" "rI,K")
+ (match_operand:SI 3 "register_operand" "0,0")))]
""
"@
mov%d1\\t%0, %2
@@ -3374,10 +3374,10 @@
(define_insn "*movsfcc_hard_insn"
[(set (match_operand:SF 0 "register_operand" "=f")
- (if_then_else (match_operator 1 "comparison_operator"
- [(reg 24) (const_int 0)])
- (match_operand:SF 2 "register_operand" "f")
- (match_operand:SF 3 "register_operand" "0")))]
+ (if_then_else:SF (match_operator 1 "comparison_operator"
+ [(reg 24) (const_int 0)])
+ (match_operand:SF 2 "register_operand" "f")
+ (match_operand:SF 3 "register_operand" "0")))]
"TARGET_HARD_FLOAT"
"mvf%d1s\\t%0, %2"
[(set_attr "type" "ffarith")
@@ -3385,10 +3385,10 @@
(define_insn "*movsfcc_soft_insn"
[(set (match_operand:SF 0 "register_operand" "=r")
- (if_then_else (match_operator 1 "comparison_operator"
- [(reg 24) (const_int 0)])
- (match_operand:SF 2 "register_operand" "r")
- (match_operand:SF 3 "register_operand" "0")))]
+ (if_then_else:SF (match_operator 1 "comparison_operator"
+ [(reg 24) (const_int 0)])
+ (match_operand:SF 2 "register_operand" "r")
+ (match_operand:SF 3 "register_operand" "0")))]
"TARGET_SOFT_FLOAT"
"mov%d1\\t%0, %2"
[(set_attr "type" "*")
@@ -3396,10 +3396,10 @@
(define_insn "*movdfcc_insn"
[(set (match_operand:DF 0 "register_operand" "=f")
- (if_then_else (match_operator 1 "comparison_operator"
- [(reg 24) (const_int 0)])
- (match_operand:DF 2 "register_operand" "f")
- (match_operand:DF 3 "register_operand" "0")))]
+ (if_then_else:DF (match_operator 1 "comparison_operator"
+ [(reg 24) (const_int 0)])
+ (match_operand:DF 2 "register_operand" "f")
+ (match_operand:DF 3 "register_operand" "0")))]
"TARGET_HARD_FLOAT"
"mvf%d1d\\t%0, %2"
[(set_attr "type" "ffarith")
diff --git a/gnu/usr.bin/gcc/config/i386/freebsd.h b/gnu/usr.bin/gcc/config/i386/freebsd.h
index 72fcdd13366..c4e9991c62f 100644
--- a/gnu/usr.bin/gcc/config/i386/freebsd.h
+++ b/gnu/usr.bin/gcc/config/i386/freebsd.h
@@ -120,12 +120,6 @@ Boston, MA 02111-1307, USA. */
#define TYPE_ASM_OP ".type"
#define SIZE_ASM_OP ".size"
-/* This is how we tell the assembler that a symbol is weak. */
-
-#define ASM_WEAKEN_LABEL(FILE,NAME) \
- do { fputs ("\t.weak\t", FILE); assemble_name (FILE, NAME); \
- fputc ('\n', FILE); } while (0)
-
/* The following macro defines the format used to output the second
operand of the .type assembler directive. Different svr4 assemblers
expect various different forms for this operand. The one given here
diff --git a/gnu/usr.bin/gcc/config/mips/mips.c b/gnu/usr.bin/gcc/config/mips/mips.c
index 205d81f3ed4..9fe34af6e06 100644
--- a/gnu/usr.bin/gcc/config/mips/mips.c
+++ b/gnu/usr.bin/gcc/config/mips/mips.c
@@ -4930,7 +4930,7 @@ mips_expand_prologue ()
enum machine_mode passed_mode = TYPE_MODE (passed_type);
rtx entry_parm;
- if (TYPE_NEEDS_CONSTRUCTING (passed_type))
+ if (TREE_ADDRESSABLE (passed_type))
{
passed_type = build_pointer_type (passed_type);
passed_mode = Pmode;
diff --git a/gnu/usr.bin/gcc/config/msdos/top.sed b/gnu/usr.bin/gcc/config/msdos/top.sed
index 7881236d9b7..bc94119ffea 100644
--- a/gnu/usr.bin/gcc/config/msdos/top.sed
+++ b/gnu/usr.bin/gcc/config/msdos/top.sed
@@ -19,9 +19,9 @@ host_xm_file=config/i386/xm-dos.h
/^xmake_file=/ d
/^tmake_file=/ d
/^version=/ c\
-version=2.7.2
+version=2.7.2.1
/^mainversion=/ c\
-mainversion=2.7.2
+mainversion=2.7.2.1
s/CC = cc/CC = gcc/
s/:\$/: \$/g
s/^ \ *\.\// /
diff --git a/gnu/usr.bin/gcc/config/pa/pa.h b/gnu/usr.bin/gcc/config/pa/pa.h
index 5422df2e7b2..85a4c15c97d 100644
--- a/gnu/usr.bin/gcc/config/pa/pa.h
+++ b/gnu/usr.bin/gcc/config/pa/pa.h
@@ -1067,7 +1067,7 @@ extern enum cmp_type hppa_branch_type;
/* Passing structs by invisible reference uses \
one general register. */ \
if (arg_size > 2 \
- || TYPE_NEEDS_CONSTRUCTING (DECL_ARG_TYPE (parm)))\
+ || TREE_ADDRESSABLE (DECL_ARG_TYPE (parm)))\
arg_size = 1; \
if (arg_size == 2 && i <= 2) \
{ \
diff --git a/gnu/usr.bin/gcc/config/rs6000/rs6000.c b/gnu/usr.bin/gcc/config/rs6000/rs6000.c
index 08ebd4e37da..e1c58b18474 100644
--- a/gnu/usr.bin/gcc/config/rs6000/rs6000.c
+++ b/gnu/usr.bin/gcc/config/rs6000/rs6000.c
@@ -1164,6 +1164,7 @@ expand_block_move_mem (mode, addr, orig_mem)
rtx orig_mem;
{
rtx mem = gen_rtx (MEM, mode, addr);
+ RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (orig_mem);
MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
MEM_IN_STRUCT_P (mem) = MEM_IN_STRUCT_P (orig_mem);
return mem;
@@ -1183,6 +1184,8 @@ int
expand_block_move (operands)
rtx operands[];
{
+ rtx orig_dest = operands[0];
+ rtx orig_src = operands[1];
rtx bytes_rtx = operands[2];
rtx align_rtx = operands[3];
int constp = (GET_CODE (bytes_rtx) == CONST_INT);
@@ -1224,8 +1227,8 @@ expand_block_move (operands)
return 0;
/* Move the address into scratch registers. */
- dest_reg = copy_addr_to_reg (XEXP (operands[0], 0));
- src_reg = copy_addr_to_reg (XEXP (operands[1], 0));
+ dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
+ src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
if (TARGET_STRING) /* string instructions are available */
{
@@ -1242,8 +1245,8 @@ expand_block_move (operands)
&& !fixed_regs[12])
{
move_bytes = (bytes > 32) ? 32 : bytes;
- emit_insn (gen_movstrsi_8reg (dest_reg,
- src_reg,
+ emit_insn (gen_movstrsi_8reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest),
+ expand_block_move_mem (BLKmode, src_reg, orig_src),
GEN_INT ((move_bytes == 32) ? 0 : move_bytes),
align_rtx));
}
@@ -1256,8 +1259,8 @@ expand_block_move (operands)
&& !fixed_regs[12])
{
move_bytes = (bytes > 24) ? 24 : bytes;
- emit_insn (gen_movstrsi_6reg (dest_reg,
- src_reg,
+ emit_insn (gen_movstrsi_6reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest),
+ expand_block_move_mem (BLKmode, src_reg, orig_src),
GEN_INT (move_bytes),
align_rtx));
}
@@ -1268,16 +1271,16 @@ expand_block_move (operands)
&& !fixed_regs[12])
{
move_bytes = (bytes > 16) ? 16 : bytes;
- emit_insn (gen_movstrsi_4reg (dest_reg,
- src_reg,
+ emit_insn (gen_movstrsi_4reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest),
+ expand_block_move_mem (BLKmode, src_reg, orig_src),
GEN_INT (move_bytes),
align_rtx));
}
else if (bytes > 4 && !TARGET_64BIT)
{ /* move up to 8 bytes at a time */
move_bytes = (bytes > 8) ? 8 : bytes;
- emit_insn (gen_movstrsi_2reg (dest_reg,
- src_reg,
+ emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest),
+ expand_block_move_mem (BLKmode, src_reg, orig_src),
GEN_INT (move_bytes),
align_rtx));
}
@@ -1285,28 +1288,28 @@ expand_block_move (operands)
{ /* move 4 bytes */
move_bytes = 4;
tmp_reg = gen_reg_rtx (SImode);
- emit_move_insn (tmp_reg, gen_rtx (MEM, SImode, src_reg));
- emit_move_insn (gen_rtx (MEM, SImode, dest_reg), tmp_reg);
+ emit_move_insn (tmp_reg, expand_block_move_mem (SImode, src_reg, orig_src));
+ emit_move_insn (expand_block_move_mem (SImode, dest_reg, orig_dest), tmp_reg);
}
else if (bytes == 2 && (align >= 2 || !STRICT_ALIGNMENT))
{ /* move 2 bytes */
move_bytes = 2;
tmp_reg = gen_reg_rtx (HImode);
- emit_move_insn (tmp_reg, gen_rtx (MEM, HImode, src_reg));
- emit_move_insn (gen_rtx (MEM, HImode, dest_reg), tmp_reg);
+ emit_move_insn (tmp_reg, expand_block_move_mem (HImode, src_reg, orig_src));
+ emit_move_insn (expand_block_move_mem (HImode, dest_reg, orig_dest), tmp_reg);
}
else if (bytes == 1) /* move 1 byte */
{
move_bytes = 1;
tmp_reg = gen_reg_rtx (QImode);
- emit_move_insn (tmp_reg, gen_rtx (MEM, QImode, src_reg));
- emit_move_insn (gen_rtx (MEM, QImode, dest_reg), tmp_reg);
+ emit_move_insn (tmp_reg, expand_block_move_mem (QImode, src_reg, orig_src));
+ emit_move_insn (expand_block_move_mem (QImode, dest_reg, orig_dest), tmp_reg);
}
else
{ /* move up to 4 bytes at a time */
move_bytes = (bytes > 4) ? 4 : bytes;
- emit_insn (gen_movstrsi_1reg (dest_reg,
- src_reg,
+ emit_insn (gen_movstrsi_1reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest),
+ expand_block_move_mem (BLKmode, src_reg, orig_src),
GEN_INT (move_bytes),
align_rtx));
}
@@ -1337,26 +1340,33 @@ expand_block_move (operands)
}
/* Generate the appropriate load and store, saving the stores for later */
- if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT))
+ if (bytes >= 8 && TARGET_64BIT && (align >= 8 || !STRICT_ALIGNMENT))
+ {
+ move_bytes = 8;
+ tmp_reg = gen_reg_rtx (DImode);
+ emit_insn (gen_movdi (tmp_reg, expand_block_move_mem (DImode, src_addr, orig_src)));
+ stores[ num_reg++ ] = gen_movdi (expand_block_move_mem (DImode, dest_addr, orig_dest), tmp_reg);
+ }
+ else if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT))
{
move_bytes = 4;
tmp_reg = gen_reg_rtx (SImode);
- emit_insn (gen_movsi (tmp_reg, gen_rtx (MEM, SImode, src_addr)));
- stores[ num_reg++ ] = gen_movsi (gen_rtx (MEM, SImode, dest_addr), tmp_reg);
+ emit_insn (gen_movsi (tmp_reg, expand_block_move_mem (SImode, src_addr, orig_src)));
+ stores[ num_reg++ ] = gen_movsi (expand_block_move_mem (SImode, dest_addr, orig_dest), tmp_reg);
}
else if (bytes >= 2 && (align >= 2 || !STRICT_ALIGNMENT))
{
move_bytes = 2;
tmp_reg = gen_reg_rtx (HImode);
- emit_insn (gen_movhi (tmp_reg, gen_rtx (MEM, HImode, src_addr)));
- stores[ num_reg++ ] = gen_movhi (gen_rtx (MEM, HImode, dest_addr), tmp_reg);
+ emit_insn (gen_movsi (tmp_reg, expand_block_move_mem (HImode, src_addr, orig_src)));
+ stores[ num_reg++ ] = gen_movhi (expand_block_move_mem (HImode, dest_addr, orig_dest), tmp_reg);
}
else
{
move_bytes = 1;
tmp_reg = gen_reg_rtx (QImode);
- emit_insn (gen_movqi (tmp_reg, gen_rtx (MEM, QImode, src_addr)));
- stores[ num_reg++ ] = gen_movqi (gen_rtx (MEM, QImode, dest_addr), tmp_reg);
+ emit_insn (gen_movsi (tmp_reg, expand_block_move_mem (QImode, src_addr, orig_src)));
+ stores[ num_reg++ ] = gen_movqi (expand_block_move_mem (QImode, dest_addr, orig_dest), tmp_reg);
}
if (num_reg >= MAX_MOVE_REG)
@@ -1367,11 +1377,8 @@ expand_block_move (operands)
}
}
- if (num_reg > 0)
- {
- for (i = 0; i < num_reg; i++)
- emit_insn (stores[i]);
- }
+ for (i = 0; i < num_reg; i++)
+ emit_insn (stores[i]);
}
return 1;
@@ -2611,6 +2618,9 @@ output_prolog (file, size)
{
rs6000_stack_t *info = rs6000_stack_info ();
char *store_reg = (TARGET_64BIT) ? "\tstd %s,%d(%s)" : "\t{st|stw} %s,%d(%s)\n";
+ int reg_size = info->reg_size;
+ int sp_reg = 1;
+ int sp_offset = 0;
if (TARGET_DEBUG_STACK)
debug_stack_info (info);
@@ -2644,12 +2654,38 @@ output_prolog (file, size)
common_mode_defined = 1;
}
+ /* For V.4, update stack before we do any saving and set back pointer. */
+#ifdef USING_SVR4_H
+ if (info->push_p && TARGET_V4_CALLS)
+ {
+ if (info->total_size < 32767)
+ {
+ asm_fprintf (file,
+ (!TARGET_64BIT) ? "\t{stu|stwu} %s,%d(%s)\n" : "\tstdu %s,%d(%s)\n",
+ reg_names[1], - info->total_size, reg_names[1]);
+ sp_offset = info->total_size;
+ }
+ else
+ {
+ int neg_size = - info->total_size;
+ sp_reg = 12;
+ asm_fprintf (file, "\tmr %s,%s\n", reg_names[12], reg_names[1]);
+ asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n",
+ reg_names[0], (neg_size >> 16) & 0xffff,
+ reg_names[0], reg_names[0], neg_size & 0xffff);
+ asm_fprintf (file,
+ (!TARGET_64BIT) ? "\t{stux|stwux} %s,%s,%s\n" : "\tstdux %s,%s,%s\n",
+ reg_names[1], reg_names[1], reg_names[0]);
+ }
+ }
+#endif
+
/* If we use the link register, get it into r0. */
if (info->lr_save_p)
asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
/* If we need to save CR, put it into r12. */
- if (info->cr_save_p)
+ if (info->cr_save_p && sp_reg != 12)
asm_fprintf (file, "\tmfcr %s\n", reg_names[12]);
/* Do any required saving of fpr's. If only one or two to save, do it
@@ -2658,10 +2694,10 @@ output_prolog (file, size)
if (FP_SAVE_INLINE (info->first_fp_reg_save))
{
int regno = info->first_fp_reg_save;
- int loc = info->fp_save_offset;
+ int loc = info->fp_save_offset + sp_offset;
for ( ; regno < 64; regno++, loc += 8)
- asm_fprintf (file, "\tstfd %s,%d(%s)\n", reg_names[regno], loc, reg_names[1]);
+ asm_fprintf (file, "\tstfd %s,%d(%s)\n", reg_names[regno], loc, reg_names[sp_reg]);
}
else if (info->first_fp_reg_save != 64)
asm_fprintf (file, "\tbl %s%d%s\n", SAVE_FP_PREFIX,
@@ -2671,29 +2707,44 @@ output_prolog (file, size)
if (! TARGET_MULTIPLE || info->first_gp_reg_save == 31 || TARGET_64BIT)
{
int regno = info->first_gp_reg_save;
- int loc = info->gp_save_offset;
- int reg_size = (TARGET_64BIT) ? 8 : 4;
+ int loc = info->gp_save_offset + sp_offset;
for ( ; regno < 32; regno++, loc += reg_size)
- asm_fprintf (file, store_reg, reg_names[regno], loc, reg_names[1]);
+ asm_fprintf (file, store_reg, reg_names[regno], loc, reg_names[sp_reg]);
}
else if (info->first_gp_reg_save != 32)
asm_fprintf (file, "\t{stm|stmw} %s,%d(%s)\n",
reg_names[info->first_gp_reg_save],
- info->gp_save_offset,
- reg_names[1]);
+ info->gp_save_offset + sp_offset,
+ reg_names[sp_reg]);
/* Save lr if we used it. */
if (info->lr_save_p)
- asm_fprintf (file, store_reg, reg_names[0], info->lr_save_offset, reg_names[1]);
+ asm_fprintf (file, store_reg, reg_names[0], info->lr_save_offset + sp_offset,
+ reg_names[sp_reg]);
/* Save CR if we use any that must be preserved. */
if (info->cr_save_p)
- asm_fprintf (file, store_reg, reg_names[12], info->cr_save_offset, reg_names[1]);
+ {
+ if (sp_reg == 12) /* If r12 is used to hold the original sp, copy cr now */
+ {
+ asm_fprintf (file, "\tmfcr %s\n", reg_names[0]);
+ asm_fprintf (file, store_reg, reg_names[0],
+ info->cr_save_offset + sp_offset,
+ reg_names[sp_reg]);
+ }
+ else
+ asm_fprintf (file, store_reg, reg_names[12], info->cr_save_offset + sp_offset,
+ reg_names[sp_reg]);
+ }
- /* Update stack and set back pointer. */
- if (info->push_p)
+ /* Update stack and set back pointer and we have already done so for V.4. */
+ if (info->push_p
+#ifdef USING_SVR4_H
+ && TARGET_AIX_CALLS
+#endif
+ )
{
if (info->total_size < 32767)
asm_fprintf (file,
@@ -2791,6 +2842,8 @@ output_epilog (file, size)
rs6000_stack_t *info = rs6000_stack_info ();
char *load_reg = (TARGET_64BIT) ? "\tld %s,%d(%s)" : "\t{l|lwz} %s,%d(%s)\n";
rtx insn = get_last_insn ();
+ int sp_reg = 1;
+ int sp_offset = 0;
int i;
/* Forget about any temporaries created */
@@ -2808,9 +2861,23 @@ output_epilog (file, size)
we know what size to update it with. */
if (frame_pointer_needed || current_function_calls_alloca
|| info->total_size > 32767)
- asm_fprintf (file, load_reg, reg_names[1], 0, reg_names[1]);
+ {
+ /* Under V.4, don't reset the stack pointer until after we're done
+ loading the saved registers. */
+#ifdef USING_SVR4_H
+ if (TARGET_V4_CALLS)
+ sp_reg = 11;
+#endif
+
+ asm_fprintf (file, load_reg, reg_names[sp_reg], 0, reg_names[1]);
+ }
else if (info->push_p)
{
+#ifdef USING_SVR4_H
+ if (TARGET_V4_CALLS)
+ sp_offset = info->total_size;
+ else
+#endif
if (TARGET_NEW_MNEMONICS)
asm_fprintf (file, "\taddi %s,%s,%d\n", reg_names[1], reg_names[1], info->total_size);
else
@@ -2819,11 +2886,11 @@ output_epilog (file, size)
/* Get the old lr if we saved it. */
if (info->lr_save_p)
- asm_fprintf (file, load_reg, reg_names[0], info->lr_save_offset, reg_names[1]);
+ asm_fprintf (file, load_reg, reg_names[0], info->lr_save_offset + sp_offset, reg_names[sp_reg]);
/* Get the old cr if we saved it. */
if (info->cr_save_p)
- asm_fprintf (file, load_reg, reg_names[12], info->cr_save_offset, reg_names[1]);
+ asm_fprintf (file, load_reg, reg_names[12], info->cr_save_offset + sp_offset, reg_names[sp_reg]);
/* Set LR here to try to overlap restores below. */
if (info->lr_save_p)
@@ -2833,27 +2900,27 @@ output_epilog (file, size)
if (! TARGET_MULTIPLE || info->first_gp_reg_save == 31 || TARGET_64BIT)
{
int regno = info->first_gp_reg_save;
- int loc = info->gp_save_offset;
+ int loc = info->gp_save_offset + sp_offset;
int reg_size = (TARGET_64BIT) ? 8 : 4;
for ( ; regno < 32; regno++, loc += reg_size)
- asm_fprintf (file, load_reg, reg_names[regno], loc, reg_names[1]);
+ asm_fprintf (file, load_reg, reg_names[regno], loc, reg_names[sp_reg]);
}
else if (info->first_gp_reg_save != 32)
asm_fprintf (file, "\t{lm|lmw} %s,%d(%s)\n",
reg_names[info->first_gp_reg_save],
- info->gp_save_offset,
- reg_names[1]);
+ info->gp_save_offset + sp_offset,
+ reg_names[sp_reg]);
/* Restore fpr's if we can do it without calling a function. */
if (FP_SAVE_INLINE (info->first_fp_reg_save))
{
int regno = info->first_fp_reg_save;
- int loc = info->fp_save_offset;
+ int loc = info->fp_save_offset + sp_offset;
for ( ; regno < 64; regno++, loc += 8)
- asm_fprintf (file, "\tlfd %s,%d(%s)\n", reg_names[regno], loc, reg_names[1]);
+ asm_fprintf (file, "\tlfd %s,%d(%s)\n", reg_names[regno], loc, reg_names[sp_reg]);
}
/* If we saved cr, restore it here. Just those of cr2, cr3, and cr4
@@ -2864,6 +2931,19 @@ output_epilog (file, size)
+ (regs_ever_live[71] != 0) * 0x10
+ (regs_ever_live[72] != 0) * 0x8, reg_names[12]);
+ /* If this is V.4, unwind the stack pointer after all of the loads have been done */
+#ifdef USING_SVR4_H
+ if (sp_offset)
+ {
+ if (TARGET_NEW_MNEMONICS)
+ asm_fprintf (file, "\taddi %s,%s,%d\n", reg_names[1], reg_names[1], sp_offset);
+ else
+ asm_fprintf (file, "\tcal %s,%d(%s)\n", reg_names[1], sp_offset, reg_names[1]);
+ }
+ else if (sp_reg != 1)
+ asm_fprintf (file, "\tmr %s,%s\n", reg_names[1], reg_names[sp_reg]);
+#endif
+
/* If we have to restore more than two FP registers, branch to the
restore function. It will return to our caller. */
if (info->first_fp_reg_save != 64 && !FP_SAVE_INLINE (info->first_fp_reg_save))
diff --git a/gnu/usr.bin/gcc/config/rs6000/rs6000.md b/gnu/usr.bin/gcc/config/rs6000/rs6000.md
index 3a975abe03f..99ca900c3dd 100644
--- a/gnu/usr.bin/gcc/config/rs6000/rs6000.md
+++ b/gnu/usr.bin/gcc/config/rs6000/rs6000.md
@@ -814,7 +814,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(not:SI (match_dup 1)))]
""
- "nor. %0,%2,%1"
+ "nor. %0,%1,%1"
[(set_attr "type" "compare")])
(define_insn ""
@@ -1492,7 +1492,9 @@
(set (reg:SI 4)
(umod:SI (reg:SI 3) (reg:SI 4)))
(clobber (match_scratch:SI 0 "=l"))
- (clobber (reg:SI 0))]
+ (clobber (reg:SI 0))
+ (clobber (match_scratch:CC 1 "=x"))
+ (clobber (reg:CC 69))]
"! TARGET_POWER && ! TARGET_POWERPC"
"bla __divus")
@@ -1507,7 +1509,9 @@
[(set (reg:SI 3)
(udiv:SI (reg:SI 3) (reg:SI 4)))
(clobber (match_scratch:SI 0 "=l"))
- (clobber (reg:SI 0))]
+ (clobber (reg:SI 0))
+ (clobber (match_scratch:CC 1 "=x"))
+ (clobber (reg:CC 69))]
"! TARGET_POWER && ! TARGET_POWERPC"
"bla __quous")
@@ -4823,10 +4827,10 @@
;; Argument 3 is the alignment
(define_expand "movstrsi"
- [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
- (match_operand:BLK 1 "memory_operand" ""))
- (use (match_operand:SI 2 "general_operand" ""))
- (use (match_operand:SI 3 "immediate_operand" ""))])]
+ [(parallel [(set (match_operand:BLK 0 "" "")
+ (match_operand:BLK 1 "" ""))
+ (use (match_operand:SI 2 "" ""))
+ (use (match_operand:SI 3 "" ""))])]
""
"
{
@@ -4839,10 +4843,10 @@
;; Move up to 32 bytes at a time. The fixed registers are needed because the
;; register allocator doesn't have a clue about allocating 8 word registers
(define_expand "movstrsi_8reg"
- [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
- (mem:BLK (match_operand:SI 1 "register_operand" "")))
- (use (match_operand:SI 2 "immediate_operand" ""))
- (use (match_operand:SI 3 "immediate_operand" ""))
+ [(parallel [(set (match_operand 0 "" "")
+ (match_operand 1 "" ""))
+ (use (match_operand 2 "" ""))
+ (use (match_operand 3 "" ""))
(clobber (reg:SI 5))
(clobber (reg:SI 6))
(clobber (reg:SI 7))
@@ -4875,7 +4879,8 @@
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
&& REGNO (operands[4]) == 5"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
- [(set_attr "length" "8")])
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
(define_insn ""
[(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
@@ -4897,15 +4902,16 @@
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
&& REGNO (operands[4]) == 5"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
- [(set_attr "length" "8")])
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
;; Move up to 24 bytes at a time. The fixed registers are needed because the
;; register allocator doesn't have a clue about allocating 6 word registers
(define_expand "movstrsi_6reg"
- [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
- (mem:BLK (match_operand:SI 1 "register_operand" "")))
- (use (match_operand:SI 2 "immediate_operand" ""))
- (use (match_operand:SI 3 "immediate_operand" ""))
+ [(parallel [(set (match_operand 0 "" "")
+ (match_operand 1 "" ""))
+ (use (match_operand 2 "" ""))
+ (use (match_operand 3 "" ""))
(clobber (reg:SI 7))
(clobber (reg:SI 8))
(clobber (reg:SI 9))
@@ -4934,7 +4940,8 @@
&& (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12)
&& REGNO (operands[4]) == 7"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
- [(set_attr "length" "8")])
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
(define_insn ""
[(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
@@ -4954,15 +4961,16 @@
&& (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12)
&& REGNO (operands[4]) == 7"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
- [(set_attr "length" "8")])
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill problems
;; with TImode
(define_expand "movstrsi_4reg"
- [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
- (mem:BLK (match_operand:SI 1 "register_operand" "")))
- (use (match_operand:SI 2 "immediate_operand" ""))
- (use (match_operand:SI 3 "immediate_operand" ""))
+ [(parallel [(set (match_operand 0 "" "")
+ (match_operand 1 "" ""))
+ (use (match_operand 2 "" ""))
+ (use (match_operand 3 "" ""))
(clobber (reg:SI 9))
(clobber (reg:SI 10))
(clobber (reg:SI 11))
@@ -4987,7 +4995,8 @@
&& (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12)
&& REGNO (operands[4]) == 9"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
- [(set_attr "length" "8")])
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
(define_insn ""
[(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
@@ -5005,14 +5014,15 @@
&& (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12)
&& REGNO (operands[4]) == 9"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
- [(set_attr "length" "8")])
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
;; Move up to 8 bytes at a time.
(define_expand "movstrsi_2reg"
- [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
- (mem:BLK (match_operand:SI 1 "register_operand" "")))
- (use (match_operand:SI 2 "immediate_operand" ""))
- (use (match_operand:SI 3 "immediate_operand" ""))
+ [(parallel [(set (match_operand 0 "" "")
+ (match_operand 1 "" ""))
+ (use (match_operand 2 "" ""))
+ (use (match_operand 3 "" ""))
(clobber (match_scratch:DI 4 ""))
(clobber (match_scratch:SI 5 ""))])]
"TARGET_STRING && !TARGET_64BIT"
@@ -5028,7 +5038,8 @@
"TARGET_STRING && TARGET_POWER && !TARGET_64BIT
&& INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
- [(set_attr "length" "8")])
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
(define_insn ""
[(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
@@ -5040,14 +5051,15 @@
"TARGET_STRING && !TARGET_POWER && !TARGET_64BIT
&& INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
- [(set_attr "length" "8")])
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
;; Move up to 4 bytes at a time.
(define_expand "movstrsi_1reg"
- [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
- (mem:BLK (match_operand:SI 1 "register_operand" "")))
- (use (match_operand:SI 2 "immediate_operand" ""))
- (use (match_operand:SI 3 "immediate_operand" ""))
+ [(parallel [(set (match_operand 0 "" "")
+ (match_operand 1 "" ""))
+ (use (match_operand 2 "" ""))
+ (use (match_operand 3 "" ""))
(clobber (match_scratch:SI 4 ""))
(clobber (match_scratch:SI 5 ""))])]
"TARGET_STRING"
@@ -5063,7 +5075,8 @@
"TARGET_STRING && TARGET_POWER
&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
- [(set_attr "length" "8")])
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
(define_insn ""
[(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
@@ -5075,7 +5088,8 @@
"TARGET_STRING && !TARGET_POWER
&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
- [(set_attr "length" "8")])
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
;; Define insns that do load or store with update. Some of these we can
diff --git a/gnu/usr.bin/gcc/config/sparc/sparc.h b/gnu/usr.bin/gcc/config/sparc/sparc.h
index 5edf530050d..d8ba186c7f2 100644
--- a/gnu/usr.bin/gcc/config/sparc/sparc.h
+++ b/gnu/usr.bin/gcc/config/sparc/sparc.h
@@ -621,18 +621,10 @@ do \
for (regno = 32; regno < FIRST_PSEUDO_REGISTER; regno++) \
fixed_regs[regno] = 1; \
} \
- if (! TARGET_APP_REGS) \
- { \
- fixed_regs[2] = 1; \
- fixed_regs[3] = 1; \
- fixed_regs[4] = 1; \
- } \
- else \
- { \
- fixed_regs[2] = 0; \
- fixed_regs[3] = 0; \
- fixed_regs[4] = TARGET_MEDANY != 0; \
- } \
+ /* Don't unfix g2-g4 if they were fixed with -ffixed-. */ \
+ fixed_regs[2] |= ! TARGET_APP_REGS; \
+ fixed_regs[3] |= ! TARGET_APP_REGS; \
+ fixed_regs[4] |= ! TARGET_APP_REGS || TARGET_MEDANY; \
if (TARGET_FLAT) \
{ \
/* Let the compiler believe the frame pointer is still \
diff --git a/gnu/usr.bin/gcc/config/svr4.h b/gnu/usr.bin/gcc/config/svr4.h
index bc80297359d..41c6ffa0e10 100644
--- a/gnu/usr.bin/gcc/config/svr4.h
+++ b/gnu/usr.bin/gcc/config/svr4.h
@@ -273,15 +273,23 @@ do { \
#define DBX_BLOCKS_FUNCTION_RELATIVE 1
/* When using stabs, gcc2_compiled must be a stabs entry, not an
- ordinary symbol, or gdb won't see it. The stabs entry must be
- before the N_SO in order for gdb to find it. */
+ ordinary symbol, or gdb won't see it. Furthermore, since gdb reads
+ the input piecemeal, starting with each N_SO, it's a lot easier if
+ the gcc2 flag symbol is *after* the N_SO rather than before it. So
+ we emit an N_OPT stab there. */
#define ASM_IDENTIFY_GCC(FILE) \
do \
{ \
if (write_symbols != DBX_DEBUG) \
fputs ("gcc2_compiled.:\n", FILE); \
- else \
+ } \
+while (0)
+
+#define ASM_IDENTIFY_GCC_AFTER_SOURCE(FILE) \
+do \
+ { \
+ if (write_symbols == DBX_DEBUG) \
fputs ("\t.stabs\t\"gcc2_compiled.\", 0x3c, 0, 0, 0\n", FILE); \
} \
while (0)
diff --git a/gnu/usr.bin/gcc/config/vax/vax.h b/gnu/usr.bin/gcc/config/vax/vax.h
index 99386c08903..10ba85509c6 100644
--- a/gnu/usr.bin/gcc/config/vax/vax.h
+++ b/gnu/usr.bin/gcc/config/vax/vax.h
@@ -963,7 +963,8 @@ gen_rtx (PLUS, Pmode, frame, gen_rtx (CONST_INT, VOIDmode, 12))
{ if (GET_CODE (EXP) == SET) \
{ if (GET_CODE (SET_SRC (EXP)) == CALL) \
CC_STATUS_INIT; \
- else if (GET_CODE (SET_DEST (EXP)) != PC) \
+ else if (GET_CODE (SET_DEST (EXP)) != ZERO_EXTRACT \
+ && GET_CODE (SET_DEST (EXP)) != PC) \
{ cc_status.flags = 0; \
cc_status.value1 = SET_DEST (EXP); \
cc_status.value2 = SET_SRC (EXP); } } \
diff --git a/gnu/usr.bin/gcc/config/vax/vax.md b/gnu/usr.bin/gcc/config/vax/vax.md
index 3dd73df62aa..0b0c5c4ac66 100644
--- a/gnu/usr.bin/gcc/config/vax/vax.md
+++ b/gnu/usr.bin/gcc/config/vax/vax.md
@@ -1341,6 +1341,7 @@
operands[0]
= adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
+ CC_STATUS_INIT;
if (INTVAL (operands[1]) == 8)
return \"movb %3,%0\";
return \"movw %3,%0\";
diff --git a/gnu/usr.bin/gcc/config/winnt/config-nt.sed b/gnu/usr.bin/gcc/config/winnt/config-nt.sed
index ee0088ad818..d70f5c6cc74 100644
--- a/gnu/usr.bin/gcc/config/winnt/config-nt.sed
+++ b/gnu/usr.bin/gcc/config/winnt/config-nt.sed
@@ -13,7 +13,7 @@ s/$(srcdir)\/c-gperf/c-gperf/g
/^lang_specs_files=/ d
/^lang_options_files=/ d
/^version=/ c\
-version=2.7.2
+version=2.7.2.1
s/CC = cc/CC = cl/
s/^SHELL =.*/SHELL =/
s/CFLAGS = -g/CFLAGS =/
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-20 06:11:18 +0000