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diff --git a/share/man/man4/man4.i386/cpu.4 b/share/man/man4/man4.i386/cpu.4 new file mode 100644 index 00000000000..aa0656394a3 --- /dev/null +++ b/share/man/man4/man4.i386/cpu.4 @@ -0,0 +1,82 @@ +.\" $OpenBSD: cpu.4,v 1.1 2004/03/17 01:28:01 tedu Exp $ +.\" +.\" Copyright (c) 2004 Ted Unangst +.\" All rights reserved. +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +.\" +.Dd March 15, 2004 +.Dt CPU 4 i386 +.Os +.Sh NAME +.Nm cpu +.Nd Central Processing Unit +.Sh SYNOPSIS +.Cd "option I386_CPU" +.Cd "option I486_CPU" +.Cd "option I586_CPU" +.Cd "option I686_CPU" +.Sh DESCRIPTION +Several processor models have additional features that extend their base +functionality, such as power and frequency control or additonal instructions. +.Sh FREQUENCY CONTROL +The +.Xr sysctl 3 +hw.cpuspeed will return the current operating freqency of the processor. +If possible, speed may be adjust by altering hw.setperf from 0 to 100, +representing percentage of maximum speed. +There are several possible implementations for setperf, all transparent +to the user. +In systems with more than one control capability, they are preferred in the +order given. +.Bl -tag -width tenletters +.It LongRun +Found on Transmeta Crusoe processors, offers frequency scaling with numerous +positions. +The processor dynamically adjusts frequency in response to load, the setperf +value is interpreted as the maximum. +.It EST +Enhanced SpeedStep found on Intel Pentium M processors, +offers freqeuncy scaling with numerous positions. +.It SpeedStep +Found on some Intel Pentium 3 and newer mobile chips, +it is capable of adjusting frequency between a low and high value. +Only enabled on some chipsets. +.It TCC +Thermal Control Circuit found on Intel Pentium 4 and newer processors, +adjusts processor duty cycle in 12.5 percent increments. +.El +.Sh INSTRUCTION SET EXTENSIONS +The presence of extended instruction sets can be determined by +sysctl machdep. +.Bl -tag -width "tenletters" +.It osfxr +Supports the fxsave instruction. +.It sse +Supports the SSE instruction set. +.It sse2 +Supports the SSE2 instruction set. +.It xcrypt +Support the VIA AES encryption instruction set. +.El +.Sh SEE ALSO +.Xr npx 4 , +.Xr sysctl 8 |