diff options
Diffstat (limited to 'sys/arch/alpha/pci')
25 files changed, 784 insertions, 540 deletions
diff --git a/sys/arch/alpha/pci/apecs.c b/sys/arch/alpha/pci/apecs.c index 5dfdd42262b..516164eec5d 100644 --- a/sys/arch/alpha/pci/apecs.c +++ b/sys/arch/alpha/pci/apecs.c @@ -1,5 +1,5 @@ -/* $OpenBSD: apecs.c,v 1.6 1996/11/23 21:44:53 kstailey Exp $ */ -/* $NetBSD: apecs.c,v 1.12 1996/10/13 03:00:00 christos Exp $ */ +/* $OpenBSD: apecs.c,v 1.7 1996/12/08 00:20:30 niklas Exp $ */ +/* $NetBSD: apecs.c,v 1.13 1996/10/23 04:12:22 cgd Exp $ */ /* * Copyright (c) 1995, 1996 Carnegie-Mellon University. @@ -45,7 +45,6 @@ #include <dev/pci/pcivar.h> #include <alpha/pci/apecsreg.h> #include <alpha/pci/apecsvar.h> -#include <alpha/pci/apecs_lca.h> #if defined(DEC_2100_A50) #include <alpha/pci/pci_2100_a50.h> #endif @@ -103,8 +102,8 @@ apecs_init(acp) * Can't set up SGMAP data here; can be called before malloc(). */ - apecs_lca_bus_io_init(&acp->ac_bc, acp); - apecs_lca_bus_mem_init(&acp->ac_bc, acp); + acp->ac_iot = apecs_lca_bus_io_init(acp); + acp->ac_memt = apecs_lca_bus_mem_init(acp); apecs_pci_init(&acp->ac_pc, acp); /* Turn off DMA window enables in PCI Base Reg 1. */ @@ -112,6 +111,13 @@ apecs_init(acp) alpha_mb(); /* XXX SGMAP? */ + + /* XXX XXX BEGIN XXX XXX */ + { /* XXX */ + extern vm_offset_t alpha_XXX_dmamap_or; /* XXX */ + alpha_XXX_dmamap_or = 0x40000000; /* XXX */ + } /* XXX */ + /* XXX XXX END XXX XXX */ } void @@ -157,7 +163,8 @@ apecsattach(parent, self, aux) } pba.pba_busname = "pci"; - pba.pba_bc = &acp->ac_bc; + pba.pba_iot = acp->ac_iot; + pba.pba_memt = acp->ac_memt; pba.pba_pc = &acp->ac_pc; pba.pba_bus = 0; config_found(self, &pba, apecsprint); diff --git a/sys/arch/alpha/pci/apecs_lca.h b/sys/arch/alpha/pci/apecs_lca.h deleted file mode 100644 index 5fd663e8ad4..00000000000 --- a/sys/arch/alpha/pci/apecs_lca.h +++ /dev/null @@ -1,35 +0,0 @@ -/* $OpenBSD: apecs_lca.h,v 1.1 1996/10/30 22:39:47 niklas Exp $ */ - -/* - * Copyright (c) 1996 Niklas Hallqvist - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Niklas Hallqvist. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -void apecs_lca_bus_io_init __P((bus_chipset_tag_t, void *)); -void apecs_lca_bus_mem_init __P((bus_chipset_tag_t, void *)); diff --git a/sys/arch/alpha/pci/apecs_lca_bus_io.c b/sys/arch/alpha/pci/apecs_lca_bus_io.c index cb38a68f56c..e388db74be7 100644 --- a/sys/arch/alpha/pci/apecs_lca_bus_io.c +++ b/sys/arch/alpha/pci/apecs_lca_bus_io.c @@ -1,4 +1,4 @@ -/* $OpenBSD: apecs_lca_bus_io.c,v 1.4 1996/11/12 20:29:33 niklas Exp $ */ +/* $OpenBSD: apecs_lca_bus_io.c,v 1.5 1996/12/08 00:20:32 niklas Exp $ */ /* $NetBSD: apecs_lca_bus_io.c,v 1.4 1996/08/27 16:29:23 cgd Exp $ */ /* @@ -35,11 +35,11 @@ #include <sys/device.h> #include <vm/vm.h> -#include <machine/bus.old.h> +#include <machine/bus.h> #include <alpha/pci/apecsreg.h> #include <alpha/pci/lcareg.h> -#include <alpha/pci/apecs_lca.h> +#include <alpha/pci/lcavar.h> #if (APECS_PCI_SIO != LCA_PCI_SIO) #error Sparse I/O addresses do not match up? diff --git a/sys/arch/alpha/pci/apecs_lca_bus_mem.c b/sys/arch/alpha/pci/apecs_lca_bus_mem.c index e0d00e83b6e..47c1dac1706 100644 --- a/sys/arch/alpha/pci/apecs_lca_bus_mem.c +++ b/sys/arch/alpha/pci/apecs_lca_bus_mem.c @@ -1,4 +1,4 @@ -/* $OpenBSD: apecs_lca_bus_mem.c,v 1.4 1996/11/12 20:29:34 niklas Exp $ */ +/* $OpenBSD: apecs_lca_bus_mem.c,v 1.5 1996/12/08 00:20:33 niklas Exp $ */ /* $NetBSD: apecs_lca_bus_mem.c,v 1.5 1996/08/27 16:29:24 cgd Exp $ */ /* @@ -35,11 +35,11 @@ #include <sys/device.h> #include <vm/vm.h> -#include <machine/bus.old.h> +#include <machine/bus.h> #include <alpha/pci/apecsreg.h> #include <alpha/pci/lcareg.h> -#include <alpha/pci/apecs_lca.h> +#include <alpha/pci/lcavar.h> #if (APECS_PCI_SPARSE != LCA_PCI_SPARSE) || (APECS_PCI_DENSE != LCA_PCI_DENSE) #error Memory addresses do not match up? diff --git a/sys/arch/alpha/pci/apecsvar.h b/sys/arch/alpha/pci/apecsvar.h index 7028f9cb039..d43c23d0b97 100644 --- a/sys/arch/alpha/pci/apecsvar.h +++ b/sys/arch/alpha/pci/apecsvar.h @@ -1,5 +1,5 @@ -/* $OpenBSD: apecsvar.h,v 1.4 1996/10/30 22:39:51 niklas Exp $ */ -/* $NetBSD: apecsvar.h,v 1.3 1996/04/12 06:08:14 cgd Exp $ */ +/* $OpenBSD: apecsvar.h,v 1.5 1996/12/08 00:20:34 niklas Exp $ */ +/* $NetBSD: apecsvar.h,v 1.4 1996/10/23 04:12:23 cgd Exp $ */ /* * Copyright (c) 1995, 1996 Carnegie-Mellon University. @@ -42,7 +42,7 @@ struct apecs_config { int ac_epic_pass2; int ac_memwidth; - struct alpha_bus_chipset ac_bc; + bus_space_tag_t ac_iot, ac_memt; struct alpha_pci_chipset ac_pc; }; @@ -54,3 +54,6 @@ struct apecs_softc { void apecs_init __P((struct apecs_config *)); void apecs_pci_init __P((pci_chipset_tag_t, void *)); + +bus_space_tag_t apecs_lca_bus_io_init __P((void *iov)); +bus_space_tag_t apecs_lca_bus_mem_init __P((void *memv)); diff --git a/sys/arch/alpha/pci/cia.c b/sys/arch/alpha/pci/cia.c index c52bec93a35..2a8731824de 100644 --- a/sys/arch/alpha/pci/cia.c +++ b/sys/arch/alpha/pci/cia.c @@ -1,5 +1,5 @@ -/* $OpenBSD: cia.c,v 1.5 1996/11/23 21:44:54 kstailey Exp $ */ -/* $NetBSD: cia.c,v 1.11 1996/10/13 03:00:03 christos Exp $ */ +/* $OpenBSD: cia.c,v 1.6 1996/12/08 00:20:34 niklas Exp $ */ +/* $NetBSD: cia.c,v 1.12 1996/10/23 04:12:24 cgd Exp $ */ /* * Copyright (c) 1995, 1996 Carnegie-Mellon University. @@ -95,12 +95,19 @@ cia_init(ccp) * Can't set up SGMAP data here; can be called before malloc(). */ - cia_bus_io_init(&ccp->cc_bc, ccp); - cia_bus_mem_init(&ccp->cc_bc, ccp); + ccp->cc_iot = cia_bus_io_init(ccp); + ccp->cc_memt = cia_bus_mem_init(ccp); cia_pci_init(&ccp->cc_pc, ccp); ccp->cc_hae_mem = REGVAL(CIA_CSR_HAE_MEM); ccp->cc_hae_io = REGVAL(CIA_CSR_HAE_IO); + + /* XXX XXX BEGIN XXX XXX */ + { /* XXX */ + extern vm_offset_t alpha_XXX_dmamap_or; /* XXX */ + alpha_XXX_dmamap_or = 0x40000000; /* XXX */ + } /* XXX */ + /* XXX XXX END XXX XXX */ } void @@ -139,7 +146,8 @@ ciaattach(parent, self, aux) } pba.pba_busname = "pci"; - pba.pba_bc = &ccp->cc_bc; + pba.pba_iot = ccp->cc_iot; + pba.pba_memt = ccp->cc_memt; pba.pba_pc = &ccp->cc_pc; pba.pba_bus = 0; config_found(self, &pba, ciaprint); diff --git a/sys/arch/alpha/pci/cia_bus_io.c b/sys/arch/alpha/pci/cia_bus_io.c index 6623986cfa0..b0352ddea0f 100644 --- a/sys/arch/alpha/pci/cia_bus_io.c +++ b/sys/arch/alpha/pci/cia_bus_io.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cia_bus_io.c,v 1.4 1996/11/12 20:29:35 niklas Exp $ */ +/* $OpenBSD: cia_bus_io.c,v 1.5 1996/12/08 00:20:35 niklas Exp $ */ /* $NetBSD: cia_bus_io.c,v 1.5 1996/08/27 16:29:25 cgd Exp $ */ /* @@ -35,7 +35,7 @@ #include <sys/device.h> #include <vm/vm.h> -#include <machine/bus.old.h> +#include <machine/bus.h> #include <alpha/pci/ciareg.h> #include <alpha/pci/ciavar.h> diff --git a/sys/arch/alpha/pci/cia_bus_mem.c b/sys/arch/alpha/pci/cia_bus_mem.c index 2293e001d09..e69819e946f 100644 --- a/sys/arch/alpha/pci/cia_bus_mem.c +++ b/sys/arch/alpha/pci/cia_bus_mem.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cia_bus_mem.c,v 1.4 1996/11/12 20:29:36 niklas Exp $ */ +/* $OpenBSD: cia_bus_mem.c,v 1.5 1996/12/08 00:20:36 niklas Exp $ */ /* $NetBSD: cia_bus_mem.c,v 1.5 1996/08/27 16:29:26 cgd Exp $ */ /* @@ -35,7 +35,7 @@ #include <sys/device.h> #include <vm/vm.h> -#include <machine/bus.old.h> +#include <machine/bus.h> #include <alpha/pci/ciareg.h> #include <alpha/pci/ciavar.h> diff --git a/sys/arch/alpha/pci/ciavar.h b/sys/arch/alpha/pci/ciavar.h index a0b5e82be37..37ae618659d 100644 --- a/sys/arch/alpha/pci/ciavar.h +++ b/sys/arch/alpha/pci/ciavar.h @@ -1,5 +1,5 @@ -/* $OpenBSD: ciavar.h,v 1.4 1996/10/30 22:39:58 niklas Exp $ */ -/* $NetBSD: ciavar.h,v 1.4 1996/06/10 00:03:59 cgd Exp $ */ +/* $OpenBSD: ciavar.h,v 1.5 1996/12/08 00:20:37 niklas Exp $ */ +/* $NetBSD: ciavar.h,v 1.5 1996/10/23 04:12:24 cgd Exp $ */ /* * Copyright (c) 1995, 1996 Carnegie-Mellon University. @@ -38,7 +38,7 @@ * do their dirty work (and more!). */ struct cia_config { - struct alpha_bus_chipset cc_bc; + bus_space_tag_t cc_iot, cc_memt; struct alpha_pci_chipset cc_pc; u_int32_t cc_hae_mem; @@ -55,5 +55,5 @@ struct cia_softc { void cia_init __P((struct cia_config *)); void cia_pci_init __P((pci_chipset_tag_t, void *)); -void cia_bus_mem_init __P((bus_chipset_tag_t bc, void *memv)); -void cia_bus_io_init __P((bus_chipset_tag_t bc, void *iov)); +bus_space_tag_t cia_bus_io_init __P((void *iov)); +bus_space_tag_t cia_bus_mem_init __P((void *memv)); diff --git a/sys/arch/alpha/pci/lca.c b/sys/arch/alpha/pci/lca.c index a0004181456..8ef53fda822 100644 --- a/sys/arch/alpha/pci/lca.c +++ b/sys/arch/alpha/pci/lca.c @@ -1,5 +1,5 @@ -/* $OpenBSD: lca.c,v 1.5 1996/11/23 21:44:54 kstailey Exp $ */ -/* $NetBSD: lca.c,v 1.10 1996/10/13 03:00:07 christos Exp $ */ +/* $OpenBSD: lca.c,v 1.6 1996/12/08 00:20:37 niklas Exp $ */ +/* $NetBSD: lca.c,v 1.11 1996/10/23 04:12:25 cgd Exp $ */ /* * Copyright (c) 1995, 1996 Carnegie-Mellon University. @@ -45,7 +45,6 @@ #include <dev/pci/pcivar.h> #include <alpha/pci/lcareg.h> #include <alpha/pci/lcavar.h> -#include <alpha/pci/apecs_lca.h> #if defined(DEC_AXPPCI_33) #include <alpha/pci/pci_axppci_33.h> #endif @@ -96,8 +95,8 @@ lca_init(lcp) * Can't set up SGMAP data here; can be called before malloc(). */ - apecs_lca_bus_io_init(&lcp->lc_bc, lcp); - apecs_lca_bus_mem_init(&lcp->lc_bc, lcp); + lcp->lc_iot = apecs_lca_bus_io_init(lcp); + lcp->lc_memt = apecs_lca_bus_mem_init(lcp); lca_pci_init(&lcp->lc_pc, lcp); /* @@ -129,6 +128,13 @@ lca_init(lcp) /* REGVAL(LCA_IOC_W_BASE0) = 0; REGVAL(LCA_IOC_W_BASE1) = 0; */ alpha_mb(); + + /* XXX XXX BEGIN XXX XXX */ + { /* XXX */ + extern vm_offset_t alpha_XXX_dmamap_or; /* XXX */ + alpha_XXX_dmamap_or = 0x40000000; /* XXX */ + } /* XXX */ + /* XXX XXX END XXX XXX */ } #ifdef notdef @@ -194,7 +200,8 @@ lcaattach(parent, self, aux) } pba.pba_busname = "pci"; - pba.pba_bc = &lcp->lc_bc; + pba.pba_iot = lcp->lc_iot; + pba.pba_memt = lcp->lc_memt; pba.pba_pc = &lcp->lc_pc; pba.pba_bus = 0; config_found(self, &pba, lcaprint); diff --git a/sys/arch/alpha/pci/lcavar.h b/sys/arch/alpha/pci/lcavar.h index 25762783af6..d09596a0d5d 100644 --- a/sys/arch/alpha/pci/lcavar.h +++ b/sys/arch/alpha/pci/lcavar.h @@ -1,5 +1,5 @@ -/* $OpenBSD: lcavar.h,v 1.4 1996/10/30 22:40:02 niklas Exp $ */ -/* $NetBSD: lcavar.h,v 1.3 1996/04/12 06:08:35 cgd Exp $ */ +/* $OpenBSD: lcavar.h,v 1.5 1996/12/08 00:20:38 niklas Exp $ */ +/* $NetBSD: lcavar.h,v 1.4 1996/10/23 04:12:26 cgd Exp $ */ /* * Copyright (c) 1995, 1996 Carnegie-Mellon University. @@ -38,7 +38,7 @@ * do their dirty work (and more!). */ struct lca_config { - struct alpha_bus_chipset lc_bc; + bus_space_tag_t lc_iot, lc_memt; struct alpha_pci_chipset lc_pc; }; @@ -50,3 +50,6 @@ struct lca_softc { void lca_init __P((struct lca_config *)); void lca_pci_init __P((pci_chipset_tag_t, void *)); + +bus_space_tag_t apecs_lca_bus_io_init __P((void *)); +bus_space_tag_t apecs_lca_bus_mem_init __P((void *)); diff --git a/sys/arch/alpha/pci/pci_2100_a50.c b/sys/arch/alpha/pci/pci_2100_a50.c index 01cacb4fb4b..e4be2215526 100644 --- a/sys/arch/alpha/pci/pci_2100_a50.c +++ b/sys/arch/alpha/pci/pci_2100_a50.c @@ -1,5 +1,5 @@ -/* $OpenBSD: pci_2100_a50.c,v 1.8 1996/11/12 20:29:37 niklas Exp $ */ -/* $NetBSD: pci_2100_a50.c,v 1.10 1996/10/13 03:00:09 christos Exp $ */ +/* $OpenBSD: pci_2100_a50.c,v 1.9 1996/12/08 00:20:39 niklas Exp $ */ +/* $NetBSD: pci_2100_a50.c,v 1.11 1996/10/23 04:12:26 cgd Exp $ */ /* * Copyright (c) 1995, 1996 Carnegie-Mellon University. @@ -37,7 +37,7 @@ #include <vm/vm.h> #include <machine/autoconf.h> -#include <machine/bus.old.h> +#include <machine/bus.h> #include <machine/intr.h> #include <dev/isa/isavar.h> @@ -65,7 +65,7 @@ void pci_2100_a50_pickintr(acp) struct apecs_config *acp; { - bus_chipset_tag_t bc = &acp->ac_bc; + bus_space_tag_t iot = acp->ac_iot; pci_chipset_tag_t pc = &acp->ac_pc; pcireg_t sioclass; int sioII; @@ -84,7 +84,7 @@ pci_2100_a50_pickintr(acp) pc->pc_intr_disestablish = dec_2100_a50_intr_disestablish; #if NSIO - sio_intr_setup(bc); + sio_intr_setup(iot); set_iointr(&sio_iointr); #else panic("pci_2100_a50_pickintr: no I/O interrupt handler (no sio)"); diff --git a/sys/arch/alpha/pci/pci_axppci_33.c b/sys/arch/alpha/pci/pci_axppci_33.c index 2808568bb69..27bd21b0d8a 100644 --- a/sys/arch/alpha/pci/pci_axppci_33.c +++ b/sys/arch/alpha/pci/pci_axppci_33.c @@ -1,5 +1,5 @@ -/* $OpenBSD: pci_axppci_33.c,v 1.7 1996/11/12 20:29:38 niklas Exp $ */ -/* $NetBSD: pci_axppci_33.c,v 1.8 1996/10/13 03:00:11 christos Exp $ */ +/* $OpenBSD: pci_axppci_33.c,v 1.8 1996/12/08 00:20:40 niklas Exp $ */ +/* $NetBSD: pci_axppci_33.c,v 1.9 1996/10/23 04:12:27 cgd Exp $ */ /* * Copyright (c) 1995, 1996 Carnegie-Mellon University. @@ -37,7 +37,7 @@ #include <vm/vm.h> #include <machine/autoconf.h> -#include <machine/bus.old.h> +#include <machine/bus.h> #include <machine/intr.h> #include <dev/isa/isavar.h> @@ -65,7 +65,7 @@ void pci_axppci_33_pickintr(lcp) struct lca_config *lcp; { - bus_chipset_tag_t bc = &lcp->lc_bc; + bus_space_tag_t iot = lcp->lc_iot; pci_chipset_tag_t pc = &lcp->lc_pc; pcireg_t sioclass; int sioII; @@ -85,7 +85,7 @@ pci_axppci_33_pickintr(lcp) pc->pc_intr_disestablish = dec_axppci_33_intr_disestablish; #if NSIO - sio_intr_setup(bc); + sio_intr_setup(iot); set_iointr(&sio_iointr); #else panic("pci_axppci_33_pickintr: no I/O interrupt handler (no sio)"); diff --git a/sys/arch/alpha/pci/pci_kn20aa.c b/sys/arch/alpha/pci/pci_kn20aa.c index 1106261c1cf..ab9683c31fa 100644 --- a/sys/arch/alpha/pci/pci_kn20aa.c +++ b/sys/arch/alpha/pci/pci_kn20aa.c @@ -1,5 +1,5 @@ -/* $OpenBSD: pci_kn20aa.c,v 1.7 1996/10/30 22:40:06 niklas Exp $ */ -/* $NetBSD: pci_kn20aa.c,v 1.18 1996/10/13 03:00:12 christos Exp $ */ +/* $OpenBSD: pci_kn20aa.c,v 1.8 1996/12/08 00:20:41 niklas Exp $ */ +/* $NetBSD: pci_kn20aa.c,v 1.19 1996/10/23 04:12:28 cgd Exp $ */ /* * Copyright (c) 1995, 1996 Carnegie-Mellon University. @@ -96,7 +96,7 @@ pci_kn20aa_pickintr(ccp) struct cia_config *ccp; { int i; - bus_chipset_tag_t bc = &ccp->cc_bc; + bus_space_tag_t iot = ccp->cc_iot; pci_chipset_tag_t pc = &ccp->cc_pc; for (i = 0; i < KN20AA_MAX_IRQ; i++) @@ -109,7 +109,7 @@ pci_kn20aa_pickintr(ccp) pc->pc_intr_disestablish = dec_kn20aa_intr_disestablish; #if NSIO - sio_intr_setup(bc); + sio_intr_setup(iot); #endif set_iointr(kn20aa_iointr); diff --git a/sys/arch/alpha/pci/pci_machdep.c b/sys/arch/alpha/pci/pci_machdep.c index 7e6573e0fbb..128fcc2676e 100644 --- a/sys/arch/alpha/pci/pci_machdep.c +++ b/sys/arch/alpha/pci/pci_machdep.c @@ -1,5 +1,5 @@ -/* $OpenBSD: pci_machdep.c,v 1.5 1996/10/30 22:40:08 niklas Exp $ */ -/* $NetBSD: pci_machdep.c,v 1.5 1996/04/12 06:08:49 cgd Exp $ */ +/* $OpenBSD: pci_machdep.c,v 1.6 1996/12/08 00:20:42 niklas Exp $ */ +/* $NetBSD: pci_machdep.c,v 1.6 1996/10/23 04:12:29 cgd Exp $ */ /* * Copyright (c) 1995, 1996 Carnegie-Mellon University. @@ -56,15 +56,16 @@ #endif void -pci_display_console(bc, pc, bus, device, function) - bus_chipset_tag_t bc; +pci_display_console(iot, memt, pc, bus, device, function) + bus_space_tag_t iot, memt; pci_chipset_tag_t pc; int bus, device, function; { pcitag_t tag; pcireg_t id, class; int match, nmatch; - void (*fn) __P((bus_chipset_tag_t, pci_chipset_tag_t, int, int, int)); + void (*fn) __P((bus_space_tag_t, bus_space_tag_t, pci_chipset_tag_t, + int, int, int)); tag = pci_make_tag(pc, bus, device, function); id = pci_conf_read(pc, tag, PCI_ID_REG); @@ -92,7 +93,7 @@ pci_display_console(bc, pc, bus, device, function) #endif if (fn != NULL) - (*fn)(bc, pc, bus, device, function); + (*fn)(iot, memt, pc, bus, device, function); else panic("pci_display_console: unconfigured device at %d/%d/%d", bus, device, function); diff --git a/sys/arch/alpha/pci/pci_machdep.h b/sys/arch/alpha/pci/pci_machdep.h index 928a78f09a5..d706b1c2e92 100644 --- a/sys/arch/alpha/pci/pci_machdep.h +++ b/sys/arch/alpha/pci/pci_machdep.h @@ -1,4 +1,4 @@ -/* $OpenBSD: pci_machdep.h,v 1.5 1996/10/30 22:40:09 niklas Exp $ */ +/* $OpenBSD: pci_machdep.h,v 1.6 1996/12/08 00:20:43 niklas Exp $ */ /* $NetBSD: pci_machdep.h,v 1.4 1996/04/12 06:08:52 cgd Exp $ */ /* @@ -89,5 +89,5 @@ struct alpha_pci_chipset { #ifdef _KERNEL void pci_display_console - __P((bus_chipset_tag_t, pci_chipset_tag_t, int, int, int)); + __P((bus_space_tag_t, bus_space_tag_t, pci_chipset_tag_t, int, int, int)); #endif /* _KERNEL */ diff --git a/sys/arch/alpha/pci/pcivga.c b/sys/arch/alpha/pci/pcivga.c index 1670af9ebb2..142ec1203c7 100644 --- a/sys/arch/alpha/pci/pcivga.c +++ b/sys/arch/alpha/pci/pcivga.c @@ -1,5 +1,5 @@ -/* $OpenBSD: pcivga.c,v 1.8 1996/11/23 21:44:55 kstailey Exp $ */ -/* $NetBSD: pcivga.c,v 1.11 1996/10/13 03:00:13 christos Exp $ */ +/* $OpenBSD: pcivga.c,v 1.9 1996/12/08 00:20:44 niklas Exp $ */ +/* $NetBSD: pcivga.c,v 1.12 1996/10/23 04:12:29 cgd Exp $ */ /* * Copyright (c) 1995, 1996 Carnegie-Mellon University. @@ -59,8 +59,8 @@ struct cfdriver pcivga_cd = { NULL, "pcivga", DV_DULL, }; -void pcivga_getdevconfig __P((bus_chipset_tag_t, pci_chipset_tag_t, - pcitag_t, struct pcivga_devconfig *dc)); +void pcivga_getdevconfig __P((bus_space_tag_t, bus_space_tag_t, + pci_chipset_tag_t, pcitag_t, struct pcivga_devconfig *dc)); struct pcivga_devconfig pcivga_console_dc; @@ -105,24 +105,25 @@ pcivgamatch(parent, match, aux) } void -pcivga_getdevconfig(bc, pc, tag, dc) - bus_chipset_tag_t bc; +pcivga_getdevconfig(iot, memt, pc, tag, dc) + bus_space_tag_t iot, memt; pci_chipset_tag_t pc; pcitag_t tag; struct pcivga_devconfig *dc; { - bus_io_handle_t ioh; + bus_space_handle_t ioh; int cpos; - dc->dc_bc = bc; + dc->dc_iot = iot; + dc->dc_memt = memt; dc->dc_pc = pc; dc->dc_pcitag = tag; /* XXX deal with mapping foo */ - if (bus_mem_map(bc, 0xb8000, 0x8000, 0, &dc->dc_memh)) + if (bus_space_map(memt, 0xb8000, 0x8000, 0, &dc->dc_memh)) panic("pcivga_getdevconfig: couldn't map memory"); - if (bus_io_map(bc, 0x3b0, 0x30, &ioh)) + if (bus_space_map(iot, 0x3b0, 0x30, 0, &ioh)) panic("pcivga_getdevconfig: couldn't map io"); dc->dc_ioh = ioh; @@ -131,10 +132,10 @@ pcivga_getdevconfig(bc, pc, tag, dc) dc->dc_ccol = dc->dc_crow = 0; - bus_io_write_1(bc, ioh, PCIVGA_6845_ADDR, 14); - cpos = bus_io_read_1(bc, ioh, PCIVGA_6845_DATA) << 8; - bus_io_write_1(bc, ioh, PCIVGA_6845_ADDR, 15); - cpos |= bus_io_read_1(bc, ioh, PCIVGA_6845_DATA); + bus_space_write_1(iot, ioh, PCIVGA_6845_ADDR, 14); + cpos = bus_space_read_1(iot, ioh, PCIVGA_6845_DATA) << 8; + bus_space_write_1(iot, ioh, PCIVGA_6845_ADDR, 15); + cpos |= bus_space_read_1(iot, ioh, PCIVGA_6845_DATA); dc->dc_crow = cpos / dc->dc_ncol; dc->dc_ccol = cpos % dc->dc_ncol; @@ -174,8 +175,8 @@ pcivgaattach(parent, self, aux) else { sc->sc_dc = (struct pcivga_devconfig *) malloc(sizeof(struct pcivga_devconfig), M_DEVBUF, M_WAITOK); - pcivga_getdevconfig(pa->pa_bc, pa->pa_pc, pa->pa_tag, - sc->sc_dc); + pcivga_getdevconfig(pa->pa_iot, pa->pa_memt, pa->pa_pc, + pa->pa_tag, sc->sc_dc); } pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); @@ -270,15 +271,15 @@ pcivgammap(dev, offset, prot) } void -pcivga_console(bc, pc, bus, device, function) - bus_chipset_tag_t bc; +pcivga_console(iot, memt, pc, bus, device, function) + bus_space_tag_t iot, memt; pci_chipset_tag_t pc; int bus, device, function; { struct pcivga_devconfig *dcp = &pcivga_console_dc; struct wscons_odev_spec wo; - pcivga_getdevconfig(bc, pc, + pcivga_getdevconfig(iot, memt, pc, pci_make_tag(pc, bus, device, function), dcp); wo.wo_ef = &pcivga_emulfuncs; @@ -302,8 +303,8 @@ pcivga_cursor(id, on, row, col) int on, row, col; { struct pcivga_devconfig *dc = id; - bus_chipset_tag_t bc = dc->dc_bc; - bus_io_handle_t ioh = dc->dc_ioh; + bus_space_tag_t iot = dc->dc_iot; + bus_space_handle_t ioh = dc->dc_ioh; int pos; #if 0 @@ -320,10 +321,10 @@ pcivga_cursor(id, on, row, col) pos = row * dc->dc_ncol + col; - bus_io_write_1(bc, ioh, PCIVGA_6845_ADDR, 14); - bus_io_write_1(bc, ioh, PCIVGA_6845_DATA, pos >> 8); - bus_io_write_1(bc, ioh, PCIVGA_6845_ADDR, 15); - bus_io_write_1(bc, ioh, PCIVGA_6845_DATA, pos); + bus_space_write_1(iot, ioh, PCIVGA_6845_ADDR, 14); + bus_space_write_1(iot, ioh, PCIVGA_6845_DATA, pos >> 8); + bus_space_write_1(iot, ioh, PCIVGA_6845_ADDR, 15); + bus_space_write_1(iot, ioh, PCIVGA_6845_DATA, pos); } void @@ -334,14 +335,14 @@ pcivga_putstr(id, row, col, cp, len) int len; { struct pcivga_devconfig *dc = id; - bus_chipset_tag_t bc = dc->dc_bc; - bus_mem_handle_t memh = dc->dc_memh; + bus_space_tag_t memt = dc->dc_memt; + bus_space_handle_t memh = dc->dc_memh; int i, off; off = (row * dc->dc_ncol + col) * 2; for (i = 0; i < len; i++, cp++, off += 2) { - bus_mem_write_1(bc, memh, off, *cp); - bus_mem_write_1(bc, memh, off + 1, + bus_space_write_1(memt, memh, off, *cp); + bus_space_write_1(memt, memh, off + 1, dc->dc_so ? dc->dc_so_at : dc->dc_at); } } @@ -352,9 +353,9 @@ pcivga_copycols(id, row, srccol, dstcol, ncols) int row, srccol, dstcol, ncols; { struct pcivga_devconfig *dc = id; - bus_chipset_tag_t bc = dc->dc_bc; - bus_mem_handle_t memh = dc->dc_memh; - bus_mem_size_t srcoff, srcend, dstoff; + bus_space_tag_t memt = dc->dc_memt; + bus_space_handle_t memh = dc->dc_memh; + bus_size_t srcoff, srcend, dstoff; /* * YUCK. Need bus copy functions. @@ -364,8 +365,8 @@ pcivga_copycols(id, row, srccol, dstcol, ncols) dstoff = (row * dc->dc_ncol + dstcol) * 2; for (; srcoff < srcend; srcoff += 2, dstoff += 2) - bus_mem_write_2(bc, memh, dstoff, - bus_mem_read_2(bc, memh, srcoff)); + bus_space_write_2(memt, memh, dstoff, + bus_space_read_2(memt, memh, srcoff)); } void @@ -374,9 +375,9 @@ pcivga_erasecols(id, row, startcol, ncols) int row, startcol, ncols; { struct pcivga_devconfig *dc = id; - bus_chipset_tag_t bc = dc->dc_bc; - bus_mem_handle_t memh = dc->dc_memh; - bus_mem_size_t off, endoff; + bus_space_tag_t memt = dc->dc_memt; + bus_space_handle_t memh = dc->dc_memh; + bus_size_t off, endoff; u_int16_t val; /* @@ -387,7 +388,7 @@ pcivga_erasecols(id, row, startcol, ncols) val = (dc->dc_at << 8) | ' '; for (; off < endoff; off += 2) - bus_mem_write_2(bc, memh, off, val); + bus_space_write_2(memt, memh, off, val); } void @@ -396,9 +397,9 @@ pcivga_copyrows(id, srcrow, dstrow, nrows) int srcrow, dstrow, nrows; { struct pcivga_devconfig *dc = id; - bus_chipset_tag_t bc = dc->dc_bc; - bus_mem_handle_t memh = dc->dc_memh; - bus_mem_size_t srcoff, srcend, dstoff; + bus_space_tag_t memt = dc->dc_memt; + bus_space_handle_t memh = dc->dc_memh; + bus_size_t srcoff, srcend, dstoff; /* * YUCK. Need bus copy functions. @@ -408,8 +409,8 @@ pcivga_copyrows(id, srcrow, dstrow, nrows) dstoff = (dstrow * dc->dc_ncol + 0) * 2; for (; srcoff < srcend; srcoff += 2, dstoff += 2) - bus_mem_write_2(bc, memh, dstoff, - bus_mem_read_2(bc, memh, srcoff)); + bus_space_write_2(memt, memh, dstoff, + bus_space_read_2(memt, memh, srcoff)); } void @@ -418,9 +419,9 @@ pcivga_eraserows(id, startrow, nrows) int startrow, nrows; { struct pcivga_devconfig *dc = id; - bus_chipset_tag_t bc = dc->dc_bc; - bus_mem_handle_t memh = dc->dc_memh; - bus_mem_size_t off, endoff; + bus_space_tag_t memt = dc->dc_memt; + bus_space_handle_t memh = dc->dc_memh; + bus_size_t off, endoff; u_int16_t val; /* @@ -431,5 +432,5 @@ pcivga_eraserows(id, startrow, nrows) val = (dc->dc_at << 8) | ' '; for (; off < endoff; off += 2) - bus_mem_write_2(bc, memh, off, val); + bus_space_write_2(memt, memh, off, val); } diff --git a/sys/arch/alpha/pci/pcivgavar.h b/sys/arch/alpha/pci/pcivgavar.h index c8a947a98dd..4783a47cc14 100644 --- a/sys/arch/alpha/pci/pcivgavar.h +++ b/sys/arch/alpha/pci/pcivgavar.h @@ -1,5 +1,5 @@ -/* $OpenBSD: pcivgavar.h,v 1.5 1996/10/30 22:40:11 niklas Exp $ */ -/* $NetBSD: pcivgavar.h,v 1.5 1996/04/12 06:08:58 cgd Exp $ */ +/* $OpenBSD: pcivgavar.h,v 1.6 1996/12/08 00:20:44 niklas Exp $ */ +/* $NetBSD: pcivgavar.h,v 1.6 1996/10/23 04:12:30 cgd Exp $ */ /* * Copyright (c) 1995, 1996 Carnegie-Mellon University. @@ -29,13 +29,13 @@ */ struct pcivga_devconfig { - bus_chipset_tag_t dc_bc; + bus_space_tag_t dc_iot; + bus_space_tag_t dc_memt; pci_chipset_tag_t dc_pc; pcitag_t dc_pcitag; /* PCI tag */ - bus_io_handle_t dc_ioh; - bus_mem_handle_t dc_memh; + bus_space_handle_t dc_ioh, dc_memh; int dc_ncol, dc_nrow; /* screen width & height */ int dc_ccol, dc_crow; /* current cursor position */ @@ -58,5 +58,5 @@ struct pcivga_softc { (PCI_CLASS(class) == PCI_CLASS_PREHISTORIC && \ PCI_SUBCLASS(class) == PCI_SUBCLASS_PREHISTORIC_VGA)) ? 1 : 0) -void pcivga_console __P((bus_chipset_tag_t, pci_chipset_tag_t, int, int, - int)); +void pcivga_console __P((bus_space_tag_t, bus_space_tag_t, + pci_chipset_tag_t, int, int, int)); diff --git a/sys/arch/alpha/pci/pcs_bus_io_common.c b/sys/arch/alpha/pci/pcs_bus_io_common.c index 59626ded968..bec40a2f12e 100644 --- a/sys/arch/alpha/pci/pcs_bus_io_common.c +++ b/sys/arch/alpha/pci/pcs_bus_io_common.c @@ -1,5 +1,5 @@ -/* $OpenBSD: pcs_bus_io_common.c,v 1.3 1996/10/30 22:40:12 niklas Exp $ */ -/* $NetBSD: pcs_bus_io_common.c,v 1.8 1996/10/13 03:00:15 christos Exp $ */ +/* $OpenBSD: pcs_bus_io_common.c,v 1.4 1996/12/08 00:20:45 niklas Exp $ */ +/* $NetBSD: pcs_bus_io_common.c,v 1.9 1996/10/23 04:12:31 cgd Exp $ */ /* * Copyright (c) 1995, 1996 Carnegie-Mellon University. @@ -40,84 +40,164 @@ #define __C(A,B) __CONCAT(A,B) #define __S(S) __STRING(S) -int __C(CHIP,_io_map) __P((void *, bus_io_addr_t, bus_io_size_t, - bus_io_handle_t *)); -void __C(CHIP,_io_unmap) __P((void *, bus_io_handle_t, - bus_io_size_t)); -int __C(CHIP,_io_subregion) __P((void *, bus_io_handle_t, - bus_io_size_t, bus_io_size_t, bus_io_handle_t *)); -u_int8_t __C(CHIP,_io_read_1) __P((void *, bus_io_handle_t, - bus_io_size_t)); -u_int16_t __C(CHIP,_io_read_2) __P((void *, bus_io_handle_t, - bus_io_size_t)); -u_int32_t __C(CHIP,_io_read_4) __P((void *, bus_io_handle_t, - bus_io_size_t)); -u_int64_t __C(CHIP,_io_read_8) __P((void *, bus_io_handle_t, - bus_io_size_t)); -void __C(CHIP,_io_read_multi_1) __P((void *, bus_io_handle_t, - bus_io_size_t, u_int8_t *, bus_io_size_t)); -void __C(CHIP,_io_read_multi_2) __P((void *, bus_io_handle_t, - bus_io_size_t, u_int16_t *, bus_io_size_t)); -void __C(CHIP,_io_read_multi_4) __P((void *, bus_io_handle_t, - bus_io_size_t, u_int32_t *, bus_io_size_t)); -void __C(CHIP,_io_read_multi_8) __P((void *, bus_io_handle_t, - bus_io_size_t, u_int64_t *, bus_io_size_t)); -void __C(CHIP,_io_write_1) __P((void *, bus_io_handle_t, - bus_io_size_t, u_int8_t)); -void __C(CHIP,_io_write_2) __P((void *, bus_io_handle_t, - bus_io_size_t, u_int16_t)); -void __C(CHIP,_io_write_4) __P((void *, bus_io_handle_t, - bus_io_size_t, u_int32_t)); -void __C(CHIP,_io_write_8) __P((void *, bus_io_handle_t, - bus_io_size_t, u_int64_t)); -void __C(CHIP,_io_write_multi_1) __P((void *, bus_io_handle_t, - bus_io_size_t, const u_int8_t *, bus_io_size_t)); -void __C(CHIP,_io_write_multi_2) __P((void *, bus_io_handle_t, - bus_io_size_t, const u_int16_t *, bus_io_size_t)); -void __C(CHIP,_io_write_multi_4) __P((void *, bus_io_handle_t, - bus_io_size_t, const u_int32_t *, bus_io_size_t)); -void __C(CHIP,_io_write_multi_8) __P((void *, bus_io_handle_t, - bus_io_size_t, const u_int64_t *, bus_io_size_t)); - -void -__C(CHIP,_bus_io_init)(bc, iov) - bus_chipset_tag_t bc; +/* mapping/unmapping */ +int __C(CHIP,_io_map) __P((void *, bus_addr_t, bus_size_t, int, + bus_space_handle_t *)); +void __C(CHIP,_io_unmap) __P((void *, bus_space_handle_t, + bus_size_t)); +int __C(CHIP,_io_subregion) __P((void *, bus_space_handle_t, + bus_size_t, bus_size_t, bus_space_handle_t *)); + +/* allocation/deallocation */ +int __C(CHIP,_io_alloc) __P((void *, bus_addr_t, bus_addr_t, + bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, + bus_space_handle_t *)); +void __C(CHIP,_io_free) __P((void *, bus_space_handle_t, + bus_size_t)); + +/* read (single) */ +u_int8_t __C(CHIP,_io_read_1) __P((void *, bus_space_handle_t, + bus_size_t)); +u_int16_t __C(CHIP,_io_read_2) __P((void *, bus_space_handle_t, + bus_size_t)); +u_int32_t __C(CHIP,_io_read_4) __P((void *, bus_space_handle_t, + bus_size_t)); +u_int64_t __C(CHIP,_io_read_8) __P((void *, bus_space_handle_t, + bus_size_t)); + +/* read multiple */ +void __C(CHIP,_io_read_multi_1) __P((void *, bus_space_handle_t, + bus_size_t, u_int8_t *, bus_size_t)); +void __C(CHIP,_io_read_multi_2) __P((void *, bus_space_handle_t, + bus_size_t, u_int16_t *, bus_size_t)); +void __C(CHIP,_io_read_multi_4) __P((void *, bus_space_handle_t, + bus_size_t, u_int32_t *, bus_size_t)); +void __C(CHIP,_io_read_multi_8) __P((void *, bus_space_handle_t, + bus_size_t, u_int64_t *, bus_size_t)); + +/* read region */ +void __C(CHIP,_io_read_region_1) __P((void *, bus_space_handle_t, + bus_size_t, u_int8_t *, bus_size_t)); +void __C(CHIP,_io_read_region_2) __P((void *, bus_space_handle_t, + bus_size_t, u_int16_t *, bus_size_t)); +void __C(CHIP,_io_read_region_4) __P((void *, bus_space_handle_t, + bus_size_t, u_int32_t *, bus_size_t)); +void __C(CHIP,_io_read_region_8) __P((void *, bus_space_handle_t, + bus_size_t, u_int64_t *, bus_size_t)); + +/* write (single) */ +void __C(CHIP,_io_write_1) __P((void *, bus_space_handle_t, + bus_size_t, u_int8_t)); +void __C(CHIP,_io_write_2) __P((void *, bus_space_handle_t, + bus_size_t, u_int16_t)); +void __C(CHIP,_io_write_4) __P((void *, bus_space_handle_t, + bus_size_t, u_int32_t)); +void __C(CHIP,_io_write_8) __P((void *, bus_space_handle_t, + bus_size_t, u_int64_t)); + +/* write multiple */ +void __C(CHIP,_io_write_multi_1) __P((void *, bus_space_handle_t, + bus_size_t, const u_int8_t *, bus_size_t)); +void __C(CHIP,_io_write_multi_2) __P((void *, bus_space_handle_t, + bus_size_t, const u_int16_t *, bus_size_t)); +void __C(CHIP,_io_write_multi_4) __P((void *, bus_space_handle_t, + bus_size_t, const u_int32_t *, bus_size_t)); +void __C(CHIP,_io_write_multi_8) __P((void *, bus_space_handle_t, + bus_size_t, const u_int64_t *, bus_size_t)); + +/* write region */ +void __C(CHIP,_io_write_region_1) __P((void *, bus_space_handle_t, + bus_size_t, const u_int8_t *, bus_size_t)); +void __C(CHIP,_io_write_region_2) __P((void *, bus_space_handle_t, + bus_size_t, const u_int16_t *, bus_size_t)); +void __C(CHIP,_io_write_region_4) __P((void *, bus_space_handle_t, + bus_size_t, const u_int32_t *, bus_size_t)); +void __C(CHIP,_io_write_region_8) __P((void *, bus_space_handle_t, + bus_size_t, const u_int64_t *, bus_size_t)); + +/* barrier */ +void __C(CHIP,_io_barrier) __P((void *, bus_space_handle_t, + bus_size_t, bus_size_t, int)); + +static struct alpha_bus_space __C(CHIP,_io_space) = { + /* cookie */ + NULL, + + /* mapping/unmapping */ + __C(CHIP,_io_map), + __C(CHIP,_io_unmap), + __C(CHIP,_io_subregion), + + /* allocation/deallocation */ + __C(CHIP,_io_alloc), + __C(CHIP,_io_free), + + /* read (single) */ + __C(CHIP,_io_read_1), + __C(CHIP,_io_read_2), + __C(CHIP,_io_read_4), + __C(CHIP,_io_read_8), + + /* read multi */ + __C(CHIP,_io_read_multi_1), + __C(CHIP,_io_read_multi_2), + __C(CHIP,_io_read_multi_4), + __C(CHIP,_io_read_multi_8), + + /* read region */ + __C(CHIP,_io_read_region_1), + __C(CHIP,_io_read_region_2), + __C(CHIP,_io_read_region_4), + __C(CHIP,_io_read_region_8), + + /* write (single) */ + __C(CHIP,_io_write_1), + __C(CHIP,_io_write_2), + __C(CHIP,_io_write_4), + __C(CHIP,_io_write_8), + + /* write multi */ + __C(CHIP,_io_write_multi_1), + __C(CHIP,_io_write_multi_2), + __C(CHIP,_io_write_multi_4), + __C(CHIP,_io_write_multi_8), + + /* write region */ + __C(CHIP,_io_write_region_1), + __C(CHIP,_io_write_region_2), + __C(CHIP,_io_write_region_4), + __C(CHIP,_io_write_region_8), + + /* set multi */ + /* XXX IMPLEMENT */ + + /* set region */ + /* XXX IMPLEMENT */ + + /* copy */ + /* XXX IMPLEMENT */ + + /* barrier */ + __C(CHIP,_io_barrier), +}; + +bus_space_tag_t +__C(CHIP,_bus_io_init)(iov) void *iov; { + bus_space_tag_t h = &__C(CHIP,_io_space);; - bc->bc_i_v = iov; - - bc->bc_i_map = __C(CHIP,_io_map); - bc->bc_i_unmap = __C(CHIP,_io_unmap); - bc->bc_i_subregion = __C(CHIP,_io_subregion); - - bc->bc_ir1 = __C(CHIP,_io_read_1); - bc->bc_ir2 = __C(CHIP,_io_read_2); - bc->bc_ir4 = __C(CHIP,_io_read_4); - bc->bc_ir8 = __C(CHIP,_io_read_8); - - bc->bc_irm1 = __C(CHIP,_io_read_multi_1); - bc->bc_irm2 = __C(CHIP,_io_read_multi_2); - bc->bc_irm4 = __C(CHIP,_io_read_multi_4); - bc->bc_irm8 = __C(CHIP,_io_read_multi_8); - - bc->bc_iw1 = __C(CHIP,_io_write_1); - bc->bc_iw2 = __C(CHIP,_io_write_2); - bc->bc_iw4 = __C(CHIP,_io_write_4); - bc->bc_iw8 = __C(CHIP,_io_write_8); - - bc->bc_iwm1 = __C(CHIP,_io_write_multi_1); - bc->bc_iwm2 = __C(CHIP,_io_write_multi_2); - bc->bc_iwm4 = __C(CHIP,_io_write_multi_4); - bc->bc_iwm8 = __C(CHIP,_io_write_multi_8); + h->abs_cookie = iov; + return (h); } int -__C(CHIP,_io_map)(v, ioaddr, iosize, iohp) +__C(CHIP,_io_map)(v, ioaddr, iosize, cacheable, iohp) void *v; - bus_io_addr_t ioaddr; - bus_io_size_t iosize; - bus_io_handle_t *iohp; + bus_addr_t ioaddr; + bus_size_t iosize; + int cacheable; + bus_space_handle_t *iohp; { #ifdef CHIP_IO_W1_START @@ -146,41 +226,68 @@ __C(CHIP,_io_map)(v, ioaddr, iosize, iohp) __S(__C(CHIP,_io_map)), CHIP_IO_W2_START(v), CHIP_IO_W2_END(v)-1); #endif - panic("%s: don't know how to map %lx non-cacheable\n", + panic("%s: don't know how to map %lx non-cacheable", __S(__C(CHIP,_io_map)), ioaddr); } + /* XXX XXX XXX XXX XXX XXX */ return (0); } void __C(CHIP,_io_unmap)(v, ioh, iosize) void *v; - bus_io_handle_t ioh; - bus_io_size_t iosize; + bus_space_handle_t ioh; + bus_size_t iosize; { /* XXX nothing to do. */ + /* XXX XXX XXX XXX XXX XXX */ } int __C(CHIP,_io_subregion)(v, ioh, offset, size, nioh) void *v; - bus_io_handle_t ioh, *nioh; - bus_io_size_t offset, size; + bus_space_handle_t ioh, *nioh; + bus_size_t offset, size; { *nioh = ioh + offset; return (0); } +int +__C(CHIP,_io_alloc)(v, rstart, rend, size, align, boundary, cacheable, + addrp, bshp) + void *v; + bus_addr_t rstart, rend, *addrp; + bus_size_t size, align, boundary; + int cacheable; + bus_space_handle_t *bshp; +{ + + /* XXX XXX XXX XXX XXX XXX */ + panic("%s not implemented", __S(__C(CHIP,_io_alloc))); +} + +void +__C(CHIP,_io_free)(v, bsh, size) + void *v; + bus_space_handle_t bsh; + bus_size_t size; +{ + + /* XXX XXX XXX XXX XXX XXX */ + panic("%s not implemented", __S(__C(CHIP,_io_free))); +} + u_int8_t __C(CHIP,_io_read_1)(v, ioh, off) void *v; - bus_io_handle_t ioh; - bus_io_size_t off; + bus_space_handle_t ioh; + bus_size_t off; { - register bus_io_handle_t tmpioh; + register bus_space_handle_t tmpioh; register u_int32_t *port, val; register u_int8_t rval; register int offset; @@ -199,10 +306,10 @@ __C(CHIP,_io_read_1)(v, ioh, off) u_int16_t __C(CHIP,_io_read_2)(v, ioh, off) void *v; - bus_io_handle_t ioh; - bus_io_size_t off; + bus_space_handle_t ioh; + bus_size_t off; { - register bus_io_handle_t tmpioh; + register bus_space_handle_t tmpioh; register u_int32_t *port, val; register u_int16_t rval; register int offset; @@ -221,10 +328,10 @@ __C(CHIP,_io_read_2)(v, ioh, off) u_int32_t __C(CHIP,_io_read_4)(v, ioh, off) void *v; - bus_io_handle_t ioh; - bus_io_size_t off; + bus_space_handle_t ioh; + bus_size_t off; { - register bus_io_handle_t tmpioh; + register bus_space_handle_t tmpioh; register u_int32_t *port, val; register u_int32_t rval; register int offset; @@ -247,107 +354,61 @@ __C(CHIP,_io_read_4)(v, ioh, off) u_int64_t __C(CHIP,_io_read_8)(v, ioh, off) void *v; - bus_io_handle_t ioh; - bus_io_size_t off; + bus_space_handle_t ioh; + bus_size_t off; { /* XXX XXX XXX */ - panic("%s not implemented\n", __S(__C(CHIP,_io_read_8))); + panic("%s not implemented", __S(__C(CHIP,_io_read_8))); } -void -__C(CHIP,_io_read_multi_1)(v, ioh, off, addr, count) - void *v; - bus_io_handle_t ioh; - bus_io_size_t off, count; - u_int8_t *addr; -{ - register bus_io_handle_t tmpioh; - register u_int32_t *port, val; - register int offset; - - alpha_mb(); - - while (count--) { - tmpioh = ioh + off; - offset = tmpioh & 3; - port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); - val = *port; - *addr++ = ((val) >> (8 * offset)) & 0xff; - off++; - } +#define CHIP_io_read_multi_N(BYTES,TYPE) \ +void \ +__C(__C(CHIP,_io_read_multi_),BYTES)(v, h, o, a, c) \ + void *v; \ + bus_space_handle_t h; \ + bus_size_t o, c; \ + TYPE *a; \ +{ \ + \ + while (c-- > 0) { \ + __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ + BUS_BARRIER_READ); \ + *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ + } \ } - -void -__C(CHIP,_io_read_multi_2)(v, ioh, off, addr, count) - void *v; - bus_io_handle_t ioh; - bus_io_size_t off, count; - u_int16_t *addr; -{ - register bus_io_handle_t tmpioh; - register u_int32_t *port, val; - register int offset; - - alpha_mb(); - - while (count--) { - tmpioh = ioh + off; - offset = tmpioh & 3; - port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); - val = *port; - *addr++ = ((val) >> (8 * offset)) & 0xffff; - off++; - } -} - -void -__C(CHIP,_io_read_multi_4)(v, ioh, off, addr, count) - void *v; - bus_io_handle_t ioh; - bus_io_size_t off, count; - u_int32_t *addr; -{ - register bus_io_handle_t tmpioh; - register u_int32_t *port, val; - register int offset; - - alpha_mb(); - - while (count--) { - tmpioh = ioh + off; - offset = tmpioh & 3; - port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); - val = *port; -#if 0 - *addr++ = ((val) >> (8 * offset)) & 0xffffffff; -#else - *addr++ = val; -#endif - off++; - } -} - -void -__C(CHIP,_io_read_multi_8)(v, ioh, off, addr, count) - void *v; - bus_io_handle_t ioh; - bus_io_size_t off, count; - u_int64_t *addr; -{ - - /* XXX XXX XXX */ - panic("%s not implemented\n", __S(__C(CHIP,_io_read_multi_8))); +CHIP_io_read_multi_N(1,u_int8_t) +CHIP_io_read_multi_N(2,u_int16_t) +CHIP_io_read_multi_N(4,u_int32_t) +CHIP_io_read_multi_N(8,u_int64_t) + +#define CHIP_io_read_region_N(BYTES,TYPE) \ +void \ +__C(__C(CHIP,_io_read_region_),BYTES)(v, h, o, a, c) \ + void *v; \ + bus_space_handle_t h; \ + bus_size_t o, c; \ + TYPE *a; \ +{ \ + \ + while (c-- > 0) { \ + *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ + o += sizeof *a; \ + } \ } +CHIP_io_read_region_N(1,u_int8_t) +CHIP_io_read_region_N(2,u_int16_t) +CHIP_io_read_region_N(4,u_int32_t) +CHIP_io_read_region_N(8,u_int64_t) void __C(CHIP,_io_write_1)(v, ioh, off, val) void *v; - bus_io_handle_t ioh; - bus_io_size_t off; + bus_space_handle_t ioh; + bus_size_t off; u_int8_t val; { - register bus_io_handle_t tmpioh; + register bus_space_handle_t tmpioh; register u_int32_t *port, nval; register int offset; @@ -362,11 +423,11 @@ __C(CHIP,_io_write_1)(v, ioh, off, val) void __C(CHIP,_io_write_2)(v, ioh, off, val) void *v; - bus_io_handle_t ioh; - bus_io_size_t off; + bus_space_handle_t ioh; + bus_size_t off; u_int16_t val; { - register bus_io_handle_t tmpioh; + register bus_space_handle_t tmpioh; register u_int32_t *port, nval; register int offset; @@ -381,11 +442,11 @@ __C(CHIP,_io_write_2)(v, ioh, off, val) void __C(CHIP,_io_write_4)(v, ioh, off, val) void *v; - bus_io_handle_t ioh; - bus_io_size_t off; + bus_space_handle_t ioh; + bus_size_t off; u_int32_t val; { - register bus_io_handle_t tmpioh; + register bus_space_handle_t tmpioh; register u_int32_t *port, nval; register int offset; @@ -400,90 +461,65 @@ __C(CHIP,_io_write_4)(v, ioh, off, val) void __C(CHIP,_io_write_8)(v, ioh, off, val) void *v; - bus_io_handle_t ioh; - bus_io_size_t off; + bus_space_handle_t ioh; + bus_size_t off; u_int64_t val; { /* XXX XXX XXX */ - panic("%s not implemented\n", __S(__C(CHIP,_io_write_8))); + panic("%s not implemented", __S(__C(CHIP,_io_write_8))); alpha_mb(); } -void -__C(CHIP,_io_write_multi_1)(v, ioh, off, addr, count) - void *v; - bus_io_handle_t ioh; - bus_io_size_t off, count; - const u_int8_t *addr; -{ - register bus_io_handle_t tmpioh; - register u_int32_t *port, nval; - register int offset; - - while (count--) { - tmpioh = ioh + off; - offset = tmpioh & 3; - nval = (*addr++) << (8 * offset); - port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); - *port = nval; - off++; - } - alpha_mb(); +#define CHIP_io_write_multi_N(BYTES,TYPE) \ +void \ +__C(__C(CHIP,_io_write_multi_),BYTES)(v, h, o, a, c) \ + void *v; \ + bus_space_handle_t h; \ + bus_size_t o, c; \ + const TYPE *a; \ +{ \ + \ + while (c-- > 0) { \ + __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ + __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ + BUS_BARRIER_WRITE); \ + } \ } - -void -__C(CHIP,_io_write_multi_2)(v, ioh, off, addr, count) - void *v; - bus_io_handle_t ioh; - bus_io_size_t off, count; - const u_int16_t *addr; -{ - register bus_io_handle_t tmpioh; - register u_int32_t *port, nval; - register int offset; - - while (count--) { - tmpioh = ioh + off; - offset = tmpioh & 3; - nval = (*addr++) << (8 * offset); - port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); - *port = nval; - off++; - } - alpha_mb(); +CHIP_io_write_multi_N(1,u_int8_t) +CHIP_io_write_multi_N(2,u_int16_t) +CHIP_io_write_multi_N(4,u_int32_t) +CHIP_io_write_multi_N(8,u_int64_t) + +#define CHIP_io_write_region_N(BYTES,TYPE) \ +void \ +__C(__C(CHIP,_io_write_region_),BYTES)(v, h, o, a, c) \ + void *v; \ + bus_space_handle_t h; \ + bus_size_t o, c; \ + const TYPE *a; \ +{ \ + \ + while (c-- > 0) { \ + __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ + o += sizeof *a; \ + } \ } +CHIP_io_write_region_N(1,u_int8_t) +CHIP_io_write_region_N(2,u_int16_t) +CHIP_io_write_region_N(4,u_int32_t) +CHIP_io_write_region_N(8,u_int64_t) void -__C(CHIP,_io_write_multi_4)(v, ioh, off, addr, count) +__C(CHIP,_io_barrier)(v, h, o, l, f) void *v; - bus_io_handle_t ioh; - bus_io_size_t off, count; - const u_int32_t *addr; + bus_space_handle_t h; + bus_size_t o, l; + int f; { - register bus_io_handle_t tmpioh; - register u_int32_t *port, nval; - register int offset; - - while (count--) { - tmpioh = ioh + off; - offset = tmpioh & 3; - nval = (*addr++) /*<< (8 * offset)*/; - port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); - *port = nval; - off++; - } - alpha_mb(); -} -void -__C(CHIP,_io_write_multi_8)(v, ioh, off, addr, count) - void *v; - bus_io_handle_t ioh; - bus_io_size_t off, count; - const u_int64_t *addr; -{ - - /* XXX XXX XXX */ - panic("%s not implemented\n", __S(__C(CHIP,_io_write_multi_8))); + if ((f & BUS_BARRIER_READ) != 0) + alpha_mb(); + else if ((f & BUS_BARRIER_WRITE) != 0) + alpha_wmb(); } diff --git a/sys/arch/alpha/pci/pcs_bus_mem_common.c b/sys/arch/alpha/pci/pcs_bus_mem_common.c index 3eb14c01f0c..fa7e953e80c 100644 --- a/sys/arch/alpha/pci/pcs_bus_mem_common.c +++ b/sys/arch/alpha/pci/pcs_bus_mem_common.c @@ -1,5 +1,5 @@ -/* $OpenBSD: pcs_bus_mem_common.c,v 1.3 1996/10/30 22:40:13 niklas Exp $ */ -/* $NetBSD: pcs_bus_mem_common.c,v 1.9 1996/10/13 03:00:17 christos Exp $ */ +/* $OpenBSD: pcs_bus_mem_common.c,v 1.4 1996/12/08 00:20:46 niklas Exp $ */ +/* $NetBSD: pcs_bus_mem_common.c,v 1.10 1996/10/23 04:12:32 cgd Exp $ */ /* * Copyright (c) 1995, 1996 Carnegie-Mellon University. @@ -41,65 +41,164 @@ #define __C(A,B) __CONCAT(A,B) #define __S(S) __STRING(S) -int __C(CHIP,_mem_map) __P((void *, bus_mem_addr_t, bus_mem_size_t, - int, bus_mem_handle_t *)); -void __C(CHIP,_mem_unmap) __P((void *, bus_mem_handle_t, - bus_mem_size_t)); -int __C(CHIP,_mem_subregion) __P((void *, bus_mem_handle_t, - bus_mem_size_t, bus_mem_size_t, bus_mem_handle_t *)); -u_int8_t __C(CHIP,_mem_read_1) __P((void *, bus_mem_handle_t, - bus_mem_size_t)); -u_int16_t __C(CHIP,_mem_read_2) __P((void *, bus_mem_handle_t, - bus_mem_size_t)); -u_int32_t __C(CHIP,_mem_read_4) __P((void *, bus_mem_handle_t, - bus_mem_size_t)); -u_int64_t __C(CHIP,_mem_read_8) __P((void *, bus_mem_handle_t, - bus_mem_size_t)); -void __C(CHIP,_mem_write_1) __P((void *, bus_mem_handle_t, - bus_mem_size_t, u_int8_t)); -void __C(CHIP,_mem_write_2) __P((void *, bus_mem_handle_t, - bus_mem_size_t, u_int16_t)); -void __C(CHIP,_mem_write_4) __P((void *, bus_mem_handle_t, - bus_mem_size_t, u_int32_t)); -void __C(CHIP,_mem_write_8) __P((void *, bus_mem_handle_t, - bus_mem_size_t, u_int64_t)); - -/* XXX DOES NOT BELONG */ -vm_offset_t __C(CHIP,_XXX_dmamap) __P((void *)); - -void -__C(CHIP,_bus_mem_init)(bc, memv) - bus_chipset_tag_t bc; - void *memv; +/* mapping/unmapping */ +int __C(CHIP,_mem_map) __P((void *, bus_addr_t, bus_size_t, int, + bus_space_handle_t *)); +void __C(CHIP,_mem_unmap) __P((void *, bus_space_handle_t, + bus_size_t)); +int __C(CHIP,_mem_subregion) __P((void *, bus_space_handle_t, + bus_size_t, bus_size_t, bus_space_handle_t *)); + +/* allocation/deallocation */ +int __C(CHIP,_mem_alloc) __P((void *, bus_addr_t, bus_addr_t, + bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, + bus_space_handle_t *)); +void __C(CHIP,_mem_free) __P((void *, bus_space_handle_t, + bus_size_t)); + +/* read (single) */ +u_int8_t __C(CHIP,_mem_read_1) __P((void *, bus_space_handle_t, + bus_size_t)); +u_int16_t __C(CHIP,_mem_read_2) __P((void *, bus_space_handle_t, + bus_size_t)); +u_int32_t __C(CHIP,_mem_read_4) __P((void *, bus_space_handle_t, + bus_size_t)); +u_int64_t __C(CHIP,_mem_read_8) __P((void *, bus_space_handle_t, + bus_size_t)); + +/* read multiple */ +void __C(CHIP,_mem_read_multi_1) __P((void *, bus_space_handle_t, + bus_size_t, u_int8_t *, bus_size_t)); +void __C(CHIP,_mem_read_multi_2) __P((void *, bus_space_handle_t, + bus_size_t, u_int16_t *, bus_size_t)); +void __C(CHIP,_mem_read_multi_4) __P((void *, bus_space_handle_t, + bus_size_t, u_int32_t *, bus_size_t)); +void __C(CHIP,_mem_read_multi_8) __P((void *, bus_space_handle_t, + bus_size_t, u_int64_t *, bus_size_t)); + +/* read region */ +void __C(CHIP,_mem_read_region_1) __P((void *, bus_space_handle_t, + bus_size_t, u_int8_t *, bus_size_t)); +void __C(CHIP,_mem_read_region_2) __P((void *, bus_space_handle_t, + bus_size_t, u_int16_t *, bus_size_t)); +void __C(CHIP,_mem_read_region_4) __P((void *, bus_space_handle_t, + bus_size_t, u_int32_t *, bus_size_t)); +void __C(CHIP,_mem_read_region_8) __P((void *, bus_space_handle_t, + bus_size_t, u_int64_t *, bus_size_t)); + +/* write (single) */ +void __C(CHIP,_mem_write_1) __P((void *, bus_space_handle_t, + bus_size_t, u_int8_t)); +void __C(CHIP,_mem_write_2) __P((void *, bus_space_handle_t, + bus_size_t, u_int16_t)); +void __C(CHIP,_mem_write_4) __P((void *, bus_space_handle_t, + bus_size_t, u_int32_t)); +void __C(CHIP,_mem_write_8) __P((void *, bus_space_handle_t, + bus_size_t, u_int64_t)); + +/* write multiple */ +void __C(CHIP,_mem_write_multi_1) __P((void *, bus_space_handle_t, + bus_size_t, const u_int8_t *, bus_size_t)); +void __C(CHIP,_mem_write_multi_2) __P((void *, bus_space_handle_t, + bus_size_t, const u_int16_t *, bus_size_t)); +void __C(CHIP,_mem_write_multi_4) __P((void *, bus_space_handle_t, + bus_size_t, const u_int32_t *, bus_size_t)); +void __C(CHIP,_mem_write_multi_8) __P((void *, bus_space_handle_t, + bus_size_t, const u_int64_t *, bus_size_t)); + +/* write region */ +void __C(CHIP,_mem_write_region_1) __P((void *, bus_space_handle_t, + bus_size_t, const u_int8_t *, bus_size_t)); +void __C(CHIP,_mem_write_region_2) __P((void *, bus_space_handle_t, + bus_size_t, const u_int16_t *, bus_size_t)); +void __C(CHIP,_mem_write_region_4) __P((void *, bus_space_handle_t, + bus_size_t, const u_int32_t *, bus_size_t)); +void __C(CHIP,_mem_write_region_8) __P((void *, bus_space_handle_t, + bus_size_t, const u_int64_t *, bus_size_t)); + +/* barrier */ +void __C(CHIP,_mem_barrier) __P((void *, bus_space_handle_t, + bus_size_t, bus_size_t, int)); + +static struct alpha_bus_space __C(CHIP,_mem_space) = { + /* cookie */ + NULL, + + /* mapping/unmapping */ + __C(CHIP,_mem_map), + __C(CHIP,_mem_unmap), + __C(CHIP,_mem_subregion), + + /* allocation/deallocation */ + __C(CHIP,_mem_alloc), + __C(CHIP,_mem_free), + + /* read (single) */ + __C(CHIP,_mem_read_1), + __C(CHIP,_mem_read_2), + __C(CHIP,_mem_read_4), + __C(CHIP,_mem_read_8), + + /* read multi */ + __C(CHIP,_mem_read_multi_1), + __C(CHIP,_mem_read_multi_2), + __C(CHIP,_mem_read_multi_4), + __C(CHIP,_mem_read_multi_8), + + /* read region */ + __C(CHIP,_mem_read_region_1), + __C(CHIP,_mem_read_region_2), + __C(CHIP,_mem_read_region_4), + __C(CHIP,_mem_read_region_8), + + /* write (single) */ + __C(CHIP,_mem_write_1), + __C(CHIP,_mem_write_2), + __C(CHIP,_mem_write_4), + __C(CHIP,_mem_write_8), + + /* write multi */ + __C(CHIP,_mem_write_multi_1), + __C(CHIP,_mem_write_multi_2), + __C(CHIP,_mem_write_multi_4), + __C(CHIP,_mem_write_multi_8), + + /* write region */ + __C(CHIP,_mem_write_region_1), + __C(CHIP,_mem_write_region_2), + __C(CHIP,_mem_write_region_4), + __C(CHIP,_mem_write_region_8), + + /* set multi */ + /* XXX IMPLEMENT */ + + /* set region */ + /* XXX IMPLEMENT */ + + /* copy */ + /* XXX IMPLEMENT */ + + /* barrier */ + __C(CHIP,_mem_barrier), +}; + +bus_space_tag_t +__C(CHIP,_bus_mem_init)(iov) + void *iov; { + bus_space_tag_t h = &__C(CHIP,_mem_space);; - bc->bc_m_v = memv; - - bc->bc_m_map = __C(CHIP,_mem_map); - bc->bc_m_unmap = __C(CHIP,_mem_unmap); - bc->bc_m_subregion = __C(CHIP,_mem_subregion); - - bc->bc_mr1 = __C(CHIP,_mem_read_1); - bc->bc_mr2 = __C(CHIP,_mem_read_2); - bc->bc_mr4 = __C(CHIP,_mem_read_4); - bc->bc_mr8 = __C(CHIP,_mem_read_8); - - bc->bc_mw1 = __C(CHIP,_mem_write_1); - bc->bc_mw2 = __C(CHIP,_mem_write_2); - bc->bc_mw4 = __C(CHIP,_mem_write_4); - bc->bc_mw8 = __C(CHIP,_mem_write_8); - - /* XXX DOES NOT BELONG */ - bc->bc_XXX_dmamap = __C(CHIP,_XXX_dmamap); + h->abs_cookie = iov; + return (h); } int __C(CHIP,_mem_map)(v, memaddr, memsize, cacheable, memhp) void *v; - bus_mem_addr_t memaddr; - bus_mem_size_t memsize; + bus_addr_t memaddr; + bus_size_t memsize; int cacheable; - bus_mem_handle_t *memhp; + bus_space_handle_t *memhp; { if (cacheable) { @@ -117,7 +216,7 @@ __C(CHIP,_mem_map)(v, memaddr, memsize, cacheable, memhp) __S(__C(CHIP,_mem_map)), CHIP_D_MEM_W1_START(v), CHIP_D_MEM_W1_END(v)-1); #endif - panic("%s: don't know how to map %lx cacheable\n", + panic("%s: don't know how to map %lx cacheable", __S(__C(CHIP,_mem_map)), memaddr); } } else { @@ -159,42 +258,69 @@ __C(CHIP,_mem_map)(v, memaddr, memsize, cacheable, memhp) __S(__C(CHIP,_mem_map)), CHIP_S_MEM_W3_START(v), CHIP_S_MEM_W3_END(v)-1); #endif - panic("%s: don't know how to map %lx non-cacheable\n", + panic("%s: don't know how to map %lx non-cacheable", __S(__C(CHIP,_mem_map)), memaddr); } } + /* XXX XXX XXX XXX XXX XXX */ return (0); } void __C(CHIP,_mem_unmap)(v, memh, memsize) void *v; - bus_mem_handle_t memh; - bus_mem_size_t memsize; + bus_space_handle_t memh; + bus_size_t memsize; { /* XXX nothing to do. */ + /* XXX XXX XXX XXX XXX XXX */ } int __C(CHIP,_mem_subregion)(v, memh, offset, size, nmemh) void *v; - bus_mem_handle_t memh, *nmemh; - bus_mem_size_t offset, size; + bus_space_handle_t memh, *nmemh; + bus_size_t offset, size; { *nmemh = memh + offset; return (0); } +int +__C(CHIP,_mem_alloc)(v, rstart, rend, size, align, boundary, cacheable, + addrp, bshp) + void *v; + bus_addr_t rstart, rend, *addrp; + bus_size_t size, align, boundary; + int cacheable; + bus_space_handle_t *bshp; +{ + + /* XXX XXX XXX XXX XXX XXX */ + panic("%s not implemented", __S(__C(CHIP,_mem_alloc))); +} + +void +__C(CHIP,_mem_free)(v, bsh, size) + void *v; + bus_space_handle_t bsh; + bus_size_t size; +{ + + /* XXX XXX XXX XXX XXX XXX */ + panic("%s not implemented", __S(__C(CHIP,_mem_free))); +} + u_int8_t __C(CHIP,_mem_read_1)(v, memh, off) void *v; - bus_mem_handle_t memh; - bus_mem_size_t off; + bus_space_handle_t memh; + bus_size_t off; { - register bus_mem_handle_t tmpmemh; + register bus_space_handle_t tmpmemh; register u_int32_t *port, val; register u_int8_t rval; register int offset; @@ -216,10 +342,10 @@ __C(CHIP,_mem_read_1)(v, memh, off) u_int16_t __C(CHIP,_mem_read_2)(v, memh, off) void *v; - bus_mem_handle_t memh; - bus_mem_size_t off; + bus_space_handle_t memh; + bus_size_t off; { - register bus_mem_handle_t tmpmemh; + register bus_space_handle_t tmpmemh; register u_int32_t *port, val; register u_int16_t rval; register int offset; @@ -241,10 +367,10 @@ __C(CHIP,_mem_read_2)(v, memh, off) u_int32_t __C(CHIP,_mem_read_4)(v, memh, off) void *v; - bus_mem_handle_t memh; - bus_mem_size_t off; + bus_space_handle_t memh; + bus_size_t off; { - register bus_mem_handle_t tmpmemh; + register bus_space_handle_t tmpmemh; register u_int32_t *port, val; register u_int32_t rval; register int offset; @@ -270,8 +396,8 @@ __C(CHIP,_mem_read_4)(v, memh, off) u_int64_t __C(CHIP,_mem_read_8)(v, memh, off) void *v; - bus_mem_handle_t memh; - bus_mem_size_t off; + bus_space_handle_t memh; + bus_size_t off; { alpha_mb(); @@ -280,17 +406,56 @@ __C(CHIP,_mem_read_8)(v, memh, off) return (*(u_int64_t *)(memh + off)); /* XXX XXX XXX */ - panic("%s not implemented\n", __S(__C(CHIP,_mem_read_8))); + panic("%s not implemented", __S(__C(CHIP,_mem_read_8))); } +#define CHIP_mem_read_multi_N(BYTES,TYPE) \ +void \ +__C(__C(CHIP,_mem_read_multi_),BYTES)(v, h, o, a, c) \ + void *v; \ + bus_space_handle_t h; \ + bus_size_t o, c; \ + TYPE *a; \ +{ \ + \ + while (c-- > 0) { \ + __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \ + BUS_BARRIER_READ); \ + *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \ + } \ +} +CHIP_mem_read_multi_N(1,u_int8_t) +CHIP_mem_read_multi_N(2,u_int16_t) +CHIP_mem_read_multi_N(4,u_int32_t) +CHIP_mem_read_multi_N(8,u_int64_t) + +#define CHIP_mem_read_region_N(BYTES,TYPE) \ +void \ +__C(__C(CHIP,_mem_read_region_),BYTES)(v, h, o, a, c) \ + void *v; \ + bus_space_handle_t h; \ + bus_size_t o, c; \ + TYPE *a; \ +{ \ + \ + while (c-- > 0) { \ + *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \ + o += sizeof *a; \ + } \ +} +CHIP_mem_read_region_N(1,u_int8_t) +CHIP_mem_read_region_N(2,u_int16_t) +CHIP_mem_read_region_N(4,u_int32_t) +CHIP_mem_read_region_N(8,u_int64_t) + void __C(CHIP,_mem_write_1)(v, memh, off, val) void *v; - bus_mem_handle_t memh; - bus_mem_size_t off; + bus_space_handle_t memh; + bus_size_t off; u_int8_t val; { - register bus_mem_handle_t tmpmemh; + register bus_space_handle_t tmpmemh; register u_int32_t *port, nval; register int offset; @@ -309,11 +474,11 @@ __C(CHIP,_mem_write_1)(v, memh, off, val) void __C(CHIP,_mem_write_2)(v, memh, off, val) void *v; - bus_mem_handle_t memh; - bus_mem_size_t off; + bus_space_handle_t memh; + bus_size_t off; u_int16_t val; { - register bus_mem_handle_t tmpmemh; + register bus_space_handle_t tmpmemh; register u_int32_t *port, nval; register int offset; @@ -332,11 +497,11 @@ __C(CHIP,_mem_write_2)(v, memh, off, val) void __C(CHIP,_mem_write_4)(v, memh, off, val) void *v; - bus_mem_handle_t memh; - bus_mem_size_t off; + bus_space_handle_t memh; + bus_size_t off; u_int32_t val; { - register bus_mem_handle_t tmpmemh; + register bus_space_handle_t tmpmemh; register u_int32_t *port, nval; register int offset; @@ -355,8 +520,8 @@ __C(CHIP,_mem_write_4)(v, memh, off, val) void __C(CHIP,_mem_write_8)(v, memh, off, val) void *v; - bus_mem_handle_t memh; - bus_mem_size_t off; + bus_space_handle_t memh; + bus_size_t off; u_int64_t val; { @@ -364,16 +529,61 @@ __C(CHIP,_mem_write_8)(v, memh, off, val) (*(u_int64_t *)(memh + off)) = val; else { /* XXX XXX XXX */ - panic("%s not implemented\n", + panic("%s not implemented", __S(__C(CHIP,_mem_write_8))); } alpha_mb(); } -vm_offset_t -__C(CHIP,_XXX_dmamap)(addr) - void *addr; +#define CHIP_mem_write_multi_N(BYTES,TYPE) \ +void \ +__C(__C(CHIP,_mem_write_multi_),BYTES)(v, h, o, a, c) \ + void *v; \ + bus_space_handle_t h; \ + bus_size_t o, c; \ + const TYPE *a; \ +{ \ + \ + while (c-- > 0) { \ + __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \ + __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \ + BUS_BARRIER_WRITE); \ + } \ +} +CHIP_mem_write_multi_N(1,u_int8_t) +CHIP_mem_write_multi_N(2,u_int16_t) +CHIP_mem_write_multi_N(4,u_int32_t) +CHIP_mem_write_multi_N(8,u_int64_t) + +#define CHIP_mem_write_region_N(BYTES,TYPE) \ +void \ +__C(__C(CHIP,_mem_write_region_),BYTES)(v, h, o, a, c) \ + void *v; \ + bus_space_handle_t h; \ + bus_size_t o, c; \ + const TYPE *a; \ +{ \ + \ + while (c-- > 0) { \ + __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \ + o += sizeof *a; \ + } \ +} +CHIP_mem_write_region_N(1,u_int8_t) +CHIP_mem_write_region_N(2,u_int16_t) +CHIP_mem_write_region_N(4,u_int32_t) +CHIP_mem_write_region_N(8,u_int64_t) + +void +__C(CHIP,_mem_barrier)(v, h, o, l, f) + void *v; + bus_space_handle_t h; + bus_size_t o, l; + int f; { - return (vtophys((vm_offset_t)addr) | 0x40000000); + if ((f & BUS_BARRIER_READ) != 0) + alpha_mb(); + else if ((f & BUS_BARRIER_WRITE) != 0) + alpha_wmb(); } diff --git a/sys/arch/alpha/pci/sio.c b/sys/arch/alpha/pci/sio.c index 021573560de..9b4e45c7aa0 100644 --- a/sys/arch/alpha/pci/sio.c +++ b/sys/arch/alpha/pci/sio.c @@ -1,5 +1,5 @@ -/* $OpenBSD: sio.c,v 1.7 1996/11/23 21:44:56 kstailey Exp $ */ -/* $NetBSD: sio.c,v 1.11 1996/10/13 03:00:18 christos Exp $ */ +/* $OpenBSD: sio.c,v 1.8 1996/12/08 00:20:48 niklas Exp $ */ +/* $NetBSD: sio.c,v 1.12 1996/10/23 04:12:33 cgd Exp $ */ /* * Copyright (c) 1995, 1996 Carnegie-Mellon University. @@ -34,7 +34,7 @@ #include <sys/device.h> #include <machine/intr.h> -#include <machine/bus.old.h> +#include <machine/bus.h> #include <dev/isa/isavar.h> #include <dev/eisa/eisavar.h> @@ -151,7 +151,8 @@ sioattach(parent, self, aux) ec.ec_intr_disestablish = sio_intr_disestablish; sa.sa_eba.eba_busname = "eisa"; - sa.sa_eba.eba_bc = pa->pa_bc; + sa.sa_eba.eba_iot = pa->pa_iot; + sa.sa_eba.eba_memt = pa->pa_memt; sa.sa_eba.eba_ec = &ec; config_found(self, &sa.sa_eba, sioprint); } @@ -162,7 +163,8 @@ sioattach(parent, self, aux) ic.ic_intr_disestablish = sio_intr_disestablish; sa.sa_iba.iba_busname = "isa"; - sa.sa_iba.iba_bc = pa->pa_bc; + sa.sa_iba.iba_iot = pa->pa_iot; + sa.sa_iba.iba_memt = pa->pa_memt; sa.sa_iba.iba_ic = ⁣ config_found(self, &sa.sa_iba, sioprint); } diff --git a/sys/arch/alpha/pci/sio_pic.c b/sys/arch/alpha/pci/sio_pic.c index 2eb744515ab..037707f5e85 100644 --- a/sys/arch/alpha/pci/sio_pic.c +++ b/sys/arch/alpha/pci/sio_pic.c @@ -1,5 +1,5 @@ -/* $OpenBSD: sio_pic.c,v 1.7 1996/11/12 20:29:39 niklas Exp $ */ -/* $NetBSD: sio_pic.c,v 1.13 1996/10/13 03:00:20 christos Exp $ */ +/* $OpenBSD: sio_pic.c,v 1.8 1996/12/08 00:20:49 niklas Exp $ */ +/* $NetBSD: sio_pic.c,v 1.14 1996/10/23 04:12:33 cgd Exp $ */ /* * Copyright (c) 1995, 1996 Carnegie-Mellon University. @@ -35,7 +35,7 @@ #include <sys/syslog.h> #include <machine/intr.h> -#include <machine/bus.old.h> +#include <machine/bus.h> #include <dev/isa/isareg.h> #include <dev/isa/isavar.h> @@ -62,8 +62,8 @@ */ static void sio_strayintr __P((int)); -bus_chipset_tag_t sio_bc; -bus_io_handle_t sio_ioh_icu1, sio_ioh_icu2, sio_ioh_elcr; +bus_space_tag_t sio_iot; +bus_space_handle_t sio_ioh_icu1, sio_ioh_icu2, sio_ioh_elcr; /* * Interrupt handler chains. sio_intr_establish() inserts a handler into @@ -135,10 +135,10 @@ sio_setirqstat(irq, enabled, type) icu = irq / 8; bit = irq % 8; - ocw1[0] = bus_io_read_1(sio_bc, sio_ioh_icu1, 1); - ocw1[1] = bus_io_read_1(sio_bc, sio_ioh_icu2, 1); - elcr[0] = bus_io_read_1(sio_bc, sio_ioh_elcr, 0); /* XXX */ - elcr[1] = bus_io_read_1(sio_bc, sio_ioh_elcr, 1); /* XXX */ + ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1); + ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1); + elcr[0] = bus_space_read_1(sio_iot, sio_ioh_elcr, 0); /* XXX */ + elcr[1] = bus_space_read_1(sio_iot, sio_ioh_elcr, 1); /* XXX */ /* * interrupt enable: set bit to mask (disable) interrupt. @@ -182,33 +182,33 @@ sio_setirqstat(irq, enabled, type) } #endif - bus_io_write_1(sio_bc, sio_ioh_icu1, 1, ocw1[0]); - bus_io_write_1(sio_bc, sio_ioh_icu2, 1, ocw1[1]); - bus_io_write_1(sio_bc, sio_ioh_elcr, 0, elcr[0]); /* XXX */ - bus_io_write_1(sio_bc, sio_ioh_elcr, 1, elcr[1]); /* XXX */ + bus_space_write_1(sio_iot, sio_ioh_icu1, 1, ocw1[0]); + bus_space_write_1(sio_iot, sio_ioh_icu2, 1, ocw1[1]); + bus_space_write_1(sio_iot, sio_ioh_elcr, 0, elcr[0]); /* XXX */ + bus_space_write_1(sio_iot, sio_ioh_elcr, 1, elcr[1]); /* XXX */ } void -sio_intr_setup(bc) - bus_chipset_tag_t bc; +sio_intr_setup(iot) + bus_space_tag_t iot; { int i; - sio_bc = bc; + sio_iot = iot; - if (bus_io_map(sio_bc, IO_ICU1, IO_ICUSIZE, &sio_ioh_icu1) || - bus_io_map(sio_bc, IO_ICU2, IO_ICUSIZE, &sio_ioh_icu2) || - bus_io_map(sio_bc, 0x4d0, 2, &sio_ioh_elcr)) + if (bus_space_map(sio_iot, IO_ICU1, IO_ICUSIZE, 0, &sio_ioh_icu1) || + bus_space_map(sio_iot, IO_ICU2, IO_ICUSIZE, 0, &sio_ioh_icu2) || + bus_space_map(sio_iot, 0x4d0, 2, 0, &sio_ioh_elcr)) panic("sio_intr_setup: can't map I/O ports"); #ifdef BROKEN_PROM_CONSOLE /* * Remember the initial values, because the prom is stupid. */ - initial_ocw1[0] = bus_io_read_1(sio_bc, sio_ioh_icu1, 1); - initial_ocw1[1] = bus_io_read_1(sio_bc, sio_ioh_icu2, 1); - initial_elcr[0] = bus_io_read_1(sio_bc, sio_ioh_elcr, 0); /* XXX */ - initial_elcr[1] = bus_io_read_1(sio_bc, sio_ioh_elcr, 1); /* XXX */ + initial_ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1); + initial_ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1); + initial_elcr[0] = bus_space_read_1(sio_iot, sio_ioh_elcr, 0); /* XXX */ + initial_elcr[1] = bus_space_read_1(sio_iot, sio_ioh_elcr, 1); /* XXX */ #if 0 printf("initial_ocw1[0] = 0x%x\n", initial_ocw1[0]); printf("initial_ocw1[1] = 0x%x\n", initial_ocw1[1]); @@ -432,8 +432,8 @@ sio_iointr(framep, vec) * by the interrupt handler. */ if (irq > 7) - bus_io_write_1(sio_bc, + bus_space_write_1(sio_iot, sio_ioh_icu2, 0, 0x20 | (irq & 0x07)); /* XXX */ - bus_io_write_1(sio_bc, + bus_space_write_1(sio_iot, sio_ioh_icu1, 0, 0x20 | (irq > 7 ? 2 : irq)); /* XXX */ } diff --git a/sys/arch/alpha/pci/siovar.h b/sys/arch/alpha/pci/siovar.h index 288341d293a..48bab3d8dfb 100644 --- a/sys/arch/alpha/pci/siovar.h +++ b/sys/arch/alpha/pci/siovar.h @@ -1,5 +1,5 @@ -/* $OpenBSD: siovar.h,v 1.4 1996/10/30 22:40:17 niklas Exp $ */ -/* $NetBSD: siovar.h,v 1.4 1996/07/14 04:08:42 cgd Exp $ */ +/* $OpenBSD: siovar.h,v 1.5 1996/12/08 00:20:50 niklas Exp $ */ +/* $NetBSD: siovar.h,v 1.5 1996/10/23 04:12:34 cgd Exp $ */ /* * Copyright (c) 1995, 1996 Carnegie-Mellon University. @@ -28,7 +28,7 @@ * rights to redistribute these changes. */ -void sio_intr_setup __P((bus_chipset_tag_t)); +void sio_intr_setup __P((bus_space_tag_t)); void sio_iointr __P((void *framep, unsigned long vec)); const char *sio_intr_string __P((void *, int)); diff --git a/sys/arch/alpha/pci/tga.c b/sys/arch/alpha/pci/tga.c index 384dd7c31e8..e8c52fc1b4f 100644 --- a/sys/arch/alpha/pci/tga.c +++ b/sys/arch/alpha/pci/tga.c @@ -1,5 +1,5 @@ -/* $OpenBSD: tga.c,v 1.7 1996/11/23 21:44:56 kstailey Exp $ */ -/* $NetBSD: tga.c,v 1.10 1996/10/13 03:00:22 christos Exp $ */ +/* $OpenBSD: tga.c,v 1.8 1996/12/08 00:20:51 niklas Exp $ */ +/* $NetBSD: tga.c,v 1.11 1996/10/23 04:12:35 cgd Exp $ */ /* * Copyright (c) 1995, 1996 Carnegie-Mellon University. @@ -37,7 +37,7 @@ #include <sys/conf.h> #include <sys/ioctl.h> -#include <machine/bus.old.h> +#include <machine/bus.h> #include <machine/intr.h> #include <dev/pci/pcireg.h> @@ -69,7 +69,7 @@ struct cfdriver tga_cd = { int tga_identify __P((tga_reg_t *)); const struct tga_conf *tga_getconf __P((int)); -void tga_getdevconfig __P((bus_chipset_tag_t bc, pci_chipset_tag_t pc, +void tga_getdevconfig __P((bus_space_tag_t memt, pci_chipset_tag_t pc, pcitag_t tag, struct tga_devconfig *dc)); struct tga_devconfig tga_console_dc; @@ -104,8 +104,8 @@ tgamatch(parent, match, aux) } void -tga_getdevconfig(bc, pc, tag, dc) - bus_chipset_tag_t bc; +tga_getdevconfig(memt, pc, tag, dc) + bus_space_tag_t memt; pci_chipset_tag_t pc; pcitag_t tag; struct tga_devconfig *dc; @@ -114,10 +114,10 @@ tga_getdevconfig(bc, pc, tag, dc) const struct tga_ramdac_conf *tgar; struct raster *rap; struct rcons *rcp; - bus_mem_size_t pcisize; + bus_size_t pcisize; int i, cacheable; - dc->dc_bc = bc; + dc->dc_memt = memt; dc->dc_pc = pc; dc->dc_pcitag = tag; @@ -129,7 +129,7 @@ tga_getdevconfig(bc, pc, tag, dc) panic("tga_getdevconfig: memory not cacheable?"); /* XXX XXX XXX */ - if (bus_mem_map(bc, dc->dc_pcipaddr, pcisize, 1, &dc->dc_vaddr)) + if (bus_space_map(memt, dc->dc_pcipaddr, pcisize, 1, &dc->dc_vaddr)) return; dc->dc_paddr = ALPHA_K0SEG_TO_PHYS(dc->dc_vaddr); /* XXX */ @@ -233,7 +233,7 @@ tgaattach(parent, self, aux) else { sc->sc_dc = (struct tga_devconfig *) malloc(sizeof(struct tga_devconfig), M_DEVBUF, M_WAITOK); - tga_getdevconfig(pa->pa_bc, pa->pa_pc, pa->pa_tag, sc->sc_dc); + tga_getdevconfig(pa->pa_memt, pa->pa_pc, pa->pa_tag, sc->sc_dc); } if (sc->sc_dc->dc_vaddr == NULL) { printf(": couldn't map memory space; punt!\n"); @@ -396,15 +396,15 @@ tgammap(dev, offset, prot) } void -tga_console(bc, pc, bus, device, function) - bus_chipset_tag_t bc; +tga_console(iot, memt, pc, bus, device, function) + bus_space_tag_t iot, memt; pci_chipset_tag_t pc; int bus, device, function; { struct tga_devconfig *dcp = &tga_console_dc; struct wscons_odev_spec wo; - tga_getdevconfig(bc, pc, pci_make_tag(pc, bus, device, function), dcp); + tga_getdevconfig(memt, pc, pci_make_tag(pc, bus, device, function), dcp); /* sanity checks */ if (dcp->dc_vaddr == NULL) diff --git a/sys/arch/alpha/pci/tgavar.h b/sys/arch/alpha/pci/tgavar.h index 9b833436a97..460f39a1799 100644 --- a/sys/arch/alpha/pci/tgavar.h +++ b/sys/arch/alpha/pci/tgavar.h @@ -1,5 +1,5 @@ -/* $OpenBSD: tgavar.h,v 1.5 1996/10/30 22:40:22 niklas Exp $ */ -/* $NetBSD: tgavar.h,v 1.5 1996/04/12 06:09:21 cgd Exp $ */ +/* $OpenBSD: tgavar.h,v 1.6 1996/12/08 00:20:52 niklas Exp $ */ +/* $NetBSD: tgavar.h,v 1.6 1996/10/23 04:12:36 cgd Exp $ */ /* * Copyright (c) 1995, 1996 Carnegie-Mellon University. @@ -77,11 +77,11 @@ struct tga_conf { }; struct tga_devconfig { - bus_chipset_tag_t dc_bc; + bus_space_tag_t dc_memt; pci_chipset_tag_t dc_pc; pcitag_t dc_pcitag; /* PCI tag */ - bus_mem_addr_t dc_pcipaddr; /* PCI phys addr. */ + bus_addr_t dc_pcipaddr; /* PCI phys addr. */ tga_reg_t *dc_regs; /* registers; XXX: need aliases */ @@ -125,7 +125,8 @@ struct tga_softc { ((PCI_VENDOR(id) == PCI_VENDOR_DEC && \ PCI_PRODUCT(id) == PCI_PRODUCT_DEC_21030) ? 10 : 0) -void tga_console __P((bus_chipset_tag_t, pci_chipset_tag_t, int, int, int)); +void tga_console __P((bus_space_tag_t, bus_space_tag_t, pci_chipset_tag_t, + int, int, int)); int tga_identify __P((tga_reg_t *)); const struct tga_conf *tga_getconf __P((int)); |