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-rw-r--r--sys/arch/arm/include/armreg.h82
-rw-r--r--sys/arch/arm/include/cpuconf.h24
-rw-r--r--sys/arch/arm/include/cpufunc.h65
-rw-r--r--sys/arch/arm/include/pmap.h11
4 files changed, 137 insertions, 45 deletions
diff --git a/sys/arch/arm/include/armreg.h b/sys/arch/arm/include/armreg.h
index e82954ef952..b1ce7f9d296 100644
--- a/sys/arch/arm/include/armreg.h
+++ b/sys/arch/arm/include/armreg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: armreg.h,v 1.4 2008/09/11 02:38:14 kevlo Exp $ */
+/* $OpenBSD: armreg.h,v 1.5 2009/05/08 02:57:32 drahn Exp $ */
/* $NetBSD: armreg.h,v 1.27 2003/09/06 08:43:02 rearnsha Exp $ */
/*
@@ -52,7 +52,7 @@
* +-+-+-+-+-+-------------------------------------+-+-+-+---------+
*/
-#define PSR_FLAGS 0xf0000000 /* flags */
+#define PSR_FLAGS 0xf0000000 /* flags */
#define PSR_N_bit (1 << 31) /* negative */
#define PSR_Z_bit (1 << 30) /* zero */
#define PSR_C_bit (1 << 29) /* carry */
@@ -118,7 +118,7 @@
#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */
#define CPU_ID_DEC 0x44000000 /* 'D' */
#define CPU_ID_INTEL 0x69000000 /* 'i' */
-#define CPU_ID_TI 0x54000000 /* 'T' */
+#define CPU_ID_TI 0x54000000 /* 'T' */
/* How to decide what format the CPUID is in. */
#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000)
@@ -143,6 +143,8 @@
#define CPU_ID_ARCH_V5 0x00030000
#define CPU_ID_ARCH_V5T 0x00040000
#define CPU_ID_ARCH_V5TE 0x00050000
+#define CPU_ID_ARCH_V6 0x00070000
+#define CPU_ID_ARCH_V7 0x00080000
#define CPU_ID_VARIANT_MASK 0x00f00000
/* Next three nybbles are part number */
@@ -187,13 +189,16 @@
#define CPU_ID_ARM926EJS 0x41069260
#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */
#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */
-#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */
-#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */
+#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */
+#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */
#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */
#define CPU_ID_ARM1022ES 0x4105a220
+#define CPU_ID_ARM1022EJS 0x4106a260
+#define CPU_ID_ARM1136JS 0x4107b360
+#define CPU_ID_ARM1136JSR1 0x4117b360
#define CPU_ID_SA110 0x4401a100
#define CPU_ID_SA1100 0x4401a110
-#define CPU_ID_TI925T 0x54029250
+#define CPU_ID_TI925T 0x54029250
#define CPU_ID_SA1110 0x6901b110
#define CPU_ID_IXP1200 0x6901c120
#define CPU_ID_80200 0x69052000
@@ -208,13 +213,16 @@
#define CPU_ID_80219_400 0x69052e20
#define CPU_ID_80219_600 0x69052e30
#define CPU_ID_PXA27X 0x69054110
-#define CPU_ID_80321_400 0x69052420
-#define CPU_ID_80321_600 0x69052430
-#define CPU_ID_80321_400_B0 0x69052c20
-#define CPU_ID_80321_600_B0 0x69052c30
-#define CPU_ID_IXP425_533 0x690541c0
-#define CPU_ID_IXP425_400 0x690541d0
-#define CPU_ID_IXP425_266 0x690541f0
+#define CPU_ID_80321_400 0x69052420
+#define CPU_ID_80321_600 0x69052430
+#define CPU_ID_80321_400_B0 0x69052c20
+#define CPU_ID_80321_600_B0 0x69052c30
+#define CPU_ID_IXP425_533 0x690541c0
+#define CPU_ID_IXP425_400 0x690541d0
+#define CPU_ID_IXP425_266 0x690541f0
+#define CPU_ID_OMAP3430 0x411fc080
+#define CPU_ID_OMAP3530 0x411fc090 /* XXX */
+
/* ARM3-specific coprocessor 15 registers */
#define ARM3_CP15_FLUSH 1
@@ -285,29 +293,29 @@
#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */
-#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */
-#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */
-#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */
-#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */
-#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */
-#define XSCALE_AUXCTL_MD_MASK 0x00000030
+#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */
+#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */
+#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */
+#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */
+#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */
+#define XSCALE_AUXCTL_MD_MASK 0x00000030
/* Cache type register definitions */
-#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */
-#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */
-#define CPU_CT_S (1U << 24) /* split cache */
-#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */
-
-#define CPU_CT_CTYPE_WT 0 /* write-through */
-#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */
-#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */
-#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */
-#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */
-
-#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */
-#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */
-#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */
-#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */
+#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */
+#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */
+#define CPU_CT_S (1U << 24) /* split cache */
+#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */
+
+#define CPU_CT_CTYPE_WT 0 /* write-through */
+#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */
+#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */
+#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */
+#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */
+
+#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */
+#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */
+#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */
+#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */
/* Fault status register definitions */
@@ -331,13 +339,13 @@
#define FAULT_PERM_S 0x0d /* Permission -- Section */
#define FAULT_PERM_P 0x0f /* Permission -- Page */
-#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */
+#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */
/*
* Address of the vector page, low and high versions.
*/
-#define ARM_VECTORS_LOW 0x00000000U
-#define ARM_VECTORS_HIGH 0xffff0000U
+#define ARM_VECTORS_LOW 0x00000000U
+#define ARM_VECTORS_HIGH 0xffff0000U
/*
* ARM Instructions
diff --git a/sys/arch/arm/include/cpuconf.h b/sys/arch/arm/include/cpuconf.h
index e54d179becf..00c6b909b9f 100644
--- a/sys/arch/arm/include/cpuconf.h
+++ b/sys/arch/arm/include/cpuconf.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpuconf.h,v 1.4 2008/09/11 02:38:14 kevlo Exp $ */
+/* $OpenBSD: cpuconf.h,v 1.5 2009/05/08 02:57:32 drahn Exp $ */
/* $NetBSD: cpuconf.h,v 1.7 2003/05/23 00:57:24 ichiro Exp $ */
/*
@@ -76,6 +76,18 @@
#define ARM_ARCH_5 0
#endif
+#if defined(CPU_ARM11)
+#define ARM_ARCH_6 1
+#else
+#define ARM_ARCH_6 0
+#endif
+
+#if defined(CPU_ARMv7)
+#define ARM_ARCH_7 1
+#else
+#define ARM_ARCH_7 0
+#endif
+
/*
* Define which MMU classes are configured:
*
@@ -99,7 +111,7 @@
#if (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \
defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) || \
- defined(CPU_ARM10))
+ defined(CPU_ARM10) || defined(CPU_ARM11) || defined(CPU_ARMv7) )
#define ARM_MMU_GENERIC 1
#else
#define ARM_MMU_GENERIC 0
@@ -119,8 +131,14 @@
#define ARM_MMU_XSCALE 0
#endif
+#if defined(CPU_ARMv7)
+#define ARM_MMU_v7 1
+#else
+#define ARM_MMU_v7 0
+#endif
+
#define ARM_NMMUS (ARM_MMU_MEMC + ARM_MMU_GENERIC + \
- ARM_MMU_SA1 + ARM_MMU_XSCALE)
+ ARM_MMU_SA1 + ARM_MMU_XSCALE + ARM_MMU_v7)
/*
* Define features that may be present on a subset of CPUs
diff --git a/sys/arch/arm/include/cpufunc.h b/sys/arch/arm/include/cpufunc.h
index 5b1d4e53879..1385cc5d9ab 100644
--- a/sys/arch/arm/include/cpufunc.h
+++ b/sys/arch/arm/include/cpufunc.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpufunc.h,v 1.5 2008/09/11 02:38:14 kevlo Exp $ */
+/* $OpenBSD: cpufunc.h,v 1.6 2009/05/08 02:57:32 drahn Exp $ */
/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */
/*
@@ -360,7 +360,26 @@ void armv5_ec_idcache_wbinv_all (void);
void armv5_ec_idcache_wbinv_range (vaddr_t, vsize_t);
#endif
-#if defined (CPU_ARM10)
+#ifdef CPU_ARM11
+void arm11_setttb (u_int);
+
+void arm11_tlb_flushID_SE (u_int);
+void arm11_tlb_flushI_SE (u_int);
+
+void arm11_context_switch (u_int);
+
+void arm11_setup (char *string);
+void arm11_tlb_flushID (void);
+void arm11_tlb_flushI (void);
+void arm11_tlb_flushD (void);
+void arm11_tlb_flushD_SE (u_int va);
+
+void arm11_drain_writebuf (void);
+void arm11_cpu_sleep (int mode);
+#endif
+
+
+#if defined (CPU_ARM10) || defined(CPU_ARM11)
void armv5_setttb (u_int);
void armv5_icache_sync_all (void);
@@ -380,6 +399,44 @@ extern unsigned armv5_dcache_index_max;
extern unsigned armv5_dcache_index_inc;
#endif
+#ifdef CPU_ARMv7
+void armv7_setttb (u_int);
+
+void armv7_tlb_flushID_SE (u_int);
+void armv7_tlb_flushI_SE (u_int);
+
+void armv7_context_switch (u_int);
+void armv7_context_switch (u_int);
+
+void armv7_setup (char *string);
+void armv7_tlb_flushID (void);
+void armv7_tlb_flushI (void);
+void armv7_tlb_flushD (void);
+void armv7_tlb_flushD_SE (u_int va);
+
+void armv7_drain_writebuf (void);
+void armv7_cpu_sleep (int mode);
+
+void armv7_setttb (u_int);
+
+void armv7_icache_sync_all (void);
+void armv7_icache_sync_range (vaddr_t, vsize_t);
+
+void armv7_dcache_wbinv_all (void);
+void armv7_dcache_wbinv_range (vaddr_t, vsize_t);
+void armv7_dcache_inv_range (vaddr_t, vsize_t);
+void armv7_dcache_wb_range (vaddr_t, vsize_t);
+
+void armv7_idcache_wbinv_all (void);
+void armv7_idcache_wbinv_range (vaddr_t, vsize_t);
+
+extern unsigned armv7_dcache_sets_max;
+extern unsigned armv7_dcache_sets_inc;
+extern unsigned armv7_dcache_index_max;
+extern unsigned armv7_dcache_index_inc;
+#endif
+
+
#if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \
defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
@@ -459,10 +516,10 @@ __set_cpsr_c(u_int bic, u_int eor)
u_int32_t tmp, ret;
__asm __volatile(
- "mrs %0, cpsr\n" /* Get the CPSR */
+ "mrs %0, cpsr\n" /* Get the CPSR */
"bic %1, %0, %2\n" /* Clear bits */
"eor %1, %1, %3\n" /* XOR bits */
- "msr cpsr_c, %1\n" /* Set the control field of CPSR */
+ "msr cpsr_c, %1\n" /* Set the control field of CPSR */
: "=&r" (ret), "=&r" (tmp)
: "r" (bic), "r" (eor));
diff --git a/sys/arch/arm/include/pmap.h b/sys/arch/arm/include/pmap.h
index 2e5b139324d..3d891b182f2 100644
--- a/sys/arch/arm/include/pmap.h
+++ b/sys/arch/arm/include/pmap.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: pmap.h,v 1.9 2007/10/10 15:53:51 art Exp $ */
+/* $OpenBSD: pmap.h,v 1.10 2009/05/08 02:57:32 drahn Exp $ */
/* $NetBSD: pmap.h,v 1.76 2003/09/06 09:10:46 rearnsha Exp $ */
/*
@@ -273,6 +273,9 @@ void pmap_postinit(void);
void vector_page_setprot(int);
+/* XXX */
+void pmap_kenter_cache(vaddr_t va, paddr_t pa, vm_prot_t prot, int cacheable);
+
const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t);
const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t);
@@ -400,6 +403,12 @@ void pmap_pte_init_arm9(void);
#if defined(CPU_ARM10)
void pmap_pte_init_arm10(void);
#endif /* CPU_ARM10 */
+#if defined(CPU_ARM11)
+void pmap_pte_init_arm11(void);
+#endif /* CPU_ARM11 */
+#if defined(CPU_ARMv7)
+void pmap_pte_init_armv7(void);
+#endif /* CPU_ARMv7 */
#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
#if ARM_MMU_SA1 == 1
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-16 19:34:19 +0000