diff options
Diffstat (limited to 'sys/arch/arm/include')
50 files changed, 7209 insertions, 0 deletions
diff --git a/sys/arch/arm/include/ansi.h b/sys/arch/arm/include/ansi.h new file mode 100644 index 00000000000..466a195e1b3 --- /dev/null +++ b/sys/arch/arm/include/ansi.h @@ -0,0 +1,109 @@ +/* $OpenBSD: ansi.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: ansi.h,v 1.4 2003/03/02 22:18:17 tshiozak Exp $ */ + +/* + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: @(#)ansi.h 8.2 (Berkeley) 1/4/94 + */ + +#ifndef _ANSI_H_ +#define _ANSI_H_ + +#if 0 +#include <machine/types.h> +#endif + +/* + * Types which are fundamental to the implementation and may appear in + * more than one standard header are defined here. Standard headers + * then use: + * #ifdef _BSD_SIZE_T_ + * typedef _BSD_SIZE_T_ size_t; + * #undef _BSD_SIZE_T_ + * #endif + */ +#ifdef __ELF__ +#define _BSD_CLOCK_T_ unsigned int /* clock() */ +#define _BSD_PTRDIFF_T_ long int /* ptr1 - ptr2 */ +#define _BSD_SIZE_T_ unsigned long int /* sizeof() */ +#define _BSD_SSIZE_T_ long int /* byte count or error */ +#define _BSD_TIME_T_ int /* time() */ +#else +#define _BSD_CLOCK_T_ unsigned long /* clock() */ +#define _BSD_PTRDIFF_T_ int /* ptr1 - ptr2 */ +#define _BSD_SIZE_T_ unsigned int /* sizeof() */ +#define _BSD_SSIZE_T_ int /* byte count or error */ +#define _BSD_TIME_T_ long /* time() */ +#endif +#define _BSD_VA_LIST_ __builtin_va_list /* va_list */ +#define _BSD_CLOCKID_T_ int /* clockid_t */ +#define _BSD_TIMER_T_ int /* timer_t */ +#define _BSD_SUSECONDS_T_ int /* suseconds_t */ +#define _BSD_USECONDS_T_ unsigned int /* useconds_t */ + +/* + * NOTE: rune_t is not covered by ANSI nor other standards, and should not + * be instantiated outside of lib/libc/locale. use wchar_t. + * + * Runes (wchar_t) is declared to be an ``int'' instead of the more natural + * ``unsigned long'' or ``long''. Two things are happening here. It is not + * unsigned so that EOF (-1) can be naturally assigned to it and used. Also, + * it looks like 10646 will be a 31 bit standard. This means that if your + * ints cannot hold 32 bits, you will be in trouble. The reason an int was + * chosen over a long is that the is*() and to*() routines take ints (says + * ANSI C), but they use _RUNE_T_ instead of int. By changing it here, you + * lose a bit of ANSI conformance, but your programs will still work. + * + * Note that _WCHAR_T_ and _RUNE_T_ must be of the same type. When wchar_t + * and rune_t are typedef'd, _WCHAR_T_ will be undef'd, but _RUNE_T remains + * defined for ctype.h. + */ +#define _BSD_WCHAR_T_ int /* wchar_t */ +#define _BSD_WINT_T_ int /* wint_t */ +#define _BSD_RUNE_T_ int /* rune_t */ +#define _BSD_WCTRANS_T_ void * /* wctrans_t */ +#define _BSD_WCTYPE_T_ void * /* wctype_t */ + +/* + * mbstate_t is an opaque object to keep conversion state, during multibyte + * stream conversions. The content must not be referenced by user programs. + */ +typedef union { + char __mbstate8[128]; + long long __mbstateL; /* for alignment */ +} __mbstate_t; +#define _BSD_MBSTATE_T_ __mbstate_t /* mbstate_t */ + +/* + * We describe off_t here so its declaration can be visible to + * stdio without pulling in all of <sys/type.h>, thus appeasing ANSI. + */ +#define _BSD_OFF_T_ long long /* file offset */ + +#endif /* _ANSI_H_ */ diff --git a/sys/arch/arm/include/armreg.h b/sys/arch/arm/include/armreg.h new file mode 100644 index 00000000000..f5c1ef567e9 --- /dev/null +++ b/sys/arch/arm/include/armreg.h @@ -0,0 +1,353 @@ +/* $OpenBSD: armreg.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: armreg.h,v 1.27 2003/09/06 08:43:02 rearnsha Exp $ */ + +/* + * Copyright (c) 1998, 2001 Ben Harris + * Copyright (c) 1994-1996 Mark Brinicombe. + * Copyright (c) 1994 Brini. + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARM_ARMREG_H +#define _ARM_ARMREG_H + +/* + * ARM Process Status Register + * + * The picture in the ARM manuals looks like this: + * 3 3 2 2 2 2 + * 1 0 9 8 7 6 8 7 6 5 4 0 + * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ + * |N|Z|C|V|Q| reserved |I|F|T|M M M M M| + * | | | | | | | | | |4 3 2 1 0| + * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ + */ + +#define PSR_FLAGS 0xf0000000 /* flags */ +#define PSR_N_bit (1 << 31) /* negative */ +#define PSR_Z_bit (1 << 30) /* zero */ +#define PSR_C_bit (1 << 29) /* carry */ +#define PSR_V_bit (1 << 28) /* overflow */ + +#define PSR_Q_bit (1 << 27) /* saturation */ + +#define I32_bit (1 << 7) /* IRQ disable */ +#define F32_bit (1 << 6) /* FIQ disable */ + +#define PSR_T_bit (1 << 5) /* Thumb state */ +#define PSR_J_bit (1 << 24) /* Java mode */ + +#define PSR_MODE 0x0000001f /* mode mask */ +#define PSR_USR26_MODE 0x00000000 +#define PSR_FIQ26_MODE 0x00000001 +#define PSR_IRQ26_MODE 0x00000002 +#define PSR_SVC26_MODE 0x00000003 +#define PSR_USR32_MODE 0x00000010 +#define PSR_FIQ32_MODE 0x00000011 +#define PSR_IRQ32_MODE 0x00000012 +#define PSR_SVC32_MODE 0x00000013 +#define PSR_ABT32_MODE 0x00000017 +#define PSR_UND32_MODE 0x0000001b +#define PSR_SYS32_MODE 0x0000001f +#define PSR_32_MODE 0x00000010 + +#define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */ +#define PSR_IN_32_MODE(psr) ((psr) & PSR_32_MODE) + +/* In 26-bit modes, the PSR is stuffed into R15 along with the PC. */ + +#define R15_MODE 0x00000003 +#define R15_MODE_USR 0x00000000 +#define R15_MODE_FIQ 0x00000001 +#define R15_MODE_IRQ 0x00000002 +#define R15_MODE_SVC 0x00000003 + +#define R15_PC 0x03fffffc + +#define R15_FIQ_DISABLE 0x04000000 +#define R15_IRQ_DISABLE 0x08000000 + +#define R15_FLAGS 0xf0000000 +#define R15_FLAG_N 0x80000000 +#define R15_FLAG_Z 0x40000000 +#define R15_FLAG_C 0x20000000 +#define R15_FLAG_V 0x10000000 + +/* + * Co-processor 15: The system control co-processor. + */ + +#define ARM_CP15_CPU_ID 0 + +/* + * The CPU ID register is theoretically structured, but the definitions of + * the fields keep changing. + */ + +/* The high-order byte is always the implementor */ +#define CPU_ID_IMPLEMENTOR_MASK 0xff000000 +#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ +#define CPU_ID_DEC 0x44000000 /* 'D' */ +#define CPU_ID_INTEL 0x69000000 /* 'i' */ +#define CPU_ID_TI 0x54000000 /* 'T' */ + +/* How to decide what format the CPUID is in. */ +#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) +#define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) +#define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) + +/* On ARM3 and ARM6, this byte holds the foundry ID. */ +#define CPU_ID_FOUNDRY_MASK 0x00ff0000 +#define CPU_ID_FOUNDRY_VLSI 0x00560000 + +/* On ARM7 it holds the architecture and variant (sub-model) */ +#define CPU_ID_7ARCH_MASK 0x00800000 +#define CPU_ID_7ARCH_V3 0x00000000 +#define CPU_ID_7ARCH_V4T 0x00800000 +#define CPU_ID_7VARIANT_MASK 0x007f0000 + +/* On more recent ARMs, it does the same, but in a different format */ +#define CPU_ID_ARCH_MASK 0x000f0000 +#define CPU_ID_ARCH_V3 0x00000000 +#define CPU_ID_ARCH_V4 0x00010000 +#define CPU_ID_ARCH_V4T 0x00020000 +#define CPU_ID_ARCH_V5 0x00030000 +#define CPU_ID_ARCH_V5T 0x00040000 +#define CPU_ID_ARCH_V5TE 0x00050000 +#define CPU_ID_VARIANT_MASK 0x00f00000 + +/* Next three nybbles are part number */ +#define CPU_ID_PARTNO_MASK 0x0000fff0 + +/* Intel XScale has sub fields in part number */ +#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ +#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ +#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ + +/* And finally, the revision number. */ +#define CPU_ID_REVISION_MASK 0x0000000f + +/* Individual CPUs are probably best IDed by everything but the revision. */ +#define CPU_ID_CPU_MASK 0xfffffff0 + +/* Fake CPU IDs for ARMs without CP15 */ +#define CPU_ID_ARM2 0x41560200 +#define CPU_ID_ARM250 0x41560250 + +/* Pre-ARM7 CPUs -- [15:12] == 0 */ +#define CPU_ID_ARM3 0x41560300 +#define CPU_ID_ARM600 0x41560600 +#define CPU_ID_ARM610 0x41560610 +#define CPU_ID_ARM620 0x41560620 + +/* ARM7 CPUs -- [15:12] == 7 */ +#define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ +#define CPU_ID_ARM710 0x41007100 +#define CPU_ID_ARM7500 0x41027100 /* XXX This is a guess. */ +#define CPU_ID_ARM710A 0x41047100 /* inc ARM7100 */ +#define CPU_ID_ARM7500FE 0x41077100 +#define CPU_ID_ARM710T 0x41807100 +#define CPU_ID_ARM720T 0x41807200 +#define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ +#define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ + +/* Post-ARM7 CPUs */ +#define CPU_ID_ARM810 0x41018100 +#define CPU_ID_ARM920T 0x41129200 +#define CPU_ID_ARM922T 0x41029220 +#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ +#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ +#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ +#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ +#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ +#define CPU_ID_ARM1022ES 0x4105a220 +#define CPU_ID_SA110 0x4401a100 +#define CPU_ID_SA1100 0x4401a110 +#define CPU_ID_TI925T 0x54029250 +#define CPU_ID_SA1110 0x6901b110 +#define CPU_ID_IXP1200 0x6901c120 +#define CPU_ID_80200 0x69052000 +#define CPU_ID_PXA250 0x69052100 /* sans core revision */ +#define CPU_ID_PXA210 0x69052120 +#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ +#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ +#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ +#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ +#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ +#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ +#define CPU_ID_80321_400 0x69052420 +#define CPU_ID_80321_600 0x69052430 +#define CPU_ID_80321_400_B0 0x69052c20 +#define CPU_ID_80321_600_B0 0x69052c30 +#define CPU_ID_IXP425_533 0x690541c0 +#define CPU_ID_IXP425_400 0x690541d0 +#define CPU_ID_IXP425_266 0x690541f0 + +/* ARM3-specific coprocessor 15 registers */ +#define ARM3_CP15_FLUSH 1 +#define ARM3_CP15_CONTROL 2 +#define ARM3_CP15_CACHEABLE 3 +#define ARM3_CP15_UPDATEABLE 4 +#define ARM3_CP15_DISRUPTIVE 5 + +/* ARM3 Control register bits */ +#define ARM3_CTL_CACHE_ON 0x00000001 +#define ARM3_CTL_SHARED 0x00000002 +#define ARM3_CTL_MONITOR 0x00000004 + +/* + * Post-ARM3 CP15 registers: + * + * 1 Control register + * + * 2 Translation Table Base + * + * 3 Domain Access Control + * + * 4 Reserved + * + * 5 Fault Status + * + * 6 Fault Address + * + * 7 Cache/write-buffer Control + * + * 8 TLB Control + * + * 9 Cache Lockdown + * + * 10 TLB Lockdown + * + * 11 Reserved + * + * 12 Reserved + * + * 13 Process ID (for FCSE) + * + * 14 Reserved + * + * 15 Implementation Dependent + */ + +/* Some of the definitions below need cleaning up for V3/V4 architectures */ + +/* CPU control register (CP15 register 1) */ +#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ +#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ +#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ +#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ +#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ +#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ +#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ +#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ +#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ +#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ +#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ +#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ +#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ +#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ +#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ +#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ + +#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE + +/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ +#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ +#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ +#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ +#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ +#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ +#define XSCALE_AUXCTL_MD_MASK 0x00000030 + +/* Cache type register definitions */ +#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ +#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ +#define CPU_CT_S (1U << 24) /* split cache */ +#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ + +#define CPU_CT_CTYPE_WT 0 /* write-through */ +#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ +#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ +#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ +#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ + +#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ +#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ +#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ +#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ + +/* Fault status register definitions */ + +#define FAULT_TYPE_MASK 0x0f +#define FAULT_USER 0x10 + +#define FAULT_WRTBUF_0 0x00 /* Vector Exception */ +#define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ +#define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ +#define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ +#define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ +#define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ +#define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ +#define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ +#define FAULT_ALIGN_0 0x01 /* Alignment */ +#define FAULT_ALIGN_1 0x03 /* Alignment */ +#define FAULT_TRANS_S 0x05 /* Translation -- Section */ +#define FAULT_TRANS_P 0x07 /* Translation -- Page */ +#define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ +#define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ +#define FAULT_PERM_S 0x0d /* Permission -- Section */ +#define FAULT_PERM_P 0x0f /* Permission -- Page */ + +#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ + +/* + * Address of the vector page, low and high versions. + */ +#define ARM_VECTORS_LOW 0x00000000U +#define ARM_VECTORS_HIGH 0xffff0000U + +/* + * ARM Instructions + * + * 3 3 2 2 2 + * 1 0 9 8 7 0 + * +-------+-------------------------------------------------------+ + * | cond | instruction dependant | + * |c c c c| | + * +-------+-------------------------------------------------------+ + */ + +#define INSN_SIZE 4 /* Always 4 bytes */ +#define INSN_COND_MASK 0xf0000000 /* Condition mask */ +#define INSN_COND_AL 0xe0000000 /* Always condition */ + +#endif diff --git a/sys/arch/arm/include/asm.h b/sys/arch/arm/include/asm.h new file mode 100644 index 00000000000..c7bd017aa70 --- /dev/null +++ b/sys/arch/arm/include/asm.h @@ -0,0 +1,130 @@ +/* $OpenBSD: asm.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: asm.h,v 1.4 2001/07/16 05:43:32 matt Exp $ */ + +/* + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * William Jolitz. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: @(#)asm.h 5.5 (Berkeley) 5/7/91 + */ + +#ifndef _ARM32_ASM_H_ +#define _ARM32_ASM_H_ + +#ifdef __ELF__ +# define _C_LABEL(x) x +#else +# ifdef __STDC__ +# define _C_LABEL(x) _ ## x +# else +# define _C_LABEL(x) _/**/x +# endif +#endif +#define _ASM_LABEL(x) x + +#ifdef __STDC__ +# define __CONCAT(x,y) x ## y +# define __STRING(x) #x +#else +# define __CONCAT(x,y) x/**/y +# define __STRING(x) "x" +#endif + +#ifndef _ALIGN_TEXT +# define _ALIGN_TEXT .align 0 +#endif + +/* + * gas/arm uses @ as a single comment character and thus cannot be used here + * Instead it recognised the # instead of an @ symbols in .type directives + * We define a couple of macros so that assembly code will not be dependant + * on one or the other. + */ +#define _ASM_TYPE_FUNCTION #function +#define _ASM_TYPE_OBJECT #object +#define _ENTRY(x) \ + .text; _ALIGN_TEXT; .globl x; .type x,_ASM_TYPE_FUNCTION; x: + +#ifdef GPROF +# ifdef __ELF__ +# define _PROF_PROLOGUE \ + mov ip, lr; bl __mcount +# else +# define _PROF_PROLOGUE \ + mov ip,lr; bl mcount +# endif +#else +# define _PROF_PROLOGUE +#endif + +#define ENTRY(y) _ENTRY(_C_LABEL(y)); _PROF_PROLOGUE +#define ENTRY_NP(y) _ENTRY(_C_LABEL(y)) +#define ASENTRY(y) _ENTRY(_ASM_LABEL(y)); _PROF_PROLOGUE +#define ASENTRY_NP(y) _ENTRY(_ASM_LABEL(y)) + +#define ASMSTR .asciz + +#if defined(__ELF__) && defined(PIC) +#ifdef __STDC__ +#define PIC_SYM(x,y) x ## ( ## y ## ) +#else +#define PIC_SYM(x,y) x/**/(/**/y/**/) +#endif +#else +#define PIC_SYM(x,y) x +#endif + +#ifdef __ELF__ +#define RCSID(x) .section ".ident"; .asciz x +#else +#define RCSID(x) .text; .asciz x +#endif + +#ifdef __ELF__ +#define WEAK_ALIAS(alias,sym) \ + .weak alias; \ + alias = sym +#endif + +#ifdef __STDC__ +#define WARN_REFERENCES(sym,msg) \ + .stabs msg ## ,30,0,0,0 ; \ + .stabs __STRING(_C_LABEL(sym)) ## ,1,0,0,0 +#elif defined(__ELF__) +#define WARN_REFERENCES(sym,msg) \ + .stabs msg,30,0,0,0 ; \ + .stabs __STRING(sym),1,0,0,0 +#else +#define WARN_REFERENCES(sym,msg) \ + .stabs msg,30,0,0,0 ; \ + .stabs __STRING(_/**/sym),1,0,0,0 +#endif /* __STDC__ */ + +#endif /* !_ARM_ASM_H_ */ diff --git a/sys/arch/arm/include/atomic.h b/sys/arch/arm/include/atomic.h new file mode 100644 index 00000000000..9ef4c687a9e --- /dev/null +++ b/sys/arch/arm/include/atomic.h @@ -0,0 +1,103 @@ +/* $OpenBSD: atomic.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */ + +/* + * Copyright (C) 1994-1997 Mark Brinicombe + * Copyright (C) 1994 Brini + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of Brini may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ARM_ATOMIC_H_ +#define _ARM_ATOMIC_H_ + +#ifndef ATOMIC_SET_BIT_NONINLINE_REQUIRED + +#if defined(__PROG26) || defined(ATOMIC_SET_BIT_NOINLINE) +#define ATOMIC_SET_BIT_NONINLINE_REQUIRED +#endif + +#endif /* ATOMIC_SET_BIT_NONINLINE_REQUIRED */ + + +#ifndef _LOCORE + +#include <sys/types.h> +#include <arm/armreg.h> /* I32_bit */ + +#ifdef ATOMIC_SET_BIT_NONINLINE_REQUIRED +void atomic_set_bit( u_int *, u_int ); +void atomic_clear_bit( u_int *, u_int ); +#endif + +#ifdef __PROG32 +#define __with_interrupts_disabled(expr) \ + do { \ + u_int cpsr_save, tmp; \ + \ + __asm __volatile( \ + "mrs %0, cpsr;" \ + "orr %1, %0, %2;" \ + "msr cpsr_all, %1;" \ + : "=r" (cpsr_save), "=r" (tmp) \ + : "I" (I32_bit) \ + : "cc" ); \ + (expr); \ + __asm __volatile( \ + "msr cpsr_all, %0" \ + : /* no output */ \ + : "r" (cpsr_save) \ + : "cc" ); \ + } while(0) + +static __inline void +inline_atomic_set_bit( u_int *address, u_int setmask ) +{ + __with_interrupts_disabled( *address |= setmask ); +} + +static __inline void +inline_atomic_clear_bit( u_int *address, u_int clearmask ) +{ + __with_interrupts_disabled( *address &= ~clearmask ); +} + +#if !defined(ATOMIC_SET_BIT_NOINLINE) + +#define atomic_set_bit(a,m) inline_atomic_set_bit(a,m) +#define atomic_clear_bit(a,m) inline_atomic_clear_bit(a,m) + +#endif + +#endif /* __PROG32 */ + +#undef __with_interrupts_disabled + +#endif /* _LOCORE */ +#endif /* _ARM_ATOMIC_H_ */ diff --git a/sys/arch/arm/include/blockio.h b/sys/arch/arm/include/blockio.h new file mode 100644 index 00000000000..ce071c4717b --- /dev/null +++ b/sys/arch/arm/include/blockio.h @@ -0,0 +1,54 @@ +/* $OpenBSD: blockio.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: blockio.h,v 1.2 2001/06/02 10:44:56 bjh21 Exp $ */ + +/*- + * Copyright (c) 2001 Ben Harris + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * blockio.h - low level functions for bulk PIO data transfer + */ + +#ifndef _ARM_BLOCKIO_H_ +#define _ARM_BLOCKIO_H_ + +/* + * All these take three arguments: + * I/O address + * Memory address + * Number of bytes to copy + */ + +void read_multi_1(u_int, void *, u_int); +void write_multi_1(u_int, const void *, u_int); +#define read_multi_2 insw16 +#define write_multi_2 outsw16 + +void insw(u_int, void *, u_int); +void outsw(u_int, void *, u_int); +void insw16(u_int, void *, u_int); +void outsw16(u_int, void *, u_int); + +#endif diff --git a/sys/arch/arm/include/bus.h b/sys/arch/arm/include/bus.h new file mode 100644 index 00000000000..b1a508e9903 --- /dev/null +++ b/sys/arch/arm/include/bus.h @@ -0,0 +1,1071 @@ +/* $NetBSD: bus.h,v 1.12 2003/10/23 15:03:24 scw Exp $ */ + +/*- + * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Copyright (c) 1996 Charles M. Hannum. All rights reserved. + * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Christopher G. Demetriou + * for the NetBSD Project. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ARM32_BUS_H_ +#define _ARM32_BUS_H_ + +#if defined(_KERNEL_OPT) +#include "opt_arm_bus_space.h" +#endif + +/* + * Addresses (in bus space). + */ +typedef u_long bus_addr_t; +typedef u_long bus_size_t; + +/* + * Access methods for bus space. + */ +typedef struct bus_space *bus_space_tag_t; +typedef u_long bus_space_handle_t; + +/* + * int bus_space_map __P((bus_space_tag_t t, bus_addr_t addr, + * bus_size_t size, int flags, bus_space_handle_t *bshp)); + * + * Map a region of bus space. + */ + +#define BUS_SPACE_MAP_CACHEABLE 0x01 +#define BUS_SPACE_MAP_LINEAR 0x02 +#define BUS_SPACE_MAP_PREFETCHABLE 0x04 + +struct bus_space { + /* cookie */ + void *bs_cookie; + + /* mapping/unmapping */ + int (*bs_map) __P((void *, bus_addr_t, bus_size_t, + int, bus_space_handle_t *)); + void (*bs_unmap) __P((void *, bus_space_handle_t, + bus_size_t)); + int (*bs_subregion) __P((void *, bus_space_handle_t, + bus_size_t, bus_size_t, bus_space_handle_t *)); + + /* allocation/deallocation */ + int (*bs_alloc) __P((void *, bus_addr_t, bus_addr_t, + bus_size_t, bus_size_t, bus_size_t, int, + bus_addr_t *, bus_space_handle_t *)); + void (*bs_free) __P((void *, bus_space_handle_t, + bus_size_t)); + + /* get kernel virtual address */ + void * (*bs_vaddr) __P((void *, bus_space_handle_t)); + + /* mmap bus space for user */ + paddr_t (*bs_mmap) __P((void *, bus_addr_t, off_t, int, int)); + + /* barrier */ + void (*bs_barrier) __P((void *, bus_space_handle_t, + bus_size_t, bus_size_t, int)); + + /* read (single) */ + u_int8_t (*bs_r_1) __P((void *, bus_space_handle_t, + bus_size_t)); + u_int16_t (*bs_r_2) __P((void *, bus_space_handle_t, + bus_size_t)); + u_int32_t (*bs_r_4) __P((void *, bus_space_handle_t, + bus_size_t)); + u_int64_t (*bs_r_8) __P((void *, bus_space_handle_t, + bus_size_t)); + + /* read multiple */ + void (*bs_rm_1) __P((void *, bus_space_handle_t, + bus_size_t, u_int8_t *, bus_size_t)); + void (*bs_rm_2) __P((void *, bus_space_handle_t, + bus_size_t, u_int16_t *, bus_size_t)); + void (*bs_rm_4) __P((void *, bus_space_handle_t, + bus_size_t, u_int32_t *, bus_size_t)); + void (*bs_rm_8) __P((void *, bus_space_handle_t, + bus_size_t, u_int64_t *, bus_size_t)); + + /* read region */ + void (*bs_rr_1) __P((void *, bus_space_handle_t, + bus_size_t, u_int8_t *, bus_size_t)); + void (*bs_rr_2) __P((void *, bus_space_handle_t, + bus_size_t, u_int16_t *, bus_size_t)); + void (*bs_rr_4) __P((void *, bus_space_handle_t, + bus_size_t, u_int32_t *, bus_size_t)); + void (*bs_rr_8) __P((void *, bus_space_handle_t, + bus_size_t, u_int64_t *, bus_size_t)); + + /* write (single) */ + void (*bs_w_1) __P((void *, bus_space_handle_t, + bus_size_t, u_int8_t)); + void (*bs_w_2) __P((void *, bus_space_handle_t, + bus_size_t, u_int16_t)); + void (*bs_w_4) __P((void *, bus_space_handle_t, + bus_size_t, u_int32_t)); + void (*bs_w_8) __P((void *, bus_space_handle_t, + bus_size_t, u_int64_t)); + + /* write multiple */ + void (*bs_wm_1) __P((void *, bus_space_handle_t, + bus_size_t, const u_int8_t *, bus_size_t)); + void (*bs_wm_2) __P((void *, bus_space_handle_t, + bus_size_t, const u_int16_t *, bus_size_t)); + void (*bs_wm_4) __P((void *, bus_space_handle_t, + bus_size_t, const u_int32_t *, bus_size_t)); + void (*bs_wm_8) __P((void *, bus_space_handle_t, + bus_size_t, const u_int64_t *, bus_size_t)); + + /* write region */ + void (*bs_wr_1) __P((void *, bus_space_handle_t, + bus_size_t, const u_int8_t *, bus_size_t)); + void (*bs_wr_2) __P((void *, bus_space_handle_t, + bus_size_t, const u_int16_t *, bus_size_t)); + void (*bs_wr_4) __P((void *, bus_space_handle_t, + bus_size_t, const u_int32_t *, bus_size_t)); + void (*bs_wr_8) __P((void *, bus_space_handle_t, + bus_size_t, const u_int64_t *, bus_size_t)); + + /* set multiple */ + void (*bs_sm_1) __P((void *, bus_space_handle_t, + bus_size_t, u_int8_t, bus_size_t)); + void (*bs_sm_2) __P((void *, bus_space_handle_t, + bus_size_t, u_int16_t, bus_size_t)); + void (*bs_sm_4) __P((void *, bus_space_handle_t, + bus_size_t, u_int32_t, bus_size_t)); + void (*bs_sm_8) __P((void *, bus_space_handle_t, + bus_size_t, u_int64_t, bus_size_t)); + + /* set region */ + void (*bs_sr_1) __P((void *, bus_space_handle_t, + bus_size_t, u_int8_t, bus_size_t)); + void (*bs_sr_2) __P((void *, bus_space_handle_t, + bus_size_t, u_int16_t, bus_size_t)); + void (*bs_sr_4) __P((void *, bus_space_handle_t, + bus_size_t, u_int32_t, bus_size_t)); + void (*bs_sr_8) __P((void *, bus_space_handle_t, + bus_size_t, u_int64_t, bus_size_t)); + + /* copy */ + void (*bs_c_1) __P((void *, bus_space_handle_t, bus_size_t, + bus_space_handle_t, bus_size_t, bus_size_t)); + void (*bs_c_2) __P((void *, bus_space_handle_t, bus_size_t, + bus_space_handle_t, bus_size_t, bus_size_t)); + void (*bs_c_4) __P((void *, bus_space_handle_t, bus_size_t, + bus_space_handle_t, bus_size_t, bus_size_t)); + void (*bs_c_8) __P((void *, bus_space_handle_t, bus_size_t, + bus_space_handle_t, bus_size_t, bus_size_t)); + +#ifdef __BUS_SPACE_HAS_STREAM_METHODS + /* read stream (single) */ + u_int8_t (*bs_r_1_s) __P((void *, bus_space_handle_t, + bus_size_t)); + u_int16_t (*bs_r_2_s) __P((void *, bus_space_handle_t, + bus_size_t)); + u_int32_t (*bs_r_4_s) __P((void *, bus_space_handle_t, + bus_size_t)); + u_int64_t (*bs_r_8_s) __P((void *, bus_space_handle_t, + bus_size_t)); + + /* read multiple stream */ + void (*bs_rm_1_s) __P((void *, bus_space_handle_t, + bus_size_t, u_int8_t *, bus_size_t)); + void (*bs_rm_2_s) __P((void *, bus_space_handle_t, + bus_size_t, u_int16_t *, bus_size_t)); + void (*bs_rm_4_s) __P((void *, bus_space_handle_t, + bus_size_t, u_int32_t *, bus_size_t)); + void (*bs_rm_8_s) __P((void *, bus_space_handle_t, + bus_size_t, u_int64_t *, bus_size_t)); + + /* read region stream */ + void (*bs_rr_1_s) __P((void *, bus_space_handle_t, + bus_size_t, u_int8_t *, bus_size_t)); + void (*bs_rr_2_s) __P((void *, bus_space_handle_t, + bus_size_t, u_int16_t *, bus_size_t)); + void (*bs_rr_4_s) __P((void *, bus_space_handle_t, + bus_size_t, u_int32_t *, bus_size_t)); + void (*bs_rr_8_s) __P((void *, bus_space_handle_t, + bus_size_t, u_int64_t *, bus_size_t)); + + /* write stream (single) */ + void (*bs_w_1_s) __P((void *, bus_space_handle_t, + bus_size_t, u_int8_t)); + void (*bs_w_2_s) __P((void *, bus_space_handle_t, + bus_size_t, u_int16_t)); + void (*bs_w_4_s) __P((void *, bus_space_handle_t, + bus_size_t, u_int32_t)); + void (*bs_w_8_s) __P((void *, bus_space_handle_t, + bus_size_t, u_int64_t)); + + /* write multiple stream */ + void (*bs_wm_1_s) __P((void *, bus_space_handle_t, + bus_size_t, const u_int8_t *, bus_size_t)); + void (*bs_wm_2_s) __P((void *, bus_space_handle_t, + bus_size_t, const u_int16_t *, bus_size_t)); + void (*bs_wm_4_s) __P((void *, bus_space_handle_t, + bus_size_t, const u_int32_t *, bus_size_t)); + void (*bs_wm_8_s) __P((void *, bus_space_handle_t, + bus_size_t, const u_int64_t *, bus_size_t)); + + /* write region stream */ + void (*bs_wr_1_s) __P((void *, bus_space_handle_t, + bus_size_t, const u_int8_t *, bus_size_t)); + void (*bs_wr_2_s) __P((void *, bus_space_handle_t, + bus_size_t, const u_int16_t *, bus_size_t)); + void (*bs_wr_4_s) __P((void *, bus_space_handle_t, + bus_size_t, const u_int32_t *, bus_size_t)); + void (*bs_wr_8_s) __P((void *, bus_space_handle_t, + bus_size_t, const u_int64_t *, bus_size_t)); +#endif /* __BUS_SPACE_HAS_STREAM_METHODS */ +}; + + +/* + * Utility macros; INTERNAL USE ONLY. + */ +#define __bs_c(a,b) __CONCAT(a,b) +#define __bs_opname(op,size) __bs_c(__bs_c(__bs_c(bs_,op),_),size) + +#define __bs_rs(sz, t, h, o) \ + (*(t)->__bs_opname(r,sz))((t)->bs_cookie, h, o) +#define __bs_ws(sz, t, h, o, v) \ + (*(t)->__bs_opname(w,sz))((t)->bs_cookie, h, o, v) +#define __bs_nonsingle(type, sz, t, h, o, a, c) \ + (*(t)->__bs_opname(type,sz))((t)->bs_cookie, h, o, a, c) +#define __bs_set(type, sz, t, h, o, v, c) \ + (*(t)->__bs_opname(type,sz))((t)->bs_cookie, h, o, v, c) +#define __bs_copy(sz, t, h1, o1, h2, o2, cnt) \ + (*(t)->__bs_opname(c,sz))((t)->bs_cookie, h1, o1, h2, o2, cnt) + +#ifdef __BUS_SPACE_HAS_STREAM_METHODS +#define __bs_opname_s(op,size) __bs_c(__bs_c(__bs_c(__bs_c(bs_,op),_),size),_s) +#define __bs_rs_s(sz, t, h, o) \ + (*(t)->__bs_opname_s(r,sz))((t)->bs_cookie, h, o) +#define __bs_ws_s(sz, t, h, o, v) \ + (*(t)->__bs_opname_s(w,sz))((t)->bs_cookie, h, o, v) +#define __bs_nonsingle_s(type, sz, t, h, o, a, c) \ + (*(t)->__bs_opname_s(type,sz))((t)->bs_cookie, h, o, a, c) +#define __bs_set_s(type, sz, t, h, o, v, c) \ + (*(t)->__bs_opname_s(type,sz))((t)->bs_cookie, h, o, v, c) +#define __bs_copy_s(sz, t, h1, o1, h2, o2, cnt) \ + (*(t)->__bs_opname_s(c,sz))((t)->bs_cookie, h1, o1, h2, o2, cnt) +#endif + +/* + * Mapping and unmapping operations. + */ +#define bus_space_map(t, a, s, c, hp) \ + (*(t)->bs_map)((t)->bs_cookie, (a), (s), (c), (hp)) +#define bus_space_unmap(t, h, s) \ + (*(t)->bs_unmap)((t)->bs_cookie, (h), (s)) +#define bus_space_subregion(t, h, o, s, hp) \ + (*(t)->bs_subregion)((t)->bs_cookie, (h), (o), (s), (hp)) + + +/* + * Allocation and deallocation operations. + */ +#define bus_space_alloc(t, rs, re, s, a, b, c, ap, hp) \ + (*(t)->bs_alloc)((t)->bs_cookie, (rs), (re), (s), (a), (b), \ + (c), (ap), (hp)) +#define bus_space_free(t, h, s) \ + (*(t)->bs_free)((t)->bs_cookie, (h), (s)) + +/* + * Get kernel virtual address for ranges mapped BUS_SPACE_MAP_LINEAR. + */ +#define bus_space_vaddr(t, h) \ + (*(t)->bs_vaddr)((t)->bs_cookie, (h)) + +/* + * MMap bus space for a user application. + */ +#define bus_space_mmap(t, a, o, p, f) \ + (*(t)->bs_mmap)((t)->bs_cookie, (a), (o), (p), (f)) + +/* + * Bus barrier operations. + */ +#define bus_space_barrier(t, h, o, l, f) \ + (*(t)->bs_barrier)((t)->bs_cookie, (h), (o), (l), (f)) + +#define BUS_SPACE_BARRIER_READ 0x01 +#define BUS_SPACE_BARRIER_WRITE 0x02 + +/* + * Bus read (single) operations. + */ +#define bus_space_read_1(t, h, o) __bs_rs(1,(t),(h),(o)) +#define bus_space_read_2(t, h, o) __bs_rs(2,(t),(h),(o)) +#define bus_space_read_4(t, h, o) __bs_rs(4,(t),(h),(o)) +#define bus_space_read_8(t, h, o) __bs_rs(8,(t),(h),(o)) +#ifdef __BUS_SPACE_HAS_STREAM_METHODS +#define bus_space_read_stream_1(t, h, o) __bs_rs_s(1,(t),(h),(o)) +#define bus_space_read_stream_2(t, h, o) __bs_rs_s(2,(t),(h),(o)) +#define bus_space_read_stream_4(t, h, o) __bs_rs_s(4,(t),(h),(o)) +#define bus_space_read_stream_8(t, h, o) __bs_rs_s(8,(t),(h),(o)) +#endif + + +/* + * Bus read multiple operations. + */ +#define bus_space_read_multi_1(t, h, o, a, c) \ + __bs_nonsingle(rm,1,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_2(t, h, o, a, c) \ + __bs_nonsingle(rm,2,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_4(t, h, o, a, c) \ + __bs_nonsingle(rm,4,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_8(t, h, o, a, c) \ + __bs_nonsingle(rm,8,(t),(h),(o),(a),(c)) +#ifdef __BUS_SPACE_HAS_STREAM_METHODS +#define bus_space_read_multi_stream_1(t, h, o, a, c) \ + __bs_nonsingle_s(rm,1,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_stream_2(t, h, o, a, c) \ + __bs_nonsingle_s(rm,2,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_stream_4(t, h, o, a, c) \ + __bs_nonsingle_s(rm,4,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_stream_8(t, h, o, a, c) \ + __bs_nonsingle_s(rm,8,(t),(h),(o),(a),(c)) +#endif + + +/* + * Bus read region operations. + */ +#define bus_space_read_region_1(t, h, o, a, c) \ + __bs_nonsingle(rr,1,(t),(h),(o),(a),(c)) +#define bus_space_read_region_2(t, h, o, a, c) \ + __bs_nonsingle(rr,2,(t),(h),(o),(a),(c)) +#define bus_space_read_region_4(t, h, o, a, c) \ + __bs_nonsingle(rr,4,(t),(h),(o),(a),(c)) +#define bus_space_read_region_8(t, h, o, a, c) \ + __bs_nonsingle(rr,8,(t),(h),(o),(a),(c)) +#ifdef __BUS_SPACE_HAS_STREAM_METHODS +#define bus_space_read_region_stream_1(t, h, o, a, c) \ + __bs_nonsingle_s(rr,1,(t),(h),(o),(a),(c)) +#define bus_space_read_region_stream_2(t, h, o, a, c) \ + __bs_nonsingle_s(rr,2,(t),(h),(o),(a),(c)) +#define bus_space_read_region_stream_4(t, h, o, a, c) \ + __bs_nonsingle_s(rr,4,(t),(h),(o),(a),(c)) +#define bus_space_read_region_stream_8(t, h, o, a, c) \ + __bs_nonsingle_s(rr,8,(t),(h),(o),(a),(c)) +#endif + + +/* + * Bus write (single) operations. + */ +#define bus_space_write_1(t, h, o, v) __bs_ws(1,(t),(h),(o),(v)) +#define bus_space_write_2(t, h, o, v) __bs_ws(2,(t),(h),(o),(v)) +#define bus_space_write_4(t, h, o, v) __bs_ws(4,(t),(h),(o),(v)) +#define bus_space_write_8(t, h, o, v) __bs_ws(8,(t),(h),(o),(v)) +#ifdef __BUS_SPACE_HAS_STREAM_METHODS +#define bus_space_write_stream_1(t, h, o, v) __bs_ws_s(1,(t),(h),(o),(v)) +#define bus_space_write_stream_2(t, h, o, v) __bs_ws_s(2,(t),(h),(o),(v)) +#define bus_space_write_stream_4(t, h, o, v) __bs_ws_s(4,(t),(h),(o),(v)) +#define bus_space_write_stream_8(t, h, o, v) __bs_ws_s(8,(t),(h),(o),(v)) +#endif + + +/* + * Bus write multiple operations. + */ +#define bus_space_write_multi_1(t, h, o, a, c) \ + __bs_nonsingle(wm,1,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_2(t, h, o, a, c) \ + __bs_nonsingle(wm,2,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_4(t, h, o, a, c) \ + __bs_nonsingle(wm,4,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_8(t, h, o, a, c) \ + __bs_nonsingle(wm,8,(t),(h),(o),(a),(c)) +#ifdef __BUS_SPACE_HAS_STREAM_METHODS +#define bus_space_write_multi_stream_1(t, h, o, a, c) \ + __bs_nonsingle_s(wm,1,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_stream_2(t, h, o, a, c) \ + __bs_nonsingle_s(wm,2,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_stream_4(t, h, o, a, c) \ + __bs_nonsingle_s(wm,4,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_stream_8(t, h, o, a, c) \ + __bs_nonsingle_s(wm,8,(t),(h),(o),(a),(c)) +#endif + + +/* + * Bus write region operations. + */ +#define bus_space_write_region_1(t, h, o, a, c) \ + __bs_nonsingle(wr,1,(t),(h),(o),(a),(c)) +#define bus_space_write_region_2(t, h, o, a, c) \ + __bs_nonsingle(wr,2,(t),(h),(o),(a),(c)) +#define bus_space_write_region_4(t, h, o, a, c) \ + __bs_nonsingle(wr,4,(t),(h),(o),(a),(c)) +#define bus_space_write_region_8(t, h, o, a, c) \ + __bs_nonsingle(wr,8,(t),(h),(o),(a),(c)) +#ifdef __BUS_SPACE_HAS_STREAM_METHODS +#define bus_space_write_region_stream_1(t, h, o, a, c) \ + __bs_nonsingle_s(wr,1,(t),(h),(o),(a),(c)) +#define bus_space_write_region_stream_2(t, h, o, a, c) \ + __bs_nonsingle_s(wr,2,(t),(h),(o),(a),(c)) +#define bus_space_write_region_stream_4(t, h, o, a, c) \ + __bs_nonsingle_s(wr,4,(t),(h),(o),(a),(c)) +#define bus_space_write_region_stream_8(t, h, o, a, c) \ + __bs_nonsingle_s(wr,8,(t),(h),(o),(a),(c)) +#endif + + +/* + * Set multiple operations. + */ +#define bus_space_set_multi_1(t, h, o, v, c) \ + __bs_set(sm,1,(t),(h),(o),(v),(c)) +#define bus_space_set_multi_2(t, h, o, v, c) \ + __bs_set(sm,2,(t),(h),(o),(v),(c)) +#define bus_space_set_multi_4(t, h, o, v, c) \ + __bs_set(sm,4,(t),(h),(o),(v),(c)) +#define bus_space_set_multi_8(t, h, o, v, c) \ + __bs_set(sm,8,(t),(h),(o),(v),(c)) + +/* + * Set region operations. + */ +#define bus_space_set_region_1(t, h, o, v, c) \ + __bs_set(sr,1,(t),(h),(o),(v),(c)) +#define bus_space_set_region_2(t, h, o, v, c) \ + __bs_set(sr,2,(t),(h),(o),(v),(c)) +#define bus_space_set_region_4(t, h, o, v, c) \ + __bs_set(sr,4,(t),(h),(o),(v),(c)) +#define bus_space_set_region_8(t, h, o, v, c) \ + __bs_set(sr,8,(t),(h),(o),(v),(c)) + +/* + * Copy operations. + */ +#define bus_space_copy_region_1(t, h1, o1, h2, o2, c) \ + __bs_copy(1, t, h1, o1, h2, o2, c) +#define bus_space_copy_region_2(t, h1, o1, h2, o2, c) \ + __bs_copy(2, t, h1, o1, h2, o2, c) +#define bus_space_copy_region_4(t, h1, o1, h2, o2, c) \ + __bs_copy(4, t, h1, o1, h2, o2, c) +#define bus_space_copy_region_8(t, h1, o1, h2, o2, c) \ + __bs_copy(8, t, h1, o1, h2, o2, c) + +void +bus_space_copy_1(bus_space_tag_t bst, bus_space_handle_t h1, + bus_space_handle_t h2, bus_size_t o1, bus_size_t o2, bus_size_t c); +void +bus_space_copy_2(bus_space_tag_t bst, bus_space_handle_t h1, + bus_space_handle_t h2, bus_size_t o1, bus_size_t o2, bus_size_t c); +void +bus_space_copy_4(bus_space_tag_t bst, bus_space_handle_t h1, + bus_space_handle_t h2, bus_size_t o1, bus_size_t o2, bus_size_t c); +#define bus_space_copy_8 \ + !!! bus_space_write_raw_multi_8 not implemented !!! + +/* + * Macros to provide prototypes for all the functions used in the + * bus_space structure + */ + +#define bs_map_proto(f) \ +int __bs_c(f,_bs_map) __P((void *t, bus_addr_t addr, \ + bus_size_t size, int cacheable, bus_space_handle_t *bshp)); + +#define bs_unmap_proto(f) \ +void __bs_c(f,_bs_unmap) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t size)); + +#define bs_subregion_proto(f) \ +int __bs_c(f,_bs_subregion) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, bus_size_t size, \ + bus_space_handle_t *nbshp)); + +#define bs_alloc_proto(f) \ +int __bs_c(f,_bs_alloc) __P((void *t, bus_addr_t rstart, \ + bus_addr_t rend, bus_size_t size, bus_size_t align, \ + bus_size_t boundary, int cacheable, bus_addr_t *addrp, \ + bus_space_handle_t *bshp)); + +#define bs_free_proto(f) \ +void __bs_c(f,_bs_free) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t size)); + +#define bs_vaddr_proto(f) \ +void * __bs_c(f,_bs_vaddr) __P((void *t, bus_space_handle_t bsh)); + +#define bs_mmap_proto(f) \ +paddr_t __bs_c(f,_bs_mmap) __P((void *, bus_addr_t, off_t, int, int)); + +#define bs_barrier_proto(f) \ +void __bs_c(f,_bs_barrier) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, bus_size_t len, int flags)); + +#define bs_r_1_proto(f) \ +u_int8_t __bs_c(f,_bs_r_1) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset)); + +#define bs_r_2_proto(f) \ +u_int16_t __bs_c(f,_bs_r_2) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset)); + +#define bs_r_4_proto(f) \ +u_int32_t __bs_c(f,_bs_r_4) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset)); + +#define bs_r_8_proto(f) \ +u_int64_t __bs_c(f,_bs_r_8) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset)); + +#define bs_w_1_proto(f) \ +void __bs_c(f,_bs_w_1) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int8_t value)); + +#define bs_w_2_proto(f) \ +void __bs_c(f,_bs_w_2) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int16_t value)); + +#define bs_w_4_proto(f) \ +void __bs_c(f,_bs_w_4) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int32_t value)); + +#define bs_w_8_proto(f) \ +void __bs_c(f,_bs_w_8) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int64_t value)); + +#define bs_rm_1_proto(f) \ +void __bs_c(f,_bs_rm_1) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int8_t *addr, bus_size_t count)); + +#define bs_rm_2_proto(f) \ +void __bs_c(f,_bs_rm_2) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int16_t *addr, bus_size_t count)); + +#define bs_rm_4_proto(f) \ +void __bs_c(f,_bs_rm_4) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int32_t *addr, bus_size_t count)); + +#define bs_rm_8_proto(f) \ +void __bs_c(f,_bs_rm_8) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int64_t *addr, bus_size_t count)); + +#define bs_wm_1_proto(f) \ +void __bs_c(f,_bs_wm_1) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, const u_int8_t *addr, bus_size_t count)); + +#define bs_wm_2_proto(f) \ +void __bs_c(f,_bs_wm_2) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, const u_int16_t *addr, bus_size_t count)); + +#define bs_wm_4_proto(f) \ +void __bs_c(f,_bs_wm_4) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, const u_int32_t *addr, bus_size_t count)); + +#define bs_wm_8_proto(f) \ +void __bs_c(f,_bs_wm_8) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, const u_int64_t *addr, bus_size_t count)); + +#define bs_rr_1_proto(f) \ +void __bs_c(f, _bs_rr_1) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int8_t *addr, bus_size_t count)); + +#define bs_rr_2_proto(f) \ +void __bs_c(f, _bs_rr_2) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int16_t *addr, bus_size_t count)); + +#define bs_rr_4_proto(f) \ +void __bs_c(f, _bs_rr_4) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int32_t *addr, bus_size_t count)); + +#define bs_rr_8_proto(f) \ +void __bs_c(f, _bs_rr_8) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int64_t *addr, bus_size_t count)); + +#define bs_wr_1_proto(f) \ +void __bs_c(f, _bs_wr_1) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, const u_int8_t *addr, bus_size_t count)); + +#define bs_wr_2_proto(f) \ +void __bs_c(f, _bs_wr_2) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, const u_int16_t *addr, bus_size_t count)); + +#define bs_wr_4_proto(f) \ +void __bs_c(f, _bs_wr_4) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, const u_int32_t *addr, bus_size_t count)); + +#define bs_wr_8_proto(f) \ +void __bs_c(f, _bs_wr_8) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, const u_int64_t *addr, bus_size_t count)); + +#define bs_sm_1_proto(f) \ +void __bs_c(f,_bs_sm_1) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int8_t value, bus_size_t count)); + +#define bs_sm_2_proto(f) \ +void __bs_c(f,_bs_sm_2) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int16_t value, bus_size_t count)); + +#define bs_sm_4_proto(f) \ +void __bs_c(f,_bs_sm_4) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int32_t value, bus_size_t count)); + +#define bs_sm_8_proto(f) \ +void __bs_c(f,_bs_sm_8) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int64_t value, bus_size_t count)); + +#define bs_sr_1_proto(f) \ +void __bs_c(f,_bs_sr_1) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int8_t value, bus_size_t count)); + +#define bs_sr_2_proto(f) \ +void __bs_c(f,_bs_sr_2) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int16_t value, bus_size_t count)); + +#define bs_sr_4_proto(f) \ +void __bs_c(f,_bs_sr_4) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int32_t value, bus_size_t count)); + +#define bs_sr_8_proto(f) \ +void __bs_c(f,_bs_sr_8) __P((void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int64_t value, bus_size_t count)); + +#define bs_c_1_proto(f) \ +void __bs_c(f,_bs_c_1) __P((void *t, bus_space_handle_t bsh1, \ + bus_size_t offset1, bus_space_handle_t bsh2, \ + bus_size_t offset2, bus_size_t count)); + +#define bs_c_2_proto(f) \ +void __bs_c(f,_bs_c_2) __P((void *t, bus_space_handle_t bsh1, \ + bus_size_t offset1, bus_space_handle_t bsh2, \ + bus_size_t offset2, bus_size_t count)); + +#define bs_c_4_proto(f) \ +void __bs_c(f,_bs_c_4) __P((void *t, bus_space_handle_t bsh1, \ + bus_size_t offset1, bus_space_handle_t bsh2, \ + bus_size_t offset2, bus_size_t count)); + +#define bs_c_8_proto(f) \ +void __bs_c(f,_bs_c_8) __P((void *t, bus_space_handle_t bsh1, \ + bus_size_t offset1, bus_space_handle_t bsh2, \ + bus_size_t offset2, bus_size_t count)); + +#define bs_protos(f) \ +bs_map_proto(f); \ +bs_unmap_proto(f); \ +bs_subregion_proto(f); \ +bs_alloc_proto(f); \ +bs_free_proto(f); \ +bs_vaddr_proto(f); \ +bs_mmap_proto(f); \ +bs_barrier_proto(f); \ +bs_r_1_proto(f); \ +bs_r_2_proto(f); \ +bs_r_4_proto(f); \ +bs_r_8_proto(f); \ +bs_w_1_proto(f); \ +bs_w_2_proto(f); \ +bs_w_4_proto(f); \ +bs_w_8_proto(f); \ +bs_rm_1_proto(f); \ +bs_rm_2_proto(f); \ +bs_rm_4_proto(f); \ +bs_rm_8_proto(f); \ +bs_wm_1_proto(f); \ +bs_wm_2_proto(f); \ +bs_wm_4_proto(f); \ +bs_wm_8_proto(f); \ +bs_rr_1_proto(f); \ +bs_rr_2_proto(f); \ +bs_rr_4_proto(f); \ +bs_rr_8_proto(f); \ +bs_wr_1_proto(f); \ +bs_wr_2_proto(f); \ +bs_wr_4_proto(f); \ +bs_wr_8_proto(f); \ +bs_sm_1_proto(f); \ +bs_sm_2_proto(f); \ +bs_sm_4_proto(f); \ +bs_sm_8_proto(f); \ +bs_sr_1_proto(f); \ +bs_sr_2_proto(f); \ +bs_sr_4_proto(f); \ +bs_sr_8_proto(f); \ +bs_c_1_proto(f); \ +bs_c_2_proto(f); \ +bs_c_4_proto(f); \ +bs_c_8_proto(f); + +#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) + +/* Bus Space DMA macros */ + +/* + * Flags used in various bus DMA methods. + */ +#define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */ +#define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */ +#define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */ +#define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */ +#define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */ +#define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */ +#define BUS_DMA_BUS2 0x020 +#define BUS_DMA_BUS3 0x040 +#define BUS_DMA_BUS4 0x080 +#define BUS_DMA_READ 0x100 /* mapping is device -> memory only */ +#define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */ +#define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */ + +/* + * Private flags stored in the DMA map. + */ +#define ARM32_DMAMAP_COHERENT 0x10000 /* no cache flush necessary on sync */ + +/* Forwards needed by prototypes below. */ +struct mbuf; +struct uio; + +/* + * Operations performed by bus_dmamap_sync(). + */ +#define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */ +#define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */ +#define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */ +#define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */ + +typedef struct arm32_bus_dma_tag *bus_dma_tag_t; +typedef struct arm32_bus_dmamap *bus_dmamap_t; + +#define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) + +/* + * bus_dma_segment_t + * + * Describes a single contiguous DMA transaction. Values + * are suitable for programming into DMA registers. + */ +struct arm32_bus_dma_segment { + /* + * PUBLIC MEMBERS: these are used by machine-independent code. + */ + bus_addr_t ds_addr; /* DMA address */ + bus_size_t ds_len; /* length of transfer */ + /* + * PRIVATE MEMBERS: not for use by machine-independent code. + */ + bus_addr_t _ds_vaddr; /* Virtual mapped address + * Used by bus_dmamem_sync() */ +}; +typedef struct arm32_bus_dma_segment bus_dma_segment_t; + +/* + * arm32_dma_range + * + * This structure describes a valid DMA range. + */ +struct arm32_dma_range { + bus_addr_t dr_sysbase; /* system base address */ + bus_addr_t dr_busbase; /* appears here on bus */ + bus_size_t dr_len; /* length of range */ +}; + +/* + * bus_dma_tag_t + * + * A machine-dependent opaque type describing the implementation of + * DMA for a given bus. + */ + +struct arm32_bus_dma_tag { + /* + * DMA range for this tag. If the page doesn't fall within + * one of these ranges, an error is returned. The caller + * may then decide what to do with the transfer. If the + * range pointer is NULL, it is ignored. + */ + struct arm32_dma_range *_ranges; + int _nranges; + + /* + * Opaque cookie for use by back-end. + */ + void *_cookie; + + /* + * DMA mapping methods. + */ + int (*_dmamap_create) __P((bus_dma_tag_t, bus_size_t, int, + bus_size_t, bus_size_t, int, bus_dmamap_t *)); + void (*_dmamap_destroy) __P((bus_dma_tag_t, bus_dmamap_t)); + int (*_dmamap_load) __P((bus_dma_tag_t, bus_dmamap_t, void *, + bus_size_t, struct proc *, int)); + int (*_dmamap_load_mbuf) __P((bus_dma_tag_t, bus_dmamap_t, + struct mbuf *, int)); + int (*_dmamap_load_uio) __P((bus_dma_tag_t, bus_dmamap_t, + struct uio *, int)); + int (*_dmamap_load_raw) __P((bus_dma_tag_t, bus_dmamap_t, + bus_dma_segment_t *, int, bus_size_t, int)); + void (*_dmamap_unload) __P((bus_dma_tag_t, bus_dmamap_t)); + void (*_dmamap_sync) __P((bus_dma_tag_t, bus_dmamap_t, + bus_addr_t, bus_size_t, int)); + + /* + * DMA memory utility functions. + */ + int (*_dmamem_alloc) __P((bus_dma_tag_t, bus_size_t, bus_size_t, + bus_size_t, bus_dma_segment_t *, int, int *, int)); + void (*_dmamem_free) __P((bus_dma_tag_t, + bus_dma_segment_t *, int)); + int (*_dmamem_map) __P((bus_dma_tag_t, bus_dma_segment_t *, + int, size_t, caddr_t *, int)); + void (*_dmamem_unmap) __P((bus_dma_tag_t, caddr_t, size_t)); + paddr_t (*_dmamem_mmap) __P((bus_dma_tag_t, bus_dma_segment_t *, + int, off_t, int, int)); +}; + +#define bus_dmamap_create(t, s, n, m, b, f, p) \ + (*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p)) +#define bus_dmamap_destroy(t, p) \ + (*(t)->_dmamap_destroy)((t), (p)) +#define bus_dmamap_load(t, m, b, s, p, f) \ + (*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f)) +#define bus_dmamap_load_mbuf(t, m, b, f) \ + (*(t)->_dmamap_load_mbuf)((t), (m), (b), (f)) +#define bus_dmamap_load_uio(t, m, u, f) \ + (*(t)->_dmamap_load_uio)((t), (m), (u), (f)) +#define bus_dmamap_load_raw(t, m, sg, n, s, f) \ + (*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f)) +#define bus_dmamap_unload(t, p) \ + (*(t)->_dmamap_unload)((t), (p)) +#define bus_dmamap_sync(t, p, o, l, ops) \ + (void)((t)->_dmamap_sync ? \ + (*(t)->_dmamap_sync)((t), (p), (o), (l), (ops)) : (void)0) + +#define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \ + (*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f)) +#define bus_dmamem_free(t, sg, n) \ + (*(t)->_dmamem_free)((t), (sg), (n)) +#define bus_dmamem_map(t, sg, n, s, k, f) \ + (*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f)) +#define bus_dmamem_unmap(t, k, s) \ + (*(t)->_dmamem_unmap)((t), (k), (s)) +#define bus_dmamem_mmap(t, sg, n, o, p, f) \ + (*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f)) + +/* + * bus_dmamap_t + * + * Describes a DMA mapping. + */ +struct arm32_bus_dmamap { + /* + * PRIVATE MEMBERS: not for use by machine-independent code. + */ + bus_size_t _dm_size; /* largest DMA transfer mappable */ + int _dm_segcnt; /* number of segs this map can map */ + bus_size_t _dm_maxsegsz; /* largest possible segment */ + bus_size_t _dm_boundary; /* don't cross this */ + int _dm_flags; /* misc. flags */ + + void *_dm_origbuf; /* pointer to original buffer */ + int _dm_buftype; /* type of buffer */ + struct proc *_dm_proc; /* proc that owns the mapping */ + + void *_dm_cookie; /* cookie for bus-specific functions */ + + /* + * PUBLIC MEMBERS: these are used by machine-independent code. + */ + bus_size_t dm_mapsize; /* size of the mapping */ + int dm_nsegs; /* # valid segments in mapping */ + bus_dma_segment_t dm_segs[1]; /* segments; variable length */ +}; + +#ifdef _ARM32_BUS_DMA_PRIVATE + +/* _dm_buftype */ +#define ARM32_BUFTYPE_INVALID 0 +#define ARM32_BUFTYPE_LINEAR 1 +#define ARM32_BUFTYPE_MBUF 2 +#define ARM32_BUFTYPE_UIO 3 +#define ARM32_BUFTYPE_RAW 4 + +int arm32_dma_range_intersect(struct arm32_dma_range *, int, + paddr_t pa, psize_t size, paddr_t *pap, psize_t *sizep); + +int _bus_dmamap_create __P((bus_dma_tag_t, bus_size_t, int, bus_size_t, + bus_size_t, int, bus_dmamap_t *)); +void _bus_dmamap_destroy __P((bus_dma_tag_t, bus_dmamap_t)); +int _bus_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, + bus_size_t, struct proc *, int)); +int _bus_dmamap_load_mbuf __P((bus_dma_tag_t, bus_dmamap_t, + struct mbuf *, int)); +int _bus_dmamap_load_uio __P((bus_dma_tag_t, bus_dmamap_t, + struct uio *, int)); +int _bus_dmamap_load_raw __P((bus_dma_tag_t, bus_dmamap_t, + bus_dma_segment_t *, int, bus_size_t, int)); +void _bus_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); +void _bus_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t, + bus_size_t, int)); + +int _bus_dmamem_alloc __P((bus_dma_tag_t tag, bus_size_t size, + bus_size_t alignment, bus_size_t boundary, + bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags)); +void _bus_dmamem_free __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, + int nsegs)); +int _bus_dmamem_map __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, + int nsegs, size_t size, caddr_t *kvap, int flags)); +void _bus_dmamem_unmap __P((bus_dma_tag_t tag, caddr_t kva, + size_t size)); +paddr_t _bus_dmamem_mmap __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, + int nsegs, off_t off, int prot, int flags)); + +int _bus_dmamem_alloc_range __P((bus_dma_tag_t tag, bus_size_t size, + bus_size_t alignment, bus_size_t boundary, + bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags, + vaddr_t low, vaddr_t high)); +#endif /* _ARM32_BUS_DMA_PRIVATE */ +/* These are OpenBSD extensions to the general NetBSD bus interface. */ +#if 0 +void +bus_space_read_raw_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh, + bus_addr_t ba, u_int8_t *dst, bus_size_t size); +void +bus_space_read_raw_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh, + bus_addr_t ba, u_int8_t *dst, bus_size_t size); +#define bus_space_read_raw_multi_8 \ + !!! bus_space_read_raw_multi_8 not implemented !!! + +void +bus_space_write_raw_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh, + bus_addr_t ba, const u_int8_t *src, bus_size_t size); +void +bus_space_write_raw_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh, + bus_addr_t ba, const u_int8_t *src, bus_size_t size); +#define bus_space_write_raw_multi_8 \ + !!! bus_space_write_raw_multi_8 not implemented !!! + +#else +/* BLECH XXXDSR */ +static inline void +bus_space_read_raw_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh, + bus_addr_t ba, u_int8_t *dst, bus_size_t size); +static inline void +bus_space_read_raw_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh, + bus_addr_t ba, u_int8_t *dst, bus_size_t size) +{ + u_int16_t *datap = (u_int16_t *)dst; + while (size > 0) { + *datap =bus_space_read_2(bst, bsh, ba); + datap++; + size -= 2; + } +} +static inline void +bus_space_read_raw_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh, + bus_addr_t ba, u_int8_t *dst, bus_size_t size); +static inline void +bus_space_read_raw_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh, + bus_addr_t ba, u_int8_t *dst, bus_size_t size) +{ + u_int32_t *datap = (u_int32_t *)dst; + while (size > 0) { + *datap =bus_space_read_4(bst, bsh, ba); + datap++; + size -= 4; + } +} + +static inline void +bus_space_write_raw_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh, + bus_addr_t ba, const u_int8_t *src, bus_size_t size); +static inline void +bus_space_write_raw_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh, + bus_addr_t ba, const u_int8_t *src, bus_size_t size) +{ + u_int16_t *datap = (u_int16_t *)src; + while (size > 0) { + bus_space_write_2(bst, bsh, ba, *datap); + datap++; + size -= 2; + } +} +static inline void +bus_space_write_raw_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh, + bus_addr_t ba, const u_int8_t *src, bus_size_t size); +static inline void +bus_space_write_raw_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh, + bus_addr_t ba, const u_int8_t *src, bus_size_t size) +{ + u_int32_t *datap = (u_int32_t *)src; + while (size > 0) { + bus_space_write_4(bst, bsh, ba, *datap); + datap++; + size -= 4; + } +} +#define bus_space_write_raw_multi_8 \ + !!! bus_space_write_raw_multi_8 not implemented !!! + +#endif + +#endif /* _ARM32_BUS_H_ */ diff --git a/sys/arch/arm/include/cdefs.h b/sys/arch/arm/include/cdefs.h new file mode 100644 index 00000000000..ddb29ed5939 --- /dev/null +++ b/sys/arch/arm/include/cdefs.h @@ -0,0 +1,13 @@ +/* $OpenBSD: cdefs.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: cdefs.h,v 1.1 2001/01/10 19:02:05 bjh21 Exp $ */ + +#ifndef _MACHINE_CDEFS_H_ +#define _MACHINE_CDEFS_H_ + +#define __weak_alias(alias,sym) \ + __asm__(".weak " __STRING(alias) " ; " __STRING(alias) " = " __STRING(sym)) +#define __warn_references(sym,msg) \ + __asm__(".section .gnu.warning." __STRING(sym) " ; .ascii \"" msg "\" ; .text") + + +#endif /* !_MACHINE_CDEFS_H_ */ diff --git a/sys/arch/arm/include/conf.h b/sys/arch/arm/include/conf.h new file mode 100644 index 00000000000..0f7dac4128a --- /dev/null +++ b/sys/arch/arm/include/conf.h @@ -0,0 +1,134 @@ +/* $OpenBSD: conf.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: conf.h,v 1.7 2002/04/19 01:04:39 wiz Exp $ */ + +/* + * Copyright (c) 1997 Mark Brinicombe. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Mark Brinicombe + * for the NetBSD Project. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * RiscBSD kernel project + * + * conf.h + * + * Prototypes for device driver functions + */ + +#ifndef _ARM_CONF_H +#define _ARM_CONF_H + + +#include <sys/conf.h> + +#define mmread mmrw +#define mmwrite mmrw +cdev_decl(mm); + +bdev_decl(wd); +cdev_decl(wd); +bdev_decl(sw); +cdev_decl(sw); +bdev_decl(fd); +cdev_decl(fd); +bdev_decl(rd); +cdev_decl(rd); +bdev_decl(raid); +cdev_decl(raid); + +/* Character device declarations */ + +/* open, close, read, write, ioctl, tty, mmap -- XXX should be a tty */ +#define cdev_physcon_init(c,n) cdev__ttym_init(c,n,0) + +/* open, close, ioctl */ +#define cdev_beep_init(c,n) cdev__oci_init(c,n) + +/* open, close, read, ioctl */ +#define cdev_kbd_init(c,n) cdev__ocri_init(c,n) + +/* open, close, ioctl, mmap */ +#define cdev_vidcvid_init(c,n) { \ + dev_init(c,n,open), dev_init(c,n,close), dev_noimpl(read,enodev), \ + dev_noimpl(write,enodev), dev_init(c,n,ioctl), \ + dev_noimpl(stop,enodev), 0, seltrue, dev_init(c,n,mmap), 0 } + +/* open, close, read, write, ioctl */ +#define cdev_iic_init(c,n) cdev__ocrwi_init(c,n) +#define cdev_rtc_init(c,n) cdev__ocrwi_init(c,n) + +/* open, close, read, ioctl */ +#define cdev_prof_init(c,n) cdev__ocri_init(c,n) + +cdev_decl(physcon); +cdev_decl(vidcconsole); +cdev_decl(biconsdev); +cdev_decl(com); +cdev_decl(lpt); +cdev_decl(qms); +cdev_decl(opms); +cdev_decl(beep); +cdev_decl(kbd); +cdev_decl(iic); +cdev_decl(rtc); +cdev_decl(fcom); +cdev_decl(pc); +cdev_decl(ofcons_); +cdev_decl(ofd); +cdev_decl(ofrtc); +cdev_decl(sacom); +cdev_decl(scr); +cdev_decl(prof); +#define ofromread ofromrw +#define ofromwrite ofromrw +cdev_decl(ofrom); +cdev_decl(joy); +cdev_decl(usb); +cdev_decl(uhid); +cdev_decl(ugen); +cdev_decl(ulpt); +cdev_decl(ucom); +cdev_decl(urio); +cdev_decl(uscanner); +cdev_decl(vc_nb_); +cdev_decl(wsdisplay); +cdev_decl(wsfont); +cdev_decl(wskbd); +cdev_decl(wsmouse); +cdev_decl(wsmux); +cdev_decl(scsibus); +cdev_decl(openfirm); +cdev_decl(pci); +cdev_decl(agp); +cdev_decl(iop); +cdev_decl(ld); +cdev_decl(mlx); +cdev_decl(mly); +cdev_decl(plcom); + +#endif /* _ARM_CONF_H_ */ diff --git a/sys/arch/arm/include/cpu.h b/sys/arch/arm/include/cpu.h new file mode 100644 index 00000000000..22b999ed8fb --- /dev/null +++ b/sys/arch/arm/include/cpu.h @@ -0,0 +1,302 @@ +/* $OpenBSD: cpu.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: cpu.h,v 1.34 2003/06/23 11:01:08 martin Exp $ */ + +/* + * Copyright (c) 1994-1996 Mark Brinicombe. + * Copyright (c) 1994 Brini. + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * RiscBSD kernel project + * + * cpu.h + * + * CPU specific symbols + * + * Created : 18/09/94 + * + * Based on kate/katelib/arm6.h + */ + +#ifndef _ARM_CPU_H_ +#define _ARM_CPU_H_ + +/* + * User-visible definitions + */ + +/* CTL_MACHDEP definitions. */ +#define CPU_DEBUG 1 /* int: misc kernel debug control */ +#define CPU_BOOTED_DEVICE 2 /* string: device we booted from */ +#define CPU_BOOTED_KERNEL 3 /* string: kernel we booted */ +#define CPU_CONSDEV 4 /* struct: dev_t of our console */ +#define CPU_POWERSAVE 5 /* int: use CPU powersave mode */ +#define CPU_MAXID 6 /* number of valid machdep ids */ + +#define CTL_MACHDEP_NAMES { \ + { 0, 0 }, \ + { "debug", CTLTYPE_INT }, \ + { "booted_device", CTLTYPE_STRING }, \ + { "booted_kernel", CTLTYPE_STRING }, \ + { "console_device", CTLTYPE_STRUCT }, \ + { "powersave", CTLTYPE_INT }, \ +} + +#ifdef _KERNEL + +/* + * Kernel-only definitions + */ + +#include <arm/cpuconf.h> + +#include <machine/intr.h> +#ifndef _LOCORE +#if 0 +#include <sys/user.h> +#endif +#include <machine/frame.h> +#include <machine/pcb.h> +#endif /* !_LOCORE */ + +#include <arm/armreg.h> + +#ifndef _LOCORE +/* 1 == use cpu_sleep(), 0 == don't */ +extern int cpu_do_powersave; +#endif + +#ifdef __PROG32 +#ifdef _LOCORE +#define IRQdisable \ + stmfd sp!, {r0} ; \ + mrs r0, cpsr ; \ + orr r0, r0, #(I32_bit) ; \ + msr cpsr_c, r0 ; \ + ldmfd sp!, {r0} + +#define IRQenable \ + stmfd sp!, {r0} ; \ + mrs r0, cpsr ; \ + bic r0, r0, #(I32_bit) ; \ + msr cpsr_c, r0 ; \ + ldmfd sp!, {r0} + +#else +#define IRQdisable __set_cpsr_c(I32_bit, I32_bit); +#define IRQenable __set_cpsr_c(I32_bit, 0); +#endif /* _LOCORE */ +#endif + +#ifndef _LOCORE + +/* All the CLKF_* macros take a struct clockframe * as an argument. */ + +/* + * CLKF_USERMODE: Return TRUE/FALSE (1/0) depending on whether the + * frame came from USR mode or not. + */ +#ifdef __PROG32 +#define CLKF_USERMODE(frame) ((frame->if_spsr & PSR_MODE) == PSR_USR32_MODE) +#else +#define CLKF_USERMODE(frame) ((frame->if_r15 & R15_MODE) == R15_MODE_USR) +#endif + +/* + * CLKF_BASEPRI: True if we were at spl0 before the interrupt. + * + * This is hard-wired to 0 on the ARM, since spllowersoftclock() might + * not actually be able to unblock the interrupt, which would cause us + * to run the softclock interrupts with hardclock blocked. + */ +#define CLKF_BASEPRI(frame) 0 + +/* + * CLKF_INTR: True if we took the interrupt from inside another + * interrupt handler. + */ +extern int current_intr_depth; +#ifdef __PROG32 +/* Hack to treat FPE time as interrupt time so we can measure it */ +#define CLKF_INTR(frame) \ + ((current_intr_depth > 1) || \ + (frame->if_spsr & PSR_MODE) == PSR_UND32_MODE) +#else +#define CLKF_INTR(frame) (current_intr_depth > 1) +#endif + +/* + * CLKF_PC: Extract the program counter from a clockframe + */ +#ifdef __PROG32 +#define CLKF_PC(frame) (frame->if_pc) +#else +#define CLKF_PC(frame) (frame->if_r15 & R15_PC) +#endif + +/* + * PROC_PC: Find out the program counter for the given process. + */ +#ifdef __PROG32 +#define PROC_PC(p) ((p)->p_addr->u_pcb.pcb_tf->tf_pc) +#else +#define PROC_PC(p) ((p)->p_addr->u_pcb.pcb_tf->tf_r15 & R15_PC) +#endif + +/* The address of the vector page. */ +extern vaddr_t vector_page; +#ifdef __PROG32 +void arm32_vector_init(vaddr_t, int); + +#define ARM_VEC_RESET (1 << 0) +#define ARM_VEC_UNDEFINED (1 << 1) +#define ARM_VEC_SWI (1 << 2) +#define ARM_VEC_PREFETCH_ABORT (1 << 3) +#define ARM_VEC_DATA_ABORT (1 << 4) +#define ARM_VEC_ADDRESS_EXCEPTION (1 << 5) +#define ARM_VEC_IRQ (1 << 6) +#define ARM_VEC_FIQ (1 << 7) + +#define ARM_NVEC 8 +#define ARM_VEC_ALL 0xffffffff +#endif + +/* + * Per-CPU information. For now we assume one CPU. + */ + +#include <sys/device.h> +/* +#include <sys/sched.h> +*/ +struct cpu_info { +#if 0 + struct schedstate_percpu ci_schedstate; /* scheduler state */ +#endif +#if defined(DIAGNOSTIC) || defined(LOCKDEBUG) + u_long ci_spin_locks; /* # of spin locks held */ + u_long ci_simple_locks; /* # of simple locks held */ +#endif + struct device *ci_dev; /* Device corresponding to this CPU */ + u_int32_t ci_arm_cpuid; /* aggregate CPU id */ + u_int32_t ci_arm_cputype; /* CPU type */ + u_int32_t ci_arm_cpurev; /* CPU revision */ + u_int32_t ci_ctrl; /* The CPU control register */ + struct evcnt ci_arm700bugcount; +#ifdef MULTIPROCESSOR + MP_CPU_INFO_MEMBERS +#endif +}; + +#ifndef MULTIPROCESSOR +extern struct cpu_info cpu_info_store; +#define curcpu() (&cpu_info_store) +#define cpu_number() 0 +#endif + +#ifdef __PROG32 +void cpu_proc_fork(struct proc *, struct proc *); +#else +#define cpu_proc_fork(p1, p2) +#endif + +/* + * Scheduling glue + */ + +extern int astpending; +#define setsoftast() (astpending = 1) + +/* + * Notify the current process (p) that it has a signal pending, + * process as soon as possible. + */ + +#define signotify(p) setsoftast() + +#define cpu_wait(p) /* nothing */ + +/* + * Preempt the current process if in interrupt from user mode, + * or after the current trap/syscall if in system mode. + */ +extern int want_resched; /* resched() was called */ +#define need_resched(ci) (want_resched = 1, setsoftast()) + +/* + * Give a profiling tick to the current process when the user profiling + * buffer pages are invalid. On the i386, request an ast to send us + * through trap(), marking the proc as needing a profiling tick. + */ +#define need_proftick(p) ((p)->p_flag |= P_OWEUPC, setsoftast()) + +#ifndef acorn26 +/* + * cpu device glue (belongs in cpuvar.h) + */ + +struct device; +void cpu_attach __P((struct device *)); +int cpu_alloc_idlepcb __P((struct cpu_info *)); +#endif + + +/* + * Random cruft + */ + +/* locore.S */ +void atomic_set_bit __P((u_int *address, u_int setmask)); +void atomic_clear_bit __P((u_int *address, u_int clearmask)); + +/* cpuswitch.S */ +struct pcb; +void savectx __P((struct pcb *pcb)); + +/* ast.c */ +void userret __P((register struct proc *p)); + +/* machdep.h */ +void bootsync __P((void)); + +/* fault.c */ +int badaddr_read __P((void *, size_t, void *)); + +/* syscall.c */ +void swi_handler __P((trapframe_t *)); + +#endif /* !_LOCORE */ + +#endif /* _KERNEL */ + +#endif /* !_ARM_CPU_H_ */ + +/* End of cpu.h */ diff --git a/sys/arch/arm/include/cpuconf.h b/sys/arch/arm/include/cpuconf.h new file mode 100644 index 00000000000..8ccd375e18e --- /dev/null +++ b/sys/arch/arm/include/cpuconf.h @@ -0,0 +1,177 @@ +/* $OpenBSD: cpuconf.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: cpuconf.h,v 1.7 2003/05/23 00:57:24 ichiro Exp $ */ + +/* + * Copyright (c) 2002 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Jason R. Thorpe for Wasabi Systems, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ARM_CPUCONF_H_ +#define _ARM_CPUCONF_H_ + +#if defined(_KERNEL_OPT) +#include "opt_cputypes.h" +#endif /* _KERNEL_OPT */ + +/* + * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF + * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm/pmap.h> FOR THE CPU TYPE + * YOU ARE ADDING SUPPORT FOR. + */ + +/* + * Step 1: Count the number of CPU types configured into the kernel. + */ +#if defined(_KERNEL_OPT) +#define CPU_NTYPES (defined(CPU_ARM2) + defined(CPU_ARM250) + \ + defined(CPU_ARM3) + \ + defined(CPU_ARM6) + defined(CPU_ARM7) + \ + defined(CPU_ARM7TDMI) + \ + defined(CPU_ARM8) + defined(CPU_ARM9) + \ + defined(CPU_ARM10) + \ + defined(CPU_SA110) + defined(CPU_SA1100) + \ + defined(CPU_SA1110) + \ + defined(CPU_IXP12X0) + \ + defined(CPU_XSCALE_80200) + \ + defined(CPU_XSCALE_80321) + \ + defined(CPU_XSCALE_PXA2X0) + \ + defined(CPU_XSCALE_IXP425)) +#else +#define CPU_NTYPES 2 +#endif /* _KERNEL_OPT */ + +/* + * Step 2: Determine which ARM architecture versions are configured. + */ +#if !defined(_KERNEL_OPT) || \ + (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) +#define ARM_ARCH_2 1 +#else +#define ARM_ARCH_2 0 +#endif + +#if !defined(_KERNEL_OPT) || \ + (defined(CPU_ARM6) || defined(CPU_ARM7)) +#define ARM_ARCH_3 1 +#else +#define ARM_ARCH_3 0 +#endif + +#if !defined(_KERNEL_OPT) || \ + (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ + defined(CPU_ARM10) || defined(CPU_SA110) || defined(CPU_SA1100) || \ + defined(CPU_SA1110) || defined(CPU_IXP12X0) || defined(CPU_XSCALE_IXP425)) +#define ARM_ARCH_4 1 +#else +#define ARM_ARCH_4 0 +#endif + +#if !defined(_KERNEL_OPT) || \ + (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ + defined(CPU_XSCALE_PXA2X0)) +#define ARM_ARCH_5 1 +#else +#define ARM_ARCH_5 0 +#endif + +#define ARM_NARCH (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + ARM_ARCH_5) +#if ARM_NARCH == 0 +#error ARM_NARCH is 0 +#endif + +/* + * Step 3: Define which MMU classes are configured: + * + * ARM_MMU_MEMC Prehistoric, external memory controller + * and MMU for ARMv2 CPUs. + * + * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARM6. + * + * ARM_MMU_SA1 StrongARM SA-1 MMU. Compatible with generic + * ARM MMU, but has no write-through cache mode. + * + * ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM + * MMU, but also has several extensions which + * require different PTE layout to use. + */ +#if !defined(_KERNEL_OPT) || \ + (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) +#define ARM_MMU_MEMC 1 +#else +#define ARM_MMU_MEMC 0 +#endif + +#if !defined(_KERNEL_OPT) || \ + (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \ + defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM10)) +#define ARM_MMU_GENERIC 1 +#else +#define ARM_MMU_GENERIC 0 +#endif + +#if !defined(_KERNEL_OPT) || \ + (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\ + defined(CPU_IXP12X0)) +#define ARM_MMU_SA1 1 +#else +#define ARM_MMU_SA1 0 +#endif + +#if !defined(_KERNEL_OPT) || \ + (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ + defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)) +#define ARM_MMU_XSCALE 1 +#else +#define ARM_MMU_XSCALE 0 +#endif + +#define ARM_NMMUS (ARM_MMU_MEMC + ARM_MMU_GENERIC + \ + ARM_MMU_SA1 + ARM_MMU_XSCALE) +#if ARM_NMMUS == 0 +#error ARM_NMMUS is 0 +#endif + +/* + * Step 4: Define features that may be present on a subset of CPUs + * + * ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321 + */ + +#if !defined(_KERNEL_OPT) || \ + (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321)) +#define ARM_XSCALE_PMU 1 +#else +#define ARM_XSCALE_PMU 0 +#endif + +#endif /* _ARM_CPUCONF_H_ */ diff --git a/sys/arch/arm/include/cpufunc.h b/sys/arch/arm/include/cpufunc.h new file mode 100644 index 00000000000..f732dfe03c2 --- /dev/null +++ b/sys/arch/arm/include/cpufunc.h @@ -0,0 +1,524 @@ +/* $OpenBSD: cpufunc.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ + +/* + * Copyright (c) 1997 Mark Brinicombe. + * Copyright (c) 1997 Causality Limited + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Causality Limited. + * 4. The name of Causality Limited may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * RiscBSD kernel project + * + * cpufunc.h + * + * Prototypes for cpu, mmu and tlb related functions. + */ + +#ifndef _ARM32_CPUFUNC_H_ +#define _ARM32_CPUFUNC_H_ + +#ifdef _KERNEL + +#include <sys/types.h> +#include <arm/cpuconf.h> + +struct cpu_functions { + + /* CPU functions */ + + u_int (*cf_id) __P((void)); + void (*cf_cpwait) __P((void)); + + /* MMU functions */ + + u_int (*cf_control) __P((u_int bic, u_int eor)); + void (*cf_domains) __P((u_int domains)); + void (*cf_setttb) __P((u_int ttb)); + u_int (*cf_faultstatus) __P((void)); + u_int (*cf_faultaddress) __P((void)); + + /* TLB functions */ + + void (*cf_tlb_flushID) __P((void)); + void (*cf_tlb_flushID_SE) __P((u_int va)); + void (*cf_tlb_flushI) __P((void)); + void (*cf_tlb_flushI_SE) __P((u_int va)); + void (*cf_tlb_flushD) __P((void)); + void (*cf_tlb_flushD_SE) __P((u_int va)); + + /* + * Cache operations: + * + * We define the following primitives: + * + * icache_sync_all Synchronize I-cache + * icache_sync_range Synchronize I-cache range + * + * dcache_wbinv_all Write-back and Invalidate D-cache + * dcache_wbinv_range Write-back and Invalidate D-cache range + * dcache_inv_range Invalidate D-cache range + * dcache_wb_range Write-back D-cache range + * + * idcache_wbinv_all Write-back and Invalidate D-cache, + * Invalidate I-cache + * idcache_wbinv_range Write-back and Invalidate D-cache, + * Invalidate I-cache range + * + * Note that the ARM term for "write-back" is "clean". We use + * the term "write-back" since it's a more common way to describe + * the operation. + * + * There are some rules that must be followed: + * + * I-cache Synch (all or range): + * The goal is to synchronize the instruction stream, + * so you may beed to write-back dirty D-cache blocks + * first. If a range is requested, and you can't + * synchronize just a range, you have to hit the whole + * thing. + * + * D-cache Write-Back and Invalidate range: + * If you can't WB-Inv a range, you must WB-Inv the + * entire D-cache. + * + * D-cache Invalidate: + * If you can't Inv the D-cache, you must Write-Back + * and Invalidate. Code that uses this operation + * MUST NOT assume that the D-cache will not be written + * back to memory. + * + * D-cache Write-Back: + * If you can't Write-back without doing an Inv, + * that's fine. Then treat this as a WB-Inv. + * Skipping the invalidate is merely an optimization. + * + * All operations: + * Valid virtual addresses must be passed to each + * cache operation. + */ + void (*cf_icache_sync_all) __P((void)); + void (*cf_icache_sync_range) __P((vaddr_t, vsize_t)); + + void (*cf_dcache_wbinv_all) __P((void)); + void (*cf_dcache_wbinv_range) __P((vaddr_t, vsize_t)); + void (*cf_dcache_inv_range) __P((vaddr_t, vsize_t)); + void (*cf_dcache_wb_range) __P((vaddr_t, vsize_t)); + + void (*cf_idcache_wbinv_all) __P((void)); + void (*cf_idcache_wbinv_range) __P((vaddr_t, vsize_t)); + + /* Other functions */ + + void (*cf_flush_prefetchbuf) __P((void)); + void (*cf_drain_writebuf) __P((void)); + void (*cf_flush_brnchtgt_C) __P((void)); + void (*cf_flush_brnchtgt_E) __P((u_int va)); + + void (*cf_sleep) __P((int mode)); + + /* Soft functions */ + + int (*cf_dataabt_fixup) __P((void *arg)); + int (*cf_prefetchabt_fixup) __P((void *arg)); + + void (*cf_context_switch) __P((void)); + + void (*cf_setup) __P((char *string)); +}; + +extern struct cpu_functions cpufuncs; +extern u_int cputype; + +#define cpu_id() cpufuncs.cf_id() +#define cpu_cpwait() cpufuncs.cf_cpwait() + +#define cpu_control(c, e) cpufuncs.cf_control(c, e) +#define cpu_domains(d) cpufuncs.cf_domains(d) +#define cpu_setttb(t) cpufuncs.cf_setttb(t) +#define cpu_faultstatus() cpufuncs.cf_faultstatus() +#define cpu_faultaddress() cpufuncs.cf_faultaddress() + +#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() +#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) +#define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() +#define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) +#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() +#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) + +#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() +#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) + +#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() +#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) +#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) +#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) + +#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() +#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) + +#define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() +#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() +#define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C() +#define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e) + +#define cpu_sleep(m) cpufuncs.cf_sleep(m) + +#define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a) +#define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a) +#define ABORT_FIXUP_OK 0 /* fixup succeeded */ +#define ABORT_FIXUP_FAILED 1 /* fixup failed */ +#define ABORT_FIXUP_RETURN 2 /* abort handler should return */ + +#define cpu_setup(a) cpufuncs.cf_setup(a) + +int set_cpufuncs __P((void)); +#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ +#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ + +void cpufunc_nullop __P((void)); +int cpufunc_null_fixup __P((void *)); +int early_abort_fixup __P((void *)); +int late_abort_fixup __P((void *)); +u_int cpufunc_id __P((void)); +u_int cpufunc_control __P((u_int clear, u_int bic)); +void cpufunc_domains __P((u_int domains)); +u_int cpufunc_faultstatus __P((void)); +u_int cpufunc_faultaddress __P((void)); + +#ifdef CPU_ARM3 +u_int arm3_control __P((u_int clear, u_int bic)); +void arm3_cache_flush __P((void)); +#endif /* CPU_ARM3 */ + +#if defined(CPU_ARM6) || defined(CPU_ARM7) +void arm67_setttb __P((u_int ttb)); +void arm67_tlb_flush __P((void)); +void arm67_tlb_purge __P((u_int va)); +void arm67_cache_flush __P((void)); +void arm67_context_switch __P((void)); +#endif /* CPU_ARM6 || CPU_ARM7 */ + +#ifdef CPU_ARM6 +void arm6_setup __P((char *string)); +#endif /* CPU_ARM6 */ + +#ifdef CPU_ARM7 +void arm7_setup __P((char *string)); +#endif /* CPU_ARM7 */ + +#ifdef CPU_ARM7TDMI +int arm7_dataabt_fixup __P((void *arg)); +void arm7tdmi_setup __P((char *string)); +void arm7tdmi_setttb __P((u_int ttb)); +void arm7tdmi_tlb_flushID __P((void)); +void arm7tdmi_tlb_flushID_SE __P((u_int va)); +void arm7tdmi_cache_flushID __P((void)); +void arm7tdmi_context_switch __P((void)); +#endif /* CPU_ARM7TDMI */ + +#ifdef CPU_ARM8 +void arm8_setttb __P((u_int ttb)); +void arm8_tlb_flushID __P((void)); +void arm8_tlb_flushID_SE __P((u_int va)); +void arm8_cache_flushID __P((void)); +void arm8_cache_flushID_E __P((u_int entry)); +void arm8_cache_cleanID __P((void)); +void arm8_cache_cleanID_E __P((u_int entry)); +void arm8_cache_purgeID __P((void)); +void arm8_cache_purgeID_E __P((u_int entry)); + +void arm8_cache_syncI __P((void)); +void arm8_cache_cleanID_rng __P((vaddr_t start, vsize_t end)); +void arm8_cache_cleanD_rng __P((vaddr_t start, vsize_t end)); +void arm8_cache_purgeID_rng __P((vaddr_t start, vsize_t end)); +void arm8_cache_purgeD_rng __P((vaddr_t start, vsize_t end)); +void arm8_cache_syncI_rng __P((vaddr_t start, vsize_t end)); + +void arm8_context_switch __P((void)); + +void arm8_setup __P((char *string)); + +u_int arm8_clock_config __P((u_int, u_int)); +#endif + +#ifdef CPU_SA110 +void sa110_setup __P((char *string)); +void sa110_context_switch __P((void)); +#endif /* CPU_SA110 */ + +#if defined(CPU_SA1100) || defined(CPU_SA1110) +void sa11x0_drain_readbuf __P((void)); + +void sa11x0_context_switch __P((void)); +void sa11x0_cpu_sleep __P((int mode)); + +void sa11x0_setup __P((char *string)); +#endif + +#if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) +void sa1_setttb __P((u_int ttb)); + +void sa1_tlb_flushID_SE __P((u_int va)); + +void sa1_cache_flushID __P((void)); +void sa1_cache_flushI __P((void)); +void sa1_cache_flushD __P((void)); +void sa1_cache_flushD_SE __P((u_int entry)); + +void sa1_cache_cleanID __P((void)); +void sa1_cache_cleanD __P((void)); +void sa1_cache_cleanD_E __P((u_int entry)); + +void sa1_cache_purgeID __P((void)); +void sa1_cache_purgeID_E __P((u_int entry)); +void sa1_cache_purgeD __P((void)); +void sa1_cache_purgeD_E __P((u_int entry)); + +void sa1_cache_syncI __P((void)); +void sa1_cache_cleanID_rng __P((vaddr_t start, vsize_t end)); +void sa1_cache_cleanD_rng __P((vaddr_t start, vsize_t end)); +void sa1_cache_purgeID_rng __P((vaddr_t start, vsize_t end)); +void sa1_cache_purgeD_rng __P((vaddr_t start, vsize_t end)); +void sa1_cache_syncI_rng __P((vaddr_t start, vsize_t end)); + +#endif + +#ifdef CPU_ARM9 +void arm9_setttb __P((u_int)); + +void arm9_tlb_flushID_SE __P((u_int va)); + +void arm9_cache_flushID __P((void)); +void arm9_cache_flushID_SE __P((u_int)); +void arm9_cache_flushI __P((void)); +void arm9_cache_flushI_SE __P((u_int)); +void arm9_cache_flushD __P((void)); +void arm9_cache_flushD_SE __P((u_int)); + +void arm9_cache_cleanID __P((void)); + +void arm9_cache_syncI __P((void)); +void arm9_cache_flushID_rng __P((vaddr_t, vsize_t)); +void arm9_cache_flushD_rng __P((vaddr_t, vsize_t)); +void arm9_cache_syncI_rng __P((vaddr_t, vsize_t)); + +void arm9_context_switch __P((void)); + +void arm9_setup __P((char *string)); +#endif + +#ifdef CPU_ARM10 +void arm10_setttb __P((u_int)); + +void arm10_tlb_flushID_SE __P((u_int)); +void arm10_tlb_flushI_SE __P((u_int)); + +void arm10_icache_sync_all __P((void)); +void arm10_icache_sync_range __P((vaddr_t, vsize_t)); + +void arm10_dcache_wbinv_all __P((void)); +void arm10_dcache_wbinv_range __P((vaddr_t, vsize_t)); +void arm10_dcache_inv_range __P((vaddr_t, vsize_t)); +void arm10_dcache_wb_range __P((vaddr_t, vsize_t)); + +void arm10_idcache_wbinv_all __P((void)); +void arm10_idcache_wbinv_range __P((vaddr_t, vsize_t)); + +void arm10_context_switch __P((void)); + +void arm10_setup __P((char *string)); + +extern unsigned arm10_dcache_sets_max; +extern unsigned arm10_dcache_sets_inc; +extern unsigned arm10_dcache_index_max; +extern unsigned arm10_dcache_index_inc; +#endif + +#if defined(CPU_ARM9) || defined(CPU_ARM10) || defined(CPU_SA110) || \ + defined(CPU_SA1100) || defined(CPU_SA1110) || \ + defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ + defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) + +void armv4_tlb_flushID __P((void)); +void armv4_tlb_flushI __P((void)); +void armv4_tlb_flushD __P((void)); +void armv4_tlb_flushD_SE __P((u_int va)); + +void armv4_drain_writebuf __P((void)); +#endif + +#if defined(CPU_IXP12X0) +void ixp12x0_drain_readbuf __P((void)); +void ixp12x0_context_switch __P((void)); +void ixp12x0_setup __P((char *string)); +#endif + +#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ + defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ + (ARM_MMU_XSCALE == 1) +void xscale_cpwait __P((void)); + +void xscale_cpu_sleep __P((int mode)); + +u_int xscale_control __P((u_int clear, u_int bic)); + +void xscale_setttb __P((u_int ttb)); + +void xscale_tlb_flushID_SE __P((u_int va)); + +void xscale_cache_flushID __P((void)); +void xscale_cache_flushI __P((void)); +void xscale_cache_flushD __P((void)); +void xscale_cache_flushD_SE __P((u_int entry)); + +void xscale_cache_cleanID __P((void)); +void xscale_cache_cleanD __P((void)); +void xscale_cache_cleanD_E __P((u_int entry)); + +void xscale_cache_clean_minidata __P((void)); + +void xscale_cache_purgeID __P((void)); +void xscale_cache_purgeID_E __P((u_int entry)); +void xscale_cache_purgeD __P((void)); +void xscale_cache_purgeD_E __P((u_int entry)); + +void xscale_cache_syncI __P((void)); +void xscale_cache_cleanID_rng __P((vaddr_t start, vsize_t end)); +void xscale_cache_cleanD_rng __P((vaddr_t start, vsize_t end)); +void xscale_cache_purgeID_rng __P((vaddr_t start, vsize_t end)); +void xscale_cache_purgeD_rng __P((vaddr_t start, vsize_t end)); +void xscale_cache_syncI_rng __P((vaddr_t start, vsize_t end)); +void xscale_cache_flushD_rng __P((vaddr_t start, vsize_t end)); + +void xscale_context_switch __P((void)); + +void xscale_setup __P((char *string)); +#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */ + +#define tlb_flush cpu_tlb_flushID +#define setttb cpu_setttb +#define drain_writebuf cpu_drain_writebuf + +/* + * Macros for manipulating CPU interrupts + */ +#ifdef __PROG32 +static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__)); + +static __inline u_int32_t +__set_cpsr_c(u_int bic, u_int eor) +{ + u_int32_t tmp, ret; + + __asm __volatile( + "mrs %0, cpsr\n" /* Get the CPSR */ + "bic %1, %0, %2\n" /* Clear bits */ + "eor %1, %1, %3\n" /* XOR bits */ + "msr cpsr_c, %1\n" /* Set the control field of CPSR */ + : "=&r" (ret), "=&r" (tmp) + : "r" (bic), "r" (eor)); + + return ret; +} + +#define disable_interrupts(mask) \ + (__set_cpsr_c((mask) & (I32_bit | F32_bit), \ + (mask) & (I32_bit | F32_bit))) + +#define enable_interrupts(mask) \ + (__set_cpsr_c((mask) & (I32_bit | F32_bit), 0)) + +#define restore_interrupts(old_cpsr) \ + (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) +#else /* ! __PROG32 */ +#define disable_interrupts(mask) \ + (set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), \ + (mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE))) + +#define enable_interrupts(mask) \ + (set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), 0)) + +#define restore_interrupts(old_r15) \ + (set_r15((R15_IRQ_DISABLE | R15_FIQ_DISABLE), \ + (old_r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE))) +#endif /* __PROG32 */ + +#ifdef __PROG32 +/* Functions to manipulate the CPSR. */ +u_int SetCPSR(u_int bic, u_int eor); +u_int GetCPSR(void); +#else +/* Functions to manipulate the processor control bits in r15. */ +u_int set_r15(u_int bic, u_int eor); +u_int get_r15(void); +#endif /* __PROG32 */ + +/* + * Functions to manipulate cpu r13 + * (in arm/arm/setstack.S) + */ + +void set_stackptr __P((u_int mode, u_int address)); +u_int get_stackptr __P((u_int mode)); + +/* + * Miscellany + */ + +int get_pc_str_offset __P((void)); + +/* + * CPU functions from locore.S + */ + +void cpu_reset __P((void)) __attribute__((__noreturn__)); + +/* + * Cache info variables. + */ + +/* PRIMARY CACHE VARIABLES */ +extern int arm_picache_size; +extern int arm_picache_line_size; +extern int arm_picache_ways; + +extern int arm_pdcache_size; /* and unified */ +extern int arm_pdcache_line_size; +extern int arm_pdcache_ways; + +extern int arm_pcache_type; +extern int arm_pcache_unified; + +extern int arm_dcache_align; +extern int arm_dcache_align_mask; + +#endif /* _KERNEL */ +#endif /* _ARM32_CPUFUNC_H_ */ + +/* End of cpufunc.h */ diff --git a/sys/arch/arm/include/db_machdep.h b/sys/arch/arm/include/db_machdep.h new file mode 100644 index 00000000000..073bd60d296 --- /dev/null +++ b/sys/arch/arm/include/db_machdep.h @@ -0,0 +1,117 @@ +/* $OpenBSD: db_machdep.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: db_machdep.h,v 1.5 2001/11/22 18:00:00 thorpej Exp $ */ + +/* + * Copyright (c) 1996 Scott K Stevens + * + * Mach Operating System + * Copyright (c) 1991,1990 Carnegie Mellon University + * All Rights Reserved. + * + * Permission to use, copy, modify and distribute this software and its + * documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR + * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie Mellon + * the rights to redistribute these changes. + */ + +#ifndef _ARM_DB_MACHDEP_H_ +#define _ARM_DB_MACHDEP_H_ + +/* + * Machine-dependent defines for new kernel debugger. + */ + +#include <uvm/uvm_extern.h> +#include <arm/armreg.h> +#include <machine/frame.h> +#include <machine/trap.h> + +/* end of mangling */ + +typedef vaddr_t db_addr_t; /* address - unsigned */ +typedef long db_expr_t; /* expression - signed */ + +typedef trapframe_t db_regs_t; + +extern db_regs_t ddb_regs; /* register state */ +#define DDB_REGS (&ddb_regs) + +#ifdef __PROG26 +#define PC_REGS(regs) ((db_addr_t)(regs)->tf_r15 & R15_PC) +#define PC_ADVANCE(regs) ((regs)->tf_r15 += 4) +#else +#define PC_REGS(regs) ((db_addr_t)(regs)->tf_pc) +#endif + +#define BKPT_INST (KERNEL_BREAKPOINT) /* breakpoint instruction */ +#define BKPT_SIZE (INSN_SIZE) /* size of breakpoint inst */ +#define BKPT_SET(inst) (BKPT_INST) + +/*#define FIXUP_PC_AFTER_BREAK(regs) ((regs)->tf_pc -= BKPT_SIZE)*/ + +#define T_BREAKPOINT (1) + +#define IS_BREAKPOINT_TRAP(type, code) ((type) == T_BREAKPOINT) +#define IS_WATCHPOINT_TRAP(type, code) (0) + +#define inst_trap_return(ins) (0) +/* ldmxx reg, {..., pc} + 01800000 stack mode + 000f0000 register + 0000ffff register list */ +/* mov pc, reg + 0000000f register */ +#define inst_return(ins) (((ins) & 0x0e108000) == 0x08108000 || \ + ((ins) & 0x0ff0fff0) == 0x01a0f000) +/* bl ... + 00ffffff offset>>2 */ +#define inst_call(ins) (((ins) & 0x0f000000) == 0x0b000000) +/* b ... + 00ffffff offset>>2 */ +/* ldr pc, [pc, reg, lsl #2] + 0000000f register */ +#define inst_branch(ins) (((ins) & 0x0f000000) == 0x0a000000 || \ + ((ins) & 0x0fdffff0) == 0x079ff100) +#define inst_load(ins) (0) +#define inst_store(ins) (0) +#define inst_unconditional_flow_transfer(ins) \ + ((((ins) & INSN_COND_MASK) == INSN_COND_AL) && \ + (inst_branch(ins) || inst_call(ins) || inst_return(ins))) + +#define getreg_val (0) +#define next_instr_address(pc, bd) ((bd) ? (pc) : ((pc) + INSN_SIZE)) + +#define DB_MACHINE_COMMANDS + +#define SOFTWARE_SSTEP + +db_addr_t db_branch_taken(u_int inst, db_addr_t pc, db_regs_t *regs); +int kdb_trap __P((int, db_regs_t *)); +void db_machine_init __P((void)); + +#define branch_taken(ins, pc, fun, regs) \ + db_branch_taken((ins), (pc), (regs)) + +#define DB_ELF_SYMBOLS +#define DB_ELFSIZE 32 +#define DB_NO_AOUT + +void db_show_panic_cmd __P((db_expr_t, int, db_expr_t, char *)); +void db_show_frame_cmd __P((db_expr_t, int, db_expr_t, char *)); + +#endif /* _ARM_DB_MACHDEP_H_ */ diff --git a/sys/arch/arm/include/disklabel.h b/sys/arch/arm/include/disklabel.h new file mode 100644 index 00000000000..28db2c8195b --- /dev/null +++ b/sys/arch/arm/include/disklabel.h @@ -0,0 +1,151 @@ +/* $OpenBSD: disklabel.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $OpenBSD: disklabel.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: disklabel.h,v 1.2 2001/11/25 19:02:03 thorpej Exp $ */ + +/* + * Copyright (c) 1994 Mark Brinicombe. + * Copyright (c) 1994 Brini. + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * RiscBSD kernel project + * + * disklabel.h + * + * machine specific disk label info + * + * Created : 04/10/94 + */ + +#ifndef _ARM_DISKLABEL_H_ +#define _ARM_DISKLABEL_H_ + +#define LABELSECTOR 1 /* sector containing label */ +#define LABELOFFSET 0 /* offset of label in sector */ +#define MAXPARTITIONS 16 /* number of partitions */ +#define RAW_PART 2 /* raw partition: XX?c */ + +#include <sys/dkbad.h> +#if 0 +#include <arm/disklabel_acorn.h> +#include <sys/disklabel_mbr.h> +#endif + +/* MBR partition table */ +#define DOSBBSECTOR 0 /* MBR sector number */ +#define DOSPARTOFF 446 /* Offset of MBR partition table */ +#define NDOSPART 4 /* # of partitions in MBR */ +#define DOSMAGICOFF 510 /* Offset of magic number */ +#define DOSMAGIC 0xaa55 /* Actual magic number */ +#define MBRMAGIC DOSMAGIC +#define DOSMBR_SIGNATURE MBRMAGIC +#define DOSMBR_SIGNATURE_OFF DOSMAGICOFF +#define DOSACTIVE 0x80 + + +struct dos_partition { + u_int8_t dp_flag; /* bootstrap flags */ + u_int8_t dp_shd; /* starting head */ + u_int8_t dp_ssect; /* starting sector */ + u_int8_t dp_scyl; /* starting cylinder */ + u_int8_t dp_typ; /* partition type (see below) */ + u_int8_t dp_ehd; /* end head */ + u_int8_t dp_esect; /* end sector */ + u_int8_t dp_ecyl; /* end cylinder */ + u_int32_t dp_start; /* absolute starting sector number */ + u_int32_t dp_size; /* partition size in sectors */ +}; + +/* Known DOS partition types. */ +#define DOSPTYP_UNUSED 0x00 /* Unused partition */ +#define DOSPTYP_FAT12 0x01 /* 12-bit FAT */ +#define DOSPTYP_FAT16S 0x04 /* 16-bit FAT, less than 32M */ +#define DOSPTYP_EXTEND 0x05 /* Extended; contains sub-partitions */ +#define DOSPTYP_FAT16B 0x06 /* 16-bit FAT, more than 32M */ +#define DOSPTYP_FAT32 0x0b /* 32-bit FAT */ +#define DOSPTYP_FAT32L 0x0c /* 32-bit FAT, LBA-mapped */ +#define DOSPTYP_FAT16C 0x0e /* 16-bit FAT, CHS-mapped */ +#define DOSPTYP_EXTENDL 0x0f /* Extended, LBA-mapped; contains sub-partitions */ +#define DOSPTYP_ONTRACK 0x54 +#define DOSPTYP_LINUX 0x83 /* That other thing */ +#define DOSPTYP_FREEBSD 0xa5 /* FreeBSD partition type */ +#define DOSPTYP_OPENBSD 0xa6 /* OpenBSD partition type */ +#define DOSPTYP_NETBSD 0xa9 /* NetBSD partition type */ + +#include <sys/dkbad.h> + +/* Isolate the relevant bits to get sector and cylinder. */ +#define DPSECT(s) ((s) & 0x3f) +#define DPCYL(c, s) ((c) + (((s) & 0xc0) << 2)) + + +#ifdef __ARMEL__ +#define get_le(x) (*((u_int32_t *)x)) +#else +static __inline u_int32_t get_le(void *p); +static __inline u_int32_t +#ifdef __cplusplus +get_le(void *p) +#else +get_le(p) + void *p; +#endif +{ + u_int8_t *_p = (u_int8_t *)p; + int x; + x = _p[0]; + x |= _p[1] << 8; + x |= _p[2] << 16; + x |= _p[3] << 24; + return x; +} +#endif + + +#define NMBRPART 4 +struct cpu_disklabel { + struct dos_partition dosparts[NMBRPART]; + struct dkbad bad; +}; + +#ifdef _KERNEL +struct buf; +struct disklabel; +/* for readdisklabel. rv != 0 -> matches, msg == NULL -> success */ +int mbr_label_read __P((dev_t, void (*)(struct buf *), struct disklabel *, + struct cpu_disklabel *, char **, int *, int *)); + +/* for writedisklabel. rv == 0 -> dosen't match, rv > 0 -> success */ +int mbr_label_locate __P((dev_t, void (*)(struct buf *), + struct disklabel *, struct cpu_disklabel *, int *, int *)); +#endif /* _KERNEL */ + +#endif /* _ARM_DISKLABEL_H_ */ diff --git a/sys/arch/arm/include/elf_abi.h b/sys/arch/arm/include/elf_abi.h new file mode 100644 index 00000000000..3115568b7c3 --- /dev/null +++ b/sys/arch/arm/include/elf_abi.h @@ -0,0 +1,7 @@ +/* $OpenBSD: elf_abi.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +#ifndef _ARM_ELF_ABI_H +#define _ARM_ELF_ABI_H + +#define DT_PROCNUM 0 + +#endif /* _ARM_ELF_ABI_H */ diff --git a/sys/arch/arm/include/endian.h b/sys/arch/arm/include/endian.h new file mode 100644 index 00000000000..b9e046a3d37 --- /dev/null +++ b/sys/arch/arm/include/endian.h @@ -0,0 +1,8 @@ +/* $OpenBSD: endian.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ + +#ifdef __ARMEB__ +#define BYTE_ORDER BIG_ENDIAN +#else +#define BYTE_ORDER LITTLE_ENDIAN +#endif +#include <sys/endian.h> diff --git a/sys/arch/arm/include/fiq.h b/sys/arch/arm/include/fiq.h new file mode 100644 index 00000000000..e246323b57f --- /dev/null +++ b/sys/arch/arm/include/fiq.h @@ -0,0 +1,69 @@ +/* $OpenBSD: fiq.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: fiq.h,v 1.1 2001/12/20 01:20:23 thorpej Exp $ */ + +/* + * Copyright (c) 2001 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Jason R. Thorpe for Wasabi Systems, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ARM_FIQ_H_ +#define _ARM_FIQ_H_ + +#include <sys/queue.h> + +struct fiqregs { + u_int fr_r8; /* FIQ mode r8 */ + u_int fr_r9; /* FIQ mode r9 */ + u_int fr_r10; /* FIQ mode r10 */ + u_int fr_r11; /* FIQ mode r11 */ + u_int fr_r12; /* FIQ mode r12 */ + u_int fr_r13; /* FIQ mode r13 */ +}; + +struct fiqhandler { + TAILQ_ENTRY(fiqhandler) fh_list;/* link in the FIQ handler stack */ + void *fh_func; /* FIQ handler routine */ + size_t fh_size; /* size of FIQ handler */ + int fh_flags; /* flags; see below */ + struct fiqregs *fh_regs; /* pointer to regs structure */ +}; + +#define FH_CANPUSH 0x01 /* can push this handler out of the way */ + +int fiq_claim(struct fiqhandler *); +void fiq_release(struct fiqhandler *); + +void fiq_getregs(struct fiqregs *); +void fiq_setregs(struct fiqregs *); + +#endif /* _ARM_FIQ_H_ */ diff --git a/sys/arch/arm/include/float.h b/sys/arch/arm/include/float.h new file mode 100644 index 00000000000..1466dd4e7d7 --- /dev/null +++ b/sys/arch/arm/include/float.h @@ -0,0 +1,90 @@ +/* $OpenBSD: float.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: float.h,v 1.1 2001/01/10 19:02:06 bjh21 Exp $ */ + +/* + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This software was developed by the Computer Systems Engineering group + * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and + * contributed to Berkeley. + * + * All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Lawrence Berkeley Laboratory. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)float.h 8.1 (Berkeley) 6/11/93 + */ + +#ifndef _ARM32_FLOAT_H_ +#define _ARM32_FLOAT_H_ + +#include <sys/cdefs.h> + +__BEGIN_DECLS +extern int __flt_rounds __P((void)); +__END_DECLS + +#define FLT_RADIX 2 /* b */ +#define FLT_ROUNDS __flt_rounds() + +#define FLT_MANT_DIG 24 /* p */ +#define FLT_EPSILON 1.19209290E-7F /* b**(1-p) */ +#define FLT_DIG 6 /* floor((p-1)*log10(b))+(b == 10) */ +#define FLT_MIN_EXP (-125) /* emin */ +#define FLT_MIN 1.17549435E-38F /* b**(emin-1) */ +#define FLT_MIN_10_EXP (-37) /* ceil(log10(b**(emin-1))) */ +#define FLT_MAX_EXP 128 /* emax */ +#define FLT_MAX 3.40282347E+38F /* (1-b**(-p))*b**emax */ +#define FLT_MAX_10_EXP 38 /* floor(log10((1-b**(-p))*b**emax)) */ + +#define DBL_MANT_DIG 53 +#define DBL_EPSILON 2.2204460492503131E-16 +#define DBL_DIG 15 +#define DBL_MIN_EXP (-1021) +#define DBL_MIN 2.2250738585072014E-308 +#define DBL_MIN_10_EXP (-307) +#define DBL_MAX_EXP 1024 +#define DBL_MAX 1.7976931348623157E+308 +#define DBL_MAX_10_EXP 308 + +#define LDBL_MANT_DIG DBL_MANT_DIG +#define LDBL_EPSILON DBL_EPSILON +#define LDBL_DIG DBL_DIG +#define LDBL_MIN_EXP DBL_MIN_EXP +#define LDBL_MIN DBL_MIN +#define LDBL_MIN_10_EXP DBL_MIN_10_EXP +#define LDBL_MAX_EXP DBL_MAX_EXP +#define LDBL_MAX DBL_MAX +#define LDBL_MAX_10_EXP DBL_MAX_10_EXP + +#endif /* _ARM32_FLOAT_H_ */ diff --git a/sys/arch/arm/include/fp.h b/sys/arch/arm/include/fp.h new file mode 100644 index 00000000000..5d9096e0fa5 --- /dev/null +++ b/sys/arch/arm/include/fp.h @@ -0,0 +1,87 @@ +/* $OpenBSD: fp.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: fp.h,v 1.1 2001/01/10 19:02:06 bjh21 Exp $ */ + +/* + * Copyright (c) 1995 Mark Brinicombe. + * Copyright (c) 1995 Brini. + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * RiscBSD kernel project + * + * fp.h + * + * FP info + * + * Created : 10/10/95 + */ + +#ifndef __ARM32_FP_H +#define __ARM32_FP_H + +/* + * An extended precision floating point number + */ + +typedef struct fp_extended_precision { + u_int32_t fp_exponent; + u_int32_t fp_mantissa_hi; + u_int32_t fp_mantissa_lo; +} fp_extended_precision_t; + +typedef struct fp_extended_precision fp_reg_t; + +/* + * Information about the FPE-SP state that is stored in the pcb + * + * This needs to move and be hidden from userland. + */ + +struct fpe_sp_state { + unsigned int fp_flags; + unsigned int fp_sr; + unsigned int fp_cr; + fp_reg_t fp_registers[16]; +}; + +/* + * Type for a saved FP context, if we want to translate the context to a + * user-readable form + */ + +typedef struct { + u_int32_t fpsr; + fp_extended_precision_t regs[8]; +} fp_state_t; + +#endif + +/* End of fp.h */ diff --git a/sys/arch/arm/include/frame.h b/sys/arch/arm/include/frame.h new file mode 100644 index 00000000000..2db8310770d --- /dev/null +++ b/sys/arch/arm/include/frame.h @@ -0,0 +1,412 @@ +/* $OpenBSD: frame.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: frame.h,v 1.9 2003/12/01 08:48:33 scw Exp $ */ + +/* + * Copyright (c) 1994-1997 Mark Brinicombe. + * Copyright (c) 1994 Brini. + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * RiscBSD kernel project + * + * frame.h + * + * Stack frames structures + * + * Created : 30/09/94 + */ + +#ifndef _ARM_FRAME_H_ +#define _ARM_FRAME_H_ + +#ifndef _LOCORE + +#include <sys/signal.h> + +/* + * Trap frame. Pushed onto the kernel stack on a trap (synchronous exception). + */ + +typedef struct trapframe { + register_t tf_spsr; /* Zero on arm26 */ + register_t tf_r0; + register_t tf_r1; + register_t tf_r2; + register_t tf_r3; + register_t tf_r4; + register_t tf_r5; + register_t tf_r6; + register_t tf_r7; + register_t tf_r8; + register_t tf_r9; + register_t tf_r10; + register_t tf_r11; + register_t tf_r12; + register_t tf_usr_sp; + register_t tf_usr_lr; + register_t tf_svc_sp; /* Not used on arm26 */ + register_t tf_svc_lr; /* Not used on arm26 */ + register_t tf_pc; +} trapframe_t; + +/* Register numbers */ +#define tf_r13 tf_usr_sp +#define tf_r14 tf_usr_lr +#define tf_r15 tf_pc + +/* + * Signal frame. Pushed onto user stack before calling sigcode. + */ + +struct sigframe { + int sf_signum; + siginfo_t *sf_sip; + struct sigcontext *sf_scp; + sig_t sf_handler; + struct sigcontext sf_sc; + siginfo_t sf_si; +}; + +/* the pointers are use in the trampoline code to locate the ucontext */ +#if 0 +struct sigframe_siginfo { + siginfo_t sf_si; /* actual saved siginfo */ + ucontext_t sf_uc; /* actual saved ucontext */ +}; +#endif + +#if 0 +#ifdef _KERNEL +void sendsig_sigcontext(const ksiginfo_t *, const sigset_t *); +#endif +#endif + +#endif /* _LOCORE */ + +#ifndef _LOCORE + +/* + * System stack frames. + */ + +typedef struct irqframe { + unsigned int if_spsr; + unsigned int if_r0; + unsigned int if_r1; + unsigned int if_r2; + unsigned int if_r3; + unsigned int if_r4; + unsigned int if_r5; + unsigned int if_r6; + unsigned int if_r7; + unsigned int if_r8; + unsigned int if_r9; + unsigned int if_r10; + unsigned int if_r11; + unsigned int if_r12; + unsigned int if_usr_sp; + unsigned int if_usr_lr; + unsigned int if_svc_sp; + unsigned int if_svc_lr; + unsigned int if_pc; +} irqframe_t; + +#define clockframe irqframe + +/* + * Switch frame + */ + +struct switchframe { + u_int sf_r4; + u_int sf_r5; + u_int sf_r6; + u_int sf_r7; + u_int sf_pc; +}; + +/* + * Stack frame. Used during stack traces (db_trace.c) + */ +struct frame { + u_int fr_fp; + u_int fr_sp; + u_int fr_lr; + u_int fr_pc; +}; + +#ifdef _KERNEL +void validate_trapframe __P((trapframe_t *, int)); +#endif /* _KERNEL */ + +#else /* _LOCORE */ + +/* + * AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS + * These are used in order to support dynamic enabling/disabling of + * alignment faults when executing old a.out ARM binaries. + */ +#if defined(COMPAT_15) && defined(EXEC_AOUT) +#ifndef MULTIPROCESSOR + +/* + * Local variables needed by the AST/Alignment Fault macroes + */ +#define AST_ALIGNMENT_FAULT_LOCALS \ +.Laflt_astpending: ;\ + .word _C_LABEL(astpending) ;\ +.Laflt_cpufuncs: ;\ + .word _C_LABEL(cpufuncs) ;\ +.Laflt_curpcb: ;\ + .word _C_LABEL(curpcb) ;\ +.Laflt_cpu_info_store: ;\ + .word _C_LABEL(cpu_info_store) + +#define GET_CURPCB_ENTER \ + ldr r1, .Laflt_curpcb ;\ + ldr r1, [r1] + +#define GET_CPUINFO_ENTER \ + ldr r0, .Laflt_cpu_info_store + +#define GET_CURPCB_EXIT \ + ldr r1, .Laflt_curpcb ;\ + ldr r2, .Laflt_cpu_info_store ;\ + ldr r1, [r1] + +#else /* !MULTIPROCESSOR */ + +#define AST_ALIGNMENT_FAULT_LOCALS \ +.Laflt_astpending: ;\ + .word _C_LABEL(astpending) ;\ +.Laflt_cpufuncs: ;\ + .word _C_LABEL(cpufuncs) ;\ +.Laflt_cpu_info: ;\ + .word _C_LABEL(cpu_info) + +#define GET_CURPCB_ENTER \ + ldr r4, .Laflt_cpu_info ;\ + bl _C_LABEL(cpu_number) ;\ + ldr r0, [r4, r0, lsl #2] ;\ + ldr r1, [r0, #CI_CURPCB] + +#define GET_CPUINFO_ENTER /* nothing to do */ + +#define GET_CURPCB_EXIT \ + ldr r7, .Laflt_cpu_info ;\ + bl _C_LABEL(cpu_number) ;\ + ldr r2, [r7, r0, lsl #2] ;\ + ldr r1, [r2, #CI_CURPCB] +#endif /* MULTIPROCESSOR */ + +/* + * This macro must be invoked following PUSHFRAMEINSVC or PUSHFRAME at + * the top of interrupt/exception handlers. + * + * When invoked, r0 *must* contain the value of SPSR on the current + * trap/interrupt frame. This is always the case if ENABLE_ALIGNMENT_FAULTS + * is invoked immediately after PUSHFRAMEINSVC or PUSHFRAME. + */ +#define ENABLE_ALIGNMENT_FAULTS \ + and r0, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\ + teq r0, #(PSR_USR32_MODE) ;\ + bne 1f /* Not USR mode skip AFLT */ ;\ + GET_CURPCB_ENTER /* r1 = curpcb */ ;\ + cmp r1, #0x00 /* curpcb NULL? */ ;\ + ldrne r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\ + tstne r1, #PCB_NOALIGNFLT ;\ + beq 1f /* AFLTs already enabled */ ;\ + GET_CPUINFO_ENTER /* r0 = cpuinfo */ ;\ + ldr r2, .Laflt_cpufuncs ;\ + ldr r1, [r0, #CI_CTRL] /* Fetch control register */ ;\ + mov r0, #-1 ;\ + mov lr, pc ;\ + ldr pc, [r2, #CF_CONTROL] /* Enable alignment faults */ ;\ +1: + +/* + * This macro must be invoked just before PULLFRAMEFROMSVCANDEXIT or + * PULLFRAME at the end of interrupt/exception handlers. + */ +#define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ + ldr r0, [sp] /* Get the SPSR from stack */ ;\ + mrs r4, cpsr /* save CPSR */ ;\ + and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ + teq r0, #(PSR_USR32_MODE) ;\ + ldreq r5, .Laflt_astpending ;\ + bne 3f /* Nope, get out now */ ;\ + bic r4, r4, #(I32_bit) ;\ +1: orr r0, r4, #(I32_bit) /* Disable IRQs */ ;\ + msr cpsr_c, r0 ;\ + ldr r1, [r5] /* Pending AST? */ ;\ + teq r1, #0x00000000 ;\ + bne 2f /* Yup. Go deal with it */ ;\ + GET_CURPCB_EXIT /* r1 = curpcb, r2 = cpuinfo */ ;\ + cmp r1, #0x00 /* curpcb NULL? */ ;\ + ldrne r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\ + tstne r1, #PCB_NOALIGNFLT ;\ + beq 3f /* Keep AFLTs enabled */ ;\ + ldr r1, [r2, #CI_CTRL] /* Fetch control register */ ;\ + ldr r2, .Laflt_cpufuncs ;\ + mov r0, #-1 ;\ + bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable AFLTs */ ;\ + adr lr, 3f ;\ + ldr pc, [r2, #CF_CONTROL] /* Set new CTRL reg value */ ;\ +2: mov r1, #0x00000000 ;\ + str r1, [r5] /* Clear astpending */ ;\ + msr cpsr_c, r4 /* Restore interrupts */ ;\ + mov r0, sp ;\ + adr lr, 1b ;\ + b _C_LABEL(ast) /* ast(frame) */ ;\ +3: + +#else /* !(COMPAT_15 && EXEC_AOUT) */ + +#define AST_ALIGNMENT_FAULT_LOCALS ;\ +.Laflt_astpending: ;\ + .word _C_LABEL(astpending) + +#define ENABLE_ALIGNMENT_FAULTS /* nothing */ + +#define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ + ldr r0, [sp] /* Get the SPSR from stack */ ;\ + mrs r4, cpsr /* save CPSR */ ;\ + and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ + teq r0, #(PSR_USR32_MODE) ;\ + ldreq r5, .Laflt_astpending ;\ + bne 2f /* Nope, get out now */ ;\ + bic r4, r4, #(I32_bit) ;\ +1: orr r0, r4, #(I32_bit) /* Disable IRQs */ ;\ + msr cpsr_c, r0 ;\ + ldr r1, [r5] /* Pending AST? */ ;\ + teq r1, #0x00000000 ;\ + beq 2f /* Nope. Just bail */ ;\ + mov r1, #0x00000000 ;\ + str r1, [r5] /* Clear astpending */ ;\ + msr cpsr_c, r4 /* Restore interrupts */ ;\ + mov r0, sp ;\ + adr lr, 1b ;\ + b _C_LABEL(ast) /* ast(frame) */ ;\ +2: +#endif /* COMPAT_15 && EXEC_AOUT */ + +/* + * ASM macros for pushing and pulling trapframes from the stack + * + * These macros are used to handle the irqframe and trapframe structures + * defined above. + */ + +/* + * PUSHFRAME - macro to push a trap frame on the stack in the current mode + * Since the current mode is used, the SVC lr field is not defined. + * + * NOTE: r13 and r14 are stored separately as a work around for the + * SA110 rev 2 STM^ bug + */ + +#define PUSHFRAME \ + str lr, [sp, #-4]!; /* Push the return address */ \ + sub sp, sp, #(4*17); /* Adjust the stack pointer */ \ + stmia sp, {r0-r12}; /* Push the user mode registers */ \ + add r0, sp, #(4*13); /* Adjust the stack pointer */ \ + stmia r0, {r13-r14}^; /* Push the user mode registers */ \ + mov r0, r0; /* NOP for previous instruction */ \ + mrs r0, spsr_all; /* Put the SPSR on the stack */ \ + str r0, [sp, #-4]! + +/* + * PULLFRAME - macro to pull a trap frame from the stack in the current mode + * Since the current mode is used, the SVC lr field is ignored. + */ + +#define PULLFRAME \ + ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \ + msr spsr_all, r0; \ + ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ + mov r0, r0; /* NOP for previous instruction */ \ + add sp, sp, #(4*17); /* Adjust the stack pointer */ \ + ldr lr, [sp], #0x0004 /* Pull the return address */ + +/* + * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode + * This should only be used if the processor is not currently in SVC32 + * mode. The processor mode is switched to SVC mode and the trap frame is + * stored. The SVC lr field is used to store the previous value of + * lr in SVC mode. + * + * NOTE: r13 and r14 are stored separately as a work around for the + * SA110 rev 2 STM^ bug + */ + +#define PUSHFRAMEINSVC \ + stmdb sp, {r0-r3}; /* Save 4 registers */ \ + mov r0, lr; /* Save xxx32 r14 */ \ + mov r1, sp; /* Save xxx32 sp */ \ + mrs r3, spsr; /* Save xxx32 spsr */ \ + mrs r2, cpsr; /* Get the CPSR */ \ + bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \ + orr r2, r2, #(PSR_SVC32_MODE); \ + msr cpsr_c, r2; /* Punch into SVC mode */ \ + mov r2, sp; /* Save SVC sp */ \ + str r0, [sp, #-4]!; /* Push return address */ \ + str lr, [sp, #-4]!; /* Push SVC lr */ \ + str r2, [sp, #-4]!; /* Push SVC sp */ \ + msr spsr_all, r3; /* Restore correct spsr */ \ + ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ + sub sp, sp, #(4*15); /* Adjust the stack pointer */ \ + stmia sp, {r0-r12}; /* Push the user mode registers */ \ + add r0, sp, #(4*13); /* Adjust the stack pointer */ \ + stmia r0, {r13-r14}^; /* Push the user mode registers */ \ + mov r0, r0; /* NOP for previous instruction */ \ + mrs r0, spsr_all; /* Put the SPSR on the stack */ \ + str r0, [sp, #-4]! + +/* + * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack + * in SVC32 mode and restore the saved processor mode and PC. + * This should be used when the SVC lr register needs to be restored on + * exit. + */ + +#define PULLFRAMEFROMSVCANDEXIT \ + ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \ + msr spsr_all, r0; /* restore SPSR */ \ + ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ + mov r0, r0; /* NOP for previous instruction */ \ + add sp, sp, #(4*15); /* Adjust the stack pointer */ \ + ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ + +#endif /* _LOCORE */ + +#endif /* _ARM_FRAME_H_ */ + +/* End of frame.h */ diff --git a/sys/arch/arm/include/ieee.h b/sys/arch/arm/include/ieee.h new file mode 100644 index 00000000000..5f9b89ecc0e --- /dev/null +++ b/sys/arch/arm/include/ieee.h @@ -0,0 +1,191 @@ +/* $OpenBSD: ieee.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: ieee.h,v 1.2 2001/02/21 17:43:50 bjh21 Exp $ */ + +/* + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This software was developed by the Computer Systems Engineering group + * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and + * contributed to Berkeley. + * + * All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Lawrence Berkeley Laboratory. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)ieee.h 8.1 (Berkeley) 6/11/93 + */ + +/* + * ieee.h defines the machine-dependent layout of the machine's IEEE + * floating point. + */ + +/* + * Define the number of bits in each fraction and exponent. + * + * k k+1 + * Note that 1.0 x 2 == 0.1 x 2 and that denorms are represented + * + * (-exp_bias+1) + * as fractions that look like 0.fffff x 2 . This means that + * + * -126 + * the number 0.10000 x 2 , for instance, is the same as the normalized + * + * -127 -128 + * float 1.0 x 2 . Thus, to represent 2 , we need one leading zero + * + * -129 + * in the fraction; to represent 2 , we need two, and so on. This + * + * (-exp_bias-fracbits+1) + * implies that the smallest denormalized number is 2 + * + * for whichever format we are talking about: for single precision, for + * + * -126 -149 + * instance, we get .00000000000000000000001 x 2 , or 1.0 x 2 , and + * + * -149 == -127 - 23 + 1. + */ + +/* + * The ARM has two sets of FP data formats. The FPA supports 32-bit, 64-bit + * and 96-bit IEEE formats, with the words in big-endian order. VFP supports + * 32-bin and 64-bit IEEE formats with the words in the CPU's native byte + * order. + * + * The FPA also has two packed decimal formats, but we ignore them here. + */ + +#define SNG_EXPBITS 8 +#define SNG_FRACBITS 23 + +#define DBL_EXPBITS 11 +#define DBL_FRACBITS 52 + +#ifndef __VFP_FP__ +#define E80_EXPBITS 15 +#define E80_FRACBITS 64 + +#define EXT_EXPBITS 15 +#define EXT_FRACBITS 112 +#endif + +struct ieee_single { + u_int sng_frac:23; + u_int sng_exponent:8; + u_int sng_sign:1; +}; + +#ifdef __VFP_FP__ +struct ieee_double { +#ifdef __ARMEB__ + u_int dbl_sign:1; + u_int dbl_exp:11; + u_int dbl_frach:20; + u_int dbl_fracl; +#else /* !__ARMEB__ */ + u_int dbl_fracl; + u_int dbl_frach:20; + u_int dbl_exp:11; + u_int dbl_sign:1; +#endif /* !__ARMEB__ */ +}; +#else /* !__VFP_FP__ */ +struct ieee_double { + u_int dbl_frach:20; + u_int dbl_exp:11; + u_int dbl_sign:1; + u_int dbl_fracl; +}; + +union ieee_double_u { + double dblu_d; + struct ieee_double dblu_dbl; +}; + + +struct ieee_e80 { + u_int e80_exp:15; + u_int e80_zero:16; + u_int e80_sign:1; + u_int e80_frach:31; + u_int e80_j:1; + u_int e80_fracl; +}; + +struct ieee_ext { + u_int ext_frach:16; + u_int ext_exp:15; + u_int ext_sign:1; + u_int ext_frachm; + u_int ext_fraclm; + u_int ext_fracl; +}; +#endif /* !__VFP_FP__ */ + +/* + * Floats whose exponent is in [1..INFNAN) (of whatever type) are + * `normal'. Floats whose exponent is INFNAN are either Inf or NaN. + * Floats whose exponent is zero are either zero (iff all fraction + * bits are zero) or subnormal values. + * + * A NaN is a `signalling NaN' if its QUIETNAN bit is clear in its + * high fraction; if the bit is set, it is a `quiet NaN'. + */ +#define SNG_EXP_INFNAN 255 +#define DBL_EXP_INFNAN 2047 +#ifndef __VFP_FP__ +#define E80_EXP_INFNAN 32767 +#define EXT_EXP_INFNAN 32767 +#endif /* !__VFP_FP__ */ + +#if 0 +#define SNG_QUIETNAN (1 << 22) +#define DBL_QUIETNAN (1 << 19) +#ifndef __VFP_FP__ +#define E80_QUIETNAN (1 << 15) +#define EXT_QUIETNAN (1 << 15) +#endif /* !__VFP_FP__ */ +#endif + +/* + * Exponent biases. + */ +#define SNG_EXP_BIAS 127 +#define DBL_EXP_BIAS 1023 +#ifndef __VFP_FP__ +#define E80_EXP_BIAS 16383 +#define EXT_EXP_BIAS 16383 +#endif /* !__VFP_FP__ */ diff --git a/sys/arch/arm/include/ieeefp.h b/sys/arch/arm/include/ieeefp.h new file mode 100644 index 00000000000..6aaf2b950e1 --- /dev/null +++ b/sys/arch/arm/include/ieeefp.h @@ -0,0 +1,41 @@ +/* $OpenBSD: ieeefp.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: ieeefp.h,v 1.1 2001/01/10 19:02:06 bjh21 Exp $ */ + +/* + * Based on ieeefp.h written by J.T. Conklin, Apr 28, 1995 + * Public domain. + */ + +#ifndef _ARM32_IEEEFP_H_ +#define _ARM32_IEEEFP_H_ + +/* FP exception codes */ + +#define FP_EXCEPT_INV 0 +#define FP_EXCEPT_DZ 1 +#define FP_EXCEPT_OFL 2 +#define FP_EXCEPT_UFL 3 +#define FP_EXCEPT_IMP 4 + +/* Exception type (used by fpsetmask() et al.) */ + +typedef int fp_except; + +/* Bit defines for fp_except */ + +#define FP_X_INV (1 << FP_EXCEPT_INV) /* invalid operation exception */ +#define FP_X_DZ (1 << FP_EXCEPT_DZ) /* divide-by-zero exception */ +#define FP_X_OFL (1 << FP_EXCEPT_OFL) /* overflow exception */ +#define FP_X_UFL (1 << FP_EXCEPT_UFL) /* underflow exception */ +#define FP_X_IMP (1 << FP_EXCEPT_IMP) /* imprecise (loss of precision; "inexact") */ + +/* Rounding modes */ + +typedef enum { + FP_RN=0, /* round to nearest representable number */ + FP_RP=1, /* round toward positive infinity */ + FP_RM=2, /* round toward negative infinity */ + FP_RZ=3 /* round to zero (truncate) */ +} fp_rnd; + +#endif /* _ARM32_IEEEFP_H_ */ diff --git a/sys/arch/arm/include/internal_types.h b/sys/arch/arm/include/internal_types.h new file mode 100644 index 00000000000..96546cfacb9 --- /dev/null +++ b/sys/arch/arm/include/internal_types.h @@ -0,0 +1,6 @@ +/* $OpenBSD: internal_types.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* Public domain */ +#ifndef _ARM_INTERNAL_TYPES_H_ +#define _ARM_INTERNAL_TYPES_H_ + +#endif diff --git a/sys/arch/arm/include/isa_machdep.h b/sys/arch/arm/include/isa_machdep.h new file mode 100644 index 00000000000..97e2c1171c8 --- /dev/null +++ b/sys/arch/arm/include/isa_machdep.h @@ -0,0 +1,193 @@ +/* $OpenBSD: isa_machdep.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: isa_machdep.h,v 1.3 2002/01/07 22:58:07 chris Exp $ */ + +/*- + * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ARM32_ISA_MACHDEP_H_ +#define _ARM32_ISA_MACHDEP_H_ + +#include <machine/bus.h> +#include <dev/isa/isadmavar.h> + +#define __NO_ISA_INTR_CHECK +/* + * Types provided to machine-independent ISA code. + */ +struct arm32_isa_chipset { + /* + struct isa_dma_state ic_dmastate; + */ +}; + +typedef struct arm32_isa_chipset *isa_chipset_tag_t; + +struct device; /* XXX */ +struct isabus_attach_args; /* XXX */ + +/* + * Functions provided to machine-independent ISA code. + */ +void isa_attach_hook(struct device *, struct device *, + struct isabus_attach_args *); +const struct evcnt *isa_intr_evcnt(isa_chipset_tag_t ic, int irq); +void *isa_intr_establish(isa_chipset_tag_t ic, int irq, int type, + int level, int (*ih_fun)(void *), void *ih_arg, char *name); +void isa_intr_disestablish(isa_chipset_tag_t ic, void *handler); + +#if 0 +#define isa_dmainit(ic, bst, dmat, d) \ + _isa_dmainit(&(ic)->ic_dmastate, (bst), (dmat), (d)) +#define isa_dmacascade(ic, c) \ + _isa_dmacascade(&(ic)->ic_dmastate, (c)) +#define isa_dmamaxsize(ic, c) \ + _isa_dmamaxsize(&(ic)->ic_dmastate, (c)) +#define isa_dmamap_create(ic, c, s, f) \ + _isa_dmamap_create(&(ic)->ic_dmastate, (c), (s), (f)) +#define isa_dmamap_destroy(ic, c) \ + _isa_dmamap_destroy(&(ic)->ic_dmastate, (c)) +#define isa_dmastart(ic, c, a, n, p, f, bf) \ + _isa_dmastart(&(ic)->ic_dmastate, (c), (a), (n), (p), (f), (bf)) +#define isa_dmaabort(ic, c) \ + _isa_dmaabort(&(ic)->ic_dmastate, (c)) +#define isa_dmacount(ic, c) \ + _isa_dmacount(&(ic)->ic_dmastate, (c)) +#define isa_dmafinished(ic, c) \ + _isa_dmafinished(&(ic)->ic_dmastate, (c)) +#define isa_dmadone(ic, c) \ + _isa_dmadone(&(ic)->ic_dmastate, (c)) +#define isa_dmafreeze(ic) \ + _isa_dmafreeze(&(ic)->ic_dmastate) +#define isa_dmathaw(ic) \ + _isa_dmathaw(&(ic)->ic_dmastate) +#define isa_dmamem_alloc(ic, c, s, ap, f) \ + _isa_dmamem_alloc(&(ic)->ic_dmastate, (c), (s), (ap), (f)) +#define isa_dmamem_free(ic, c, a, s) \ + _isa_dmamem_free(&(ic)->ic_dmastate, (c), (a), (s)) +#define isa_dmamem_map(ic, c, a, s, kp, f) \ + _isa_dmamem_map(&(ic)->ic_dmastate, (c), (a), (s), (kp), (f)) +#define isa_dmamem_unmap(ic, c, k, s) \ + _isa_dmamem_unmap(&(ic)->ic_dmastate, (c), (k), (s)) +#define isa_dmamem_mmap(ic, c, a, s, o, p, f) \ + _isa_dmamem_mmap(&(ic)->ic_dmastate, (c), (a), (s), (o), (p), (f)) +#define isa_drq_alloc(ic, c) \ + _isa_drq_alloc(&(ic)->ic_dmastate, c) +#define isa_drq_free(ic, c) \ + _isa_drq_free(&(ic)->ic_dmastate, c) +#define isa_drq_isfree(ic, c) \ + _isa_drq_isfree(&(ic)->ic_dmastate, (c)) +#define isa_malloc(ic, c, s, p, f) \ + _isa_malloc(&(ic)->ic_dmastate, (c), (s), (p), (f)) +#define isa_free(a, p) \ + _isa_free((a), (p)) +#define isa_mappage(m, o, p) \ + _isa_mappage((m), (o), (p)) +#endif + +/* + * ALL OF THE FOLLOWING ARE MACHINE-DEPENDENT, AND SHOULD NOT BE USED + * BY PORTABLE CODE. + */ + +extern struct arm32_bus_dma_tag isa_bus_dma_tag; + +/* + * Cookie used by ISA DMA. A pointer to one of these is stashed in + * the DMA map. + */ +struct arm32_isa_dma_cookie { + int id_flags; /* flags; see below */ + + /* + * Information about the original buffer used during + * DMA map syncs. Note that origbuflen is only used + * for ID_BUFTYPE_LINEAR. + */ + void *id_origbuf; /* pointer to orig buffer if + bouncing */ + bus_size_t id_origbuflen; /* ...and size */ + int id_buftype; /* type of buffer */ + + void *id_bouncebuf; /* pointer to the bounce buffer */ + bus_size_t id_bouncebuflen; /* ...and size */ + int id_nbouncesegs; /* number of valid bounce segs */ + bus_dma_segment_t id_bouncesegs[0]; /* array of bounce buffer + physical memory segments */ +}; + +/* id_flags */ +#define ID_MIGHT_NEED_BOUNCE 0x01 /* map could need bounce buffers */ +#define ID_HAS_BOUNCE 0x02 /* map currently has bounce buffers */ +#define ID_IS_BOUNCING 0x04 /* map is bouncing current xfer */ + +/* id_buftype */ +#define ID_BUFTYPE_INVALID 0 +#define ID_BUFTYPE_LINEAR 1 +#define ID_BUFTYPE_MBUF 2 +#define ID_BUFTYPE_UIO 3 +#define ID_BUFTYPE_RAW 4 + +/* bus space tags */ +extern struct bus_space isa_io_bs_tag; +extern struct bus_space isa_mem_bs_tag; + +/* ISA chipset */ +extern struct arm32_isa_chipset isa_chipset_tag; + +/* for pccons.c */ +#define MONO_BASE 0x3B4 +#define MONO_BUF 0x000B0000 +#define CGA_BASE 0x3D4 +#define CGA_BUF 0x000B8000 +#define VGA_BUF 0xA0000 +#define VGA_BUF_LEN (0xBFFFF - 0xA0000) + +void isa_init(vaddr_t, vaddr_t); +void isa_io_init(vaddr_t, vaddr_t); +void isa_dma_init(void); +vaddr_t isa_io_data_vaddr(void); +vaddr_t isa_mem_data_vaddr(void); +int isa_intr_alloc(isa_chipset_tag_t ic, int mask, int type, int *irq); +void isa_intr_init(void); + +/* + * Miscellanous functions. + */ +void sysbeep(int, int); /* beep with the system speaker */ +void isa_fillw(u_int val, void *addr, size_t len); + +#endif /* _ARM32_ISA_MACHDEP_H_ XXX */ diff --git a/sys/arch/arm/include/katelib.h b/sys/arch/arm/include/katelib.h new file mode 100644 index 00000000000..b17905d0ce7 --- /dev/null +++ b/sys/arch/arm/include/katelib.h @@ -0,0 +1,99 @@ +/* $OpenBSD: katelib.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: katelib.h,v 1.3 2001/11/23 19:21:48 thorpej Exp $ */ + +/* + * Copyright (c) 1994-1996 Mark Brinicombe. + * Copyright (c) 1994 Brini. + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * RiscBSD kernel project + * + * katelib.h + * + * Prototypes for machine specific functions. Most of these + * could be inlined. + * + * This should not really be a separate header file. Eventually I will merge + * this into other header files once I have decided where the declarations + * should go. + * + * Created : 18/09/94 + * + * Based on kate/katelib/prototypes.h + */ + +/* + * USE OF THIS FILE IS DEPRECATED + */ + +#include <sys/types.h> +#include <arm/cpufunc.h> + +#ifdef _KERNEL + +/* Assembly modules */ + +/* In blockio.S */ +#include <arm/blockio.h> + +/* Macros for reading and writing words, shorts, bytes */ + +#define WriteWord(a, b) \ +*((volatile unsigned int *)(a)) = (b) + +#define ReadWord(a) \ +(*((volatile unsigned int *)(a))) + +#define WriteShort(a, b) \ +*((volatile unsigned int *)(a)) = ((b) | ((b) << 16)) + +#define ReadShort(a) \ +((*((volatile unsigned int *)(a))) & 0xffff) + +#define WriteByte(a, b) \ +*((volatile unsigned char *)(a)) = (b) + +#define ReadByte(a) \ +(*((volatile unsigned char *)(a))) + +/* Define in/out macros */ + +#define inb(port) ReadByte((port)) +#define outb(port, byte) WriteByte((port), (byte)) +#define inw(port) ReadShort((port)) +#define outw(port, word) WriteShort((port), (word)) +#define inl(port) ReadWord((port)) +#define outl(port, lword) WriteWord((port), (lword)) + +#endif + +/* End of katelib.h */ diff --git a/sys/arch/arm/include/limits.h b/sys/arch/arm/include/limits.h new file mode 100644 index 00000000000..44c99876b4f --- /dev/null +++ b/sys/arch/arm/include/limits.h @@ -0,0 +1,54 @@ +/* $OpenBSD: limits.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: limits.h,v 1.4 2003/04/28 23:16:18 bjh21 Exp $ */ + +/* + * Copyright (c) 1988 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: @(#)limits.h 7.2 (Berkeley) 6/28/90 + */ + +#ifndef _ARM32_LIMITS_H_ +#define _ARM32_LIMITS_H_ + +#define MB_LEN_MAX 1 /* no multibyte characters */ + +#if !defined(_ANSI_SOURCE) +#define SIZE_MAX UINT_MAX /* max value for a size_t */ +#define SSIZE_MAX INT_MAX /* max value for a ssize_t */ + +#if !defined(_POSIX_SOURCE) && !defined(_XOPEN_SOURCE) +#define SIZE_T_MAX UINT_MAX /* max value for a size_t */ + +#define UQUAD_MAX 0xffffffffffffffffULL /* max unsigned quad */ +#define QUAD_MAX 0x7fffffffffffffffLL /* max signed quad */ +#define QUAD_MIN (-0x7fffffffffffffffLL-1) /* min signed quad */ + +#endif /* !_POSIX_SOURCE && !_XOPEN_SOURCE */ +#endif /* !_ANSI_SOURCE */ + +#endif /* _ARM32_LIMITS_H_ */ diff --git a/sys/arch/arm/include/lock.h b/sys/arch/arm/include/lock.h new file mode 100644 index 00000000000..f949eb8d3b9 --- /dev/null +++ b/sys/arch/arm/include/lock.h @@ -0,0 +1,90 @@ +/* $OpenBSD: lock.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: lock.h,v 1.3 2002/10/07 23:19:49 bjh21 Exp $ */ + +/*- + * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Machine-dependent spin lock operations. + * + * NOTE: The SWP insn used here is available only on ARM architecture + * version 3 and later (as well as 2a). What we are going to do is + * expect that the kernel will trap and emulate the insn. That will + * be slow, but give us the atomicity that we need. + */ + +#ifndef _ARM_LOCK_H_ +#define _ARM_LOCK_H_ + +static __inline int +__swp(int __val, __volatile int *__ptr) +{ + + __asm __volatile("swp %0, %1, [%2]" + : "=r" (__val) : "r" (__val), "r" (__ptr) : "memory"); + return __val; +} + +static __inline void __attribute__((__unused__)) +__cpu_simple_lock_init(__cpu_simple_lock_t *alp) +{ + + *alp = __SIMPLELOCK_UNLOCKED; +} + +static __inline void __attribute__((__unused__)) +__cpu_simple_lock(__cpu_simple_lock_t *alp) +{ + + while (__swp(__SIMPLELOCK_LOCKED, alp) != __SIMPLELOCK_UNLOCKED) + continue; +} + +static __inline int __attribute__((__unused__)) +__cpu_simple_lock_try(__cpu_simple_lock_t *alp) +{ + + return (__swp(__SIMPLELOCK_LOCKED, alp) == __SIMPLELOCK_UNLOCKED); +} + +static __inline void __attribute__((__unused__)) +__cpu_simple_unlock(__cpu_simple_lock_t *alp) +{ + + *alp = __SIMPLELOCK_UNLOCKED; +} + +#endif /* _ARM_LOCK_H_ */ diff --git a/sys/arch/arm/include/machdep.h b/sys/arch/arm/include/machdep.h new file mode 100644 index 00000000000..4abb8321219 --- /dev/null +++ b/sys/arch/arm/include/machdep.h @@ -0,0 +1,27 @@ +/* $OpenBSD: machdep.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: machdep.h,v 1.7 2002/02/21 02:52:21 thorpej Exp $ */ + +#ifndef _ARM32_BOOT_MACHDEP_H_ +#define _ARM32_BOOT_MACHDEP_H_ + +/* misc prototypes used by the many arm machdeps */ +void halt __P((void)); +void parse_mi_bootargs __P((char *)); +void data_abort_handler __P((trapframe_t *)); +void prefetch_abort_handler __P((trapframe_t *)); +void undefinedinstruction_bounce __P((trapframe_t *)); +void dumpsys __P((void)); + +/* + * note that we use void * as all the platforms have different ideas on what + * the structure is + */ +u_int initarm __P((void *)); + +/* from arm/arm/intr.c */ +void dosoftints __P((void)); +void set_spl_masks __P((void)); +#ifdef DIAGNOSTIC +void dump_spl_masks __P((void)); +#endif +#endif diff --git a/sys/arch/arm/include/math.h b/sys/arch/arm/include/math.h new file mode 100644 index 00000000000..a5818196591 --- /dev/null +++ b/sys/arch/arm/include/math.h @@ -0,0 +1,4 @@ +/* $OpenBSD: math.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: math.h,v 1.2 2002/02/19 13:08:14 simonb Exp $ */ + +#define __HAVE_NANF diff --git a/sys/arch/arm/include/param.h b/sys/arch/arm/include/param.h new file mode 100644 index 00000000000..72926990653 --- /dev/null +++ b/sys/arch/arm/include/param.h @@ -0,0 +1,241 @@ +/* $OpenBSD: param.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: param.h,v 1.9 2002/03/24 03:37:23 thorpej Exp $ */ + +/* + * Copyright (c) 1994,1995 Mark Brinicombe. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the RiscBSD team. + * 4. The name "RiscBSD" nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARM_ARM_PARAM_H_ +#define _ARM_ARM_PARAM_H_ + + +/* + * Machine dependent constants for ARM6+ processors + */ +/* These are defined in the Port File before it includes + * this file. */ + +#define PAGE_SHIFT 12 /* LOG2(NBPG) */ +#define PGSHIFT 12 /* LOG2(NBPG) */ +#define PAGE_SIZE (1 << PAGE_SHIFT) /* bytes/page */ +#define NBPG (1 << PAGE_SHIFT) /* bytes/page */ +#define PAGE_MASK (PAGE_SIZE - 1) +#define PGOFSET (PAGE_SIZE - 1) +#define NPTEPG (PAGE_SIZE/(sizeof (pt_entry_t))) + +#define SSIZE 1 /* initial stack size/NBPG */ +#define SINCR 1 /* increment of stack/NBPG */ +#define UPAGES 2 /* pages of u-area */ +#define USPACE (UPAGES * PAGE_SIZE) /* total size of u-area */ + +#ifndef MSGBUFSIZE +#define MSGBUFSIZE PAGE_SIZE /* default message buffer size */ +#endif + +#ifndef NMBCLUSTERS +#ifdef GATEWAY +#define NMBCLUSTERS 2048 /* map size, max cluster allocation */ +#else +#define NMBCLUSTERS 1024 /* map size, max cluster allocation */ +#endif +#endif + +/* + * Minimum and maximum sizes of the kernel malloc arena in PAGE_SIZE-sized + * logical pages. + */ +#define NKMEMPAGES_MIN_DEFAULT ((6 * 1024 * 1024) >> PAGE_SHIFT) +#define NKMEMPAGES_MAX_DEFAULT ((7 * 1024 * 1024) >> PAGE_SHIFT) + +/* Constants used to divide the USPACE area */ + +/* + * The USPACE area contains : + * 1. the user structure for the process + * 2. the fp context for FP emulation + * 3. the kernel (svc) stack + * 4. the undefined instruction stack + * + * The layout of the area looks like this + * + * | user area | FP context | undefined stack | kernel stack | + * + * The size of the user area is known. + * The size of the FP context is variable depending of the FP emulator + * in use and whether there is hardware FP support. However we can put + * an upper limit on it. + * The undefined stack needs to be at least 512 bytes. This is a requirement + * if the FP emulators + * The kernel stack should be at least 4K is size. + * + * The stack top addresses are used to set the stack pointers. The stack bottom + * addresses at the addresses monitored by the diagnostic code for stack overflows + * + */ + +#define FPCONTEXTSIZE (0x100) +#define USPACE_SVC_STACK_TOP (USPACE) +#define USPACE_SVC_STACK_BOTTOM (USPACE_SVC_STACK_TOP - 0x1000) +#define USPACE_UNDEF_STACK_TOP (USPACE_SVC_STACK_BOTTOM - 0x10) +#define USPACE_UNDEF_STACK_BOTTOM (sizeof(struct user) + FPCONTEXTSIZE + 10) + +#define arm_btop(x) ((x) >> PAGE_SHIFT) +#define arm_ptob(x) ((x) << PAGE_SHIFT) +#define arm_trunc_page(x) ((unsigned)(x) & ~PAGE_MASK) + +#ifdef _KERNEL +#ifndef _LOCORE +void delay __P((unsigned)); +#define DELAY(x) delay(x) +#endif +#endif + +/* + * Machine dependent constants for all ARM processors + */ + +/* + * For KERNEL code: + * MACHINE must be defined by the individual port. This is so that + * uname returns the correct thing, etc. + * + * MACHINE_ARCH may be defined by individual ports as a temporary + * measure while we're finishing the conversion to ELF. + * + * For non-KERNEL code: + * If ELF, MACHINE and MACHINE_ARCH are forced to "arm/armeb". + */ + +#if defined(_KERNEL) +#ifndef MACHINE_ARCH /* XXX For now */ +#ifndef __ARMEB__ +#define _MACHINE_ARCH arm +#define MACHINE_ARCH "arm" +#else +#define _MACHINE_ARCH armeb +#define MACHINE_ARCH "armeb" +#endif /* __ARMEB__ */ +#endif /* MACHINE_ARCH */ +#elif defined(__ELF__) +#undef _MACHINE +#undef MACHINE +#undef _MACHINE_ARCH +#undef MACHINE_ARCH +#define _MACHINE arm +#define MACHINE "arm" +#ifndef __ARMEB__ +#define _MACHINE_ARCH arm +#define MACHINE_ARCH "arm" +#else +#define _MACHINE_ARCH armeb +#define MACHINE_ARCH "armeb" +#endif /* __ARMEB__ */ +#endif /* __ELF__ */ + +#define MID_MACHINE MID_ARM6 + +/* + * Round p (pointer or byte index) up to a correctly-aligned value + * for all data types (int, long, ...). The result is u_int and + * must be cast to any desired pointer type. + * + * ALIGNED_POINTER is a boolean macro that checks whether an address + * is valid to fetch data elements of type t from on this architecture. + * This does not reflect the optimal alignment, just the possibility + * (within reasonable limits). + * + */ +#define ALIGNBYTES (sizeof(int) - 1) +#define ALIGN(p) (((u_int)(p) + ALIGNBYTES) &~ ALIGNBYTES) +#define ALIGNED_POINTER(p,t) ((((u_long)(p)) & (sizeof(t)-1)) == 0) +/* ARM-specific macro to align a stack pointer (downwards). */ +#define STACKALIGNBYTES (8 - 1) +#define STACKALIGN(p) ((u_int)(p) &~ STACKALIGNBYTES) + +#define DEV_BSHIFT 9 /* log2(DEV_BSIZE) */ +#define DEV_BSIZE (1 << DEV_BSHIFT) +#define BLKDEV_IOSIZE 2048 + +#ifndef MAXPHYS +#define MAXPHYS 65536 /* max I/O transfer size */ +#endif + +/* pages ("clicks") to disk blocks */ +#define ctod(x) ((x) << (PAGE_SHIFT - DEV_BSHIFT)) +#define dtoc(x) ((x) >> (PAGE_SHIFT - DEV_BSHIFT)) +/*#define dtob(x) ((x) << DEV_BSHIFT)*/ + +#define ctob(x) ((x) << PAGE_SHIFT) + +/* bytes to pages */ +#define btoc(x) (((x) + PAGE_MASK) >> PAGE_SHIFT) + +#define btodb(bytes) /* calculates (bytes / DEV_BSIZE) */ \ + ((bytes) >> DEV_BSHIFT) +#define dbtob(db) /* calculates (db * DEV_BSIZE) */ \ + ((db) << DEV_BSHIFT) + +/* + * Map a ``block device block'' to a file system block. + * This should be device dependent, and should use the bsize + * field from the disk label. + * For now though just use DEV_BSIZE. + */ +#define bdbtofsb(bn) ((bn) / (BLKDEV_IOSIZE / DEV_BSIZE)) + +/* + * Constants related to network buffer management. + * MCLBYTES must be no larger than NBPG (the software page size), and, + * on machines that exchange pages of input or output buffers with mbuf + * clusters (MAPPED_MBUFS), MCLBYTES must also be an integral multiple + * of the hardware page size. + */ +#define MSIZE 256 /* size of an mbuf */ + +#ifndef MCLSHIFT +#define MCLSHIFT 11 /* convert bytes to m_buf clusters */ + /* 2K cluster can hold Ether frame */ +#endif /* MCLSHIFT */ + +#define MCLBYTES (1 << MCLSHIFT) /* size of a m_buf cluster */ + +#define ovbcopy bcopy + +#ifdef _KERNEL +#ifdef _LOCORE +#include <machine/psl.h> +#else +#include <sys/param.h> +#include <machine/cpu.h> +#endif +#endif + +#endif /* _ARM_ARM_PARAM_H_ */ diff --git a/sys/arch/arm/include/pcb.h b/sys/arch/arm/include/pcb.h new file mode 100644 index 00000000000..d52c0893513 --- /dev/null +++ b/sys/arch/arm/include/pcb.h @@ -0,0 +1,115 @@ +/* $OpenBSD: pcb.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: pcb.h,v 1.10 2003/10/13 21:46:39 scw Exp $ */ + +/* + * Copyright (c) 2001 Matt Thomas <matt@3am-software.com>. + * Copyright (c) 1994 Mark Brinicombe. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the RiscBSD team. + * 4. The name "RiscBSD" nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARM_PCB_H_ +#define _ARM_PCB_H_ + +#include <machine/frame.h> +#include <machine/fp.h> + +#include <arm/pte.h> + +struct trapframe; + +struct pcb_arm32 { + paddr_t pcb32_pagedir; /* PT hooks */ + pd_entry_t *pcb32_pl1vec; /* PTR to vector_base L1 entry*/ + pd_entry_t pcb32_l1vec; /* Value to stuff on ctx sw */ + u_int pcb32_dacr; /* Domain Access Control Reg */ + void *pcb32_cstate; /* &pmap->pm_cstate */ + /* + * WARNING! + * cpuswitch.S relies on pcb32_r8 being quad-aligned in struct pcb + * (due to the use of "strd" when compiled for XSCALE) + */ + u_int pcb32_r8; /* used */ + u_int pcb32_r9; /* used */ + u_int pcb32_r10; /* used */ + u_int pcb32_r11; /* used */ + u_int pcb32_r12; /* used */ + u_int pcb32_sp; /* used */ + u_int pcb32_lr; + u_int pcb32_pc; + u_int pcb32_und_sp; +}; +#define pcb_pagedir pcb_un.un_32.pcb32_pagedir +#define pcb_pl1vec pcb_un.un_32.pcb32_pl1vec +#define pcb_l1vec pcb_un.un_32.pcb32_l1vec +#define pcb_dacr pcb_un.un_32.pcb32_dacr +#define pcb_cstate pcb_un.un_32.pcb32_cstate + +struct pcb_arm26 { + struct switchframe *pcb26_sf; +}; +#define pcb_sf pcb_un.un_26.pcb26_sf + +/* + * WARNING! + * See warning for struct pcb_arm32, above, before changing struct pcb! + */ +struct pcb { + u_int pcb_flags; +#define PCB_OWNFPU 0x00000001 +#define PCB_NOALIGNFLT 0x00000002 /* For COMPAT_15/EXEC_AOUT */ + struct trapframe *pcb_tf; + caddr_t pcb_onfault; /* On fault handler */ + union { + struct pcb_arm32 un_32; + struct pcb_arm26 un_26; + } pcb_un; + struct fpe_sp_state pcb_fpstate; /* Floating Point state */ +}; +#define pcb_ff pcb_fpstate /* for arm26 */ + +/* + * No additional data for core dumps. + */ +struct md_coredump { + int md_empty; +}; + +#ifdef _KERNEL +#ifdef _KERNEL_OPT +#include "opt_multiprocessor.h" +#endif +#ifdef MULTIPROCESSOR +#define curpcb (curcpu()->ci_curpcb) +#else +extern struct pcb *curpcb; +#endif +#endif /* _KERNEL */ + +#endif /* _ARM_PCB_H_ */ diff --git a/sys/arch/arm/include/pci_machdep.h b/sys/arch/arm/include/pci_machdep.h new file mode 100644 index 00000000000..2d67a3d9120 --- /dev/null +++ b/sys/arch/arm/include/pci_machdep.h @@ -0,0 +1,103 @@ +/* $OpenBSD: pci_machdep.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: pci_machdep.h,v 1.2 2002/05/15 19:23:52 thorpej Exp $ */ + +/* + * Modified for arm32 by Mark Brinicombe + * + * from: sys/arch/alpha/pci/pci_machdep.h + * + * Copyright (c) 1996 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +/* + * Machine-specific definitions for PCI autoconfiguration. + */ + +/* + * Types provided to machine-independent PCI code + */ +typedef struct arm32_pci_chipset *pci_chipset_tag_t; +typedef u_long pcitag_t; +typedef u_long pci_intr_handle_t; + +/* + * Forward declarations. + */ +struct pci_attach_args; + +/* + * arm32-specific PCI structure and type definitions. + * NOT TO BE USED DIRECTLY BY MACHINE INDEPENDENT CODE. + */ +struct arm32_pci_chipset { + void *pc_conf_v; + void (*pc_attach_hook)(struct device *, + struct device *, struct pcibus_attach_args *); + int (*pc_bus_maxdevs)(void *, int); + pcitag_t (*pc_make_tag)(void *, int, int, int); + void (*pc_decompose_tag)(void *, pcitag_t, int *, + int *, int *); + pcireg_t (*pc_conf_read)(void *, pcitag_t, int); + void (*pc_conf_write)(void *, pcitag_t, int, pcireg_t); + + void *pc_intr_v; + int (*pc_intr_map)(struct pci_attach_args *, + pci_intr_handle_t *); + const char *(*pc_intr_string)(void *, pci_intr_handle_t); + const struct evcnt *(*pc_intr_evcnt)(void *, pci_intr_handle_t); + void *(*pc_intr_establish)(void *, pci_intr_handle_t, + int, int (*)(void *), void *, char *); + void (*pc_intr_disestablish)(void *, void *); +}; + +/* + * Functions provided to machine-independent PCI code. + */ +#define pci_attach_hook(p, s, pba) \ + (*(pba)->pba_pc->pc_attach_hook)((p), (s), (pba)) +#define pci_bus_maxdevs(c, b) \ + (*(c)->pc_bus_maxdevs)((c)->pc_conf_v, (b)) +#define pci_make_tag(c, b, d, f) \ + (*(c)->pc_make_tag)((c)->pc_conf_v, (b), (d), (f)) +#define pci_decompose_tag(c, t, bp, dp, fp) \ + (*(c)->pc_decompose_tag)((c)->pc_conf_v, (t), (bp), (dp), (fp)) +#define pci_conf_read(c, t, r) \ + (*(c)->pc_conf_read)((c)->pc_conf_v, (t), (r)) +#define pci_conf_write(c, t, r, v) \ + (*(c)->pc_conf_write)((c)->pc_conf_v, (t), (r), (v)) +#define pci_intr_map(pa, ihp) \ + (*(pa)->pa_pc->pc_intr_map)((pa), (ihp)) +#define pci_intr_string(c, ih) \ + (*(c)->pc_intr_string)((c)->pc_intr_v, (ih)) +#define pci_intr_evcnt(c, ih) \ + (*(c)->pc_intr_evcnt)((c)->pc_intr_v, (ih)) +#define pci_intr_establish(c, ih, l, h, a, n) \ + (*(c)->pc_intr_establish)((c)->pc_intr_v, (ih), (l), (h), (a), (n)) +#define pci_intr_disestablish(c, iv) \ + (*(c)->pc_intr_disestablish)((c)->pc_intr_v, (iv)) + +#define pci_enumerate_bus(sc, m, p) \ + pci_enumerate_bus_generic((sc), (m), (p)) diff --git a/sys/arch/arm/include/pio.h b/sys/arch/arm/include/pio.h new file mode 100644 index 00000000000..280c3c2d4c5 --- /dev/null +++ b/sys/arch/arm/include/pio.h @@ -0,0 +1,47 @@ +/* $OpenBSD: pio.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: pio.h,v 1.1 2001/02/23 21:23:48 reinoud Exp $ */ + +/* + * Copyright 1997 + * Digital Equipment Corporation. All rights reserved. + * + * This software is furnished under license and may be used and + * copied only in accordance with the following terms and conditions. + * Subject to these conditions, you may download, copy, install, + * use, modify and distribute this software in source and/or binary + * form. No title or ownership is transferred hereby. + * + * 1) Any source code used, modified or distributed must reproduce + * and retain this copyright notice and list of conditions as + * they appear in the source file. + * + * 2) No right is granted to use any trade name, trademark, or logo of + * Digital Equipment Corporation. Neither the "Digital Equipment + * Corporation" name nor any trademark or logo of Digital Equipment + * Corporation may be used to endorse or promote products derived + * from this software without the prior written permission of + * Digital Equipment Corporation. + * + * 3) This software is provided "AS-IS" and any express or implied + * warranties, including but not limited to, any implied warranties + * of merchantability, fitness for a particular purpose, or + * non-infringement are disclaimed. In no event shall DIGITAL be + * liable for any damages whatsoever, and in particular, DIGITAL + * shall not be liable for special, indirect, consequential, or + * incidental damages or damages for lost profits, loss of + * revenue or loss of use, whether such damages arise in contract, + * negligence, tort, under statute, in equity, at law or otherwise, + * even if advised of the possibility of such damage. + */ + +#ifndef _ARM32_PIO_H_ +#define _ARM32_PIO_H_ + +#include <machine/bus.h> + +extern struct bus_space isa_io_bs_tag; + +#define inb(port) bus_space_read_1( &isa_io_bs_tag, (bus_space_handle_t)isa_io_bs_tag.bs_cookie, (port)) +#define outb(port, byte) bus_space_write_1(&isa_io_bs_tag, (bus_space_handle_t)isa_io_bs_tag.bs_cookie, (port), (byte)) + +#endif /* _ARM32_PIO_H_ */ diff --git a/sys/arch/arm/include/pmap.h b/sys/arch/arm/include/pmap.h new file mode 100644 index 00000000000..0261d72c332 --- /dev/null +++ b/sys/arch/arm/include/pmap.h @@ -0,0 +1,595 @@ +/* $OpenBSD: pmap.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: pmap.h,v 1.76 2003/09/06 09:10:46 rearnsha Exp $ */ + +/* + * Copyright (c) 2002, 2003 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Jason R. Thorpe & Steve C. Woodford for Wasabi Systems, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Copyright (c) 1994,1995 Mark Brinicombe. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Mark Brinicombe + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ARM32_PMAP_H_ +#define _ARM32_PMAP_H_ + +#ifdef _KERNEL + +#include <arm/cpuconf.h> +#include <arm/pte.h> +#ifndef _LOCORE +#include <arm/cpufunc.h> +#include <uvm/uvm_object.h> +#endif + +/* + * a pmap describes a processes' 4GB virtual address space. this + * virtual address space can be broken up into 4096 1MB regions which + * are described by L1 PTEs in the L1 table. + * + * There is a line drawn at KERNEL_BASE. Everything below that line + * changes when the VM context is switched. Everything above that line + * is the same no matter which VM context is running. This is achieved + * by making the L1 PTEs for those slots above KERNEL_BASE reference + * kernel L2 tables. + * + * The basic layout of the virtual address space thus looks like this: + * + * 0xffffffff + * . + * . + * . + * KERNEL_BASE + * -------------------- + * . + * . + * . + * 0x00000000 + */ + +/* + * The number of L2 descriptor tables which can be tracked by an l2_dtable. + * A bucket size of 16 provides for 16MB of contiguous virtual address + * space per l2_dtable. Most processes will, therefore, require only two or + * three of these to map their whole working set. + */ +#define L2_BUCKET_LOG2 4 +#define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) + +/* + * Given the above "L2-descriptors-per-l2_dtable" constant, the number + * of l2_dtable structures required to track all possible page descriptors + * mappable by an L1 translation table is given by the following constants: + */ +#define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2) +#define L2_SIZE (1 << L2_LOG2) + +#ifndef _LOCORE + +struct l1_ttable; +struct l2_dtable; + +/* + * Track cache/tlb occupancy using the following structure + */ +union pmap_cache_state { + struct { + union { + u_int8_t csu_cache_b[2]; + u_int16_t csu_cache; + } cs_cache_u; + + union { + u_int8_t csu_tlb_b[2]; + u_int16_t csu_tlb; + } cs_tlb_u; + } cs_s; + u_int32_t cs_all; +}; +#define cs_cache_id cs_s.cs_cache_u.csu_cache_b[0] +#define cs_cache_d cs_s.cs_cache_u.csu_cache_b[1] +#define cs_cache cs_s.cs_cache_u.csu_cache +#define cs_tlb_id cs_s.cs_tlb_u.csu_tlb_b[0] +#define cs_tlb_d cs_s.cs_tlb_u.csu_tlb_b[1] +#define cs_tlb cs_s.cs_tlb_u.csu_tlb + +/* + * Assigned to cs_all to force cacheops to work for a particular pmap + */ +#define PMAP_CACHE_STATE_ALL 0xffffffffu + +/* + * This structure is used by machine-dependent code to describe + * static mappings of devices, created at bootstrap time. + */ +struct pmap_devmap { + vaddr_t pd_va; /* virtual address */ + paddr_t pd_pa; /* physical address */ + psize_t pd_size; /* size of region */ + vm_prot_t pd_prot; /* protection code */ + int pd_cache; /* cache attributes */ +}; + +/* + * The pmap structure itself + */ +struct pmap { + u_int8_t pm_domain; + boolean_t pm_remove_all; + struct l1_ttable *pm_l1; + union pmap_cache_state pm_cstate; + struct uvm_object pm_obj; +#define pm_lock pm_obj.vmobjlock + struct l2_dtable *pm_l2[L2_SIZE]; + struct pmap_statistics pm_stats; + LIST_ENTRY(pmap) pm_list; +}; + +typedef struct pmap *pmap_t; + +/* + * Physical / virtual address structure. In a number of places (particularly + * during bootstrapping) we need to keep track of the physical and virtual + * addresses of various pages + */ +typedef struct pv_addr { + SLIST_ENTRY(pv_addr) pv_list; + paddr_t pv_pa; + vaddr_t pv_va; +} pv_addr_t; + +/* + * Determine various modes for PTEs (user vs. kernel, cacheable + * vs. non-cacheable). + */ +#define PTE_KERNEL 0 +#define PTE_USER 1 +#define PTE_NOCACHE 0 +#define PTE_CACHE 1 +#define PTE_PAGETABLE 2 + +/* + * Flags that indicate attributes of pages or mappings of pages. + * + * The PVF_MOD and PVF_REF flags are stored in the mdpage for each + * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual + * pv_entry's for each page. They live in the same "namespace" so + * that we can clear multiple attributes at a time. + * + * Note the "non-cacheable" flag generally means the page has + * multiple mappings in a given address space. + */ +#define PVF_MOD 0x01 /* page is modified */ +#define PVF_REF 0x02 /* page is referenced */ +#define PVF_WIRED 0x04 /* mapping is wired */ +#define PVF_WRITE 0x08 /* mapping is writable */ +#define PVF_EXEC 0x10 /* mapping is executable */ +#define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */ +#define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */ +#define PVF_NC (PVF_UNC|PVF_KNC) + +/* + * Commonly referenced structures + */ +extern struct pmap kernel_pmap_store; +extern int pmap_debug_level; /* Only exists if PMAP_DEBUG */ + +/* + * Macros that we need to export + */ +#define pmap_kernel() (&kernel_pmap_store) +#define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) +#define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) + +#define pmap_is_modified(pg) \ + (((pg)->mdpage.pvh_attrs & PVF_MOD) != 0) +#define pmap_is_referenced(pg) \ + (((pg)->mdpage.pvh_attrs & PVF_REF) != 0) + +#define pmap_copy(dp, sp, da, l, sa) /* nothing */ + +#define pmap_phys_address(ppn) (arm_ptob((ppn))) + +/* + * Functions that we need to export + */ +void pmap_procwr(struct proc *, vaddr_t, int); +void pmap_remove_all(pmap_t); +boolean_t pmap_extract(pmap_t, vaddr_t, paddr_t *); + +#define PMAP_NEED_PROCWR +#define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */ + +/* Functions we use internally. */ +void pmap_bootstrap(pd_entry_t *, vaddr_t, vaddr_t); + +int pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int); +boolean_t pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **); +boolean_t pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **); +void pmap_set_pcb_pagedir(pmap_t, struct pcb *); + +void pmap_debug(int); +void pmap_postinit(void); + +void vector_page_setprot(int); + +const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t); +const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t); + +/* Bootstrapping routines. */ +void pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int); +void pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int); +vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int); +void pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *); +void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *); +void pmap_devmap_register(const struct pmap_devmap *); + +/* + * Special page zero routine for use by the idle loop (no cache cleans). + */ +boolean_t pmap_pageidlezero(struct vm_page *); +#define PMAP_PAGEIDLEZERO(pg) pmap_pageidlezero((pg)) + +/* + * The current top of kernel VM + */ +extern vaddr_t pmap_curmaxkvaddr; + +/* + * Useful macros and constants + */ + +/* Virtual address to page table entry */ +static __inline pt_entry_t * +vtopte(vaddr_t va) +{ + pd_entry_t *pdep; + pt_entry_t *ptep; + + if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == FALSE) + return (NULL); + return (ptep); +} + +/* + * Virtual address to physical address + */ +static __inline paddr_t +vtophys(vaddr_t va) +{ + paddr_t pa; + + if (pmap_extract(pmap_kernel(), va, &pa) == FALSE) + return (0); /* XXXSCW: Panic? */ + + return (pa); +} + +/* + * The new pmap ensures that page-tables are always mapping Write-Thru. + * Thus, on some platforms we can run fast and loose and avoid syncing PTEs + * on every change. + * + * Unfortunately, not all CPUs have a write-through cache mode. So we + * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, + * and if there is the chance for PTE syncs to be needed, we define + * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) + * the code. + */ +extern int pmap_needs_pte_sync; +#if defined(_KERNEL_OPT) +/* + * StrongARM SA-1 caches do not have a write-through mode. So, on these, + * we need to do PTE syncs. If only SA-1 is configured, then evaluate + * this at compile time. + */ +#if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1) +#define PMAP_NEEDS_PTE_SYNC 1 +#define PMAP_INCLUDE_PTE_SYNC +#elif (ARM_MMU_SA1 == 0) +#define PMAP_NEEDS_PTE_SYNC 0 +#endif +#endif /* _KERNEL_OPT */ + +/* + * Provide a fallback in case we were not able to determine it at + * compile-time. + */ +#ifndef PMAP_NEEDS_PTE_SYNC +#define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync +#define PMAP_INCLUDE_PTE_SYNC +#endif + +#define PTE_SYNC(pte) \ +do { \ + if (PMAP_NEEDS_PTE_SYNC) \ + cpu_dcache_wb_range((vaddr_t)(pte), sizeof(pt_entry_t));\ +} while (/*CONSTCOND*/0) + +#define PTE_SYNC_RANGE(pte, cnt) \ +do { \ + if (PMAP_NEEDS_PTE_SYNC) { \ + cpu_dcache_wb_range((vaddr_t)(pte), \ + (cnt) << 2); /* * sizeof(pt_entry_t) */ \ + } \ +} while (/*CONSTCOND*/0) + +#define l1pte_valid(pde) ((pde) != 0) +#define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) +#define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) +#define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) + +#define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT) +#define l2pte_valid(pte) ((pte) != 0) +#define l2pte_pa(pte) ((pte) & L2_S_FRAME) +#define l2pte_minidata(pte) (((pte) & \ + (L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\ + == (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X))) + +/* L1 and L2 page table macros */ +#define pmap_pde_v(pde) l1pte_valid(*(pde)) +#define pmap_pde_section(pde) l1pte_section_p(*(pde)) +#define pmap_pde_page(pde) l1pte_page_p(*(pde)) +#define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) + +#define pmap_pte_v(pte) l2pte_valid(*(pte)) +#define pmap_pte_pa(pte) l2pte_pa(*(pte)) + +/* Size of the kernel part of the L1 page table */ +#define KERNEL_PD_SIZE \ + (L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t)) + +/************************* ARM MMU configuration *****************************/ + +#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 +void pmap_copy_page_generic(struct vm_page *, struct vm_page *); +void pmap_zero_page_generic(struct vm_page *); + +void pmap_pte_init_generic(void); +#if defined(CPU_ARM8) +void pmap_pte_init_arm8(void); +#endif +#if defined(CPU_ARM9) +void pmap_pte_init_arm9(void); +#endif /* CPU_ARM9 */ +#if defined(CPU_ARM10) +void pmap_pte_init_arm10(void); +#endif /* CPU_ARM10 */ +#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ + +#if ARM_MMU_SA1 == 1 +void pmap_pte_init_sa1(void); +#endif /* ARM_MMU_SA1 == 1 */ + +#if ARM_MMU_XSCALE == 1 +void pmap_copy_page_xscale(struct vm_page *, struct vm_page *); +void pmap_zero_page_xscale(struct vm_page *); + +void pmap_pte_init_xscale(void); + +void xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t); + +#define PMAP_UAREA(va) pmap_uarea(va) +void pmap_uarea(vaddr_t); +#endif /* ARM_MMU_XSCALE == 1 */ + +extern pt_entry_t pte_l1_s_cache_mode; +extern pt_entry_t pte_l1_s_cache_mask; + +extern pt_entry_t pte_l2_l_cache_mode; +extern pt_entry_t pte_l2_l_cache_mask; + +extern pt_entry_t pte_l2_s_cache_mode; +extern pt_entry_t pte_l2_s_cache_mask; + +extern pt_entry_t pte_l1_s_cache_mode_pt; +extern pt_entry_t pte_l2_l_cache_mode_pt; +extern pt_entry_t pte_l2_s_cache_mode_pt; + +extern pt_entry_t pte_l2_s_prot_u; +extern pt_entry_t pte_l2_s_prot_w; +extern pt_entry_t pte_l2_s_prot_mask; + +extern pt_entry_t pte_l1_s_proto; +extern pt_entry_t pte_l1_c_proto; +extern pt_entry_t pte_l2_s_proto; + +extern void (*pmap_copy_page_func)(struct vm_page *, struct vm_page *); +extern void (*pmap_zero_page_func)(struct vm_page *); + +#endif /* !_LOCORE */ + +/*****************************************************************************/ + +/* + * tell MI code that the cache is virtually-indexed *and* virtually-tagged. + */ +#define PMAP_CACHE_VIVT + +/* + * Definitions for MMU domains + */ +#define PMAP_DOMAINS 15 /* 15 'user' domains (0-14) */ +#define PMAP_DOMAIN_KERNEL 15 /* The kernel uses domain #15 */ + +/* + * These macros define the various bit masks in the PTE. + * + * We use these macros since we use different bits on different processor + * models. + */ +#define L1_S_PROT_U (L1_S_AP(AP_U)) +#define L1_S_PROT_W (L1_S_AP(AP_W)) +#define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W) + +#define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) +#define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)) + +#define L2_L_PROT_U (L2_AP(AP_U)) +#define L2_L_PROT_W (L2_AP(AP_W)) +#define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W) + +#define L2_L_CACHE_MASK_generic (L2_B|L2_C) +#define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X)) + +#define L2_S_PROT_U_generic (L2_AP(AP_U)) +#define L2_S_PROT_W_generic (L2_AP(AP_W)) +#define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W) + +#define L2_S_PROT_U_xscale (L2_AP0(AP_U)) +#define L2_S_PROT_W_xscale (L2_AP0(AP_W)) +#define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W) + +#define L2_S_CACHE_MASK_generic (L2_B|L2_C) +#define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)) + +#define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) +#define L1_S_PROTO_xscale (L1_TYPE_S) + +#define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) +#define L1_C_PROTO_xscale (L1_TYPE_C) + +#define L2_L_PROTO (L2_TYPE_L) + +#define L2_S_PROTO_generic (L2_TYPE_S) +#define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS) + +/* + * User-visible names for the ones that vary with MMU class. + */ + +#if ARM_NMMUS > 1 +/* More than one MMU class configured; use variables. */ +#define L2_S_PROT_U pte_l2_s_prot_u +#define L2_S_PROT_W pte_l2_s_prot_w +#define L2_S_PROT_MASK pte_l2_s_prot_mask + +#define L1_S_CACHE_MASK pte_l1_s_cache_mask +#define L2_L_CACHE_MASK pte_l2_l_cache_mask +#define L2_S_CACHE_MASK pte_l2_s_cache_mask + +#define L1_S_PROTO pte_l1_s_proto +#define L1_C_PROTO pte_l1_c_proto +#define L2_S_PROTO pte_l2_s_proto + +#define pmap_copy_page(s, d) (*pmap_copy_page_func)((s), (d)) +#define pmap_zero_page(d) (*pmap_zero_page_func)((d)) +#elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 +#define L2_S_PROT_U L2_S_PROT_U_generic +#define L2_S_PROT_W L2_S_PROT_W_generic +#define L2_S_PROT_MASK L2_S_PROT_MASK_generic + +#define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic +#define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic +#define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic + +#define L1_S_PROTO L1_S_PROTO_generic +#define L1_C_PROTO L1_C_PROTO_generic +#define L2_S_PROTO L2_S_PROTO_generic + +#define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) +#define pmap_zero_page(d) pmap_zero_page_generic((d)) +#elif ARM_MMU_XSCALE == 1 +#define L2_S_PROT_U L2_S_PROT_U_xscale +#define L2_S_PROT_W L2_S_PROT_W_xscale +#define L2_S_PROT_MASK L2_S_PROT_MASK_xscale + +#define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale +#define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale +#define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale + +#define L1_S_PROTO L1_S_PROTO_xscale +#define L1_C_PROTO L1_C_PROTO_xscale +#define L2_S_PROTO L2_S_PROTO_xscale + +#define pmap_copy_page(s, d) pmap_copy_page_xscale((s), (d)) +#define pmap_zero_page(d) pmap_zero_page_xscale((d)) +#endif /* ARM_NMMUS > 1 */ + +/* + * These macros return various bits based on kernel/user and protection. + * Note that the compiler will usually fold these at compile time. + */ +#define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ + (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0)) + +#define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ + (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0)) + +#define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ + (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0)) + +/* + * Macros to test if a mapping is mappable with an L1 Section mapping + * or an L2 Large Page mapping. + */ +#define L1_S_MAPPABLE_P(va, pa, size) \ + ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) + +#define L2_L_MAPPABLE_P(va, pa, size) \ + ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) + +/* + * Hooks for the pool allocator. + */ +#define POOL_VTOPHYS(va) vtophys((vaddr_t) (va)) + +#endif /* _KERNEL */ + +#endif /* _ARM32_PMAP_H_ */ diff --git a/sys/arch/arm/include/proc.h b/sys/arch/arm/include/proc.h new file mode 100644 index 00000000000..077559e4d8d --- /dev/null +++ b/sys/arch/arm/include/proc.h @@ -0,0 +1,51 @@ +/* $OpenBSD: proc.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: proc.h,v 1.5 2003/03/01 04:36:39 thorpej Exp $ */ + +/* + * Copyright (c) 1994 Mark Brinicombe. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the RiscBSD team. + * 4. The name "RiscBSD" nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARM32_PROC_H_ +#define _ARM32_PROC_H_ + +/* + * Machine-dependent part of the proc structure for arm. + */ + +struct trapframe; + +struct mdproc { + void (*md_syscall)(struct trapframe *, struct proc *, u_int32_t); + int pmc_enabled; /* bitfield of enabled counters */ + void *pmc_state; /* port-specific pmc state */ +}; + +#endif /* _ARM32_PROC_H_ */ diff --git a/sys/arch/arm/include/profile.h b/sys/arch/arm/include/profile.h new file mode 100644 index 00000000000..a15f022bff5 --- /dev/null +++ b/sys/arch/arm/include/profile.h @@ -0,0 +1,107 @@ +/* $OpenBSD: profile.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: profile.h,v 1.5 2002/03/24 15:49:40 bjh21 Exp $ */ + +/* + * Copyright (c) 2001 Ben Harris + * Copyright (c) 1995-1996 Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Mark Brinicombe. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#define _MCOUNT_DECL void _mcount + +/* + * Cannot implement mcount in C as GCC will trash the ip register when it + * pushes a trapframe. Pity we cannot insert assembly before the function + * prologue. + */ + +#ifdef __ELF__ +#define MCOUNT_ASM_NAME "__mcount" +#ifdef PIC +#define PLTSYM "(PLT)" +#endif +#else +#define MCOUNT_ASM_NAME "mcount" +#endif + +#ifndef PLTSYM +#define PLTSYM +#endif + +#define MCOUNT \ + __asm__(".text"); \ + __asm__(".align 0"); \ + __asm__(".type " MCOUNT_ASM_NAME ",%function"); \ + __asm__(".global " MCOUNT_ASM_NAME); \ + __asm__(MCOUNT_ASM_NAME ":"); \ + /* \ + * Preserve registers that are trashed during mcount \ + */ \ + __asm__("stmfd sp!, {r0-r3, ip, lr}"); \ + /* Check what mode we're in. EQ => 32, NE => 26 */ \ + __asm__("teq r0, r0"); \ + __asm__("teq pc, r15"); \ + /* \ + * find the return address for mcount, \ + * and the return address for mcount's caller. \ + * \ + * frompcindex = pc pushed by call into self. \ + */ \ + __asm__("moveq r0, ip"); \ + __asm__("bicne r0, ip, #0xfc000003"); \ + /* \ + * selfpc = pc pushed by mcount call \ + */ \ + __asm__("moveq r1, lr"); \ + __asm__("bicne r1, lr, #0xfc000003"); \ + /* \ + * Call the real mcount code \ + */ \ + __asm__("bl " __STRING(_mcount) PLTSYM); \ + /* \ + * Restore registers that were trashed during mcount \ + */ \ + __asm__("ldmfd sp!, {r0-r3, lr, pc}"); + +#ifdef _KERNEL +#ifdef __PROG26 +extern int int_off_save(void); +extern void int_restore(int); +#define MCOUNT_ENTER (s = int_off_save()) +#define MCOUNT_EXIT int_restore(s) +#else +#include <arm/cpufunc.h> +/* + * splhigh() and splx() are heavyweight, and call mcount(). Therefore + * we disabled interrupts (IRQ, but not FIQ) directly on the CPU. + * + * We're lucky that the CPSR and 's' both happen to be 'int's. + */ +#define MCOUNT_ENTER s = __set_cpsr_c(0x0080, 0x0080); /* kill IRQ */ +#define MCOUNT_EXIT __set_cpsr_c(0xffffffff, s); /* restore old value */ +#endif /* !acorn26 */ +#endif /* _KERNEL */ diff --git a/sys/arch/arm/include/pte.h b/sys/arch/arm/include/pte.h new file mode 100644 index 00000000000..f263fffc6cd --- /dev/null +++ b/sys/arch/arm/include/pte.h @@ -0,0 +1,246 @@ +/* $OpenBSD: pte.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: pte.h,v 1.6 2003/04/18 11:08:28 scw Exp $ */ + +/* + * Copyright (c) 2001, 2002 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Jason R. Thorpe for Wasabi Systems, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ARM_PTE_H_ +#define _ARM_PTE_H_ + +/* + * The ARM MMU architecture was introduced with ARM v3 (previous ARM + * architecture versions used an optional off-CPU memory controller + * to perform address translation). + * + * The ARM MMU consists of a TLB and translation table walking logic. + * There is typically one TLB per memory interface (or, put another + * way, one TLB per software-visible cache). + * + * The ARM MMU is capable of mapping memory in the following chunks: + * + * 1M Sections (L1 table) + * + * 64K Large Pages (L2 table) + * + * 4K Small Pages (L2 table) + * + * 1K Tiny Pages (L2 table) + * + * There are two types of L2 tables: Coarse Tables and Fine Tables. + * Coarse Tables can map Large and Small Pages. Fine Tables can + * map Tiny Pages. + * + * Coarse Tables can define 4 Subpages within Large and Small pages. + * Subpages define different permissions for each Subpage within + * a Page. + * + * Coarse Tables are 1K in length. Fine tables are 4K in length. + * + * The Translation Table Base register holds the pointer to the + * L1 Table. The L1 Table is a 16K contiguous chunk of memory + * aligned to a 16K boundary. Each entry in the L1 Table maps + * 1M of virtual address space, either via a Section mapping or + * via an L2 Table. + * + * In addition, the Fast Context Switching Extension (FCSE) is available + * on some ARM v4 and ARM v5 processors. FCSE is a way of eliminating + * TLB/cache flushes on context switch by use of a smaller address space + * and a "process ID" that modifies the virtual address before being + * presented to the translation logic. + */ + +#ifndef _LOCORE +typedef uint32_t pd_entry_t; /* L1 table entry */ +typedef uint32_t pt_entry_t; /* L2 table entry */ +#endif /* _LOCORE */ + +#define L1_S_SIZE 0x00100000 /* 1M */ +#define L1_S_OFFSET (L1_S_SIZE - 1) +#define L1_S_FRAME (~L1_S_OFFSET) +#define L1_S_SHIFT 20 + +#define L2_L_SIZE 0x00010000 /* 64K */ +#define L2_L_OFFSET (L2_L_SIZE - 1) +#define L2_L_FRAME (~L2_L_OFFSET) +#define L2_L_SHIFT 16 + +#define L2_S_SIZE 0x00001000 /* 4K */ +#define L2_S_OFFSET (L2_S_SIZE - 1) +#define L2_S_FRAME (~L2_S_OFFSET) +#define L2_S_SHIFT 12 + +#define L2_T_SIZE 0x00000400 /* 1K */ +#define L2_T_OFFSET (L2_T_SIZE - 1) +#define L2_T_FRAME (~L2_T_OFFSET) +#define L2_T_SHIFT 10 + +/* + * The NetBSD VM implementation only works on whole pages (4K), + * whereas the ARM MMU's Coarse tables are sized in terms of 1K + * (16K L1 table, 1K L2 table). + * + * So, we allocate L2 tables 4 at a time, thus yielding a 4K L2 + * table. + */ +#define L1_ADDR_BITS 0xfff00000 /* L1 PTE address bits */ +#define L2_ADDR_BITS 0x000ff000 /* L2 PTE address bits */ + +#define L1_TABLE_SIZE 0x4000 /* 16K */ +#define L2_TABLE_SIZE 0x1000 /* 4K */ +/* + * The new pmap deals with the 1KB coarse L2 tables by + * allocating them from a pool. Until every port has been converted, + * keep the old L2_TABLE_SIZE define lying around. Converted ports + * should use L2_TABLE_SIZE_REAL until then. + */ +#define L2_TABLE_SIZE_REAL 0x400 /* 1K */ + +/* + * ARM L1 Descriptors + */ + +#define L1_TYPE_INV 0x00 /* Invalid (fault) */ +#define L1_TYPE_C 0x01 /* Coarse L2 */ +#define L1_TYPE_S 0x02 /* Section */ +#define L1_TYPE_F 0x03 /* Fine L2 */ +#define L1_TYPE_MASK 0x03 /* mask of type bits */ + +/* L1 Section Descriptor */ +#define L1_S_B 0x00000004 /* bufferable Section */ +#define L1_S_C 0x00000008 /* cacheable Section */ +#define L1_S_IMP 0x00000010 /* implementation defined */ +#define L1_S_DOM(x) ((x) << 5) /* domain */ +#define L1_S_DOM_MASK L1_S_DOM(0xf) +#define L1_S_AP(x) ((x) << 10) /* access permissions */ +#define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */ + +#define L1_S_XSCALE_P 0x00000200 /* ECC enable for this section */ +#define L1_S_XSCALE_TEX(x) ((x) << 12) /* Type Extension */ + +/* L1 Coarse Descriptor */ +#define L1_C_IMP0 0x00000004 /* implementation defined */ +#define L1_C_IMP1 0x00000008 /* implementation defined */ +#define L1_C_IMP2 0x00000010 /* implementation defined */ +#define L1_C_DOM(x) ((x) << 5) /* domain */ +#define L1_C_DOM_MASK L1_C_DOM(0xf) +#define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */ + +#define L1_C_XSCALE_P 0x00000200 /* ECC enable for this section */ + +/* L1 Fine Descriptor */ +#define L1_F_IMP0 0x00000004 /* implementation defined */ +#define L1_F_IMP1 0x00000008 /* implementation defined */ +#define L1_F_IMP2 0x00000010 /* implementation defined */ +#define L1_F_DOM(x) ((x) << 5) /* domain */ +#define L1_F_DOM_MASK L1_F_DOM(0xf) +#define L1_F_ADDR_MASK 0xfffff000 /* phys address of L2 Table */ + +#define L1_F_XSCALE_P 0x00000200 /* ECC enable for this section */ + +/* + * ARM L2 Descriptors + */ + +#define L2_TYPE_INV 0x00 /* Invalid (fault) */ +#define L2_TYPE_L 0x01 /* Large Page */ +#define L2_TYPE_S 0x02 /* Small Page */ +#define L2_TYPE_T 0x03 /* Tiny Page */ +#define L2_TYPE_MASK 0x03 /* mask of type bits */ + + /* + * This L2 Descriptor type is available on XScale processors + * when using a Coarse L1 Descriptor. The Extended Small + * Descriptor has the same format as the XScale Tiny Descriptor, + * but describes a 4K page, rather than a 1K page. + */ +#define L2_TYPE_XSCALE_XS 0x03 /* XScale Extended Small Page */ + +#define L2_B 0x00000004 /* Bufferable page */ +#define L2_C 0x00000008 /* Cacheable page */ +#define L2_AP0(x) ((x) << 4) /* access permissions (sp 0) */ +#define L2_AP1(x) ((x) << 6) /* access permissions (sp 1) */ +#define L2_AP2(x) ((x) << 8) /* access permissions (sp 2) */ +#define L2_AP3(x) ((x) << 10) /* access permissions (sp 3) */ +#define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x)) + +#define L2_XSCALE_L_TEX(x) ((x) << 12) /* Type Extension */ +#define L2_XSCALE_T_TEX(x) ((x) << 6) /* Type Extension */ + +/* + * Access Permissions for L1 and L2 Descriptors. + */ +#define AP_W 0x01 /* writable */ +#define AP_U 0x02 /* user */ + +/* + * Short-hand for common AP_* constants. + * + * Note: These values assume the S (System) bit is set and + * the R (ROM) bit is clear in CP15 register 1. + */ +#define AP_KR 0x00 /* kernel read */ +#define AP_KRW 0x01 /* kernel read/write */ +#define AP_KRWUR 0x02 /* kernel read/write usr read */ +#define AP_KRWURW 0x03 /* kernel read/write usr read/write */ + +/* + * Domain Types for the Domain Access Control Register. + */ +#define DOMAIN_FAULT 0x00 /* no access */ +#define DOMAIN_CLIENT 0x01 /* client */ +#define DOMAIN_RESERVED 0x02 /* reserved */ +#define DOMAIN_MANAGER 0x03 /* manager */ + +/* + * Type Extension bits for XScale processors. + * + * Behavior of C and B when X == 0: + * + * C B Cacheable Bufferable Write Policy Line Allocate Policy + * 0 0 N N - - + * 0 1 N Y - - + * 1 0 Y Y Write-through Read Allocate + * 1 1 Y Y Write-back Read Allocate + * + * Behavior of C and B when X == 1: + * C B Cacheable Bufferable Write Policy Line Allocate Policy + * 0 0 - - - - DO NOT USE + * 0 1 N Y - - + * 1 0 Mini-Data - - - + * 1 1 Y Y Write-back R/W Allocate + */ +#define TEX_XSCALE_X 0x01 /* X modifies C and B */ + +#endif /* _ARM_PTE_H_ */ diff --git a/sys/arch/arm/include/ptrace.h b/sys/arch/arm/include/ptrace.h new file mode 100644 index 00000000000..d0a556e41bc --- /dev/null +++ b/sys/arch/arm/include/ptrace.h @@ -0,0 +1,44 @@ +/* $OpenBSD: ptrace.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: ptrace.h,v 1.2 2001/10/19 00:18:20 bjh21 Exp $ */ + +/* + * Copyright (c) 1995 Frank Lancaster + * Copyright (c) 1995 Tools GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Christopher G. Demetriou. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * arm-dependent ptrace definitions + */ +#ifndef _KERNEL +#define PT_STEP (PT_FIRSTMACH + 0) /* Not implemented */ +#endif +#define PT_GETREGS (PT_FIRSTMACH + 1) +#define PT_SETREGS (PT_FIRSTMACH + 2) +#define PT_GETFPREGS (PT_FIRSTMACH + 3) +#define PT_SETFPREGS (PT_FIRSTMACH + 4) diff --git a/sys/arch/arm/include/reg.h b/sys/arch/arm/include/reg.h new file mode 100644 index 00000000000..28c1b43b26e --- /dev/null +++ b/sys/arch/arm/include/reg.h @@ -0,0 +1,55 @@ +/* $OpenBSD: reg.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: reg.h,v 1.1 2001/02/11 14:51:55 bjh21 Exp $ */ + +/* + * Copyright (C) 1994, 1995 Frank Lancaster + * Copyright (C) 1994, 1995 TooLs GmbH. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by TooLs GmbH. + * 4. The name of TooLs GmbH may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @(#)reg.h 5.5 (Berkeley) 1/18/91 + */ + +#ifndef _ARM32_REG_H_ +#define _ARM32_REG_H_ + +#include <machine/fp.h> + +struct reg { + unsigned int r[13]; + unsigned int r_sp; + unsigned int r_lr; + unsigned int r_pc; + unsigned int r_cpsr; +}; + +struct fpreg { + unsigned int fpr_fpsr; + fp_reg_t fpr[8]; +}; + +#endif /* !_ARM32_REG_H_ */ diff --git a/sys/arch/arm/include/reloc.h b/sys/arch/arm/include/reloc.h new file mode 100644 index 00000000000..f53ab524f26 --- /dev/null +++ b/sys/arch/arm/include/reloc.h @@ -0,0 +1,53 @@ +/* Processor specific relocation types */ + +#define R_ARM_NONE 0 +#define R_ARM_PC24 1 +#define R_ARM_ABS32 2 +#define R_ARM_REL32 3 +#define R_ARM_PC13 4 +#define R_ARM_ABS16 5 +#define R_ARM_ABS12 6 +#define R_ARM_THM_ABS5 7 +#define R_ARM_ABS8 8 +#define R_ARM_SBREL32 9 +#define R_ARM_THM_PC22 10 +#define R_ARM_THM_PC8 11 +#define R_ARM_AMP_VCALL9 12 +#define R_ARM_SWI24 13 +#define R_ARM_THM_SWI8 14 +#define R_ARM_XPC25 15 +#define R_ARM_THM_XPC22 16 + +/* 17-31 are reserved for ARM Linux. */ +#define R_ARM_COPY 20 +#define R_ARM_GLOB_DAT 21 +#define R_ARM_JUMP_SLOT 22 +#define R_ARM_RELATIVE 23 +#define R_ARM_GOTOFF 24 +#define R_ARM_GOTPC 25 +#define R_ARM_GOT32 26 +#define R_ARM_PLT32 27 + +#define R_ARM_ALU_PCREL_7_0 32 +#define R_ARM_ALU_PCREL_15_8 33 +#define R_ARM_ALU_PCREL_23_15 34 +#define R_ARM_ALU_SBREL_11_0 35 +#define R_ARM_ALU_SBREL_19_12 36 +#define R_ARM_ALU_SBREL_27_20 37 + +/* 96-111 are reserved to G++. */ +#define R_ARM_GNU_VTENTRY 100 +#define R_ARM_GNU_VTINHERIT 101 +#define R_ARM_THM_PC11 102 +#define R_ARM_THM_PC9 103 + +/* 112-127 are reserved for private experiments. */ + +#define R_ARM_RXPC25 249 +#define R_ARM_RSBREL32 250 +#define R_ARM_THM_RPC22 251 +#define R_ARM_RREL32 252 +#define R_ARM_RABS32 253 +#define R_ARM_RPC24 254 +#define R_ARM_RBASE 255 + diff --git a/sys/arch/arm/include/rtc.h b/sys/arch/arm/include/rtc.h new file mode 100644 index 00000000000..6c6a1666d52 --- /dev/null +++ b/sys/arch/arm/include/rtc.h @@ -0,0 +1,84 @@ +/* $OpenBSD: rtc.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: rtc.h,v 1.1 2001/02/23 21:23:50 reinoud Exp $ */ + +/* + * Copyright (c) 1994 Mark Brinicombe. + * Copyright (c) 1994 Brini. + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * RiscBSD kernel project + * + * rtc.h + * + * Header file for RTC / CMOS stuff + * + * Created : 13/10/94 + * Updated : 15/07/2000 + * + * Based of kate/display/iiccontrol.c + */ + +/* + * IIC addresses for RTC chip + * Two PCF8583 chips are supported on the IIC bus + */ + +#define IIC_PCF8583_MASK 0xfc +#define IIC_PCF8583_ADDR 0xa0 + +#define RTC_Write (IIC_PCF8583_ADDR | IIC_WRITE) +#define RTC_Read (IIC_PCF8583_ADDR | IIC_READ) + +typedef struct { + u_char rtc_micro; + u_char rtc_centi; + u_char rtc_sec; + u_char rtc_min; + u_char rtc_hour; + u_char rtc_day; + u_char rtc_mon; + u_char rtc_year; + u_char rtc_cen; +} rtc_t; + +#define RTC_ADDR_CHECKSUM 0x3f +#define RTC_ADDR_BOOTOPTS 0x90 +#define RTC_ADDR_REBOOTCNT 0x91 +#define RTC_ADDR_YEAR 0xc0 +#define RTC_ADDR_CENT 0xc1 + +#ifdef _KERNEL +int cmos_read __P((int)); +int cmos_write __P((int, int)); +#endif /* _KERNEL */ + +/* End of rtc.h */ diff --git a/sys/arch/arm/include/setjmp.h b/sys/arch/arm/include/setjmp.h new file mode 100644 index 00000000000..f20cab2e929 --- /dev/null +++ b/sys/arch/arm/include/setjmp.h @@ -0,0 +1,87 @@ +/* $OpenBSD: setjmp.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: setjmp.h,v 1.2 2001/08/25 14:45:59 bjh21 Exp $ */ + +/* + * machine/setjmp.h: machine dependent setjmp-related information. + */ + +#ifdef __ELF__ +#define _JBLEN 64 /* size, in longs, of a jmp_buf */ +#else +#define _JBLEN 29 /* size, in longs, of a jmp_buf */ +#endif + +/* + * NOTE: The internal structure of a jmp_buf is *PRIVATE* + * This information is provided as there is software + * that fiddles with this with obtain the stack pointer + * (yes really ! and its commercial !). + * + * Description of the setjmp buffer + * + * word 0 magic number (dependant on creator) + * 1 - 3 f4 fp register 4 + * 4 - 6 f5 fp register 5 + * 7 - 9 f6 fp register 6 + * 10 - 12 f7 fp register 7 + * 13 fpsr fp status register + * 14 r4 register 4 + * 15 r5 register 5 + * 16 r6 register 6 + * 17 r7 register 7 + * 18 r8 register 8 + * 19 r9 register 9 + * 20 r10 register 10 (sl) + * 21 r11 register 11 (fp) + * 22 r12 register 12 (ip) + * 23 r13 register 13 (sp) + * 24 r14 register 14 (lr) + * 25 signal mask (dependant on magic) + * 26 (con't) + * 27 (con't) + * 28 (con't) + * + * The magic number number identifies the jmp_buf and + * how the buffer was created as well as providing + * a sanity check + * + * A side note I should mention - Please do not tamper + * with the floating point fields. While they are + * always saved and restored at the moment this cannot + * be garenteed especially if the compiler happens + * to be generating soft-float code so no fp + * registers will be used. + * + * Whilst this can be seen an encouraging people to + * use the setjmp buffer in this way I think that it + * is for the best then if changes occur compiles will + * break rather than just having new builds falling over + * mysteriously. + */ + +#define _JB_MAGIC__SETJMP 0x4278f500 +#define _JB_MAGIC_SETJMP 0x4278f501 + +/* Valid for all jmp_buf's */ + +#define _JB_MAGIC 0 +#define _JB_REG_F4 1 +#define _JB_REG_F5 4 +#define _JB_REG_F6 7 +#define _JB_REG_F7 10 +#define _JB_REG_FPSR 13 +#define _JB_REG_R4 14 +#define _JB_REG_R5 15 +#define _JB_REG_R6 16 +#define _JB_REG_R7 17 +#define _JB_REG_R8 18 +#define _JB_REG_R9 19 +#define _JB_REG_R10 20 +#define _JB_REG_R11 21 +#define _JB_REG_R12 22 +#define _JB_REG_R13 23 +#define _JB_REG_R14 24 + +/* Only valid with the _JB_MAGIC_SETJMP magic */ + +#define _JB_SIGMASK 25 diff --git a/sys/arch/arm/include/signal.h b/sys/arch/arm/include/signal.h new file mode 100644 index 00000000000..d0d5122166d --- /dev/null +++ b/sys/arch/arm/include/signal.h @@ -0,0 +1,134 @@ +/* $OpenBSD: signal.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: signal.h,v 1.5 2003/10/18 17:57:21 briggs Exp $ */ + +/* + * Copyright (c) 1994-1996 Mark Brinicombe. + * Copyright (c) 1994 Brini. + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * RiscBSD kernel project + * + * signal.h + * + * Architecture dependant signal types and structures + * + * Created : 30/09/94 + */ + +#ifndef _ARM32_SIGNAL_H_ +#define _ARM32_SIGNAL_H_ + +#ifndef _LOCORE +typedef int sig_atomic_t; +#endif + +#define __HAVE_SIGINFO + + +#ifndef _LOCORE +/* + * Information pushed on stack when a signal is delivered. + * This is used by the kernel to restore state following + * execution of the signal handler. It is also made available + * to the handler to allow it to restore state properly if + * a non-standard exit is performed. + */ + +struct sigcontext { + int sc_onstack; /* sigstack state to restore */ + int sc_mask; /* signal mask to restore (old style) */ + + unsigned int sc_spsr; + unsigned int sc_r0; + unsigned int sc_r1; + unsigned int sc_r2; + unsigned int sc_r3; + unsigned int sc_r4; + unsigned int sc_r5; + unsigned int sc_r6; + unsigned int sc_r7; + unsigned int sc_r8; + unsigned int sc_r9; + unsigned int sc_r10; + unsigned int sc_r11; + unsigned int sc_r12; + unsigned int sc_usr_sp; + unsigned int sc_usr_lr; + unsigned int sc_svc_lr; + unsigned int sc_pc; + +#if 0 + sigset_t sc_mask; /* signal mask to restore (new style) */ +#endif +}; + +#endif /* !_LOCORE */ + +/* Signals codes */ + +/* + * SIGFPE codes + * + * see ieeefp.h for definition of FP exception codes + */ + +#define SIG_CODE_FPE_CODE_MASK 0x00000f00 /* Mask for exception code */ +#define SIG_CODE_FPE_CODE_SHIFT 8 /* Shift for exception code */ +#define SIG_CODE_FPE_TYPE_MASK 0x000000ff /* Mask for specific code */ + +/* + * SIGILL codes + * + * the signal code is the instruction that raised the signal + */ + +/* + * SIGBUS and SIGSEGV codes + * + * The signal code is combination of the fault address and the fault code. + * + * The fault code is the coproc #15 fault status code + * + * The exception to this is a SIGBUS or SIGSEGV from a prefetch abort. + * In this case the fault status code is not valid so the TYPE_MASK + * should be treated as undefined (in practice it is the bottom 4 bits + * of the fault address). + */ + +#define SIG_CODE_BUS_ADDR_MASK 0xfffffff0 +#define SIG_CODE_BUS_TYPE_MASK 0x0000000f +#define SIG_CODE_SEGV_ADDR_MASK SIG_CODE_BUS_ADDR_MASK +#define SIG_CODE_SEGV_TYPE_MASK SIG_CODE_BUS_TYPE_MASK + +#endif /* !_ARM_SIGNAL_H_ */ + +/* End of signal.h */ diff --git a/sys/arch/arm/include/softintr.h b/sys/arch/arm/include/softintr.h new file mode 100644 index 00000000000..fdd618dc841 --- /dev/null +++ b/sys/arch/arm/include/softintr.h @@ -0,0 +1,106 @@ +/* $OpenBSD: softintr.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: softintr.h,v 1.1 2002/01/29 22:54:14 thorpej Exp $ */ + +/* + * Copyright (c) 2001 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Jason R. Thorpe for Wasabi Systems, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ARM_SOFTINTR_H_ +#define _ARM_SOFTINTR_H_ + +#ifdef _KERNEL + +/* + * Generic software interrupt support for all ARM platforms. + * + * To use this code, include <arm/softintr.h> from your platform's + * <machine/intr.h>. + */ + +#define SI_SOFT 0 /* for IPL_SOFT */ +#define SI_SOFTCLOCK 1 /* for IPL_SOFTCLOCK */ +#define SI_SOFTNET 2 /* for IPL_SOFTNET */ +#define SI_SOFTSERIAL 3 /* for IPL_SOFTSERIAL */ + +#define SI_NQUEUES 4 + +#define SI_QUEUENAMES { \ + "generic", \ + "clock", \ + "net", \ + "serial", \ +} + +struct soft_intrhand { + TAILQ_ENTRY(soft_intrhand) sih_list; + void (*sih_func)(void *); + void *sih_arg; + struct soft_intrq *sih_siq; + int sih_pending; +}; + +struct soft_intrq { + TAILQ_HEAD(, soft_intrhand) siq_list; + struct evcnt siq_evcnt; + int siq_si; +}; + +void *softintr_establish(int, void (*)(void *), void *); +void softintr_disestablish(void *); +void softintr_init(void); +void softintr_dispatch(int); + +#define softintr_schedule(arg) \ +do { \ + struct soft_intrhand *__sih = (arg); \ + struct soft_intrq *__siq = __sih->sih_siq; \ + int __s; \ + \ + __s = splhigh(); \ + if (__sih->sih_pending == 0) { \ + TAILQ_INSERT_TAIL(&__siq->siq_list, __sih, sih_list); \ + __sih->sih_pending = 1; \ + _setsoftintr(__siq->siq_si); \ + } \ + splx(__s); \ +} while (/*CONSTCOND*/0) + +/* XXX For legacy software interrupts. */ +extern struct soft_intrhand *softnet_intrhand; + +#define setsoftnet() softintr_schedule(softnet_intrhand) + +#endif /* _KERNEL */ + +#endif /* _ARM_SOFTINTR_H_ */ diff --git a/sys/arch/arm/include/spinlock.h b/sys/arch/arm/include/spinlock.h new file mode 100644 index 00000000000..5b68222836d --- /dev/null +++ b/sys/arch/arm/include/spinlock.h @@ -0,0 +1,10 @@ +/* $OpenBSD: spinlock.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ + +#ifndef _ARM_SPINLOCK_H_ +#define _ARM_SPINLOCK_H_ + +#define _SPINLOCK_UNLOCKED (0) +#define _SPINLOCK_LOCKED (1) +typedef int _spinlock_lock_t; + +#endif diff --git a/sys/arch/arm/include/swi.h b/sys/arch/arm/include/swi.h new file mode 100644 index 00000000000..19a0145ab92 --- /dev/null +++ b/sys/arch/arm/include/swi.h @@ -0,0 +1,23 @@ +/* $OpenBSD: swi.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: swi.h,v 1.1 2002/01/13 15:03:06 bjh21 Exp $ */ + +/* + * This file is in the Public Domain. + * Ben Harris, 2002. + */ + +#ifndef _ARM_SWI_H_ +#define _ARM_SWI_H_ + +#define SWI_OS_MASK 0xf00000 +#define SWI_OS_RISCOS 0x000000 +#define SWI_OS_RISCIX 0x800000 +#define SWI_OS_LINUX 0x900000 +#define SWI_OS_NETBSD 0xa00000 +#define SWI_OS_ARM 0xf00000 + +#define SWI_IMB 0xf00000 +#define SWI_IMBrange 0xf00001 + +#endif + diff --git a/sys/arch/arm/include/sysarch.h b/sys/arch/arm/include/sysarch.h new file mode 100644 index 00000000000..b379abbecd3 --- /dev/null +++ b/sys/arch/arm/include/sysarch.h @@ -0,0 +1,61 @@ +/* $OpenBSD: sysarch.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: sysarch.h,v 1.4 2002/03/30 06:23:39 thorpej Exp $ */ + +/* + * Copyright (c) 1996-1997 Mark Brinicombe. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Mark Brinicombe. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARM_SYSARCH_H_ +#define _ARM_SYSARCH_H_ + +#include <sys/cdefs.h> + +/* + * Architecture specific syscalls (arm) + */ + +#define ARM_SYNC_ICACHE 0 +#define ARM_DRAIN_WRITEBUF 1 + +struct arm_sync_icache_args { + u_int32_t addr; /* Virtual start address */ + size_t len; /* Region size */ +}; + +#ifndef _KERNEL +__BEGIN_DECLS +int arm_sync_icache __P((u_int addr, int len)); +int arm_drain_writebuf __P((void)); +int sysarch __P((int, void *)); +__END_DECLS +#endif + +#endif /* !_ARM_SYSARCH_H_ */ diff --git a/sys/arch/arm/include/trap.h b/sys/arch/arm/include/trap.h new file mode 100644 index 00000000000..d6346a42ef4 --- /dev/null +++ b/sys/arch/arm/include/trap.h @@ -0,0 +1,71 @@ +/* $OpenBSD: trap.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: trap.h,v 1.4 2003/04/28 01:54:50 briggs Exp $ */ + +/* + * Copyright (c) 1995 Mark Brinicombe. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Mark Brinicombe. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * RiscBSD kernel project + * + * trap.h + * + * Various trap definitions + */ + +/* + * Instructions used for breakpoints. + * + * These are undefined instructions. + * Technically the userspace breakpoint could be a SWI but we want to + * keep this the same as IPKDB which needs an undefined instruction as + * a break point. + * + * Ideally ARM would define several standard instruction sequences for + * use as breakpoints. + * + * The BKPT instruction isn't much use to us, since its behaviour is + * unpredictable on ARMv3 and lower. + * + * The ARM ARM says that for maximum compatibility, we should use undefined + * instructions that look like 0x.7f...f. . + */ + +#define GDB_BREAKPOINT 0xe6000011 /* Used by GDB 4.x */ +#define IPKDB_BREAKPOINT 0xe6000010 /* Used by IPKDB */ +#define GDB5_BREAKPOINT 0xe7ffdefe /* Used by GDB 5.0 */ +#define KERNEL_BREAKPOINT 0xe7ffffff /* Used by DDB */ + +#define KBPT_ASM ".word 0xe7ffdefe" + +#define USER_BREAKPOINT GDB_BREAKPOINT + +#define T_FAULT 1 + +/* End of trap.h */ diff --git a/sys/arch/arm/include/types.h b/sys/arch/arm/include/types.h new file mode 100644 index 00000000000..d14f21478f0 --- /dev/null +++ b/sys/arch/arm/include/types.h @@ -0,0 +1,119 @@ +/* $OpenBSD: types.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: types.h,v 1.4 2002/02/28 03:17:25 simonb Exp $ */ + +/* + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: @(#)types.h 7.5 (Berkeley) 3/9/91 + */ + +#ifndef _ARM_TYPES_H_ +#define _ARM_TYPES_H_ + +/* OpenBSD only supports arm32 */ +#ifdef _KERNEL +#define __PROG32 /* indicate 32-bit mode */ +#endif + +#include <sys/cdefs.h> + +#if defined(_KERNEL) +typedef struct label_t { /* Used by setjmp & longjmp */ + int val[11]; +} label_t; +#endif + +/* NB: This should probably be if defined(_KERNEL) */ +#if !defined(_POSIX_C_SOURCE) && !defined(_XOPEN_SOURCE) +typedef unsigned long vm_offset_t; +typedef unsigned long vm_size_t; + +typedef vm_offset_t paddr_t; +typedef vm_size_t psize_t; +typedef vm_offset_t vaddr_t; +typedef vm_size_t vsize_t; +#endif + +#define __HAVE_MINIMAL_EMUL + +/* + * Basic integral types. Omit the typedef if + * not possible for a machine/compiler combination. + */ +#define __BIT_TYPES_DEFINED__ +typedef __signed char int8_t; +typedef unsigned char u_int8_t; +typedef unsigned char uint8_t; +typedef short int16_t; +typedef unsigned short u_int16_t; +typedef unsigned short uint16_t; +typedef int int32_t; +typedef unsigned int u_int32_t; +typedef unsigned int uint32_t; +/* LONGLONG */ +typedef long long int64_t; +/* LONGLONG */ +typedef unsigned long long u_int64_t; +/* LONGLONG */ +typedef unsigned long long uint64_t; + +typedef int32_t register_t; + +/* + * 7.18.1 Integer types + */ + +/* 7.18.1.1 Exact-width integer types */ + +typedef __signed char __int8_t; +typedef unsigned char __uint8_t; +typedef short int __int16_t; +typedef unsigned short int __uint16_t; +typedef int __int32_t; +typedef unsigned int __uint32_t; +#ifdef __COMPILER_INT64__ +typedef __COMPILER_INT64__ __int64_t; +typedef __COMPILER_UINT64__ __uint64_t; +#else +/* LONGLONG */ +typedef long long int __int64_t; +/* LONGLONG */ +typedef unsigned long long int __uint64_t; +#endif + + +/* 7.18.1.4 Integer types capable of holding object pointers */ + +typedef long int __intptr_t; +typedef unsigned long int __uintptr_t; + +#endif /* _ARM_TYPES_H_ */ diff --git a/sys/arch/arm/include/undefined.h b/sys/arch/arm/include/undefined.h new file mode 100644 index 00000000000..dfb22764ed7 --- /dev/null +++ b/sys/arch/arm/include/undefined.h @@ -0,0 +1,89 @@ +/* $OpenBSD: undefined.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: undefined.h,v 1.4 2001/12/20 01:20:23 thorpej Exp $ */ + +/* + * Copyright (c) 1995-1996 Mark Brinicombe. + * Copyright (c) 1995 Brini. + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * RiscBSD kernel project + * + * undefined.h + * + * Undefined instruction types, symbols and prototypes + * + * Created : 08/02/95 + */ + + +#ifndef _ARM_UNDEFINED_H_ +#define _ARM_UNDEFINED_H_ +#ifdef _KERNEL + +#include <sys/queue.h> + +typedef int (*undef_handler_t) __P((unsigned int, unsigned int, trapframe_t *, int)); + +#define FP_COPROC 1 +#define FP_COPROC2 2 +#define MAX_COPROCS 16 + +/* Prototypes for undefined.c */ + +void *install_coproc_handler __P((int, undef_handler_t)); +void remove_coproc_handler __P((void *)); +void undefined_init __P((void)); + +/* + * XXX Stuff below here is for use before malloc() is available. Most code + * shouldn't use it. + */ + +struct undefined_handler { + LIST_ENTRY(undefined_handler) uh_link; + undef_handler_t uh_handler; +}; + +/* + * Handlers installed using install_coproc_handler_static shouldn't be + * removed. + */ +void install_coproc_handler_static __P((int, struct undefined_handler *)); + +/* Calls up to undefined.c from trap handlers */ +void undefinedinstruction(struct trapframe *); + +#endif + +/* End of undefined.h */ + +#endif /* _ARM_UNDEFINED_H_ */ diff --git a/sys/arch/arm/include/vmparam.h b/sys/arch/arm/include/vmparam.h new file mode 100644 index 00000000000..3a6aebc4b26 --- /dev/null +++ b/sys/arch/arm/include/vmparam.h @@ -0,0 +1,152 @@ +/* $OpenBSD: vmparam.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: vmparam.h,v 1.18 2003/05/21 18:04:44 thorpej Exp $ */ + +/* + * Copyright (c) 2001, 2002 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Jason R. Thorpe for Wasabi Systems, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ARM_ARM_VMPARAM_H_ +#define _ARM_ARM_VMPARAM_H_ + +#ifdef _KERNEL + +/* + * Virtual Memory parameters common to all arm32 platforms. + */ + +#include <sys/lock.h> /* struct simplelock */ +#include <arm/pte.h> /* pt_entry_t */ +#endif /* _KERNEL */ + +#define USRTEXT VM_MIN_ADDRESS +#define USRSTACK VM_MAXUSER_ADDRESS +#define KERNBASE VM_MAXUSER_ADDRESS + +/* + * The time for a process to be blocked before being very swappable. + * This is a number of seconds which the system takes as being a non-trivial + * amount of real time. You probably shouldn't change this; + * it is used in subtle ways (fractions and multiples of it are, that is, like + * half of a ``long time'', almost a long time, etc.) + * It is related to human patience and other factors which don't really + * change over time. + */ +#define MAXSLP 20 + +/* + * Note that MAXTSIZ can't be larger than 32M, otherwise the compiler + * would have to be changed to not generate "bl" instructions. + */ +#define MAXTSIZ (16*1024*1024) /* max text size */ +#ifndef DFLDSIZ +#define DFLDSIZ (128*1024*1024) /* initial data size limit */ +#endif +#ifndef MAXDSIZ +#define MAXDSIZ (512*1024*1024) /* max data size */ +#endif +#ifndef DFLSSIZ +#define DFLSSIZ (2*1024*1024) /* initial stack size limit */ +#endif +#ifndef MAXSSIZ +#define MAXSSIZ (8*1024*1024) /* max stack size */ +#endif + +/* + * Size of SysV shared memory map + */ +#ifndef SHMMAXPGS +#define SHMMAXPGS 1024 +#endif + +/* + * While the ARM architecture defines Section mappings, large pages, + * and small pages, the standard page size is (and will always be) 4K. + */ +#define PAGE_SHIFT 12 +#define PAGE_SIZE (1 << PAGE_SHIFT) /* bytes/page */ +#define PAGE_MASK (PAGE_SIZE - 1) + +/* + * Mach derived constants + */ +#define VM_MIN_ADDRESS ((vaddr_t) 0x00001000) +#define VM_MAXUSER_ADDRESS ((vaddr_t) ARM_KERNEL_BASE) +#define VM_MAX_ADDRESS VM_MAXUSER_ADDRESS + +#define VM_MIN_KERNEL_ADDRESS ((vaddr_t) ARM_KERNEL_BASE) +#define VM_MAX_KERNEL_ADDRESS ((vaddr_t) 0xffffffff) + +#ifdef _KERNEL + +/* XXX max. amount of KVM to be used by buffers. */ +#ifndef VM_MAX_KERNEL_BUF +extern vaddr_t virtual_avail; +extern vaddr_t virtual_end; + +#define VM_MAX_KERNEL_BUF \ + ((virtual_end - virtual_avail) * 4 / 10) +#endif + +/* + * pmap-specific data store in the vm_page structure. + */ +#define __HAVE_VM_PAGE_MD +struct vm_page_md { + struct pv_entry *pvh_list; /* pv_entry list */ + struct simplelock pvh_slock; /* lock on this head */ + int pvh_attrs; /* page attributes */ + u_int uro_mappings; + u_int urw_mappings; + union { + u_short s_mappings[2]; /* Assume kernel count <= 65535 */ + u_int i_mappings; + } k_u; +#define kro_mappings k_u.s_mappings[0] +#define krw_mappings k_u.s_mappings[1] +#define k_mappings k_u.i_mappings +}; + +#define VM_MDPAGE_INIT(pg) \ +do { \ + (pg)->mdpage.pvh_list = NULL; \ + simple_lock_init(&(pg)->mdpage.pvh_slock); \ + (pg)->mdpage.pvh_attrs = 0; \ + (pg)->mdpage.uro_mappings = 0; \ + (pg)->mdpage.urw_mappings = 0; \ + (pg)->mdpage.k_mappings = 0; \ +} while (/*CONSTCOND*/0) + +#endif /* _KERNEL */ + +#endif /* _ARM_ARM_VMPARAM_H_ */ |