summaryrefslogtreecommitdiff
path: root/sys/arch/arm/xscale
diff options
context:
space:
mode:
Diffstat (limited to 'sys/arch/arm/xscale')
-rw-r--r--sys/arch/arm/xscale/i80321_clock.c4
-rw-r--r--sys/arch/arm/xscale/i80321_intr.c20
-rw-r--r--sys/arch/arm/xscale/i80321_pci.c4
-rw-r--r--sys/arch/arm/xscale/pxa2x0.c4
-rw-r--r--sys/arch/arm/xscale/pxa2x0_apm.c6
-rw-r--r--sys/arch/arm/xscale/pxa2x0_apm_asm.S30
-rw-r--r--sys/arch/arm/xscale/pxa2x0_gpio.c4
-rw-r--r--sys/arch/arm/xscale/pxa2x0_intr.c34
-rw-r--r--sys/arch/arm/xscale/pxa2x0_lcd.c4
9 files changed, 55 insertions, 55 deletions
diff --git a/sys/arch/arm/xscale/i80321_clock.c b/sys/arch/arm/xscale/i80321_clock.c
index 1df195b3423..1417b089992 100644
--- a/sys/arch/arm/xscale/i80321_clock.c
+++ b/sys/arch/arm/xscale/i80321_clock.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: i80321_clock.c,v 1.10 2015/06/13 07:16:36 jsg Exp $ */
+/* $OpenBSD: i80321_clock.c,v 1.11 2016/01/31 00:14:50 jsg Exp $ */
/*
* Copyright (c) 2006 Dale Rahn <drahn@openbsd.org>
@@ -285,7 +285,7 @@ cpu_initclocks()
int new_tps;
int tps_diff;
- psw = disable_interrupts(I32_bit);
+ psw = disable_interrupts(PSR_I);
first_sec = rtctime.tv_sec;
do {
diff --git a/sys/arch/arm/xscale/i80321_intr.c b/sys/arch/arm/xscale/i80321_intr.c
index 0f829563f6d..d77944d6891 100644
--- a/sys/arch/arm/xscale/i80321_intr.c
+++ b/sys/arch/arm/xscale/i80321_intr.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: i80321_intr.c,v 1.16 2014/04/03 10:17:34 mpi Exp $ */
+/* $OpenBSD: i80321_intr.c,v 1.17 2016/01/31 00:14:50 jsg Exp $ */
/*
* Copyright (c) 2006 Dale Rahn <drahn@openbsd.org>
@@ -104,7 +104,7 @@ i80321intc_setipl(int new)
{
int psw;
- psw = disable_interrupts(I32_bit);
+ psw = disable_interrupts(PSR_I);
current_ipl_level = new;
i80321intc_write_intctl(i80321intc_imask[new]);
restore_interrupts(psw);
@@ -177,7 +177,7 @@ i80321intc_do_pending(void)
static int processing = 0;
int oldirqstate, spl_save;
- oldirqstate = disable_interrupts(I32_bit);
+ oldirqstate = disable_interrupts(PSR_I);
spl_save = current_ipl_level;
@@ -194,7 +194,7 @@ i80321intc_do_pending(void)
i80321intc_setipl(ipl); \
restore_interrupts(oldirqstate); \
softintr_dispatch(si); \
- oldirqstate = disable_interrupts(I32_bit); \
+ oldirqstate = disable_interrupts(PSR_I); \
i80321intc_setipl(spl_save); \
}
@@ -253,7 +253,7 @@ _setsoftintr(int si)
{
int oldirqstate;
- oldirqstate = disable_interrupts(I32_bit);
+ oldirqstate = disable_interrupts(PSR_I);
softint_pending |= SI_TO_IRQBIT(si);
restore_interrupts(oldirqstate);
@@ -296,7 +296,7 @@ i80321intc_init(void)
i80321intc_calc_mask();
/* Enable IRQs (don't yet use FIQs). */
- enable_interrupts(I32_bit);
+ enable_interrupts(PSR_I);
}
void *
@@ -328,7 +328,7 @@ i80321_intr_establish(int irq, int ipl, int (*func)(void *), void *arg,
/* All IOP321 interrupts are level-triggered. */
iq->iq_ist = IST_LEVEL;
- oldirqstate = disable_interrupts(I32_bit);
+ oldirqstate = disable_interrupts(PSR_I);
TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list);
@@ -347,7 +347,7 @@ i80321_intr_disestablish(void *cookie)
struct intrq *iq = &i80321_handler[ih->ih_irq];
int oldirqstate;
- oldirqstate = disable_interrupts(I32_bit);
+ oldirqstate = disable_interrupts(PSR_I);
TAILQ_REMOVE(&iq->iq_list, ih, ih_list);
if (ih->ih_name != NULL)
@@ -380,14 +380,14 @@ i80321_irq_handler(void *arg)
i80321intc_setipl(i80321_handler[irq].iq_irq);
/* Enable interrupt */
- enable_interrupts(I32_bit);
+ enable_interrupts(PSR_I);
TAILQ_FOREACH(ih, &i80321_handler[irq].iq_list, ih_list) {
if ((ih->ih_func)( ih->ih_arg == 0
? frame : ih->ih_arg))
ih->ih_count.ec_count++;
}
/* Disable interrupt */
- disable_interrupts(I32_bit);
+ disable_interrupts(PSR_I);
hwpend &= ~(1<<irq);
}
uvmexp.intrs++;
diff --git a/sys/arch/arm/xscale/i80321_pci.c b/sys/arch/arm/xscale/i80321_pci.c
index a1c33ecf8bf..cf2ce32f62f 100644
--- a/sys/arch/arm/xscale/i80321_pci.c
+++ b/sys/arch/arm/xscale/i80321_pci.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: i80321_pci.c,v 1.4 2010/12/04 17:06:31 miod Exp $ */
+/* $OpenBSD: i80321_pci.c,v 1.5 2016/01/31 00:14:50 jsg Exp $ */
/* $NetBSD: i80321_pci.c,v 1.7 2005/12/15 01:44:00 briggs Exp $ */
/*
@@ -67,7 +67,7 @@ int i80321_pci_conf_size(void *, pcitag_t);
pcireg_t i80321_pci_conf_read(void *, pcitag_t, int);
void i80321_pci_conf_write(void *, pcitag_t, int, pcireg_t);
-#define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit)
+#define PCI_CONF_LOCK(s) (s) = disable_interrupts(PSR_I)
#define PCI_CONF_UNLOCK(s) restore_interrupts((s))
void
diff --git a/sys/arch/arm/xscale/pxa2x0.c b/sys/arch/arm/xscale/pxa2x0.c
index e550efb2cff..baefb42bf37 100644
--- a/sys/arch/arm/xscale/pxa2x0.c
+++ b/sys/arch/arm/xscale/pxa2x0.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: pxa2x0.c,v 1.19 2014/10/18 12:21:56 miod Exp $ */
+/* $OpenBSD: pxa2x0.c,v 1.20 2016/01/31 00:14:50 jsg Exp $ */
/* $NetBSD: pxa2x0.c,v 1.5 2003/12/12 16:42:44 thorpej Exp $ */
/*
@@ -285,7 +285,7 @@ pxaip_measure_cpuclock(struct pxaip_softc *sc)
int irq;
ioh = sc->sc_bush_rtc;
- irq = disable_interrupts(I32_bit|F32_bit);
+ irq = disable_interrupts(PSR_I|PSR_F);
__asm volatile( "mrc p14, 0, %0, c0, c1, 0" : "=r" (pmcr_save));
/* Enable clock counter */
diff --git a/sys/arch/arm/xscale/pxa2x0_apm.c b/sys/arch/arm/xscale/pxa2x0_apm.c
index 71561fed1be..10dc039297f 100644
--- a/sys/arch/arm/xscale/pxa2x0_apm.c
+++ b/sys/arch/arm/xscale/pxa2x0_apm.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: pxa2x0_apm.c,v 1.43 2014/09/20 09:28:24 kettenis Exp $ */
+/* $OpenBSD: pxa2x0_apm.c,v 1.44 2016/01/31 00:14:50 jsg Exp $ */
/*-
* Copyright (c) 2001 Alexander Guy. All rights reserved.
@@ -900,7 +900,7 @@ pxa2x0_apm_sleep(struct pxa2x0_apm_softc *sc)
goto out;
}
- save = disable_interrupts(I32_bit|F32_bit);
+ save = disable_interrupts(PSR_I|PSR_F);
sd.sd_oscr0 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSCR0);
sd.sd_oscr4 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSCR4);
@@ -1483,7 +1483,7 @@ pxa2x0_setperf(int speed)
DPRINTF(("setperf speed %d newfreq %d, maxfreq %d\n",
speed, newfreq, xscale_maxspeed));
- s = disable_interrupts(I32_bit|F32_bit);
+ s = disable_interrupts(PSR_I|PSR_F);
if (newfreq == 91) {
if (freq > 91) {
diff --git a/sys/arch/arm/xscale/pxa2x0_apm_asm.S b/sys/arch/arm/xscale/pxa2x0_apm_asm.S
index 72caf0d2b85..83907fea32d 100644
--- a/sys/arch/arm/xscale/pxa2x0_apm_asm.S
+++ b/sys/arch/arm/xscale/pxa2x0_apm_asm.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: pxa2x0_apm_asm.S,v 1.4 2007/11/02 05:18:25 miod Exp $ */
+/* $OpenBSD: pxa2x0_apm_asm.S,v 1.5 2016/01/31 00:14:50 jsg Exp $ */
/*
* Copyright (c) 2005 Uwe Stuehler <uwe@openbsd.org>
@@ -166,31 +166,31 @@ ENTRY(pxa2x0_cpu_suspend)
str r2, [r3], #4 /* Save SVC saved CPSR. */
str sp, [r3], #4 /* Save SVC stack pointer. */
- mov r1, #(PSR_FIQ32_MODE | I32_bit | F32_bit)
+ mov r1, #(PSR_FIQ32_MODE | PSR_I | PSR_F)
msr cpsr, r1 /* Enter FIQ mode. */
mrs r2, spsr /* Load FIQ mode saved CPSR. */
stmia r3!, {r2, r8-r12, sp, lr} /* Save FIQ mode registers. */
- mov r1, #(PSR_IRQ32_MODE | I32_bit | F32_bit)
+ mov r1, #(PSR_IRQ32_MODE | PSR_I | PSR_F)
msr cpsr, r1 /* Enter IRQ mode. */
mrs r0, spsr /* Load IRQ mode saved CPSR. */
stmia r3!, {r0, sp, lr} /* Save IRQ mode registers. */
- mov r1, #(PSR_ABT32_MODE | I32_bit | F32_bit)
+ mov r1, #(PSR_ABT32_MODE | PSR_I | PSR_F)
msr cpsr, r1 /* Enter ABT mode. */
mrs r0, spsr /* Load ABT mode saved CPSR. */
stmia r3!, {r0, sp, lr} /* Save ABT mode registers. */
- mov r1, #(PSR_UND32_MODE | I32_bit | F32_bit)
+ mov r1, #(PSR_UND32_MODE | PSR_I | PSR_F)
msr cpsr, r1 /* Enter UND mode. */
mrs r0, spsr /* Load UND mode saved CPSR. */
stmia r3!, {r0, sp, lr} /* Save UND mode registers. */
- mov r1, #(PSR_SYS32_MODE | I32_bit | F32_bit)
+ mov r1, #(PSR_SYS32_MODE | PSR_I | PSR_F)
msr cpsr, r1 /* Enter SYS mode. */
stmia r3!, {sp, lr} /* Save SYS mode registers. */
- mov r1, #(PSR_SVC32_MODE | I32_bit | F32_bit)
+ mov r1, #(PSR_SVC32_MODE | PSR_I | PSR_F)
msr cpsr, r1 /* Return to SVC mode. */
/* At this point all critical registers have been saved. */
@@ -211,14 +211,14 @@ ENTRY(pxa2x0_cpu_suspend)
cache_flush_loop:
mrs r2, cpsr
- orr r2, r2, #(I32_bit|F32_bit)
+ orr r2, r2, #(PSR_I|PSR_F)
msr cpsr_c, r2 /* disable IRQ/FIQ */
mcr p15, 0, r0, c7, c2, 5 /* allocate cache line */
mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
mrs r2, cpsr
- and r2, r2, #~(I32_bit|F32_bit)
+ and r2, r2, #~(PSR_I|PSR_F)
msr cpsr_c, r2 /* enable IRQ/FIQ */
add r0, r0, #CACHELINESIZE
@@ -329,7 +329,7 @@ pxa2x0_cpu_resume_virt:
ldr sp, [r2], #4
/* Restore FIQ mode registers. */
- mov r1, #(PSR_FIQ32_MODE | I32_bit | F32_bit)
+ mov r1, #(PSR_FIQ32_MODE | PSR_I | PSR_F)
msr cpsr, r1
ldr r0, [r2], #4
msr spsr, r0
@@ -342,7 +342,7 @@ pxa2x0_cpu_resume_virt:
ldr lr, [r2], #4
/* Restore IRQ mode registers. */
- mov r1, #(PSR_IRQ32_MODE | I32_bit | F32_bit)
+ mov r1, #(PSR_IRQ32_MODE | PSR_I | PSR_F)
msr cpsr, r1
ldr r0, [r2], #4
msr spsr, r0
@@ -350,7 +350,7 @@ pxa2x0_cpu_resume_virt:
ldr lr, [r2], #4
/* Restore ABT mode registers. */
- mov r1, #(PSR_ABT32_MODE | I32_bit | F32_bit)
+ mov r1, #(PSR_ABT32_MODE | PSR_I | PSR_F)
msr cpsr, r1
ldr r0, [r2], #4
msr spsr, r0
@@ -358,7 +358,7 @@ pxa2x0_cpu_resume_virt:
ldr lr, [r2], #4
/* Restore UND mode registers. */
- mov r1, #(PSR_UND32_MODE | I32_bit | F32_bit)
+ mov r1, #(PSR_UND32_MODE | PSR_I | PSR_F)
msr cpsr, r1
ldr r0, [r2], #4
msr spsr, r0
@@ -366,13 +366,13 @@ pxa2x0_cpu_resume_virt:
ldr lr, [r2], #4
/* Restore SYS mode registers. */
- mov r1, #(PSR_SYS32_MODE | I32_bit | F32_bit)
+ mov r1, #(PSR_SYS32_MODE | PSR_I | PSR_F)
msr cpsr, r1
ldr sp, [r2], #4
ldr lr, [r2], #4
/* Return to SVC mode. */
- mov r1, #(PSR_SVC32_MODE | I32_bit | F32_bit)
+ mov r1, #(PSR_SVC32_MODE | PSR_I | PSR_F)
msr cpsr, r1
ldmia sp!, {r0-r12, pc}
diff --git a/sys/arch/arm/xscale/pxa2x0_gpio.c b/sys/arch/arm/xscale/pxa2x0_gpio.c
index 2cc410a10f4..5c86d1425af 100644
--- a/sys/arch/arm/xscale/pxa2x0_gpio.c
+++ b/sys/arch/arm/xscale/pxa2x0_gpio.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: pxa2x0_gpio.c,v 1.24 2014/07/12 18:44:41 tedu Exp $ */
+/* $OpenBSD: pxa2x0_gpio.c,v 1.25 2016/01/31 00:14:50 jsg Exp $ */
/* $NetBSD: pxa2x0_gpio.c,v 1.2 2003/07/15 00:24:55 lukem Exp $ */
/*
@@ -338,7 +338,7 @@ void
pxa2x0_gpio_intr_fixup(int minipl, int maxipl)
{
struct pxagpio_softc *sc = pxagpio_softc;
- int save = disable_interrupts(I32_bit);
+ int save = disable_interrupts(PSR_I);
if (maxipl == IPL_NONE && minipl == IPL_HIGH) {
/* no remaining interrupts */
diff --git a/sys/arch/arm/xscale/pxa2x0_intr.c b/sys/arch/arm/xscale/pxa2x0_intr.c
index 72d41a3f2b5..0743c9643e5 100644
--- a/sys/arch/arm/xscale/pxa2x0_intr.c
+++ b/sys/arch/arm/xscale/pxa2x0_intr.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: pxa2x0_intr.c,v 1.26 2014/07/12 18:44:41 tedu Exp $ */
+/* $OpenBSD: pxa2x0_intr.c,v 1.27 2016/01/31 00:14:50 jsg Exp $ */
/* $NetBSD: pxa2x0_intr.c,v 1.5 2003/07/15 00:24:55 lukem Exp $ */
/*
@@ -158,7 +158,7 @@ pxaintc_attach(struct device *parent, struct device *self, void *args)
pxa2x0_init_interrupt_masks();
_splraise(IPL_HIGH);
- enable_interrupts(I32_bit);
+ enable_interrupts(PSR_I);
}
/*
@@ -219,7 +219,7 @@ pxa2x0_irq_handler(void *arg)
pxa2x0_setipl(extirq_level[irqno]);
/* Enable interrupt */
- enable_interrupts(I32_bit);
+ enable_interrupts(PSR_I);
#ifndef MULTIPLE_HANDLERS_ON_ONE_IRQ
(* handler[irqno].func)(
@@ -235,7 +235,7 @@ pxa2x0_irq_handler(void *arg)
#endif
/* Disable interrupt */
- disable_interrupts(I32_bit);
+ disable_interrupts(PSR_I);
irqbits &= ~(1<<irqno);
}
@@ -254,7 +254,7 @@ pxa2x0_stray_interrupt(void *cookie)
printf("stray interrupt %d\n", irqno);
if (PXA2X0_IRQ_MIN <= irqno && irqno < ICU_LEN){
- int save = disable_interrupts(I32_bit);
+ int save = disable_interrupts(PSR_I);
write_icu(SAIPIC_MR,
read_icu(SAIPIC_MR) & ~(1U<<irqno));
restore_interrupts(save);
@@ -289,7 +289,7 @@ pxa2x0_update_intr_masks(int irqno, int irqlevel)
int level;
#endif
struct intrhand *ih;
- psw = disable_interrupts(I32_bit);
+ psw = disable_interrupts(PSR_I);
/* First figure out which levels each IRQ uses. */
for (irq = 0; irq < ICU_LEN; irq++) {
@@ -339,7 +339,7 @@ pxa2x0_update_intr_masks(int irqno, int irqlevel)
int level; /* debug */
int mask = 1U<<irqno;
int i;
- psw = disable_interrupts(I32_bit);
+ psw = disable_interrupts(PSR_I);
for(i = 0; i < irqlevel; ++i)
pxa2x0_imask[i] |= mask; /* Enable interrupt at lower level */
@@ -456,7 +456,7 @@ pxa2x0_do_pending(void)
spl_save = current_spl_level;
- oldirqstate = disable_interrupts(I32_bit);
+ oldirqstate = disable_interrupts(PSR_I);
#if 1
#define DO_SOFTINT(si,ipl) \
@@ -467,7 +467,7 @@ pxa2x0_do_pending(void)
pxa2x0_setipl(ipl); \
restore_interrupts(oldirqstate); \
softintr_dispatch(si); \
- oldirqstate = disable_interrupts(I32_bit); \
+ oldirqstate = disable_interrupts(PSR_I); \
pxa2x0_setipl(spl_save); \
}
@@ -484,7 +484,7 @@ pxa2x0_do_pending(void)
pxa2x0_setipl(ipl);
restore_interrupts(oldirqstate);
softintr_dispatch(si);
- oldirqstate = disable_interrupts(I32_bit);
+ oldirqstate = disable_interrupts(PSR_I);
pxa2x0_setipl(spl_save);
}
#endif
@@ -541,7 +541,7 @@ pxa2x0_intr_establish(int irqno, int level,
if (irqno < PXA2X0_IRQ_MIN || irqno >= ICU_LEN)
panic("intr_establish: bogus irq number %d", irqno);
- psw = disable_interrupts(I32_bit);
+ psw = disable_interrupts(PSR_I);
#ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
/* no point in sleeping unless someone can free memory. */
@@ -587,7 +587,7 @@ pxa2x0_intr_disestablish(void *cookie)
struct intrhand *ih = cookie;
int irqno = ih->ih_irq;
- psw = disable_interrupts(I32_bit);
+ psw = disable_interrupts(PSR_I);
TAILQ_REMOVE(&handler[irqno].list, ih, ih_list);
free(ih, M_DEVBUF, 0);
@@ -605,7 +605,7 @@ pxa2x0_intr_disestablish(void *cookie)
if (irqno < PXA2X0_IRQ_MIN || irqno >= ICU_LEN)
panic("intr_disestablish: bogus irq number %d", irqno);
- psw = disable_interrupts(I32_bit);
+ psw = disable_interrupts(PSR_I);
ih = &handler[irqno];
if (ih->name != NULL)
@@ -648,7 +648,7 @@ pxa2x0_splx(int new)
{
int psw;
- psw = disable_interrupts(I32_bit);
+ psw = disable_interrupts(PSR_I);
pxa2x0_setipl(new);
restore_interrupts(psw);
@@ -665,7 +665,7 @@ pxa2x0_splraise(int ipl)
old = current_spl_level;
if( ipl > current_spl_level ){
- psw = disable_interrupts(I32_bit);
+ psw = disable_interrupts(PSR_I);
pxa2x0_setipl(ipl);
restore_interrupts(psw);
}
@@ -677,7 +677,7 @@ int
pxa2x0_spllower(int ipl)
{
int old = current_spl_level;
- int psw = disable_interrupts(I32_bit);
+ int psw = disable_interrupts(PSR_I);
pxa2x0_splx(ipl);
restore_interrupts(psw);
return(old);
@@ -723,7 +723,7 @@ pxa2x0_splassert_check(int wantipl, const char *func)
* If the splassert_ctl is set to not panic, raise the ipl
* in a feeble attempt to reduce damage.
*/
- psw = disable_interrupts(I32_bit);
+ psw = disable_interrupts(PSR_I);
pxa2x0_setipl(wantipl);
restore_interrupts(psw);
}
diff --git a/sys/arch/arm/xscale/pxa2x0_lcd.c b/sys/arch/arm/xscale/pxa2x0_lcd.c
index 119782c61d3..9238889c8e4 100644
--- a/sys/arch/arm/xscale/pxa2x0_lcd.c
+++ b/sys/arch/arm/xscale/pxa2x0_lcd.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: pxa2x0_lcd.c,v 1.26 2014/07/12 18:44:41 tedu Exp $ */
+/* $OpenBSD: pxa2x0_lcd.c,v 1.27 2016/01/31 00:14:50 jsg Exp $ */
/* $NetBSD: pxa2x0_lcd.c,v 1.8 2003/10/03 07:24:05 bsh Exp $ */
/*
@@ -292,7 +292,7 @@ pxa2x0_lcd_start_dma(bus_space_tag_t iot, bus_space_handle_t ioh,
uint32_t tmp;
int val, save;
- save = disable_interrupts(I32_bit);
+ save = disable_interrupts(PSR_I);
switch (scr->depth) {
case 1: val = 0; break;
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-18 16:51:55 +0000