diff options
Diffstat (limited to 'sys/arch/aviion/dev')
| -rw-r--r-- | sys/arch/aviion/dev/dartreg.h | 181 | ||||
| -rw-r--r-- | sys/arch/aviion/dev/if_le_vme.c | 382 | ||||
| -rw-r--r-- | sys/arch/aviion/dev/if_le_vmereg.h | 85 |
3 files changed, 648 insertions, 0 deletions
diff --git a/sys/arch/aviion/dev/dartreg.h b/sys/arch/aviion/dev/dartreg.h new file mode 100644 index 00000000000..6218b9e91af --- /dev/null +++ b/sys/arch/aviion/dev/dartreg.h @@ -0,0 +1,181 @@ +/* $OpenBSD: dartreg.h,v 1.1.1.1 2006/05/09 18:24:15 miod Exp $ */ + +#define MAXPORTS 2 /* max count of PORTS/DUART */ + +#define A_PORT 0 /* flag for port a */ +#define B_PORT 1 /* flag for port b */ + +/* the access to the same command register must be delayed, + because the chip has some hardware problems in this case */ +#define DELAY_CR do { volatile int i; for (i = 0; i < 250; ++i); } while (0) + +/*********************** MC68681 DEFINITIONS ************************/ + +/* mode register 1: MR1x operations */ +#define RXRTS 0x80 /* enable receiver RTS */ +#define PAREN 0x00 /* with parity */ +#define PARDIS 0x10 /* no parity */ +#define EVENPAR 0x00 /* even parity */ +#define ODDPAR 0x04 /* odd parity */ +#define CL5 0x00 /* 5 bits per char */ +#define CL6 0x01 /* 6 bits per char */ +#define CL7 0x02 /* 7 bits per char */ +#define CL8 0x03 /* 8 bits per char */ +#define PARMODEMASK 0x18 /* parity mode mask */ +#define PARTYPEMASK 0x04 /* parity type mask */ +#define CLMASK 0x03 /* character length mask */ + +/* mode register 2: MR2x operations */ +#define TXRTS 0x20 /* enable transmitter RTS */ +#define TXCTS 0x10 /* enable transmitter CTS */ +#define SB2 0x0f /* 2 stop bits */ +#define SB1 0x07 /* 1 stop bit */ +#define SB1L5 0x00 /* 1 stop bit at 5 bits per character */ + +#define SBMASK 0x0f /* stop bit mask */ + +/* clock-select register: CSRx operations */ +#define NOBAUD -1 /* 50 and 200 baud are not possible */ +/* they are not in Baud register set 2 */ +#define BD75 0x00 /* 75 baud */ +#define BD110 0x11 /* 110 baud */ +#define BD134 0x22 /* 134.5 baud */ +#define BD150 0x33 /* 150 baud */ +#define BD300 0x44 /* 300 baud */ +#define BD600 0x55 /* 600 baud */ +#define BD1200 0x66 /* 1200 baud */ +#define BD1800 0xaa /* 1800 baud */ +#define BD2400 0x88 /* 2400 baud */ +#define BD4800 0x99 /* 4800 baud */ +#define BD9600 0xbb /* 9600 baud */ +#define BD19200 0xcc /* 19200 baud */ + +#define DEFBAUD BD9600 /* default value if baudrate is not possible */ + + +/* channel command register: CRx operations */ +#define MRRESET 0x10 /* reset mr pointer to mr1 */ +#define RXRESET 0x20 /* reset receiver */ +#define TXRESET 0x30 /* reset transmitter */ +#define ERRRESET 0x40 /* reset error status */ +#define BRKINTRESET 0x50 /* reset channel's break interrupt */ +#define BRKSTART 0x60 /* start break */ +#define BRKSTOP 0x70 /* stop break */ +#define TXDIS 0x08 /* disable transmitter */ +#define TXEN 0x04 /* enable transmitter */ +#define RXDIS 0x02 /* disable receiver */ +#define RXEN 0x01 /* enable receiver */ + +/* status register: SRx status */ +#define RBRK 0x80 /* received break */ +#define FRERR 0x40 /* frame error */ +#define PERR 0x20 /* parity error */ +#define ROVRN 0x10 /* receiver overrun error */ +#define TXEMT 0x08 /* transmitter empty */ +#define TXRDY 0x04 /* transmitter ready */ +#define FFULL 0x02 /* receiver FIFO full */ +#define RXRDY 0x01 /* receiver ready */ + +/* output port configuration register: OPCR operations */ +#define OPSET 0x00 /* set all op lines to op function */ +#define OPSETTO 0x04 /* use OP3 for timer output */ + +/* output port register: OP operations */ +#define OPDTRB 0x20 /* DTR line output b on the VME188, 181, 141 */ +#define OPDTRA 0x04 /* DTR line output a */ +#define OPRTSB 0x02 /* RTS line output b */ +#define OPRTSA 0x01 /* RTS line output a */ + +/* auxiliary control register: ACR operations */ +#define BDSET1 0x00 /* baudrate generator set 1 */ +#define BDSET2 0x80 /* baudrate generator set 2 */ +#define CCLK1 0x60 /* timer clock: external rate. TA */ +#define CCLK16 0x30 /* counter clock: x1 clk divided by 16 */ +#define SLCTIM 0x7800/* timer count to get 60 Hz time slice (16.6ms ticks) */ +#define IPDCDIB 0x08 /* IP3 change == DCD input on port B */ +#define IPDCDIA 0x04 /* IP2 change == DCD input on port A */ + +/* input port change register: IPCR operations */ +#define IPCRDCDB 0x80 /* IP3 change == DCD change on port B */ +#define IPCRDCDA 0x40 /* IP2 change == DCD change on port A */ + +/* Defines for mvme335 */ +#define IPDCDB 0x20 /* DCD line input b */ +#define IPDCDA 0x10 /* DCD line input a */ + +#define IPDSRB 0x08 /* DSR line input b */ +#define IPDSRA 0x04 /* DSR line input a */ +#define IPCTSB 0x02 /* CTS line input b */ +#define IPCTSA 0x01 /* CTS line input a */ + +/* interrupt status and mask register: ISR status and IMR mask */ +#define IIPCHG 0x80 /* input port change */ +#define IBRKB 0x40 /* delta break b */ +#define IRXRDYB 0x20 /* receiver ready b */ +#define ITXRDYB 0x10 /* transmitter ready b */ +#define ITIMER 0x08 /* Enable timer interrupts. */ +#define IBRKA 0x04 /* delta break a */ +#define IRXRDYA 0x02 /* receiver ready a */ +#define ITXRDYA 0x01 /* transmitter ready a */ + +/* interrupts from port a or b */ +#define AINTPORT ( IRXRDYA | ITXRDYA ) +#define BINTPORT ( IRXRDYB | ITXRDYB ) + +/* HW write register index for ut_wr_regs[] */ +#define MR1A 0 /* mode register 1 a */ +#define CSRA 1 /* clock-select register a*/ +#define CRA 2 /* command register a */ +#define TBA 3 /* transmitter buffer a */ +#define ACR 4 /* auxiliary control register*/ +#define IMR 5 /* interrupt mask register */ +#define CTUR 6 /* counter/timer upper reg */ +#define CTLR 7 /* counter/timer lower reg */ +#define MR1B 8 /* mode register 1 b */ +#define CSRB 9 /* clock-select register b*/ +#define CRB 10 /* command register b */ +#define TBB 11 /* transmitter buffer b */ +#define IVR 12 /* interrupt vector register */ +#define OPCR 13 /* output port config reg */ +#define OPRSET 14 /* output port: bit set cmd */ +#define OPRRESET 15 /* output port: bit reset cmd */ +#define MR2A 16 /* mode register 2 a */ +#define MR2B 17 /* mode register 2 b */ +#define MAXREG 18 /* max count of registers */ + +/* + * MC68681 hardware registers. + */ + +#define DART_MR1A 0x00 /* RW: mode register A */ +#define DART_MR2A 0x00 /* RW: mode register A */ +#define DART_SRA 0x01 /* R: status register A */ +#define DART_CSRA 0x01 /* W: clock select register A */ +#define DART_CRA 0x02 /* W: command register A */ +#define DART_RBA 0x03 /* R: receiver buffer A */ +#define DART_TBA 0x03 /* W: transmit buffer A */ +#define DART_IPCR 0x04 /* R: input port change register */ +#define DART_ACR 0x04 /* W: auxiliary control register */ +#define DART_ISR 0x05 /* R: interrupt status register */ +#define DART_IMR 0x05 /* W: interrupt mask register */ +#define DART_CUR 0x06 /* R: count upper register */ +#define DART_CTUR 0x06 /* W: counter/timer upper register */ +#define DART_CLR 0x07 /* R: count lower register */ +#define DART_CTLR 0x07 /* W: counter/timer lower register */ +#define DART_MR1B 0x08 /* RW: mode register B */ +#define DART_MR2B 0x08 /* RW: mode register B */ +#define DART_SRB 0x09 /* R: status register B */ +#define DART_CSRB 0x09 /* W: clock select register B */ +#define DART_CRB 0x0a /* W: command register B */ +#define DART_RBB 0x0b /* R: receiver buffer B */ +#define DART_TBB 0x0b /* W: transmit buffer B */ +#define DART_IVR 0x0c /* RW: interrupt vector register */ +#define DART_IP 0x0d /* R: input port (unlatched) */ +#define DART_OPCR 0x0d /* W: output port configuration register */ +#define DART_CTSTART 0x0e /* R: start counter command */ +#define DART_OPRS 0x0e /* W: output port bit set */ +#define DART_CTSTOP 0x0f /* R: stop counter command */ +#define DART_OPRR 0x0f /* W: output port bit reset */ + +#define DART_A_BASE 0x00 +#define DART_B_BASE 0x08 diff --git a/sys/arch/aviion/dev/if_le_vme.c b/sys/arch/aviion/dev/if_le_vme.c new file mode 100644 index 00000000000..658ec2ddd16 --- /dev/null +++ b/sys/arch/aviion/dev/if_le_vme.c @@ -0,0 +1,382 @@ +/* $OpenBSD: if_le_vme.c,v 1.1 2006/05/09 18:24:32 miod Exp $ */ + +/*- + * Copyright (c) 1982, 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)if_le.c 8.2 (Berkeley) 10/30/93 + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/mbuf.h> +#include <sys/syslog.h> +#include <sys/socket.h> +#include <sys/device.h> +#include <sys/malloc.h> + +#include <net/if.h> + +#ifdef INET +#include <netinet/in.h> +#include <netinet/if_ether.h> +#endif + +#include <net/if_media.h> + +#include <machine/autoconf.h> +#include <machine/bus.h> +#include <machine/cpu.h> + +#include <dev/ic/am7990reg.h> +#include <dev/ic/am7990var.h> + +#include <aviion/dev/if_le_vmereg.h> +#include <aviion/dev/vmevar.h> + +struct le_softc { + struct am7990_softc sc_am7990; /* glue to MI code */ + + bus_space_tag_t sc_memt; /* dual-ported memory access */ + bus_space_handle_t sc_memh; + + bus_space_tag_t sc_iot; /* short io access */ + bus_space_handle_t sc_ioh; + + struct intrhand sc_ih; /* interrupt vectoring */ + u_int sc_csr; /* CSR image */ + u_int sc_ipl; + u_int sc_vec; +}; + +void le_vme_attach(struct device *, struct device *, void *); +int le_vme_match(struct device *, void *, void *); + +struct cfattach le_vme_ca = { + sizeof(struct le_softc), le_vme_match, le_vme_attach +}; + +void le_vme_wrcsr(struct am7990_softc *, u_int16_t, u_int16_t); +u_int16_t le_vme_rdcsr(struct am7990_softc *, u_int16_t); +void nvram_cmd(struct am7990_softc *, u_int, u_int); +u_int16_t nvram_read(struct am7990_softc *, u_int); +void le_vme_etheraddr(struct am7990_softc *); +void le_vme_init(struct am7990_softc *); +void le_vme_reset(struct am7990_softc *); +int le_vme_intr(void *); +#if 0 +void le_vme_copyfrombuf_contig(struct am7990_softc *, void *, int, int); +void le_vme_copytobuf_contig(struct am7990_softc *, void *, int, int); +void le_vme_zerobuf_contig(struct am7990_softc *, int, int); +#endif + +/* send command to the nvram controller */ +void +nvram_cmd(sc, cmd, addr) + struct am7990_softc *sc; + u_int cmd; + u_int addr; +{ + struct le_softc *lesc = (void *)sc; + int i; + + for (i = 0; i < 8; i++) { + bus_space_write_2(lesc->sc_iot, lesc->sc_ioh, LEREG_EAR, + (cmd | (addr << 1)) >> i); + CDELAY; + } +} + +/* read nvram one bit at a time */ +u_int16_t +nvram_read(sc, nvram_addr) + struct am7990_softc *sc; + u_int nvram_addr; +{ + struct le_softc *lesc = (void *)sc; + u_int val = 0, mask = 0x04000; + u_int16_t wbit; + + lesc->sc_csr = HW_RS | NVRAM_EN | 0x07; + ENABLE_NVRAM; + nvram_cmd(sc, NVRAM_RCL, 0); + DISABLE_NVRAM; + CDELAY; + ENABLE_NVRAM; + nvram_cmd(sc, NVRAM_READ, nvram_addr); + for (wbit = 0; wbit < 15; wbit++) { + if (bus_space_read_2(lesc->sc_iot, lesc->sc_ioh, + LEREG_EAR) & 0x01) + val |= mask; + else + val &= ~mask; + mask = mask >> 1; + CDELAY; + } + if (bus_space_read_2(lesc->sc_iot, lesc->sc_ioh, LEREG_EAR) & 0x01) + val |= 0x8000; + else + val &= 0x7fff; + CDELAY; + DISABLE_NVRAM; + return (val); +} + +void +le_vme_etheraddr(sc) + struct am7990_softc *sc; +{ + u_char *cp = sc->sc_arpcom.ac_enaddr; + u_int16_t ival[3]; + int i; + + for (i = 0; i < 3; i++) { + ival[i] = nvram_read(sc, i); + } + memcpy(cp, &ival[0], 6); +} + +void +le_vme_wrcsr(sc, port, val) + struct am7990_softc *sc; + u_int16_t port, val; +{ + struct le_softc *lesc = (void *)sc; + + bus_space_write_2(lesc->sc_iot, lesc->sc_ioh, LEREG_RAP, port); + bus_space_write_2(lesc->sc_iot, lesc->sc_ioh, LEREG_RDP, val); +} + +u_int16_t +le_vme_rdcsr(sc, port) + struct am7990_softc *sc; + u_int16_t port; +{ + struct le_softc *lesc = (void *)sc; + + bus_space_write_2(lesc->sc_iot, lesc->sc_ioh, LEREG_RAP, port); + return (bus_space_read_2(lesc->sc_iot, lesc->sc_ioh, LEREG_RDP)); +} + +/* init board, set ipl and vec */ +void +le_vme_init(sc) + struct am7990_softc *sc; +{ + struct le_softc *lesc = (void *)sc; + + lesc->sc_csr = 0x4f; + WRITE_CSR_AND(lesc->sc_ipl); + SET_VEC(lesc->sc_vec); + return; +} + +/* board reset */ +void +le_vme_reset(sc) + struct am7990_softc *sc; +{ + struct le_softc *lesc = (void *)sc; + + RESET_HW; +#ifdef LEDEBUG + if (sc->sc_debug) + printf("%s: hardware reset\n", sc->sc_dev.dv_xname); +#endif + SYSFAIL_CL; +} + +int +le_vme_intr(sc) + void *sc; +{ + struct le_softc *lesc = (void *)sc; + int rc; + + rc = am7990_intr(sc); + ENABLE_INTR; + return (rc); +} + +#if 0 +void +le_vme_copytobuf_contig(sc, from, boff, len) + struct am7990_softc *sc; + void *from; + int boff, len; +{ + struct le_softc *lesc = (void *)sc; + + bus_space_write_region_1(lesc->sc_memt, lesc->sc_memh, boff, from, len); +} + +void +le_vme_copyfrombuf_contig(sc, to, boff, len) + struct am7990_softc *sc; + void *to; + int boff, len; +{ + struct le_softc *lesc = (void *)sc; + + bus_space_read_region_1(lesc->sc_memt, lesc->sc_memh, boff, to, len); +} + +void +le_vme_zerobuf_contig(sc, boff, len) + struct am7990_softc *sc; + int boff, len; +{ + struct le_softc *lesc = (void *)sc; + + bus_space_set_region_1(lesc->sc_memt, lesc->sc_memh, boff, 0, len); +} +#endif + +int +le_vme_match(parent, vcf, args) + struct device *parent; + void *vcf, *args; +{ + struct vme_attach_args *vaa = args; + bus_space_tag_t iot, memt; + bus_space_handle_t ioh; + int rc; + + /* we expect a32 and a16 locators */ + if (vaa->vaa_addr_a16 == (vme_addr_t)-1 || + vaa->vaa_addr_a32 == (vme_addr_t)-1) + return (0); + + /* check the dual ported memory */ + if (vmebus_get_bst(parent, VME_A32, VME_D32, &memt) != 0) + return (0); + if (bus_space_map(memt, vaa->vaa_addr_a32, PAGE_SIZE, 0, &ioh) != 0) + return (0); + rc = badaddr((vaddr_t)bus_space_vaddr(memt, ioh), 2); + bus_space_unmap(memt, ioh, PAGE_SIZE); + vmebus_release_bst(parent, memt); + + /* check the control space */ + if (vmebus_get_bst(parent, VME_A16, VME_D16, &iot) != 0) + return (0); + if (bus_space_map(iot, vaa->vaa_addr_a16, PAGE_SIZE, 0, &ioh) != 0) + return (0); + rc |= badaddr((vaddr_t)bus_space_vaddr(iot, ioh), 2); + bus_space_unmap(iot, ioh, PAGE_SIZE); + vmebus_release_bst(parent, iot); + + return (rc == 0); +} + +void +le_vme_attach(parent, self, aux) + struct device *parent; + struct device *self; + void *aux; +{ + struct le_softc *lesc = (struct le_softc *)self; + struct am7990_softc *sc = &lesc->sc_am7990; + struct vme_attach_args *vaa = aux; + + /* + * Allocate an interrupt vector. + */ + if (vmeintr_allocate(1, VMEINTR_ANY, &lesc->sc_vec) != 0) { + printf(": no more interrupts!\n"); + return; + } + lesc->sc_ipl = vaa->vaa_ipl == 0 ? IPL_NET : vaa->vaa_ipl; + + /* + * Map the dual-ported memory. + */ + if (vmebus_get_bst(parent, VME_A32, VME_D32, &lesc->sc_memt) != 0) { + printf(": can't map memory\n"); + return; + } + if (bus_space_map(lesc->sc_memt, vaa->vaa_addr_a32, VLEMEMSIZE, + BUS_SPACE_MAP_LINEAR, &lesc->sc_memh) != 0) { + printf(": can't map memory\n"); + goto fail3; + } + + /* + * Map the control space. + */ + if (vmebus_get_bst(parent, VME_A16, VME_D16, &lesc->sc_iot) != 0) { + printf(": can't map registers\n"); + goto fail2; + } + if (bus_space_map(lesc->sc_iot, vaa->vaa_addr_a16, PAGE_SIZE, + 0, &lesc->sc_ioh) != 0) { + printf(": can't map registers\n"); + goto fail1; + } + + sc->sc_mem = (void *)bus_space_vaddr(lesc->sc_memt, lesc->sc_memh); + sc->sc_memsize = VLEMEMSIZE; + sc->sc_addr = vaa->vaa_addr_a32 & 0x00ffffff; + sc->sc_conf3 = LE_C3_BSWP; + sc->sc_hwreset = le_vme_reset; + sc->sc_rdcsr = le_vme_rdcsr; + sc->sc_wrcsr = le_vme_wrcsr; + sc->sc_hwinit = le_vme_init; +#if 0 + sc->sc_copytodesc = le_vme_copytobuf_contig; + sc->sc_copyfromdesc = le_vme_copyfrombuf_contig; + sc->sc_copytobuf = le_vme_copytobuf_contig; + sc->sc_copyfrombuf = le_vme_copyfrombuf_contig; + sc->sc_zerobuf = le_vme_zerobuf_contig; +#else + sc->sc_copytodesc = am7990_copytobuf_contig; + sc->sc_copyfromdesc = am7990_copyfrombuf_contig; + sc->sc_copytobuf = am7990_copytobuf_contig; + sc->sc_copyfrombuf = am7990_copyfrombuf_contig; + sc->sc_zerobuf = am7990_zerobuf_contig; +#endif + + /* get Ethernet address */ + le_vme_etheraddr(sc); + + am7990_config(sc); + + /* connect the interrupt */ + lesc->sc_ih.ih_fn = le_vme_intr; + lesc->sc_ih.ih_arg = sc; + lesc->sc_ih.ih_wantframe = 0; + lesc->sc_ih.ih_ipl = lesc->sc_ipl; + vmeintr_establish(lesc->sc_vec, &lesc->sc_ih, self->dv_xname); + + return; + +fail1: + vmebus_release_bst(parent, lesc->sc_iot); +fail2: + bus_space_unmap(lesc->sc_memt, lesc->sc_memh, VLEMEMSIZE); +fail3: + vmebus_release_bst(parent, lesc->sc_memt); +} diff --git a/sys/arch/aviion/dev/if_le_vmereg.h b/sys/arch/aviion/dev/if_le_vmereg.h new file mode 100644 index 00000000000..f006b23edba --- /dev/null +++ b/sys/arch/aviion/dev/if_le_vmereg.h @@ -0,0 +1,85 @@ +/* $OpenBSD: if_le_vmereg.h,v 1.1.1.1 2006/05/09 18:25:00 miod Exp $ */ + +/*- + * Copyright (c) 1982, 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)if_lereg.h 8.2 (Berkeley) 10/30/93 + */ + +#define VLEMEMSIZE 0x00040000 /* 256 KB */ + +/* + * LANCE registers for Interphase 3207 Hawk + */ + +#define LEREG_CSR 0x00 +#define LEREG_VEC 0x02 +#define LEREG_RDP 0x04 +#define LEREG_RAP 0x06 +#define LEREG_EAR 0x08 + +/* CSR bits */ +#define NVRAM_EN 0x0008 /* NVRAM enable bit (active low) */ +#define INTR_EN 0x0010 /* interrupt enable bit (active low) */ +#define PARITYB 0x0020 /* parity error clear bit */ +#define HW_RS 0x0040 /* hardware reset bit (active low) */ +#define SYSFAILB 0x0080 /* SYSFAIL bit */ + +#define NVRAM_RWEL 0xe0 /* Reset write enable latch */ +#define NVRAM_STO 0x60 /* Store ram to eeprom */ +#define NVRAM_SLP 0xa0 /* Novram into low power mode */ +#define NVRAM_WRITE 0x20 /* Writes word from location x */ +#define NVRAM_SWEL 0xc0 /* Set write enable latch */ +#define NVRAM_RCL 0x40 /* Recall eeprom data into ram */ +#define NVRAM_READ 0x00 /* Reads word from location x */ + +#define CDELAY delay(10000) +#define WRITE_CSR_OR(x) \ + do { \ + lesc->sc_csr |= (x); \ + bus_space_write_2(lesc->sc_iot, lesc->sc_ioh, \ + LEREG_CSR, lesc->sc_csr); \ + } while (0) +#define WRITE_CSR_AND(x) \ + do { \ + lesc->sc_csr &= ~(x); \ + bus_space_write_2(lesc->sc_iot, lesc->sc_ioh, \ + LEREG_CSR, lesc->sc_csr); \ + } while (0) +#define ENABLE_NVRAM WRITE_CSR_AND(NVRAM_EN) +#define DISABLE_NVRAM WRITE_CSR_OR(NVRAM_EN) +#define ENABLE_INTR WRITE_CSR_AND(INTR_EN) +#define DISABLE_INTR WRITE_CSR_OR(INTR_EN) +#define RESET_HW \ + do { \ + WRITE_CSR_AND(HW_RS); \ + CDELAY; \ + } while (0) +#define SET_VEC(x) \ + bus_space_write_2(lesc->sc_iot, lesc->sc_ioh, LEREG_VEC, (x)) +#define SYSFAIL_CL WRITE_CSR_AND(SYSFAILB) |