diff options
Diffstat (limited to 'sys/arch/hppa/include')
| -rw-r--r-- | sys/arch/hppa/include/intr.h | 58 |
1 files changed, 24 insertions, 34 deletions
diff --git a/sys/arch/hppa/include/intr.h b/sys/arch/hppa/include/intr.h index ffdf73770ca..78a0a4f6a9c 100644 --- a/sys/arch/hppa/include/intr.h +++ b/sys/arch/hppa/include/intr.h @@ -1,4 +1,4 @@ -/* $OpenBSD: intr.h,v 1.7 1999/02/25 17:27:57 mickey Exp $ */ +/* $OpenBSD: intr.h,v 1.8 1999/08/14 03:36:11 mickey Exp $ */ /* * Copyright (c) 1990,1991,1992,1994 The University of Utah and @@ -30,70 +30,60 @@ #include <machine/psl.h> #define CPU_NINTS 32 +#define CPU_INTITMR (0x80000000) -/* hardwired clock int line */ -#define INT_NONE (0) -#define INT_ITMR (0x80000000) -#define INT_IO (0x80000000) -#define INT_ALL (0xffffffff) - -#define IPL_NONE 0 -#define IPL_BIO 1 -#define IPL_NET 2 -#define IPL_TTY 3 -#define IPL_CLOCK 4 -#define IPL_HIGH 5 +#define IPL_NONE (0xffffffff) +#define IPL_BIO (0x80000000) +#define IPL_NET (0x80000000) +#define IPL_TTY (0x80000000) +#define IPL_IO (IPL_BIO|IPL_NET|IPL_TTY) +#define IPL_CLOCK (0) +#define IPL_HIGH (0) #define IST_NONE 0 #define IST_PULSE 1 #define IST_EDGE 2 #define IST_LEVEL 3 - #if !defined(_LOCORE) /* * Define the machine-independent SPL routines in terms of splx(). */ #define __splhigh(splhval) ({ \ register u_int _ctl_r; \ - __asm __volatile("rsm %2, %%r0\n\t" \ - "mfctl %%cr15,%0\n\t" \ + __asm __volatile("mfctl %%cr15,%0\n\t" \ "mtctl %1,%%cr15" \ - : "=r" (_ctl_r): "r" (splhval), "i" (PSW_I)); \ + : "=&r" (_ctl_r): "r" (splhval)); \ _ctl_r; \ }) #define __spllow(spllval) ({ \ register u_int _ctl_r; \ __asm __volatile("mfctl %%cr15,%0\n\t" \ - "mtctl %1,%%cr15\n\t" \ - "ssm %2, %%r0" \ - : "=r" (_ctl_r): "r" (spllval), "i" (PSW_I)); \ + "mtctl %1,%%cr15" \ + : "=&r" (_ctl_r): "r" (spllval)); \ _ctl_r; \ }) #define splx(splval) ({ \ register u_int _ctl_r; \ - __asm __volatile("rsm %2,%%r0\n\t" \ - "mfctl %%cr15,%0\n\t" \ + __asm __volatile("mfctl %%cr15,%0\n\t" \ "mtctl %1,%%cr15\n\t" \ - "comiclr,= 0,%1,0\n\t" \ - "ssm %2,%%r0" \ - : "=r" (_ctl_r): "r" (splval), "i" (PSW_I)); \ + : "=&r" (_ctl_r): "r" (splval)); \ _ctl_r; \ }) -#define spl0() __spllow(INT_ALL) -#define splsoft() __spllow(INT_ITMR) +#define spl0() __spllow(IPL_NONE) +#define splsoft() __spllow(IPL_CLOCK) #define splsoftnet() splsoft() #define splsoftclock() splsoft() -#define splnet() __spllow(INT_IO) -#define splbio() __spllow(INT_IO) -#define splimp() __spllow(INT_IO) -#define spltty() __spllow(INT_IO) -#define splclock() __spllow(INT_NONE) -#define splstatclock() __spllow(INT_NONE) -#define splhigh() __splhigh(INT_NONE) +#define splbio() __spllow(IPL_BIO) +#define splnet() __spllow(IPL_NET) +#define spltty() __spllow(IPL_TTY) +#define splimp() __spllow(IPL_CLOCK) +#define splclock() __spllow(IPL_CLOCK) +#define splstatclock() __spllow(IPL_CLOCK) +#define splhigh() __splhigh(IPL_HIGH) /* software interrupt register */ extern u_int32_t sir; |