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-rw-r--r--sys/arch/m68k/include/asm_single.h14
-rw-r--r--sys/arch/m68k/include/cacheops_20.h16
-rw-r--r--sys/arch/m68k/include/cacheops_30.h16
-rw-r--r--sys/arch/m68k/include/cacheops_40.h40
-rw-r--r--sys/arch/m68k/include/cacheops_60.h40
5 files changed, 63 insertions, 63 deletions
diff --git a/sys/arch/m68k/include/asm_single.h b/sys/arch/m68k/include/asm_single.h
index 9e6ca71469d..e362f2f933f 100644
--- a/sys/arch/m68k/include/asm_single.h
+++ b/sys/arch/m68k/include/asm_single.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: asm_single.h,v 1.2 1998/04/25 07:09:06 d Exp $ */
+/* $OpenBSD: asm_single.h,v 1.3 2001/01/15 19:50:37 deraadt Exp $ */
/* $NetBSD: asm_single.h,v 1.1 1996/09/16 06:03:58 leo Exp $ */
/*
@@ -42,18 +42,18 @@
*/
#define single_inst_bset_b(var, bit) \
- asm volatile ("orb %0,%1" : : "di" ((u_char)bit), "g" (var))
+ __asm__ __volatile__ ("orb %0,%1" : : "di" ((u_char)bit), "g" (var))
#define single_inst_bclr_b(var, bit) \
- asm volatile ("andb %0,%1" : : "di" ((u_char)~(bit)), "g" (var));
+ __asm__ __volatile__ ("andb %0,%1" : : "di" ((u_char)~(bit)), "g" (var));
#define single_inst_bset_w(var, bit) \
- asm volatile ("orw %0,%1" : : "di" ((u_short)bit), "g" (var))
+ __asm__ __volatile__ ("orw %0,%1" : : "di" ((u_short)bit), "g" (var))
#define single_inst_bclr_w(var, bit) \
- asm volatile ("andw %0,%1" : : "di" ((u_short)~(bit)), "g" (var));
+ __asm__ __volatile__ ("andw %0,%1" : : "di" ((u_short)~(bit)), "g" (var));
#define single_inst_bset_l(var, bit) \
- asm volatile ("orl %0,%1" : : "di" ((u_long)bit), "g" (var))
+ __asm__ __volatile__ ("orl %0,%1" : : "di" ((u_long)bit), "g" (var))
#define single_inst_bclr_l(var, bit) \
- asm volatile ("andl %0,%1" : : "di" ((u_long)~(bit)), "g" (var));
+ __asm__ __volatile__ ("andl %0,%1" : : "di" ((u_long)~(bit)), "g" (var));
#endif /* _M68K_ASM_SINGLE_H */
diff --git a/sys/arch/m68k/include/cacheops_20.h b/sys/arch/m68k/include/cacheops_20.h
index 5dc67cd4e22..d5156b6085f 100644
--- a/sys/arch/m68k/include/cacheops_20.h
+++ b/sys/arch/m68k/include/cacheops_20.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: cacheops_20.h,v 1.1 1997/07/06 07:46:23 downsj Exp $ */
+/* $OpenBSD: cacheops_20.h,v 1.2 2001/01/15 19:50:37 deraadt Exp $ */
/* $NetBSD: cacheops_20.h,v 1.1 1997/06/02 20:26:39 leo Exp $ */
/*-
@@ -41,7 +41,7 @@
* Invalidate entire TLB.
*/
void TBIA_20 __P((void));
-extern inline void
+extern __inline__ void
TBIA_20()
{
__asm __volatile (" pflusha");
@@ -51,7 +51,7 @@ TBIA_20()
* Invalidate any TLB entry for given VA (TB Invalidate Single)
*/
void TBIS_20 __P((void *));
-extern inline void
+extern __inline__ void
TBIS_20(va)
void *va;
{
@@ -63,7 +63,7 @@ TBIS_20(va)
* Invalidate supervisor side of TLB
*/
void TBIAS_20 __P((void));
-extern inline void
+extern __inline__ void
TBIAS_20()
{
__asm __volatile (" pflushs #4,#4");
@@ -73,7 +73,7 @@ TBIAS_20()
* Invalidate user side of TLB
*/
void TBIAU_20 __P((void));
-extern inline void
+extern __inline__ void
TBIAU_20()
{
__asm __volatile (" pflushs #0,#4;");
@@ -83,14 +83,14 @@ TBIAU_20()
* Invalidate instruction cache
*/
void ICIA_20 __P((void));
-extern inline void
+extern __inline__ void
ICIA_20()
{
__asm __volatile (" movc %0,cacr;" : : "d" (IC_CLEAR));
}
void ICPA_20 __P((void));
-extern inline void
+extern __inline__ void
ICPA_20()
{
__asm __volatile (" movc %0,cacr;" : : "d" (IC_CLEAR));
@@ -109,7 +109,7 @@ ICPA_20()
#define DCIAS_20()
void PCIA_20 __P((void));
-extern inline void
+extern __inline__ void
PCIA_20()
{
__asm __volatile (" movc %0,cacr;" : : "d" (DC_CLEAR));
diff --git a/sys/arch/m68k/include/cacheops_30.h b/sys/arch/m68k/include/cacheops_30.h
index 6a9f782361d..f03af6255f3 100644
--- a/sys/arch/m68k/include/cacheops_30.h
+++ b/sys/arch/m68k/include/cacheops_30.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: cacheops_30.h,v 1.1 1997/07/06 07:46:24 downsj Exp $ */
+/* $OpenBSD: cacheops_30.h,v 1.2 2001/01/15 19:50:37 deraadt Exp $ */
/* $NetBSD: cacheops_30.h,v 1.1 1997/06/02 20:26:40 leo Exp $ */
/*-
@@ -41,7 +41,7 @@
* Invalidate entire TLB.
*/
void TBIA_30 __P((void));
-extern inline void
+extern __inline__ void
TBIA_30()
{
int tmp = DC_CLEAR;
@@ -54,7 +54,7 @@ TBIA_30()
* Invalidate any TLB entry for given VA (TB Invalidate Single)
*/
void TBIS_30 __P((vm_offset_t));
-extern inline void
+extern __inline__ void
TBIS_30(va)
vm_offset_t va;
{
@@ -66,7 +66,7 @@ TBIS_30(va)
* Invalidate supervisor side of TLB
*/
void TBIAS_30 __P((void));
-extern inline void
+extern __inline__ void
TBIAS_30()
{
__asm __volatile (" pflush #4,#4;"
@@ -77,7 +77,7 @@ TBIAS_30()
* Invalidate user side of TLB
*/
void TBIAU_30 __P((void));
-extern inline void
+extern __inline__ void
TBIAU_30()
{
__asm __volatile (" pflush #0,#4;"
@@ -88,14 +88,14 @@ TBIAU_30()
* Invalidate instruction cache
*/
void ICIA_30 __P((void));
-extern inline void
+extern __inline__ void
ICIA_30()
{
__asm __volatile (" movc %0,cacr;" : : "d" (IC_CLEAR));
}
void ICPA_30 __P((void));
-extern inline void
+extern __inline__ void
ICPA_30()
{
__asm __volatile (" movc %0,cacr;" : : "d" (IC_CLEAR));
@@ -115,7 +115,7 @@ ICPA_30()
void PCIA_30 __P((void));
-extern inline void
+extern __inline__ void
PCIA_30()
{
__asm __volatile (" movc %0,cacr;" : : "d" (DC_CLEAR));
diff --git a/sys/arch/m68k/include/cacheops_40.h b/sys/arch/m68k/include/cacheops_40.h
index 845c9550161..3dd35b447fe 100644
--- a/sys/arch/m68k/include/cacheops_40.h
+++ b/sys/arch/m68k/include/cacheops_40.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: cacheops_40.h,v 1.1 1997/07/06 07:46:24 downsj Exp $ */
+/* $OpenBSD: cacheops_40.h,v 1.2 2001/01/15 19:50:37 deraadt Exp $ */
/* $NetBSD: cacheops_40.h,v 1.1 1997/06/02 20:26:41 leo Exp $ */
/*-
@@ -41,7 +41,7 @@
* Invalidate entire TLB.
*/
void TBIA_40 __P((void));
-extern inline void
+extern __inline__ void
TBIA_40()
{
__asm __volatile (" .word 0xf518" ); /* pflusha */
@@ -51,7 +51,7 @@ TBIA_40()
* Invalidate any TLB entry for given VA (TB Invalidate Single)
*/
void TBIS_40 __P((vm_offset_t));
-extern inline void
+extern __inline__ void
TBIS_40(va)
vm_offset_t va;
{
@@ -70,7 +70,7 @@ TBIS_40(va)
* Invalidate supervisor side of TLB
*/
void TBIAS_40 __P((void));
-extern inline void
+extern __inline__ void
TBIAS_40()
{
/*
@@ -83,7 +83,7 @@ TBIAS_40()
* Invalidate user side of TLB
*/
void TBIAU_40 __P((void));
-extern inline void
+extern __inline__ void
TBIAU_40()
{
/*
@@ -96,14 +96,14 @@ TBIAU_40()
* Invalidate instruction cache
*/
void ICIA_40 __P((void));
-extern inline void
+extern __inline__ void
ICIA_40()
{
__asm __volatile (" .word 0xf498;"); /* cinva ic */
}
void ICPA_40 __P((void));
-extern inline void
+extern __inline__ void
ICPA_40()
{
__asm __volatile (" .word 0xf498;"); /* cinva ic */
@@ -113,28 +113,28 @@ ICPA_40()
* Invalidate data cache.
*/
void DCIA_40 __P((void));
-extern inline void
+extern __inline__ void
DCIA_40()
{
__asm __volatile (" .word 0xf478;"); /* cpusha dc */
}
void DCIS_40 __P((void));
-extern inline void
+extern __inline__ void
DCIS_40()
{
__asm __volatile (" .word 0xf478;"); /* cpusha dc */
}
void DCIU_40 __P((void));
-extern inline void
+extern __inline__ void
DCIU_40()
{
__asm __volatile (" .word 0xf478;"); /* cpusha dc */
}
void DCIAS_40 __P((vm_offset_t));
-extern inline void
+extern __inline__ void
DCIAS_40(va)
vm_offset_t va;
{
@@ -144,14 +144,14 @@ DCIAS_40(va)
}
void PCIA_40 __P((void));
-extern inline void
+extern __inline__ void
PCIA_40()
{
__asm __volatile (" .word 0xf478;"); /* cpusha dc */
}
void DCFA_40 __P((void));
-extern inline void
+extern __inline__ void
DCFA_40()
{
__asm __volatile (" .word 0xf478;"); /* cpusha dc */
@@ -159,7 +159,7 @@ DCFA_40()
/* invalidate instruction physical cache line */
void ICPL_40 __P((vm_offset_t));
-extern inline void
+extern __inline__ void
ICPL_40(va)
vm_offset_t va;
{
@@ -170,7 +170,7 @@ ICPL_40(va)
/* invalidate instruction physical cache page */
void ICPP_40 __P((vm_offset_t));
-extern inline void
+extern __inline__ void
ICPP_40(va)
vm_offset_t va;
{
@@ -181,7 +181,7 @@ ICPP_40(va)
/* invalidate data physical cache line */
void DCPL_40 __P((vm_offset_t));
-extern inline void
+extern __inline__ void
DCPL_40(va)
vm_offset_t va;
{
@@ -192,7 +192,7 @@ DCPL_40(va)
/* invalidate data physical cache page */
void DCPP_40 __P((vm_offset_t));
-extern inline void
+extern __inline__ void
DCPP_40(va)
vm_offset_t va;
{
@@ -203,7 +203,7 @@ DCPP_40(va)
/* invalidate data physical all */
void DCPA_40 __P((void));
-extern inline void
+extern __inline__ void
DCPA_40()
{
__asm __volatile (" .word 0xf458;"); /* cinva dc */
@@ -211,7 +211,7 @@ DCPA_40()
/* data cache flush line */
void DCFL_40 __P((vm_offset_t));
-extern inline void
+extern __inline__ void
DCFL_40(va)
vm_offset_t va;
{
@@ -222,7 +222,7 @@ DCFL_40(va)
/* data cache flush page */
void DCFP_40 __P((vm_offset_t));
-extern inline void
+extern __inline__ void
DCFP_40(va)
vm_offset_t va;
{
diff --git a/sys/arch/m68k/include/cacheops_60.h b/sys/arch/m68k/include/cacheops_60.h
index 1c7f8c5983f..6b1c846cab4 100644
--- a/sys/arch/m68k/include/cacheops_60.h
+++ b/sys/arch/m68k/include/cacheops_60.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: cacheops_60.h,v 1.1 1997/07/06 07:46:25 downsj Exp $ */
+/* $OpenBSD: cacheops_60.h,v 1.2 2001/01/15 19:50:38 deraadt Exp $ */
/* $NetBSD: cacheops_60.h,v 1.1 1997/06/02 20:26:43 leo Exp $ */
/*-
@@ -41,7 +41,7 @@
* Invalidate entire TLB.
*/
void TBIA_60 __P((void));
-extern inline void
+extern __inline__ void
TBIA_60()
{
__asm __volatile (" .word 0xf518" ); /* pflusha */
@@ -51,7 +51,7 @@ TBIA_60()
* Invalidate any TLB entry for given VA (TB Invalidate Single)
*/
void TBIS_60 __P((vm_offset_t));
-extern inline void
+extern __inline__ void
TBIS_60(va)
vm_offset_t va;
{
@@ -74,7 +74,7 @@ TBIS_60(va)
* Invalidate supervisor side of TLB
*/
void TBIAS_60 __P((void));
-extern inline void
+extern __inline__ void
TBIAS_60()
{
int tmp;
@@ -92,7 +92,7 @@ TBIAS_60()
* Invalidate user side of TLB
*/
void TBIAU_60 __P((void));
-extern inline void
+extern __inline__ void
TBIAU_60()
{
int tmp;
@@ -110,7 +110,7 @@ TBIAU_60()
* Invalidate instruction cache
*/
void ICIA_60 __P((void));
-extern inline void
+extern __inline__ void
ICIA_60()
{
/* inva ic (also clears branch cache) */
@@ -118,7 +118,7 @@ ICIA_60()
}
void ICPA_60 __P((void));
-extern inline void
+extern __inline__ void
ICPA_60()
{
/* inva ic (also clears branch cache) */
@@ -129,28 +129,28 @@ ICPA_60()
* Invalidate data cache.
*/
void DCIA_60 __P((void));
-extern inline void
+extern __inline__ void
DCIA_60()
{
__asm __volatile (" .word 0xf478;"); /* cpusha dc */
}
void DCIS_60 __P((void));
-extern inline void
+extern __inline__ void
DCIS_60()
{
__asm __volatile (" .word 0xf478;"); /* cpusha dc */
}
void DCIU_60 __P((void));
-extern inline void
+extern __inline__ void
DCIU_60()
{
__asm __volatile (" .word 0xf478;"); /* cpusha dc */
}
void DCIAS_60 __P((vm_offset_t));
-extern inline void
+extern __inline__ void
DCIAS_60(va)
vm_offset_t va;
{
@@ -160,14 +160,14 @@ DCIAS_60(va)
}
void PCIA_60 __P((void));
-extern inline void
+extern __inline__ void
PCIA_60()
{
__asm __volatile (" .word 0xf478;"); /* cpusha dc */
}
void DCFA_60 __P((void));
-extern inline void
+extern __inline__ void
DCFA_60()
{
__asm __volatile (" .word 0xf478;"); /* cpusha dc */
@@ -175,7 +175,7 @@ DCFA_60()
/* invalidate instruction physical cache line */
void ICPL_60 __P((vm_offset_t));
-extern inline void
+extern __inline__ void
ICPL_60(va)
vm_offset_t va;
{
@@ -186,7 +186,7 @@ ICPL_60(va)
/* invalidate instruction physical cache page */
void ICPP_60 __P((vm_offset_t));
-extern inline void
+extern __inline__ void
ICPP_60(va)
vm_offset_t va;
{
@@ -197,7 +197,7 @@ ICPP_60(va)
/* invalidate data physical cache line */
void DCPL_60 __P((vm_offset_t));
-extern inline void
+extern __inline__ void
DCPL_60(va)
vm_offset_t va;
{
@@ -208,7 +208,7 @@ DCPL_60(va)
/* invalidate data physical cache page */
void DCPP_60 __P((vm_offset_t));
-extern inline void
+extern __inline__ void
DCPP_60(va)
vm_offset_t va;
{
@@ -219,7 +219,7 @@ DCPP_60(va)
/* invalidate data physical all */
void DCPA_60 __P((void));
-extern inline void
+extern __inline__ void
DCPA_60()
{
__asm __volatile (" .word 0xf458;"); /* cinva dc */
@@ -227,7 +227,7 @@ DCPA_60()
/* data cache flush line */
void DCFL_60 __P((vm_offset_t));
-extern inline void
+extern __inline__ void
DCFL_60(va)
vm_offset_t va;
{
@@ -238,7 +238,7 @@ DCFL_60(va)
/* data cache flush page */
void DCFP_60 __P((vm_offset_t));
-extern inline void
+extern __inline__ void
DCFP_60(va)
vm_offset_t va;
{
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-14 01:47:06 +0000