diff options
Diffstat (limited to 'sys/arch/mips64')
| -rw-r--r-- | sys/arch/mips64/mips64/disksubr.c | 4 | ||||
| -rw-r--r-- | sys/arch/mips64/mips64/interrupt.c | 14 | ||||
| -rw-r--r-- | sys/arch/mips64/mips64/sendsig.c | 4 | ||||
| -rw-r--r-- | sys/arch/mips64/mips64/tlbhandler.S | 10 |
4 files changed, 16 insertions, 16 deletions
diff --git a/sys/arch/mips64/mips64/disksubr.c b/sys/arch/mips64/mips64/disksubr.c index 536eeaad725..1284ae3a8c9 100644 --- a/sys/arch/mips64/mips64/disksubr.c +++ b/sys/arch/mips64/mips64/disksubr.c @@ -1,4 +1,4 @@ -/* $OpenBSD: disksubr.c,v 1.10 2006/01/22 00:40:01 miod Exp $ */ +/* $OpenBSD: disksubr.c,v 1.11 2006/03/04 19:33:21 miod Exp $ */ /* * Copyright (c) 1999 Michael Shalayeff @@ -250,7 +250,7 @@ readdisklabel(dev, strat, lp, osdep, spoofonly) int i; struct disklabel minilabel, fallbacklabel; - /* minimal requirements for archtypal disk label */ + /* minimal requirements for archetypal disk label */ if (lp->d_secsize < DEV_BSIZE) lp->d_secsize = DEV_BSIZE; if (lp->d_secperunit == 0) diff --git a/sys/arch/mips64/mips64/interrupt.c b/sys/arch/mips64/mips64/interrupt.c index 6005ffd2fc5..eed49306e4d 100644 --- a/sys/arch/mips64/mips64/interrupt.c +++ b/sys/arch/mips64/mips64/interrupt.c @@ -1,4 +1,4 @@ -/* $OpenBSD: interrupt.c,v 1.19 2005/12/20 06:57:52 miod Exp $ */ +/* $OpenBSD: interrupt.c,v 1.20 2006/03/04 19:33:21 miod Exp $ */ /* * Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -81,7 +81,7 @@ int netisr; /* * Modern versions of MIPS processors have extended interrupt - * capabilites. How these are handeled differs from implementation + * capabilities. How these are handled differs from implementation * to implementation. This code tries to hide away some of these * in "higher level" interrupt code. * @@ -96,7 +96,7 @@ int netisr; * * The interrupt mechanism in this port uses a delayed masking model * where interrupts are not really masked when doing an spl(). Instead - * a masked interrupt will be taken and validiated in the various + * a masked interrupt will be taken and validated in the various * handlers. If the handler finds that an interrupt is masked it will * register this interrupt as pending and return a new mask to this * code that will turn off the interrupt hardware wise. Later when @@ -113,13 +113,13 @@ int netisr; * in the RM7000. IPL12 extra timer is currently not used. * * irq's maps into the software spl register to the bit corresponding - * to it's status/mask bit in the cause/sr register shifted right eight + * to its status/mask bit in the cause/sr register shifted right eight * places. * * A well designed system uses the CPUs interrupt inputs in a way, such * that masking can be done according to the IPL in the CPU status and - * interrupt vontrol register. However support for an external masking - * register is provided but will case a slightly higher overhead when + * interrupt control register. However support for an external masking + * register is provided but will cause a slightly higher overhead when * used. When an external masking register is used, no masking in the * CPU is done. Instead a fixed mask is set and used throughout. */ @@ -128,7 +128,7 @@ void interrupt (struct trap_frame *); void softintr (void); /* - * Handle an interrupt. Both kernel and user mode is handeled here. + * Handle an interrupt. Both kernel and user mode is handled here. * * The interrupt handler is called with the CR_INT bits set that * was given when the handlers was registred that needs servicing. diff --git a/sys/arch/mips64/mips64/sendsig.c b/sys/arch/mips64/mips64/sendsig.c index 326abbc652d..698697f2aad 100644 --- a/sys/arch/mips64/mips64/sendsig.c +++ b/sys/arch/mips64/mips64/sendsig.c @@ -1,4 +1,4 @@ -/* $OpenBSD: sendsig.c,v 1.8 2005/12/20 06:58:19 miod Exp $ */ +/* $OpenBSD: sendsig.c,v 1.9 2006/03/04 19:33:21 miod Exp $ */ /* * Copyright (c) 1990 The Regents of the University of California. @@ -210,7 +210,7 @@ bail: * Return to previous pc and psl as specified by * context left by sendsig. Check carefully to * make sure that the user has not modified the - * psl to gain improper priviledges or to cause + * psl to gain improper privileges or to cause * a machine fault. */ /* ARGSUSED */ diff --git a/sys/arch/mips64/mips64/tlbhandler.S b/sys/arch/mips64/mips64/tlbhandler.S index 13efe4d25e8..cedf1938507 100644 --- a/sys/arch/mips64/mips64/tlbhandler.S +++ b/sys/arch/mips64/mips64/tlbhandler.S @@ -1,4 +1,4 @@ -/* $OpenBSD: tlbhandler.S,v 1.12 2005/12/20 07:06:26 miod Exp $ */ +/* $OpenBSD: tlbhandler.S,v 1.13 2006/03/04 19:33:21 miod Exp $ */ /* * Copyright (c) 1995-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -179,7 +179,7 @@ tlb_miss_nopt: .set at /* - * Trampolines copied to exception vectors when code is to big. + * Trampolines copied to exception vectors when code is too big. */ .globl tlb_miss_tramp tlb_miss_tramp: @@ -464,7 +464,7 @@ LEAF(tlb_flush_addr, 0) mtc0 v0, COP_0_STATUS_REG # Disable interrupts ITLBNOPFIX li v0, (PG_HVPN | PG_ASID) - and a0, a0, v0 # Make shure valid hi value. + and a0, a0, v0 # Make sure valid hi value. dmfc0 ta0, COP_0_TLB_HI # Get current PID dmtc0 a0, COP_0_TLB_HI # look for addr & PID nop @@ -582,9 +582,9 @@ LEAF(tlb_update, 0) nop li v0, 0 -4: # Make shure pipeline +4: # Make sure pipeline nop # advances before we - nop # uses the tlb. + nop # use the tlb. dmtc0 ta0, COP_0_TLB_HI # restore PID mtc0 v1, COP_0_STATUS_REG # Restore the status register ITLBNOPFIX |