diff options
Diffstat (limited to 'sys/arch/mips64')
| -rw-r--r-- | sys/arch/mips64/conf/files.mips64 | 3 | ||||
| -rw-r--r-- | sys/arch/mips64/include/cpu.h | 9 | ||||
| -rw-r--r-- | sys/arch/mips64/mips64/cache_octeon.c | 112 |
3 files changed, 122 insertions, 2 deletions
diff --git a/sys/arch/mips64/conf/files.mips64 b/sys/arch/mips64/conf/files.mips64 index f1e2eafb434..4cbaa6bb8b4 100644 --- a/sys/arch/mips64/conf/files.mips64 +++ b/sys/arch/mips64/conf/files.mips64 @@ -1,4 +1,4 @@ -# $OpenBSD: files.mips64,v 1.14 2009/12/12 20:06:50 miod Exp $ +# $OpenBSD: files.mips64,v 1.15 2010/09/20 12:10:26 syuu Exp $ file arch/mips64/mips64/arcbios.c arcbios file arch/mips64/mips64/clock.c @@ -16,6 +16,7 @@ file arch/mips64/mips64/vm_machdep.c file arch/mips64/mips64/cache_loongson2.S cpu_loongson2 file arch/mips64/mips64/cache_r5k.S cpu_r5000 | cpu_rm7000 file arch/mips64/mips64/cache_r10k.S cpu_r10000 +file arch/mips64/mips64/cache_octeon.c cpu_octeon file arch/mips64/mips64/context.S file arch/mips64/mips64/cp0access.S file arch/mips64/mips64/exception.S diff --git a/sys/arch/mips64/include/cpu.h b/sys/arch/mips64/include/cpu.h index 4b3f6e66bb0..429bd17d05f 100644 --- a/sys/arch/mips64/include/cpu.h +++ b/sys/arch/mips64/include/cpu.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.h,v 1.63 2010/09/17 00:35:51 miod Exp $ */ +/* $OpenBSD: cpu.h,v 1.64 2010/09/20 12:10:26 syuu Exp $ */ /*- * Copyright (c) 1992, 1993 @@ -590,6 +590,13 @@ void tlb_set_wired(int); /* * Available cache operation routines. See <machine/cpu.h> for more. */ +int Octeon_ConfigCache(struct cpu_info *); +void Octeon_SyncCache(struct cpu_info *); +void Octeon_InvalidateICache(struct cpu_info *, vaddr_t, size_t); +void Octeon_SyncDCachePage(struct cpu_info *, paddr_t); +void Octeon_HitSyncDCache(struct cpu_info *, paddr_t, size_t); +void Octeon_HitInvalidateDCache(struct cpu_info *, paddr_t, size_t); +void Octeon_IOSyncDCache(struct cpu_info *, paddr_t, size_t, int); int Loongson2_ConfigCache(struct cpu_info *); void Loongson2_SyncCache(struct cpu_info *); diff --git a/sys/arch/mips64/mips64/cache_octeon.c b/sys/arch/mips64/mips64/cache_octeon.c new file mode 100644 index 00000000000..4b1d261be27 --- /dev/null +++ b/sys/arch/mips64/mips64/cache_octeon.c @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2010 Takuya ASADA. + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +/* + * Copyright (c) 1998-2004 Opsycon AB (www.opsycon.se) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/kernel.h> + +#include <uvm/uvm_extern.h> + +#include <machine/cpu.h> + +#define SYNC() asm volatile("sync\n") +#define SYNCI() \ + asm volatile( \ + ".set push\n" \ + ".set mips64r2\n" \ + ".word 0x041f0000\n" \ + "nop\n" \ + ".set pop") + +int +Octeon_ConfigCache(struct cpu_info *ci) +{ + ci->ci_cacheways = 4; + ci->ci_l1instcachesize = 32 * 1024; + ci->ci_l1instcacheline = 128; + ci->ci_l1datacachesize = 16 * 1024; + ci->ci_l1datacacheline = 128; + ci->ci_l2size = 128 * 1024; + ci->ci_l3size = 0; + return 0; +} + +void +Octeon_SyncCache(struct cpu_info *ci) +{ + SYNC(); +} + +void +Octeon_InvalidateICache(struct cpu_info *ci, vaddr_t addr, size_t len) +{ + /* A SYNCI flushes the entire icache on OCTEON */ + SYNCI(); +} + +void +Octeon_SyncDCachePage(struct cpu_info *ci, paddr_t addr) +{ +} + +void +Octeon_HitSyncDCache(struct cpu_info *ci, paddr_t addr, size_t len) +{ +} + +void +Octeon_HitInvalidateDCache(struct cpu_info *ci, paddr_t addr, size_t len) +{ +} + +void +Octeon_IOSyncDCache(struct cpu_info *ci, paddr_t addr, size_t len, int how) +{ + switch (how) { + default: + case 0: + break; + case 1: /* writeback */ + case 2: /* writeback and invalidate */ + SYNC(); + break; + } +} |