diff options
Diffstat (limited to 'sys/arch/mvme88k/dev/pcctworeg.h')
| -rw-r--r-- | sys/arch/mvme88k/dev/pcctworeg.h | 197 |
1 files changed, 76 insertions, 121 deletions
diff --git a/sys/arch/mvme88k/dev/pcctworeg.h b/sys/arch/mvme88k/dev/pcctworeg.h index 268d481ef5c..41a95b770fa 100644 --- a/sys/arch/mvme88k/dev/pcctworeg.h +++ b/sys/arch/mvme88k/dev/pcctworeg.h @@ -1,141 +1,101 @@ -/* $OpenBSD: pcctworeg.h,v 1.6 2002/01/14 21:34:39 miod Exp $ */ +/* $OpenBSD: pcctworeg.h,v 1.7 2004/04/24 19:51:48 miod Exp $ */ /* - * Memory map for PCC2 chip found in mvme1x7 boards. + * Memory map for PCC2 chip found in MVME1x7 boards. * * PCCchip2 control and status register can be accessed as bytes (8 bits), * two-bytes (16 bits), or four-bytes (32 bits). */ -struct pcctworeg { - volatile u_char pcc2_chipid; - volatile u_char pcc2_chiprev; - volatile u_char pcc2_genctl; - volatile u_char pcc2_vecbase; /* irq vector base */ - volatile u_long pcc2_t1cmp; /* timer1 compare */ - volatile u_long pcc2_t1count; /* timer1 count */ - volatile u_long pcc2_t2cmp; /* timer2 compare */ - volatile u_long pcc2_t2count; /* timer2 count */ - volatile u_char pcc2_pscalecnt; /* timer prescaler counter */ - volatile u_char pcc2_pscaleadj; /* timer prescaler adjust */ - volatile u_char pcc2_t2ctl; /* timer2 ctrl reg */ - volatile u_char pcc2_t1ctl; /* timer1 ctrl reg */ - volatile u_char pcc2_gpioirq; /* gpio irq */ - volatile u_char pcc2_gpio; /* gpio i/o */ - volatile u_char pcc2_t2irq; - volatile u_char pcc2_t1irq; - volatile u_char pcc2_sccerr; - volatile u_char pcc2_sccirq; - volatile u_char pcc2_scctx; - volatile u_char pcc2_sccrx; - volatile u_char :8; - volatile u_char :8; - volatile u_char :8; - volatile u_char pcc2_sccmoiack; - volatile u_char :8; - volatile u_char pcc2_scctxiack; - volatile u_char :8; - volatile u_char pcc2_sccrxiack; - volatile u_char pcc2_ieerr; - volatile u_char :8; - volatile u_char pcc2_ieirq; - volatile u_char pcc2_iefailirq; - volatile u_char pcc2_ncrerr; - volatile u_char :8; - volatile u_char :8; - volatile u_char pcc2_ncrirq; - volatile u_char pcc2_prtairq; - volatile u_char pcc2_prtfirq; - volatile u_char pcc2_prtsirq; - volatile u_char pcc2_prtpirq; - volatile u_char pcc2_prtbirq; - volatile u_char :8; - volatile u_char pcc2_prtstat; - volatile u_char pcc2_prtctl; - volatile u_short pcc2_speed; /* DO NOT USE */ - volatile u_short pcc2_prtdat; - volatile u_short :16; - /* The following regs are not valid on MVME197 */ - volatile u_char pcc2_ipl; - volatile u_char pcc2_mask; -}; -#define PCC2_PCC2CHIP_OFF 0x42000 -#define PCC2_CHIPID 0x20 -#define PCC2_BASE_ADDR 0xFFF42000 /* base address */ -#define PCC2_SIZE 0x1000 /* size */ -#define PCC2_CHIP_REV 0x00 - -/* General Control Register */ - +#define PCC2_BASE 0x00042000 +#define PCC2_SIZE 0x0040 + +#define PCCTWO_CHIPID 0x0000 +#define PCCTWO_CHIPREV 0x0001 +#define PCCTWO_GENCTL 0x0002 +#define PCCTWO_VECBASE 0x0003 +#define PCCTWO_T1CMP 0x0004 +#define PCCTWO_T1COUNT 0x0008 +#define PCCTWO_T2CMP 0x000c +#define PCCTWO_T2COUNT 0x0010 +#define PCCTWO_PSCALECNT 0x0014 +#define PCCTWO_PSCALEADJ 0x0015 +#define PCCTWO_T2CTL 0x0016 +#define PCCTWO_T1CTL 0x0017 +#define PCCTWO_GPIO_ICR 0x0018 +#define PCCTWO_GPIO_PCR 0x0019 +#define PCCTWO_T2ICR 0x001a +#define PCCTWO_T1ICR 0x001b +#define PCCTWO_SCCERR 0x001c +#define PCCTWO_SCCICR 0x001d +#define PCCTWO_SCCTX 0x001e +#define PCCTWO_SCCRX 0x001f +#define PCCTWO_SCCMOIACK 0x0023 +#define PCCTWO_SCCTXIACK 0x0025 +#define PCCTWO_SCCRXIACK 0x0027 +#define PCCTWO_IEERR 0x0028 +#define PCCTWO_IEICR 0x002a +#define PCCTWO_IEBERR 0x002b +#define PCCTWO_SCSIERR 0x002c +#define PCCTWO_SCSIICR 0x002f +#define PCCTWO_PRTICR 0x0030 +#define PCCTWO_PTRFICR 0x0031 +#define PCCTWO_PTRSICR 0x0032 +#define PCCTWO_PTRPICR 0x0033 +#define PCCTWO_PRTBICR 0x0034 +#define PCCTWO_PRTSTATUS 0x0036 +#define PCCTWO_PRTCTL 0x0037 +#define PCCTWO_SPEED 0x0038 +#define PCCTWO_PRTDATA 0x003a +/* The following registers are not valid on MVME197 */ +#define PCCTWO_IPL 0x003e +#define PCCTWO_MASK 0x003f + +#define PCC2_ID 0x20 /* value at CHIPID */ + +/* General Control Register */ #define PCC2_DR0 0x80 #define PCC2_C040 0x04 #define PCC2_MIEN 0x02 #define PCC2_FAST 0x01 /* Top 4 bits of the PCC2 VBR. Will be the top 4 bits of the vector */ - #define PCC2_VECT 0x50 /* Bottom 4 bits of the vector returned during IACK cycle */ -#define PPBSY 0x00 /* lowest */ -#define PPSE 0x01 -#define PPSEL 0x02 -#define PPFLT 0x03 -#define PPACK 0x04 -#define SCSIIRQ 0x05 -#define LANCERR 0x06 -#define LANCIRQ 0x07 -#define TIMER1IRQ 0x08 -#define TIMER2IRQ 0x09 -#define GPIOIRQ 0x0a -#define SRXEIRQ 0x0c -#define SMOIRQ 0x0d -#define STxIRQ 0x0e -#define SRxIRQ 0x0f - +#define PCC2V_PPBUSY 0x00 /* lowest */ +#define PCC2V_PPPE 0x01 +#define PCC2V_PPSELECT 0x02 +#define PCC2V_PPFAULT 0x03 +#define PCC2V_PPACK 0x04 +#define PCC2V_SCSI 0x05 +#define PCC2V_IEFAIL 0x06 +#define PCC2V_IE 0x07 +#define PCC2V_TIMER2 0x08 +#define PCC2V_TIMER1 0x09 +#define PCC2V_GPIO 0x0a +#define PCC2V_SCC_RXE 0x0c +#define PCC2V_SCC_M (PCC2V_SCC_RXE + 1) +#define PCC2V_SCC_TX (PCC2V_SCC_M + 1) +#define PCC2V_SCC_RX (PCC2V_SCC_TX + 1) /* * Vaddrs for interrupt mask and pri registers */ -extern u_char *volatile pcc2intr_mask; -extern u_char *volatile pcc2intr_ipl; - -/* - * points to system's PCCTWO. This is not active until the pcctwo0 - * device has been attached. - */ -extern struct pcctworeg *sys_pcc2; +extern u_int8_t *volatile pcc2intr_mask; +extern u_int8_t *volatile pcc2intr_ipl; /* * We lock off our interrupt vector at 0x50. */ #define PCC2_VECBASE 0x50 -#define PCC2_NVEC 16 - -/* - * Vectors we use - */ -#define PCC2V_NCR 0x05 -#define PCC2V_IEFAIL 0x06 -#define PCC2V_IE 0x07 -#define PCC2V_TIMER2 0x08 -#define PCC2V_TIMER1 0x09 -#define PCC2V_GPIO 0x0a -#define PCC2V_SCC_RXE 0x0c -#define PCC2V_SCC_M 0x0d -#define PCC2V_SCC_TX 0x0e -#define PCC2V_SCC_RX 0x0f +#define PCC2_NVEC 0x10 #define PCC2_TCTL_CEN 0x01 #define PCC2_TCTL_COC 0x02 #define PCC2_TCTL_COVF 0x04 #define PCC2_TCTL_OVF 0xf0 -#define PCC2_TICTL_CEN 0x01 -#define PCC2_TICTL_COC 0x02 -#define PCC2_TICTL_COVF 0x04 -#define PCC2_TTCTL_OVF_MASK (1 << 4) /* overflow bits mask */ - #define PCC2_GPIO_PLTY 0x80 #define PCC2_GPIO_EL 0x40 @@ -143,10 +103,11 @@ extern struct pcctworeg *sys_pcc2; #define PCC2_GPIOCR_O 0x1 #define PCC2_SCC_AVEC 0x08 -#define PCC2_SCCRX_INHIBIT (0 << 6) -#define PCC2_SCCRX_SNOOP (1 << 6) -#define PCC2_SCCRX_INVAL (2 << 6) -#define PCC2_SCCRX_RESV (3 << 6) + +#define PCC2_SC_INHIBIT (0 << 6) +#define PCC2_SC_SNOOP (1 << 6) +#define PCC2_SC_INVAL (2 << 6) +#define PCC2_SC_RESV (3 << 6) #define pcc2_timer_us2lim(us) (us) /* timer increments in "us" */ @@ -156,19 +117,13 @@ extern struct pcctworeg *sys_pcc2; #define PCC2_IRQ_INT 0x20 /* Tick Timer Interrupt Control Register */ - -#define PCC2_TTIRQ_INT 0x20 -#define PCC2_TTIRQ_IEN 0x10 -#define PCC2_TTIRQ_ICLR 0x08 -#define PCC2_TTIRQ_IL 0x07 /* mask for IL2-IL0 */ +#define PCC2_TTIRQ_INT 0x20 +#define PCC2_TTIRQ_IEN 0x10 +#define PCC2_TTIRQ_ICLR 0x08 +#define PCC2_TTIRQ_IL 0x07 /* mask for IL2-IL0 */ #define PCC2_IEERR_SCLR 0x01 #define PCC2_GENCTL_FAST 0x01 #define PCC2_GENCTL_IEN 0x02 #define PCC2_GENCTL_C040 0x03 - -#define PCC2_SC_INHIBIT (0 << 6) -#define PCC2_SC_SNOOP (1 << 6) -#define PCC2_SC_INVAL (2 << 6) -#define PCC2_SC_RESV (3 << 6) |