diff options
Diffstat (limited to 'sys/arch/mvme88k/dev/pcctworeg.h')
| -rw-r--r-- | sys/arch/mvme88k/dev/pcctworeg.h | 229 |
1 files changed, 112 insertions, 117 deletions
diff --git a/sys/arch/mvme88k/dev/pcctworeg.h b/sys/arch/mvme88k/dev/pcctworeg.h index b029797bd54..3a4cbbb1f2f 100644 --- a/sys/arch/mvme88k/dev/pcctworeg.h +++ b/sys/arch/mvme88k/dev/pcctworeg.h @@ -1,3 +1,5 @@ +/* $OpenBSD: pcctworeg.h,v 1.2 1998/12/15 05:52:30 smurph Exp $ */ + /* * Memory map for PCC2 chip found in mvme1x7 boards. * @@ -5,68 +7,61 @@ * two-bytes (16 bits), or four-bytes (32 bits). */ -struct pcc2reg { - volatile u_char pcc2_chipid; - volatile u_char pcc2_chiprev; - volatile u_char pcc2_gcr; - volatile u_char pcc2_vbr; /* vector base reg. */ - volatile u_long pcc2_t1cmp; /* timer1 compare reg */ - volatile u_long pcc2_t1cntr; /* timer1 counter reg */ - volatile u_long pcc2_t2cmp; /* timer2 compare reg */ - volatile u_long pcc2_t2cntr; /* timer2 counter reg */ - volatile u_char pcc2_pscntreg; /* prescalar count reg */ - volatile u_char pcc2_psclkadj; /* clock adjust reg */ - volatile u_char pcc2_t2ctl; /* timer2 control */ - volatile u_char pcc2_t1ctl; /* timer1 control */ - volatile u_char pcc2_gpiirq; /* GPIO intr ctl */ - volatile u_char pcc2_gpiopctl; /* GPIO pin control */ - volatile u_char pcc2_t2irq; /* Timer2 intr ctl */ - volatile u_char pcc2_t1irq; /* Timer1 intr ctl */ - volatile u_char pcc2_sccerrstat; /* SCC error status */ - volatile u_char pcc2_sccmoirq; /* Modem intr control */ - volatile u_char pcc2_scctxirq; /* Tx intr control */ - volatile u_char pcc2_sccrxirq; /* Rx intr control */ - volatile u_int :24; - volatile u_char pcc2_sccmopiack; /* modem PIACK */ - volatile u_char :8; - volatile u_char pcc2_scctxpiack; /* Tx PIACK */ - volatile u_char :8; - volatile u_char pcc2_sccrxpiack; /* Rx PIACK */ - volatile u_char pcc2_lancerrstat; /* LANC error status */ - volatile u_char :8; - volatile u_char pcc2_lancirq; /* LANC intr control */ - volatile u_char pcc2_lancerrirq; /* LANC err intr ctl */ - volatile u_char pcc2_scsierrstat; /* SCSI err status */ - volatile u_char :8; - volatile u_char :8; - volatile u_char pcc2_scsiirq; /* SCSI intr control */ - volatile u_char pcc2_packirq; /* printer ACK intr */ - volatile u_char pcc2_pfltirq; /* printer FAULT intr */ - volatile u_char pcc2_pselirq; /* printer SEL intr */ - volatile u_char pcc2_ppeirq; /* printer PE intr */ - volatile u_char pcc2_pbusyirq; /* printer BUSY intr */ - volatile u_char :8; - volatile u_char pcc2_pstat; /* printer status reg */ - volatile u_char pcc2_pctl; /* printer port ctl */ - volatile u_short pcc2_chipspeed; /* chip speed (factory testing only) */ - volatile u_short pcc2_pdata; /* printer data */ - volatile u_int :16; - volatile u_char pcc2_ipl; /* interrupt IPL */ - volatile u_char pcc2_imask; /* intr mask level */ +struct pcctworeg { + volatile u_char pcc2_chipid; + volatile u_char pcc2_chiprev; + volatile u_char pcc2_genctl; + volatile u_char pcc2_vecbase; /* irq vector base */ + volatile u_long pcc2_t1cmp; /* timer1 compare */ + volatile u_long pcc2_t1count; /* timer1 count */ + volatile u_long pcc2_t2cmp; /* timer2 compare */ + volatile u_long pcc2_t2count; /* timer2 count */ + volatile u_char pcc2_pscalecnt; /* timer prescaler counter */ + volatile u_char pcc2_pscaleadj; /* timer prescaler adjust */ + volatile u_char pcc2_t2ctl; /* timer2 ctrl reg */ + volatile u_char pcc2_t1ctl; /* timer1 ctrl reg */ + volatile u_char pcc2_gpioirq; /* gpio irq */ + volatile u_char pcc2_gpio; /* gpio i/o */ + volatile u_char pcc2_t2irq; + volatile u_char pcc2_t1irq; + volatile u_char pcc2_sccerr; + volatile u_char pcc2_sccirq; + volatile u_char pcc2_scctx; + volatile u_char pcc2_sccrx; + volatile u_char :8; + volatile u_char :8; + volatile u_char :8; + volatile u_char pcc2_sccmoiack; + volatile u_char :8; + volatile u_char pcc2_scctxiack; + volatile u_char :8; + volatile u_char pcc2_sccrxiack; + volatile u_char pcc2_ieerr; + volatile u_char :8; + volatile u_char pcc2_ieirq; + volatile u_char pcc2_iefailirq; + volatile u_char pcc2_ncrerr; + volatile u_char :8; + volatile u_char :8; + volatile u_char pcc2_ncrirq; + volatile u_char pcc2_prtairq; + volatile u_char pcc2_prtfirq; + volatile u_char pcc2_prtsirq; + volatile u_char pcc2_prtpirq; + volatile u_char pcc2_prtbirq; + volatile u_char :8; + volatile u_char pcc2_prtstat; + volatile u_char pcc2_prtctl; + volatile u_short pcc2_speed; /* DO NOT USE */ + volatile u_short pcc2_prtdat; + volatile u_short :16; + volatile u_char pcc2_ipl; + volatile u_char pcc2_mask; }; - -/* - * Vaddrs for interrupt mask and pri registers - */ -extern volatile u_char *pcc2intr_mask; -extern volatile u_char *pcc2intr_ipl; - -extern volatile struct pcc2reg *pcc2addr; - +#define PCC2_PCC2CHIP_OFF 0x42000 +#define PCC2_CHIPID 0x20 #define PCC2_BASE_ADDR 0xFFF42000 /* base address */ #define PCC2_SIZE 0x1000 /* size */ - -#define PCC2_CHIP_ID 0x20 #define PCC2_CHIP_REV 0x00 /* General Control Register */ @@ -97,29 +92,67 @@ extern volatile struct pcc2reg *pcc2addr; #define STxIRQ 0x0e #define SRxIRQ 0x0f + +/* + * Vaddrs for interrupt mask and pri registers + */ +extern volatile u_char *pcc2intr_mask; +extern volatile u_char *pcc2intr_ipl; + +/* + * points to system's PCCTWO. This is not active until the pcctwo0 + * device has been attached. + */ +extern struct pcctworeg *sys_pcc2; + +/* + * We lock off our interrupt vector at 0x50. + */ +#define PCC2_VECBASE 0x50 +#define PCC2_NVEC 16 + /* - * Timer control regs + * Vectors we use */ +#define PCC2V_NCR 0x05 +#define PCC2V_IEFAIL 0x06 +#define PCC2V_IE 0x07 +#define PCC2V_TIMER2 0x08 +#define PCC2V_TIMER1 0x09 +#define PCC2V_GPIO 0x0a +#define PCC2V_SCC_RXE 0x0c +#define PCC2V_SCC_M 0x0d +#define PCC2V_SCC_TX 0x0e +#define PCC2V_SCC_RX 0x0f + +#define PCC2_TCTL_CEN 0x01 +#define PCC2_TCTL_COC 0x02 +#define PCC2_TCTL_COVF 0x04 +#define PCC2_TCTL_OVF 0xf0 #define PCC2_TICTL_CEN 0x01 #define PCC2_TICTL_COC 0x02 #define PCC2_TICTL_COVF 0x04 #define PCC2_TTCTL_OVF_MASK (1 << 4) /* overflow bits mask */ -/* GPIO interrupt control */ +#define PCC2_GPIO_PLTY 0x80 +#define PCC2_GPIO_EL 0x40 -#define PCC2_GPIIRQ_PLTY 0x80 -#define PCC2_GPIIRQ_EL 0x40 -#define PCC2_GPIIRQ_INT 0x20 -#define PCC2_GPIIRQ_IEN 0x10 -#define PCC2_GPIIRQ_ICLR 0x08 -#define PCC2_GPIIRQ_IL 0x07 /* IL2-IL0 */ +#define PCC2_GPIOCR_OE 0x2 +#define PCC2_GPIOCR_O 0x1 -/* GPIO Pin Control Register */ +#define PCC2_SCC_AVEC 0x08 +#define PCC2_SCCRX_INHIBIT (0 << 6) +#define PCC2_SCCRX_SNOOP (1 << 6) +#define PCC2_SCCRX_INVAL (2 << 6) +#define PCC2_SCCRX_RESV (3 << 6) -#define PCC2_GPIOPCTL_GPI 0x04 -#define PCC2_GPIOPCTL_GPOE 0x02 -#define PCC2_GPIOPCTL_GPO 0x01 +#define pcc2_timer_us2lim(us) (us) /* timer increments in "us" */ + +#define PCC2_IRQ_IPL 0x07 +#define PCC2_IRQ_ICLR 0x08 +#define PCC2_IRQ_IEN 0x10 +#define PCC2_IRQ_INT 0x20 /* Tick Timer Interrupt Control Register */ @@ -128,51 +161,13 @@ extern volatile struct pcc2reg *pcc2addr; #define PCC2_TTIRQ_ICLR 0x08 #define PCC2_TTIRQ_IL 0x07 /* mask for IL2-IL0 */ -/* SCC Error Status Register */ - -#define PCC2_SCCERRSTAT_RTRY 0x10 -#define PCC2_SCCERRSTAT_PRTY 0x08 -#define PCC2_SCCERRSTAT_EXT 0x04 -#define PCC2_SCCERRSTAT_LTO 0x02 -#define PCC2_SCCERRSTAT_SCLR 0x01 - -/* SCC Modem Interrupt Control Register */ - -#define PCC2_SCCMOIRQ_IRQ 0x20 -#define PCC2_SCCMOIRQ_IEN 0x10 -#define PCC2_SCCMOIRQ_AVEC 0x08 -#define PCC2_SCCMOIRQ_IL 0x07 /* int level mask */ - -/* SCC Tx Interrupt Control Register */ - -#define PCC2_SCCTXIRQ_IRQ 0x20 -#define PCC2_SCCTXIRQ_IEN 0x10 -#define PCC2_SCCTXIRQ_AVEC 0x08 -#define PCC2_SCCTXIRQ_IL 0x07 - -/* SCC Tx Interrupt Control Register */ - -#define PCC2_SCCRXIRQ_SNOOP (1 << 6) -#define PCC2_SCCRXIRQ_IRQ 0x20 -#define PCC2_SCCRXIRQ_IEN 0x10 -#define PCC2_SCCRXIRQ_AVEC 0x08 -#define PCC2_SCCRXIRQ_IL 0x07 - -/* SCSI Interrupt Control Register */ - -#define PCC2_SCSIIRQ_IEN 0x10 - -/* Interrupt Priority Level Register */ - -#define PCC2_IPL_IPL 0x07 - -/* Interrupt Mask Level Register */ +#define PCC2_IEERR_SCLR 0x01 -#define PCC2_IMASK_MSK 0x07 +#define PCC2_GENCTL_FAST 0x01 +#define PCC2_GENCTL_IEN 0x02 +#define PCC2_GENCTL_C040 0x03 -#define PCC2_IRQ_IPL 0x07 -#define PCC2_IRQ_ICLR 0x08 -#define PCC2_IRQ_IEN 0x10 -#define PCC2_IRQ_INT 0x20 - -#define PCC2_IEERR_SCLR 0x01 +#define PCC2_SC_INHIBIT (0 << 6) +#define PCC2_SC_SNOOP (1 << 6) +#define PCC2_SC_INVAL (2 << 6) +#define PCC2_SC_RESV (3 << 6) |