diff options
Diffstat (limited to 'sys/arch/mvmeppc/include/cpu.h')
| -rw-r--r-- | sys/arch/mvmeppc/include/cpu.h | 100 |
1 files changed, 100 insertions, 0 deletions
diff --git a/sys/arch/mvmeppc/include/cpu.h b/sys/arch/mvmeppc/include/cpu.h new file mode 100644 index 00000000000..f2fe9897e39 --- /dev/null +++ b/sys/arch/mvmeppc/include/cpu.h @@ -0,0 +1,100 @@ +/* $OpenBSD: cpu.h,v 1.1 2001/06/26 21:57:44 smurph Exp $ */ +/* $NetBSD: cpu.h,v 1.1 1996/09/30 16:34:21 ws Exp $ */ + +/* + * Copyright (C) 1995, 1996 Wolfgang Solfrank. + * Copyright (C) 1995, 1996 TooLs GmbH. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by TooLs GmbH. + * 4. The name of TooLs GmbH may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _MACHINE_CPU_H_ +#define _MACHINE_CPU_H_ + +#include <machine/frame.h> + +#include <machine/psl.h> + +#define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0) +#define CLKF_BASEPRI(frame) ((frame)->pri == 0) +#define CLKF_PC(frame) ((frame)->srr0) +#define CLKF_INTR(frame) ((frame)->depth != 0) + +#define cpu_swapout(p) +#define cpu_wait(p) + +extern void delay __P((unsigned)); +#define DELAY(n) delay(n) + +extern volatile int want_resched; +extern volatile int astpending; + +#define need_resched() (want_resched = 1, astpending = 1) +#define need_proftick(p) ((p)->p_flag |= P_OWEUPC, astpending = 1) +#define signotify(p) (astpending = 1) + +#define CACHELINESIZE 32 /* For now XXX */ + +extern __inline void +syncicache(from, len) + void *from; + int len; +{ + int l = len; + char *p = from; + + do { + __asm__ __volatile__ ("dcbst 0,%0" :: "r"(p)); + p += CACHELINESIZE; + } while ((l -= CACHELINESIZE) > 0); + __asm__ __volatile__ ("sync"); + p = from; + l = len; + do { + __asm__ __volatile__ ("icbi 0,%0" :: "r"(p)); + p += CACHELINESIZE; + } while ((l -= CACHELINESIZE) > 0); + __asm__ __volatile__ ("isync"); +} + +extern __inline void +invdcache(from, len) + void *from; + int len; +{ + int l = len; + char *p = from; + + do { + __asm__ __volatile__ ("dcbi 0,%0" :: "r"(p)); + p += CACHELINESIZE; + } while ((l -= CACHELINESIZE) > 0); + __asm__ __volatile__ ("sync"); +} + +extern char *bootpath; + +#endif /* _MACHINE_CPU_H_ */ |