diff options
Diffstat (limited to 'sys/arch/octeon')
| -rw-r--r-- | sys/arch/octeon/include/cpu.h | 16 | ||||
| -rw-r--r-- | sys/arch/octeon/octeon/bus_dma.c | 21 |
2 files changed, 12 insertions, 25 deletions
diff --git a/sys/arch/octeon/include/cpu.h b/sys/arch/octeon/include/cpu.h index edaea5ce55b..b8e76774aab 100644 --- a/sys/arch/octeon/include/cpu.h +++ b/sys/arch/octeon/include/cpu.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.h,v 1.3 2011/03/23 16:54:36 pirofti Exp $ */ +/* $OpenBSD: cpu.h,v 1.4 2012/04/21 12:20:30 miod Exp $ */ /*- * Copyright (c) 1992, 1993 * The Regents of the University of California. All rights reserved. @@ -63,13 +63,13 @@ void hw_cpu_init_secondary(struct cpu_info *); #define Mips_InvalidateICache(ci, va, l) \ Octeon_InvalidateICache((ci), (va), (l)) #define Mips_SyncDCachePage(ci, va, pa) \ - Octeon_SyncDCachePage((ci), (pa)) -#define Mips_HitSyncDCache(ci, va, pa, l) \ - Octeon_HitSyncDCache((ci), (pa), (l)) -#define Mips_IOSyncDCache(ci, va, pa, l, h) \ - Octeon_IOSyncDCache((ci), (pa), (l), (h)) -#define Mips_HitInvalidateDCache(ci, va, pa, l) \ - Octeon_HitInvalidateDCache((ci), (pa), (l)) + Octeon_SyncDCachePage((ci), (va), (pa)) +#define Mips_HitSyncDCache(ci, va, l) \ + Octeon_HitSyncDCache((ci), (va), (l)) +#define Mips_IOSyncDCache(ci, va, l, h) \ + Octeon_IOSyncDCache((ci), (va), (l), (h)) +#define Mips_HitInvalidateDCache(ci, va, l) \ + Octeon_HitInvalidateDCache((ci), (va), (l)) #endif/* _KERNEL */ diff --git a/sys/arch/octeon/octeon/bus_dma.c b/sys/arch/octeon/octeon/bus_dma.c index a0addf3ceee..b9a5a3c2648 100644 --- a/sys/arch/octeon/octeon/bus_dma.c +++ b/sys/arch/octeon/octeon/bus_dma.c @@ -1,4 +1,4 @@ -/* $OpenBSD: bus_dma.c,v 1.5 2012/03/25 13:52:52 miod Exp $ */ +/* $OpenBSD: bus_dma.c,v 1.6 2012/04/21 12:20:30 miod Exp $ */ /* * Copyright (c) 2003-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -350,24 +350,16 @@ _dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t addr, * Otherwise, just invalidate (if noncoherent). */ if (op & BUS_DMASYNC_PREWRITE) { -#ifdef TGT_COHERENT - Mips_IOSyncDCache(ci, vaddr, paddr, - ssize, CACHE_SYNC_W); -#else if (op & BUS_DMASYNC_PREREAD) - Mips_IOSyncDCache(ci, vaddr, paddr, + Mips_IOSyncDCache(ci, vaddr, ssize, CACHE_SYNC_X); else - Mips_IOSyncDCache(ci, vaddr, paddr, + Mips_IOSyncDCache(ci, vaddr, ssize, CACHE_SYNC_W); -#endif } else if (op & (BUS_DMASYNC_PREREAD | BUS_DMASYNC_POSTREAD)) { -#ifdef TGT_COHERENT -#else - Mips_IOSyncDCache(ci, vaddr, paddr, + Mips_IOSyncDCache(ci, vaddr, ssize, CACHE_SYNC_R); -#endif } size -= ssize; } @@ -435,11 +427,6 @@ _dmamem_map(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs, size_t size, bus_addr_t addr; int curseg, error; -#ifdef TGT_COHERENT - if (ISSET(flags, BUS_DMA_COHERENT)) - CLR(flags, BUS_DMA_COHERENT); -#endif - if (nsegs == 1) { pa = (*t->_device_to_pa)(segs[0].ds_addr); if (flags & BUS_DMA_COHERENT) |