diff options
Diffstat (limited to 'sys/arch/powerpc/mac')
| -rw-r--r-- | sys/arch/powerpc/mac/dbdma.c | 140 | ||||
| -rw-r--r-- | sys/arch/powerpc/mac/dbdma.h | 230 | ||||
| -rw-r--r-- | sys/arch/powerpc/mac/if_bm.c | 1089 | ||||
| -rw-r--r-- | sys/arch/powerpc/mac/if_bmreg.h | 140 | ||||
| -rw-r--r-- | sys/arch/powerpc/mac/macintr.c | 518 | ||||
| -rw-r--r-- | sys/arch/powerpc/mac/wdc_obio.c | 270 |
6 files changed, 2387 insertions, 0 deletions
diff --git a/sys/arch/powerpc/mac/dbdma.c b/sys/arch/powerpc/mac/dbdma.c new file mode 100644 index 00000000000..5e29b65de5e --- /dev/null +++ b/sys/arch/powerpc/mac/dbdma.c @@ -0,0 +1,140 @@ +/* $OpenBSD: dbdma.c,v 1.1 1999/11/08 23:46:00 rahnds Exp $ */ +/* $NetBSD: dbdma.c,v 1.2 1998/08/21 16:13:28 tsubai Exp $ */ + +/* + * Copyright 1991-1998 by Open Software Foundation, Inc. + * All Rights Reserved + * + * Permission to use, copy, modify, and distribute this software and + * its documentation for any purpose and without fee is hereby granted, + * provided that the above copyright notice appears in all copies and + * that both the copyright notice and this permission notice appear in + * supporting documentation. + * + * OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT, + * NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION + * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include <sys/param.h> +#include <sys/malloc.h> +#include <sys/systm.h> + +#include <vm/vm.h> + +#include <machine/pio.h> +#include <powerpc/mac/dbdma.h> + + + +static int dbdma_alloc_index = 0; +dbdma_command_t *dbdma_alloc_commands = NULL; + +void +dbdma_start(dmap, commands) + dbdma_regmap_t *dmap; + dbdma_command_t *commands; +{ + u_int32_t addr = vtophys((vaddr_t)commands); + + if (addr & 0xf) + panic("dbdma_start command structure not 16-byte aligned"); + +#if 1 + dmap->d_intselect = 0xff; /* Endian magic - clear out interrupts */ +#else + DBDMA_ST4_ENDIAN(&dmap->d_intselect, DBDMA_CLEAR_CNTRL( (0xffff))); +#endif + DBDMA_ST4_ENDIAN(&dmap->d_control, + DBDMA_CLEAR_CNTRL( (DBDMA_CNTRL_ACTIVE | + DBDMA_CNTRL_DEAD | + DBDMA_CNTRL_WAKE | + DBDMA_CNTRL_FLUSH | + DBDMA_CNTRL_PAUSE | + DBDMA_CNTRL_RUN ))); + + do { + delay(10); + } while (DBDMA_LD4_ENDIAN(&dmap->d_status) & DBDMA_CNTRL_ACTIVE); + + + DBDMA_ST4_ENDIAN(&dmap->d_cmdptrhi, 0); /* 64-bit not yet */ + DBDMA_ST4_ENDIAN(&dmap->d_cmdptrlo, addr); + + DBDMA_ST4_ENDIAN(&dmap->d_control, + DBDMA_SET_CNTRL(DBDMA_CNTRL_RUN|DBDMA_CNTRL_WAKE)| + DBDMA_CLEAR_CNTRL(DBDMA_CNTRL_PAUSE|DBDMA_CNTRL_DEAD) ); +} + +void +dbdma_stop(dmap) + dbdma_regmap_t *dmap; +{ + DBDMA_ST4_ENDIAN(&dmap->d_control, DBDMA_CLEAR_CNTRL(DBDMA_CNTRL_RUN) | + DBDMA_SET_CNTRL(DBDMA_CNTRL_FLUSH)); + + while (DBDMA_LD4_ENDIAN(&dmap->d_status) & + (DBDMA_CNTRL_ACTIVE|DBDMA_CNTRL_FLUSH)); +} + +void +dbdma_flush(dmap) + dbdma_regmap_t *dmap; +{ + DBDMA_ST4_ENDIAN(&dmap->d_control, DBDMA_SET_CNTRL(DBDMA_CNTRL_FLUSH)); + + while (DBDMA_LD4_ENDIAN(&dmap->d_status) & (DBDMA_CNTRL_FLUSH)); +} + +void +dbdma_reset(dmap) + dbdma_regmap_t *dmap; +{ + DBDMA_ST4_ENDIAN(&dmap->d_control, + DBDMA_CLEAR_CNTRL( (DBDMA_CNTRL_ACTIVE | + DBDMA_CNTRL_DEAD | + DBDMA_CNTRL_WAKE | + DBDMA_CNTRL_FLUSH | + DBDMA_CNTRL_PAUSE | + DBDMA_CNTRL_RUN ))); + + while (DBDMA_LD4_ENDIAN(&dmap->d_status) & DBDMA_CNTRL_RUN); +} + +void +dbdma_continue(dmap) + dbdma_regmap_t *dmap; +{ + DBDMA_ST4_ENDIAN(&dmap->d_control, + DBDMA_SET_CNTRL(DBDMA_CNTRL_RUN | DBDMA_CNTRL_WAKE) | + DBDMA_CLEAR_CNTRL(DBDMA_CNTRL_PAUSE | DBDMA_CNTRL_DEAD)); +} + +void +dbdma_pause(dmap) + dbdma_regmap_t *dmap; +{ + DBDMA_ST4_ENDIAN(&dmap->d_control,DBDMA_SET_CNTRL(DBDMA_CNTRL_PAUSE)); + + while (DBDMA_LD4_ENDIAN(&dmap->d_status) & DBDMA_CNTRL_ACTIVE) + ; +} + +dbdma_command_t * +dbdma_alloc(size) + int size; +{ + u_int buf; + + buf = (u_int)malloc(size + 0x0f, M_DEVBUF, M_WAITOK); + buf = (buf + 0x0f) & ~0x0f; + + return (dbdma_command_t *)buf; +} diff --git a/sys/arch/powerpc/mac/dbdma.h b/sys/arch/powerpc/mac/dbdma.h new file mode 100644 index 00000000000..fda700cfdbe --- /dev/null +++ b/sys/arch/powerpc/mac/dbdma.h @@ -0,0 +1,230 @@ +/* $OpenBSD: dbdma.h,v 1.1 1999/11/08 23:46:00 rahnds Exp $ */ +/* $NetBSD: dbdma.h,v 1.2 1998/08/21 16:13:28 tsubai Exp $ */ + +/* + * Copyright 1991-1998 by Open Software Foundation, Inc. + * All Rights Reserved + * + * Permission to use, copy, modify, and distribute this software and + * its documentation for any purpose and without fee is hereby granted, + * provided that the above copyright notice appears in all copies and + * that both the copyright notice and this permission notice appear in + * supporting documentation. + * + * OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT, + * NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION + * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "machine/pio.h" + +#ifndef _POWERMAC_DBDMA_H_ +#define _POWERMAC_DBDMA_H_ + +#define DBDMA_CMD_OUT_MORE 0 +#define DBDMA_CMD_OUT_LAST 1 +#define DBDMA_CMD_IN_MORE 2 +#define DBDMA_CMD_IN_LAST 3 +#define DBDMA_CMD_STORE_QUAD 4 +#define DBDMA_CMD_LOAD_QUAD 5 +#define DBDMA_CMD_NOP 6 +#define DBDMA_CMD_STOP 7 + +/* Keys */ + +#define DBDMA_KEY_STREAM0 0 +#define DBDMA_KEY_STREAM1 1 +#define DBDMA_KEY_STREAM2 2 +#define DBDMA_KEY_STREAM3 3 + +/* value 4 is reserved */ +#define DBDMA_KEY_REGS 5 +#define DBDMA_KEY_SYSTEM 6 +#define DBDMA_KEY_DEVICE 7 + +#define DBDMA_INT_NEVER 0 +#define DBDMA_INT_IF_TRUE 1 +#define DBDMA_INT_IF_FALSE 2 +#define DBDMA_INT_ALWAYS 3 + +#define DBDMA_BRANCH_NEVER 0 +#define DBDMA_BRANCH_IF_TRUE 1 +#define DBDMA_BRANCH_IF_FALSE 2 +#define DBDMA_BRANCH_ALWAYS 3 + +#define DBDMA_WAIT_NEVER 0 +#define DBDMA_WAIT_IF_TRUE 1 +#define DBDMA_WAIT_IF_FALSE 2 +#define DBDMA_WAIT_ALWAYS 3 + + +/* Channels */ + +#define DBDMA_SCSI0 0x0 +#define DBDMA_CURIO_SCSI DBDMA_SCSI0 +#define DBDMA_FLOPPY 0x1 +#define DBDMA_ETHERNET_TX 0x2 +#define DBDMA_ETHERNET_RV 0x3 +#define DBDMA_SCC_XMIT_A 0x4 +#define DBDMA_SCC_RECV_A 0x5 +#define DBDMA_SCC_XMIT_B 0x6 +#define DBDMA_SCC_RECV_B 0x7 +#define DBDMA_AUDIO_OUT 0x8 +#define DBDMA_AUDIO_IN 0x9 +#define DBDMA_SCSI1 0xA + +/* Control register values (in little endian) */ + +#define DBDMA_STATUS_MASK 0x000000ff /* Status Mask */ +#define DBDMA_CNTRL_BRANCH 0x00000100 + /* 0x200 reserved */ +#define DBDMA_CNTRL_ACTIVE 0x00000400 +#define DBDMA_CNTRL_DEAD 0x00000800 +#define DBDMA_CNTRL_WAKE 0x00001000 +#define DBDMA_CNTRL_FLUSH 0x00002000 +#define DBDMA_CNTRL_PAUSE 0x00004000 +#define DBDMA_CNTRL_RUN 0x00008000 + +#define DBDMA_SET_CNTRL(x) ( ((x) | (x) << 16) ) +#define DBDMA_CLEAR_CNTRL(x) ( (x) << 16) + + +#define DBDMA_REGMAP(channel) \ + (dbdma_regmap_t *)((v_u_char *) POWERMAC_IO(PCI_DMA_BASE_PHYS) \ + + (channel << 8)) + +/* This struct is layout in little endian format */ + +struct dbdma_command { + u_int16_t d_count; + u_int16_t d_command; + u_int32_t d_address; + u_int32_t d_cmddep; + u_int16_t d_resid; + u_int16_t d_status; +}; + +typedef struct dbdma_command dbdma_command_t; + +#define DBDMA_BUILD_CMD(d, cmd, key, interrupt, wait, branch) { \ + dbdma_st16(&(d)->d_command, \ + ((cmd) << 12) | ((key) << 8) | \ + ((interrupt) << 4) | \ + ((branch) << 2) | (wait)); \ + } + +#define DBDMA_BUILD(d, cmd, key, count, address, interrupt, wait, branch) { \ + dbdma_st16(&(d)->d_count, count); \ + dbdma_st32(&(d)->d_address, address); \ + (d)->d_resid = 0; \ + (d)->d_status = 0; \ + (d)->d_cmddep = 0; \ + dbdma_st16(&(d)->d_command, \ + ((cmd) << 12) | ((key) << 8) | \ + ((interrupt) << 4) | \ + ((branch) << 2) | (wait)); \ + } + +#if 0 +static __inline__ void +dbdma_st32(a, x) + volatile u_int32_t *a; + u_int32_t x; +{ + __asm__ volatile + ("stwbrx %0,0,%1" : : "r" (x), "r" (a) : "memory"); + __asm__ volatile ("eieio"); +} + +static __inline__ void +dbdma_st16(a, x) + volatile u_int16_t *a; + u_int16_t x; +{ + __asm__ volatile + ("sthbrx %0,0,%1" : : "r" (x), "r" (a) : "memory"); + __asm__ volatile ("eieio"); +} + +static __inline__ u_int32_t +dbdma_ld32(a) + volatile u_int32_t *a; +{ + u_int32_t swap; + + __asm__ volatile ("eieio"); + __asm__ volatile + ("lwbrx %0,0,%1" : "=r" (swap) : "r" (a)); + + return swap; +} + +static __inline__ u_int16_t +dbdma_ld16(a) + volatile u_int16_t *a; +{ + u_int16_t swap; + + __asm__ volatile ("eieio"); + __asm__ volatile + ("lhbrx %0,0,%1" : "=r" (swap) : "r" (a)); + + return swap; +} + +#define DBDMA_LD4_ENDIAN(a) dbdma_ld32(a) +#define DBDMA_ST4_ENDIAN(a, x) dbdma_st32(a, x) +#else +#define DBDMA_LD4_ENDIAN(a) in32rb(a) +#define DBDMA_ST4_ENDIAN(a, x) out32rb(a, x) +#define dbdma_st16(a,x) out16rb((a),(x)) +#define dbdma_ld16(a) in16rb(a) +#define dbdma_st32(a,x) out32rb((a),(x)) +#define dbdma_ld32(a) in32rb(a) +#endif + + +/* + * DBDMA Channel layout + * + * NOTE - This structure is in little-endian format. + */ + +struct dbdma_regmap { + u_int32_t d_control; /* Control Register */ + u_int32_t d_status; /* DBDMA Status Register */ + u_int32_t d_cmdptrhi; /* MSB of command pointer (not used yet) */ + u_int32_t d_cmdptrlo; /* LSB of command pointer */ + u_int32_t d_intselect; /* Interrupt Select */ + u_int32_t d_branch; /* Branch selection */ + u_int32_t d_wait; /* Wait selection */ + u_int32_t d_transmode; /* Transfer modes */ + u_int32_t d_dataptrhi; /* MSB of Data Pointer */ + u_int32_t d_dataptrlo; /* LSB of Data Pointer */ + u_int32_t d_reserved; /* Reserved for the moment */ + u_int32_t d_branchptrhi; /* MSB of Branch Pointer */ + u_int32_t d_branchptrlo; /* LSB of Branch Pointer */ + /* The remaining fields are undefinied and unimplemented */ +}; + +typedef volatile struct dbdma_regmap dbdma_regmap_t; + +/* DBDMA routines */ + +void dbdma_start(dbdma_regmap_t *channel, dbdma_command_t *commands); +void dbdma_stop(dbdma_regmap_t *channel); +void dbdma_flush(dbdma_regmap_t *channel); +void dbdma_reset(dbdma_regmap_t *channel); +void dbdma_continue(dbdma_regmap_t *channel); +void dbdma_pause(dbdma_regmap_t *channel); + +dbdma_command_t *dbdma_alloc(int); /* Allocate command structures */ + +#endif /* !defined(_POWERMAC_DBDMA_H_) */ diff --git a/sys/arch/powerpc/mac/if_bm.c b/sys/arch/powerpc/mac/if_bm.c new file mode 100644 index 00000000000..1e912b6604a --- /dev/null +++ b/sys/arch/powerpc/mac/if_bm.c @@ -0,0 +1,1089 @@ +/* $OpenBSD: if_bm.c,v 1.1 1999/11/08 23:46:01 rahnds Exp $ */ +/* $NetBSD: if_bm.c,v 1.1 1999/01/01 01:27:52 tsubai Exp $ */ + +/*- + * Copyright (C) 1998, 1999 Tsubai Masanari. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef __NetBSD__ +#include "opt_inet.h" +#include "opt_ns.h" +#endif /* __NetBSD__ */ +#include "bpfilter.h" + +#include <sys/param.h> +#include <sys/device.h> +#include <sys/ioctl.h> +#include <sys/mbuf.h> +#include <sys/socket.h> +#include <sys/systm.h> + +#include <net/if.h> +#include <netinet/in.h> +#include <netinet/if_ether.h> +#include <net/if_media.h> + +#if NBPFILTER > 0 +#include <net/bpf.h> +#include <net/bpfdesc.h> +#endif + +#include <vm/vm.h> + +#include <dev/ofw/openfirm.h> + +#include <machine/autoconf.h> +#include <machine/pio.h> + +#include <powerpc/mac/dbdma.h> +#include <powerpc/mac/if_bmreg.h> + +#define BMAC_TXBUFS 2 +#define BMAC_RXBUFS 16 +#define BMAC_BUFLEN 2048 + +struct bmac_softc { + struct device sc_dev; +#ifdef __OpenBSD__ + struct arpcom arpcom; /* per-instance network data */ +#define sc_if arpcom.ac_if +#define sc_enaddr arpcom.ac_enaddr +#else + struct ethercom sc_ethercom; +#define sc_if sc_ethercom.ec_if + u_char sc_enaddr[6]; +#endif + struct ifmedia sc_media; + vaddr_t sc_regs; + dbdma_regmap_t *sc_txdma; + dbdma_regmap_t *sc_rxdma; + dbdma_command_t *sc_txcmd; + dbdma_command_t *sc_rxcmd; + caddr_t sc_txbuf; + caddr_t sc_rxbuf; + int sc_rxlast; + int sc_flags; + int sc_debug; + int txcnt_outstanding; +}; + +#define BMAC_BMACPLUS 0x01 + +extern u_int *heathrow_FCR; + +static __inline int bmac_read_reg __P((struct bmac_softc *, int)); +static __inline void bmac_write_reg __P((struct bmac_softc *, int, int)); +static __inline void bmac_set_bits __P((struct bmac_softc *, int, int)); +static __inline void bmac_reset_bits __P((struct bmac_softc *, int, int)); + +static int bmac_match __P((struct device *, void *, void *)); +static void bmac_attach __P((struct device *, struct device *, void *)); +static void bmac_reset_chip __P((struct bmac_softc *)); +static void bmac_init __P((struct bmac_softc *)); +static void bmac_init_dma __P((struct bmac_softc *)); +static int bmac_intr __P((void *)); +static int bmac_tx_intr __P((void *)); +static int bmac_rint __P((void *)); +static void bmac_reset __P((struct bmac_softc *)); +static void bmac_stop __P((struct bmac_softc *)); +static void bmac_start __P((struct ifnet *)); +static void bmac_transmit_packet __P((struct bmac_softc *, void *, int)); +static int bmac_put __P((struct bmac_softc *, caddr_t, struct mbuf *)); +static struct mbuf *bmac_get __P((struct bmac_softc *, caddr_t, int)); +static void bmac_watchdog __P((struct ifnet *)); +static int bmac_ioctl __P((struct ifnet *, u_long, caddr_t)); +static int bmac_mediachange __P((struct ifnet *)); +static void bmac_mediastatus __P((struct ifnet *, struct ifmediareq *)); +static void bmac_setladrf __P((struct bmac_softc *)); +void bmac_init_mif __P((struct bmac_softc *sc)); + +struct cfattach bm_ca = { + sizeof(struct bmac_softc), bmac_match, bmac_attach +}; + +struct cfdriver bm_cd = { + NULL, "bm", DV_IFNET +}; + +int +bmac_read_reg(sc, off) + struct bmac_softc *sc; + int off; +{ + return in16rb(sc->sc_regs + off); +} + +void +bmac_write_reg(sc, off, val) + struct bmac_softc *sc; + int off, val; +{ + out16rb(sc->sc_regs + off, val); +} + +void +bmac_set_bits(sc, off, val) + struct bmac_softc *sc; + int off, val; +{ + val |= bmac_read_reg(sc, off); + bmac_write_reg(sc, off, val); +} + +void +bmac_reset_bits(sc, off, val) + struct bmac_softc *sc; + int off, val; +{ + bmac_write_reg(sc, off, bmac_read_reg(sc, off) & ~val); +} + +int +bmac_match(parent, cf, aux) + struct device *parent; + void *cf; + void *aux; +{ + struct confargs *ca = aux; + + if (ca->ca_nreg < 24 || ca->ca_nintr < 12) + return 0; + + if (strcmp(ca->ca_name, "bmac") == 0) /* bmac */ + return 1; + if (strcmp(ca->ca_name, "ethernet") == 0) /* bmac+ */ + return 1; + + return 0; +} + +void +bmac_attach(parent, self, aux) + struct device *parent, *self; + void *aux; +{ + struct confargs *ca = aux; + struct bmac_softc *sc = (void *)self; + struct ifnet *ifp = &sc->sc_if; + u_char laddr[6]; + int i; + + sc->sc_flags =0; + if (strcmp(ca->ca_name, "ethernet") == 0) { + sc->sc_flags |= BMAC_BMACPLUS; + } + + ca->ca_reg[0] += ca->ca_baseaddr; + ca->ca_reg[2] += ca->ca_baseaddr; + ca->ca_reg[4] += ca->ca_baseaddr; + printf("D: reg0 %x, reg2 %x reg4 %x\n", + ca->ca_reg[0], + ca->ca_reg[2], + ca->ca_reg[4]); + + + sc->sc_regs = (vaddr_t)mapiodev(ca->ca_reg[0], NBPG); + + bmac_write_reg(sc, INTDISABLE, NoEventsMask); + + if (OF_getprop(ca->ca_node, "local-mac-address", laddr, 6) == -1 && + OF_getprop(ca->ca_node, "mac-address", laddr, 6) == -1) { + printf(": cannot get mac-address\n"); + return; + } + bcopy(laddr, sc->arpcom.ac_enaddr, 6); + + sc->sc_txdma = mapiodev(ca->ca_reg[2], 0x100); + sc->sc_rxdma = mapiodev(ca->ca_reg[4], 0x100); + sc->sc_txcmd = dbdma_alloc(BMAC_TXBUFS * sizeof(dbdma_command_t)); + sc->sc_rxcmd = dbdma_alloc((BMAC_RXBUFS + 1) * sizeof(dbdma_command_t)); + sc->sc_txbuf = malloc(BMAC_BUFLEN * BMAC_TXBUFS, M_DEVBUF, M_NOWAIT); + sc->sc_rxbuf = malloc(BMAC_BUFLEN * BMAC_RXBUFS, M_DEVBUF, M_NOWAIT); + if (sc->sc_txbuf == NULL || sc->sc_rxbuf == NULL || + sc->sc_txcmd == NULL || sc->sc_rxcmd == NULL) { + printf("cannot allocate memory\n"); + return; + } + + printf(" irq %d,%d: address %s\n", ca->ca_intr[0], ca->ca_intr[2], + ether_sprintf(laddr)); + + mac_intr_establish(ca->ca_intr[0], IST_LEVEL, IPL_NET, bmac_intr, sc); + /* + mac_intr_establish(ca->ca_intr[1], IST_LEVEL, IPL_NET, bmac_tx_intr, sc); + */ + mac_intr_establish(ca->ca_intr[2], IST_LEVEL, IPL_NET, bmac_rint, sc); + + bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); + ifp->if_softc = sc; + ifp->if_ioctl = bmac_ioctl; + ifp->if_start = bmac_start; + ifp->if_flags = + IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; + ifp->if_watchdog = bmac_watchdog; + + ifmedia_init(&sc->sc_media, 0, bmac_mediachange, bmac_mediastatus); + ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10_T, 0, NULL); + ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); + + bmac_reset_chip(sc); + + if_attach(ifp); + ether_ifattach(ifp); + +#if NBPFILTER > 0 + bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); +#endif +} + +/* + * Reset and enable bmac by heathrow FCR. + */ +void +bmac_reset_chip(sc) + struct bmac_softc *sc; +{ + u_int v; + + dbdma_reset(sc->sc_txdma); + dbdma_reset(sc->sc_rxdma); + + v = in32rb(heathrow_FCR); + + v |= EnetEnable; + out32rb(heathrow_FCR, v); + delay(50000); + + /* assert reset */ + v |= ResetEnetCell; + out32rb(heathrow_FCR, v); + delay(70000); + + /* deassert reset */ + v &= ~ResetEnetCell; + out32rb(heathrow_FCR, v); + delay(50000); + + /* enable */ + v |= EnetEnable; + out32rb(heathrow_FCR, v); + delay(50000); + + /* make certain they stay set? */ + out32rb(heathrow_FCR, v); + v = in32rb(heathrow_FCR); +} + +void +bmac_init(sc) + struct bmac_softc *sc; +{ + struct ifnet *ifp = &sc->sc_if; + struct ether_header *eh; + caddr_t data; + int i, tb; + u_short *p; + + bmac_init_mif(sc); + bmac_reset_chip(sc); + + bmac_write_reg(sc, RXRST, RxResetValue); + bmac_write_reg(sc, TXRST, TxResetBit); + + /* Wait for reset completion. */ + do { + delay(10000); + } while (bmac_read_reg(sc, TXRST) & TxResetBit); + + if (! (sc->sc_flags & BMAC_BMACPLUS)) { + bmac_set_bits(sc, XCVRIF, ClkBit|SerialMode|COLActiveLow); + delay(100); + } + + __asm __volatile ("mftb %0" : "=r"(tb)); + bmac_write_reg(sc, RSEED, tb); + bmac_set_bits(sc, XIFC, TxOutputEnable); + bmac_read_reg(sc, PAREG); + + /* Reset various counters. */ + bmac_write_reg(sc, NCCNT, 0); + bmac_write_reg(sc, NTCNT, 0); + bmac_write_reg(sc, EXCNT, 0); + bmac_write_reg(sc, LTCNT, 0); + bmac_write_reg(sc, FRCNT, 0); + bmac_write_reg(sc, LECNT, 0); + bmac_write_reg(sc, AECNT, 0); + bmac_write_reg(sc, FECNT, 0); + bmac_write_reg(sc, RXCV, 0); + + /* Set tx fifo information. */ + bmac_write_reg(sc, TXTH, 4); /* 4 octets before tx starts */ + + bmac_write_reg(sc, TXFIFOCSR, 0); + bmac_write_reg(sc, TXFIFOCSR, TxFIFOEnable); + + /* Set rx fifo information. */ + bmac_write_reg(sc, RXFIFOCSR, 0); + bmac_write_reg(sc, RXFIFOCSR, RxFIFOEnable); + + /* Clear status register. */ + bmac_read_reg(sc, STATUS); + + bmac_write_reg(sc, HASH3, 0); + bmac_write_reg(sc, HASH2, 0); + bmac_write_reg(sc, HASH1, 0); + bmac_write_reg(sc, HASH0, 0); + + /* Set MAC address. */ + p = (u_short *)sc->sc_enaddr; + bmac_write_reg(sc, MADD0, *p++); + bmac_write_reg(sc, MADD1, *p++); + bmac_write_reg(sc, MADD2, *p); + + bmac_write_reg(sc, RXCFG, + RxCRCEnable | RxHashFilterEnable | RxRejectOwnPackets); + + if (ifp->if_flags & IFF_PROMISC) + bmac_set_bits(sc, RXCFG, RxPromiscEnable); + + bmac_init_dma(sc); + + /* Enable TX/RX */ + bmac_set_bits(sc, RXCFG, RxMACEnable); + bmac_set_bits(sc, TXCFG, TxMACEnable); + + bmac_write_reg(sc, INTDISABLE, NormalIntEvents); + + ifp->if_flags |= IFF_RUNNING; + ifp->if_flags &= ~IFF_OACTIVE; + ifp->if_timer = 0; + + data = sc->sc_txbuf; + eh = (struct ether_header *)data; + + bzero(data, sizeof(eh) + ETHERMIN); + bcopy(sc->sc_enaddr, eh->ether_dhost, ETHER_ADDR_LEN); + bcopy(sc->sc_enaddr, eh->ether_shost, ETHER_ADDR_LEN); + bmac_transmit_packet(sc, data, sizeof(eh) + ETHERMIN); + + bmac_start(ifp); +} + +void +bmac_init_dma(sc) + struct bmac_softc *sc; +{ + dbdma_command_t *cmd = sc->sc_rxcmd; + int i; + + dbdma_reset(sc->sc_txdma); + dbdma_reset(sc->sc_rxdma); + + bzero(sc->sc_txcmd, BMAC_TXBUFS * sizeof(dbdma_command_t)); + bzero(sc->sc_rxcmd, (BMAC_RXBUFS + 1) * sizeof(dbdma_command_t)); + + for (i = 0; i < BMAC_RXBUFS; i++) { + DBDMA_BUILD(cmd, DBDMA_CMD_IN_LAST, 0, BMAC_BUFLEN, + vtophys(sc->sc_rxbuf + BMAC_BUFLEN * i), + DBDMA_INT_ALWAYS, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); + cmd++; + } + DBDMA_BUILD(cmd, DBDMA_CMD_NOP, 0, 0, 0, + DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_ALWAYS); + dbdma_st32(&cmd->d_cmddep, vtophys(sc->sc_rxcmd)); + + sc->sc_rxlast = 0; + + dbdma_start(sc->sc_rxdma, sc->sc_rxcmd); +} + +int +bmac_tx_intr(v) + void *v; +{ + struct bmac_softc *sc = v; + u_int16_t stat; + + sc->sc_if.if_flags &= ~IFF_OACTIVE; + sc->sc_if.if_timer = 0; + sc->sc_if.if_opackets++; + bmac_start(&sc->sc_if); + +#ifndef BMAC_DEBUG + printf("bmac_tx_intr \n"); +#endif + #if 0 + stat = bmac_read_reg(sc, STATUS); + if (stat == 0) { + printf("tx intr fired, but status 0\n"); + return 0; + } + + + if (stat & IntFrameSent) { + sc->sc_if.if_flags &= ~IFF_OACTIVE; + sc->sc_if.if_timer = 0; + sc->sc_if.if_opackets++; + bmac_start(&sc->sc_if); + } + #endif + return 1; +} +int +bmac_intr(v) + void *v; +{ + struct bmac_softc *sc = v; + int stat; + +#ifdef BMAC_DEBUG + printf("bmac_intr called\n"); +#endif + stat = bmac_read_reg(sc, STATUS); + if (stat == 0) + return 0; + +#ifdef BMAC_DEBUG + printf("bmac_intr status = 0x%x\n", stat); +#endif + + if (stat & IntFrameSent) { + sc->sc_if.if_flags &= ~IFF_OACTIVE; + sc->sc_if.if_timer = 0; + sc->sc_if.if_opackets++; + bmac_start(&sc->sc_if); + } + + /* XXX should do more! */ + + return 1; +} + +int +bmac_rint(v) + void *v; +{ + struct bmac_softc *sc = v; + struct ifnet *ifp = &sc->sc_if; + struct mbuf *m; + dbdma_command_t *cmd; + int status, resid, count, datalen; + int i, n; + void *data; +#ifdef BMAC_DEBUG + printf("bmac_rint() called\n"); +#endif + + i = sc->sc_rxlast; + for (n = 0; n < BMAC_RXBUFS; n++, i++) { + if (i == BMAC_RXBUFS) + i = 0; + cmd = &sc->sc_rxcmd[i]; + status = dbdma_ld16(&cmd->d_status); + resid = dbdma_ld16(&cmd->d_resid); + +#ifdef BMAC_DEBUG + if (status != 0 && status != 0x8440 && status != 0x9440) + printf("bmac_rint status = 0x%x\n", status); +#endif + + if ((status & DBDMA_CNTRL_ACTIVE) == 0) /* 0x9440 | 0x8440 */ + continue; + count = dbdma_ld16(&cmd->d_count); + datalen = count - resid; + if (datalen < sizeof(struct ether_header)) { + printf("%s: short packet len = %d\n", + ifp->if_xname, datalen); + goto next; + } + DBDMA_BUILD_CMD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 0); + data = sc->sc_rxbuf + BMAC_BUFLEN * i; + m = bmac_get(sc, data, datalen); + + if (m == NULL) { + ifp->if_ierrors++; + goto next; + } + +#if NBPFILTER > 0 + /* + * Check if there's a BPF listener on this interface. + * If so, hand off the raw packet to BPF. + */ + if (ifp->if_bpf) + bpf_mtap(ifp->if_bpf, m); +#endif +#ifdef __OpenBSD__ +#if 0 + ether_input(ifp, mtod(m, struct ether_header *), m); +#else + m_adj(m, sizeof(struct ether_header)); + ether_input(ifp, data, m); +#endif +#else + m_adj(m, sizeof(struct ether_header)); + ether_input(ifp, data, m); +#endif + ifp->if_ipackets++; + +next: + DBDMA_BUILD_CMD(cmd, DBDMA_CMD_IN_LAST, 0, DBDMA_INT_ALWAYS, + DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); + + cmd->d_status = 0; + cmd->d_resid = 0; + sc->sc_rxlast = i + 1; + } + dbdma_continue(sc->sc_rxdma); + + return 1; +} + +void +bmac_reset(sc) + struct bmac_softc *sc; +{ + int s; + + s = splnet(); + bmac_init(sc); + splx(s); +} + +void +bmac_stop(sc) + struct bmac_softc *sc; +{ + struct ifnet *ifp = &sc->sc_if; + int s; + + s = splnet(); + + /* Disable TX/RX. */ + bmac_reset_bits(sc, TXCFG, TxMACEnable); + bmac_reset_bits(sc, RXCFG, RxMACEnable); + + /* Disable all interrupts. */ + bmac_write_reg(sc, INTDISABLE, NoEventsMask); + + dbdma_stop(sc->sc_txdma); + dbdma_stop(sc->sc_rxdma); + + ifp->if_flags &= ~(IFF_UP | IFF_RUNNING); + ifp->if_timer = 0; + + splx(s); +} + +void +bmac_start(ifp) + struct ifnet *ifp; +{ + struct bmac_softc *sc = ifp->if_softc; + struct mbuf *m; + int tlen; + + if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) + return; + + while (1) { + if (ifp->if_flags & IFF_OACTIVE) + return; + + IF_DEQUEUE(&ifp->if_snd, m); + if (m == 0) + break; +#if NBPFILTER > 0 + /* + * If BPF is listening on this interface, let it see the + * packet before we commit it to the wire. + */ + if (ifp->if_bpf) + bpf_mtap(ifp->if_bpf, m); +#endif + + ifp->if_flags |= IFF_OACTIVE; + tlen = bmac_put(sc, sc->sc_txbuf, m); + + /* 5 seconds to watch for failing to transmit */ + ifp->if_timer = 5; + ifp->if_opackets++; /* # of pkts */ + + bmac_transmit_packet(sc, sc->sc_txbuf, tlen); + } +} + +void +bmac_transmit_packet(sc, buff, len) + struct bmac_softc *sc; + void *buff; + int len; +{ + dbdma_command_t *cmd = sc->sc_txcmd; + vaddr_t va = (vaddr_t)buff; + +#ifdef BMAC_DEBUG + if (vtophys(va) + len - 1 != vtophys(va + len - 1)) + panic("bmac_transmit_packet"); +#endif + + DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, len, vtophys(va), + DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); + cmd++; + DBDMA_BUILD(cmd, DBDMA_CMD_STOP, 0, 0, 0, + DBDMA_INT_ALWAYS, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); + + dbdma_start(sc->sc_txdma, sc->sc_txcmd); +} + +int +bmac_put(sc, buff, m) + struct bmac_softc *sc; + caddr_t buff; + struct mbuf *m; +{ + struct mbuf *n; + int len, tlen = 0; + + for (; m; m = n) { + len = m->m_len; + if (len == 0) { + MFREE(m, n); + continue; + } + bcopy(mtod(m, caddr_t), buff, len); + buff += len; + tlen += len; + MFREE(m, n); + } + if (tlen > NBPG) + panic("%s: putpacket packet overflow", sc->sc_dev.dv_xname); + + return tlen; +} + +struct mbuf * +bmac_get(sc, pkt, totlen) + struct bmac_softc *sc; + caddr_t pkt; + int totlen; +{ + struct mbuf *m; + struct mbuf *top, **mp; + int len; + + MGETHDR(m, M_DONTWAIT, MT_DATA); + if (m == 0) + return 0; + m->m_pkthdr.rcvif = &sc->sc_if; + m->m_pkthdr.len = totlen; + len = MHLEN; + top = 0; + mp = ⊤ + + while (totlen > 0) { + if (top) { + MGET(m, M_DONTWAIT, MT_DATA); + if (m == 0) { + m_freem(top); + return 0; + } + len = MLEN; + } + if (totlen >= MINCLSIZE) { + MCLGET(m, M_DONTWAIT); + if ((m->m_flags & M_EXT) == 0) { + m_free(m); + m_freem(top); + return 0; + } + len = MCLBYTES; + } + m->m_len = len = min(totlen, len); + bcopy(pkt, mtod(m, caddr_t), len); + pkt += len; + totlen -= len; + *mp = m; + mp = &m->m_next; + } + + return top; +} + +void +bmac_watchdog(ifp) + struct ifnet *ifp; +{ + struct bmac_softc *sc = ifp->if_softc; + + bmac_reset_bits(sc, RXCFG, RxMACEnable); + bmac_reset_bits(sc, TXCFG, TxMACEnable); + + printf("%s: device timeout\n", ifp->if_xname); + ifp->if_oerrors++; + + bmac_reset(sc); +} + +int +bmac_ioctl(ifp, cmd, data) + struct ifnet *ifp; + u_long cmd; + caddr_t data; +{ + struct bmac_softc *sc = ifp->if_softc; + struct ifaddr *ifa = (struct ifaddr *)data; + struct ifreq *ifr = (struct ifreq *)data; + int s, error = 0; + int temp; + + s = splnet(); + + switch (cmd) { + + case SIOCSIFADDR: + ifp->if_flags |= IFF_UP; + + switch (ifa->ifa_addr->sa_family) { +#ifdef INET + case AF_INET: + bmac_init(sc); +#ifdef __OpenBSD__ + arp_ifinit(&sc->arpcom, ifa); +#else + arp_ifinit(ifp, ifa); +#endif + break; +#endif +#ifdef NS + case AF_NS: + { + struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; + + if (ns_nullhost(*ina)) + ina->x_host = + *(union ns_host *)LLADDR(ifp->if_sadl); + else { + bcopy(ina->x_host.c_host, + LLADDR(ifp->if_sadl), + sizeof(sc->sc_enaddr)); + } + /* Set new address. */ + bmac_init(sc); + break; + } +#endif + default: + bmac_init(sc); + break; + } + break; + + case SIOCSIFFLAGS: + if ((ifp->if_flags & IFF_UP) == 0 && + (ifp->if_flags & IFF_RUNNING) != 0) { + /* + * If interface is marked down and it is running, then + * stop it. + */ + bmac_stop(sc); + ifp->if_flags &= ~IFF_RUNNING; + } else if ((ifp->if_flags & IFF_UP) != 0 && + (ifp->if_flags & IFF_RUNNING) == 0) { + /* + * If interface is marked up and it is stopped, then + * start it. + */ + bmac_init(sc); + } else { + /* + * Reset the interface to pick up changes in any other + * flags that affect hardware registers. + */ + /*bmac_stop(sc);*/ + bmac_init(sc); + } +#ifdef BMAC_DEBUG + if (ifp->if_flags & IFF_DEBUG) + sc->sc_debug = 1; + else + sc->sc_debug = 0; +#endif + break; + + case SIOCADDMULTI: + case SIOCDELMULTI: +#if defined(__OpenBSD__) + error = (cmd == SIOCADDMULTI) ? + ether_addmulti(ifr, &sc->arpcom) : + ether_delmulti(ifr, &sc->arpcom); +#else + error = (cmd == SIOCADDMULTI) ? + ether_addmulti(ifr, &sc->sc_ethercom) : + ether_delmulti(ifr, &sc->sc_ethercom); +#endif + + if (error == ENETRESET) { + /* + * Multicast list has changed; set the hardware filter + * accordingly. + */ + bmac_init(sc); + bmac_setladrf(sc); + error = 0; + } + break; + + case SIOCGIFMEDIA: + case SIOCSIFMEDIA: + error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); + break; + + default: + error = EINVAL; + } + + splx(s); + return error; +} + +int +bmac_mediachange(ifp) + struct ifnet *ifp; +{ + return EINVAL; +} + +void +bmac_mediastatus(ifp, ifmr) + struct ifnet *ifp; + struct ifmediareq *ifmr; +{ + if ((ifp->if_flags & IFF_UP) == 0) + return; + + ifmr->ifm_status = IFM_AVALID; + ifmr->ifm_status |= IFM_ACTIVE; +} + +#define MC_POLY_BE 0x04c11db7UL /* mcast crc, big endian */ +#define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ + +/* + * Set up the logical address filter. + */ +void +bmac_setladrf(sc) + struct bmac_softc *sc; +{ + struct ifnet *ifp = &sc->sc_if; + struct ether_multi *enm; + struct ether_multistep step; + int i, j; + u_int32_t crc; + u_int16_t hash[4]; + u_int8_t octet; + + /* + * Set up multicast address filter by passing all multicast addresses + * through a crc generator, and then using the high order 6 bits as an + * index into the 64 bit logical address filter. The high order bit + * selects the word, while the rest of the bits select the bit within + * the word. + */ + + if (ifp->if_flags & IFF_ALLMULTI) + goto allmulti; + + if (ifp->if_flags & IFF_PROMISC) { + bmac_set_bits(sc, RXCFG, RxPromiscEnable); + goto allmulti; + } + + hash[3] = hash[2] = hash[1] = hash[0] = 0; +#ifdef __OpenBSD__ + ETHER_FIRST_MULTI(step, &sc->arpcom, enm); +#else + ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); +#endif + while (enm != NULL) { + if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { + /* + * We must listen to a range of multicast addresses. + * For now, just accept all multicasts, rather than + * trying to set only those filter bits needed to match + * the range. (At this time, the only use of address + * ranges is for IP multicast routing, for which the + * range is big enough to require all bits set.) + */ + goto allmulti; + } + + crc = 0xffffffff; + for (i = 0; i < ETHER_ADDR_LEN; i++) { + octet = enm->enm_addrlo[i]; + + for (j = 0; j < 8; j++) { + if ((crc & 1) ^ (octet & 1)) { + crc >>= 1; + crc ^= MC_POLY_LE; + } + else + crc >>= 1; + octet >>= 1; + } + } + + /* Just want the 6 most significant bits. */ + crc >>= 26; + + /* Set the corresponding bit in the filter. */ + hash[crc >> 4] |= 1 << (crc & 0xf); + + ETHER_NEXT_MULTI(step, enm); + } + bmac_write_reg(sc, HASH3, hash[3]); + bmac_write_reg(sc, HASH2, hash[2]); + bmac_write_reg(sc, HASH1, hash[1]); + bmac_write_reg(sc, HASH0, hash[0]); + ifp->if_flags &= ~IFF_ALLMULTI; + return; + +allmulti: + ifp->if_flags |= IFF_ALLMULTI; + bmac_write_reg(sc, HASH3, 0xffff); + bmac_write_reg(sc, HASH2, 0xffff); + bmac_write_reg(sc, HASH1, 0xffff); + bmac_write_reg(sc, HASH0, 0xffff); +} + +#define MIFDELAY delay(1) + +unsigned int +bmac_mif_readbits(sc, nb) + struct bmac_softc *sc; + int nb; +{ + unsigned int val = 0; + + while (--nb >= 0) { + bmac_write_reg(sc, MIFCSR, 0); + MIFDELAY; + if (bmac_read_reg(sc, MIFCSR) & 8) + val |= 1 << nb; + bmac_write_reg(sc, MIFCSR, 1); + MIFDELAY; + } + bmac_write_reg(sc, MIFCSR, 0); + MIFDELAY; + bmac_write_reg(sc, MIFCSR, 1); + MIFDELAY; + return val; +} + +void +bmac_mif_writebits(sc, val, nb) + struct bmac_softc *sc; + unsigned int val; + int nb; +{ + int b; + + while (--nb >= 0) { + b = (val & (1 << nb))? 6: 4; + bmac_write_reg(sc, MIFCSR, b); + MIFDELAY; + bmac_write_reg(sc, MIFCSR, b|1); + MIFDELAY; + } +} + +unsigned int +bmac_mif_read(sc, addr) + struct bmac_softc *sc; + unsigned int addr; +{ + unsigned int val; + + bmac_write_reg(sc, MIFCSR, 4); + MIFDELAY; + bmac_mif_writebits(sc, ~0U, 32); + bmac_mif_writebits(sc, 6, 4); + bmac_mif_writebits(sc, addr, 10); + bmac_write_reg(sc, MIFCSR, 2); + MIFDELAY; + bmac_write_reg(sc, MIFCSR, 1); + MIFDELAY; + val = bmac_mif_readbits(sc, 17); + bmac_write_reg(sc, MIFCSR, 4); + MIFDELAY; + /* printk(KERN_DEBUG "bmac_mif_read(%x) -> %x\n", addr, val); */ + return val; +} + +void +bmac_mif_write(sc, addr, val) + struct bmac_softc *sc; + unsigned int addr; + unsigned int val; +{ + bmac_write_reg(sc, MIFCSR, 4); + MIFDELAY; + bmac_mif_writebits(sc, ~0U, 32); + bmac_mif_writebits(sc, 5, 4); + bmac_mif_writebits(sc, addr, 10); + bmac_mif_writebits(sc, 2, 2); + bmac_mif_writebits(sc, val, 16); + bmac_mif_writebits(sc, 3, 2); +} + +void +bmac_init_mif(sc) + struct bmac_softc *sc; +{ + int id; + if (sc->sc_flags & BMAC_BMACPLUS) { + id = bmac_mif_read(sc,2); + switch (id) { + case 0x7810: + if (bmac_mif_read(sc,4) == 0xa1) { + bmac_mif_write(sc, 0, 0x1000); + } else { + bmac_mif_write(sc, 4, 0xa1); + bmac_mif_write(sc, 0, 0x1200); + } +#if 0 + /* DEBUGGING */ + printf("mif 0 %x\n", bmac_mif_read(sc, 0)); + printf("mif 4 %x\n", bmac_mif_read(sc, 4)); +#endif + break; + default: + printf("bmac mif id %x not regcognized\n", id); + /* nothing */ + } + } + return; +} diff --git a/sys/arch/powerpc/mac/if_bmreg.h b/sys/arch/powerpc/mac/if_bmreg.h new file mode 100644 index 00000000000..9533263a043 --- /dev/null +++ b/sys/arch/powerpc/mac/if_bmreg.h @@ -0,0 +1,140 @@ +/* $NetBSD: if_bmreg.h,v 1.1 1999/01/01 01:27:52 tsubai Exp $ */ + +/* + * Copyright 1991-1998 by Open Software Foundation, Inc. + * All Rights Reserved + * + * Permission to use, copy, modify, and distribute this software and + * its documentation for any purpose and without fee is hereby granted, + * provided that the above copyright notice appears in all copies and + * that both the copyright notice and this permission notice appear in + * supporting documentation. + * + * OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT, + * NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION + * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/* -------------------------------------------------------------------- */ +/* Heathrow (F)eature (C)ontrol (R)egister Addresses */ +/* -------------------------------------------------------------------- */ +#define EnetEnable 0x60000000 /* enable Enet Xcvr/Controller */ +#define ResetEnetCell 0x80000000 /* reset Enet cell */ + +/* -------------------------------------------------------------------- */ +/* BigMac Register Numbers & Bit Assignments */ +/* -------------------------------------------------------------------- */ +#define XIFC 0x0000 +#define TxOutputEnable 0x0001 +#define MIILoopbackBits 0x0006 +#define MIIBufferEnable 0x0008 +#define SQETestEnable 0x0010 +#define LinkStatus 0x0100 +#define TXFIFOCSR 0x0100 +#define TxFIFOEnable 0x0001 +#define TxFIFO128 0x0000 +#define TXTH 0x0110 +#define RXFIFOCSR 0x0120 +#define RxFIFOEnable TxFIFOEnable +#define RxFIFO128 TxFIFO128 +#define MEMADD 0x0130 +#define MEMDATAHI 0x0140 +#define MEMDATALO 0x0150 +#define XCVRIF 0x0160 +#define COLActiveLow 0x0002 +#define SerialMode 0x0004 +#define ClkBit 0x0008 +#define CHIPID 0x0170 +#define MIFCSR 0x0180 +#define SROMCSR 0x0190 +#define TXPNTR 0x01A0 +#define RXPNTR 0x01B0 +#define STATUS 0x0200 +#define INTDISABLE 0x0210 +#define IntFrameReceived 0x0001 +#define IntRxFrameCntExp 0x0002 +#define IntRxAlignCntExp 0x0004 +#define IntRxCRCCntExp 0x0008 +#define IntRxLenCntExp 0x0010 +#define IntRxOverFlow 0x0020 +#define IntRxCodeViolation 0x0040 +#define IntSQETestError 0x0080 +#define IntFrameSent 0x0100 +#define IntTxUnderrun 0x0200 +#define IntTxMaxSizeError 0x0400 +#define IntTxNormalCollExp 0x0800 +#define IntTxExcessCollExp 0x1000 +#define IntTxLateCollExp 0x2000 +#define IntTxNetworkCollExp 0x4000 +#define IntTxDeferTimerExp 0x8000 +#define NormalIntEvents ~(IntFrameSent) +#define NoEventsMask 0xFFFF + +#define TxNeverGiveUp 0x0400 +#define TXRST 0x0420 +#define TxResetBit 0x0001 +#define TXCFG 0x0430 +#define TxMACEnable 0x0001 +#define TxThreshold 0x0004 +#define IPG1 0x0440 +#define IPG2 0x0450 +#define ALIMIT 0x0460 +#define SLOT 0x0470 +#define PALEN 0x0480 +#define PAPAT 0x0490 +#define TXSFD 0x04A0 +#define JAM 0x04B0 +#define TXMAX 0x04C0 +#define TXMIN 0x04D0 +#define PAREG 0x04E0 +#define DCNT 0x04F0 +#define NCCNT 0x0500 +#define NTCNT 0x0510 +#define EXCNT 0x0520 +#define LTCNT 0x0530 +#define RSEED 0x0540 +#define TXSM 0x0550 +#define RXRST 0x0620 +#define RxResetValue 0x0000 +#define RXCFG 0x0630 +#define RxMACEnable 0x0001 +#define ReservedValue 0x0004 +#define RxPromiscEnable 0x0040 +#define RxCRCEnable 0x0100 +#define RxRejectOwnPackets 0x0200 +#define RxHashFilterEnable 0x0800 +#define RxAddrFilterEnable 0x1000 +#define RXMAX 0x0640 +#define RXMIN 0x0650 +#define MADD2 0x0660 +#define MADD1 0x0670 +#define MADD0 0x0680 +#define FRCNT 0x0690 +#define LECNT 0x06A0 +#define AECNT 0x06B0 +#define FECNT 0x06C0 +#define RXSM 0x06D0 +#define RXCV 0x06E0 +#define HASH3 0x0700 +#define HASH2 0x0710 +#define HASH1 0x0720 +#define HASH0 0x0730 +#define AFR2 0x0740 +#define AFR1 0x0750 +#define AFR0 0x0760 +#define AFCR 0x0770 +#define EnableAllCompares 0x0fff + +/* -------------------------------------------------------------------- */ +/* Misc. Bit definitions for BMac Status word */ +/* -------------------------------------------------------------------- */ +#define RxAbortBit 0x8000 /* status bit in BMac status for rx packets */ +#define RxLengthMask 0x3FFF /* bits that determine length of rx packets */ + +#define NETWORK_BUFSIZE (ETHERMAXPACKET + ETHERCRC + 2) diff --git a/sys/arch/powerpc/mac/macintr.c b/sys/arch/powerpc/mac/macintr.c new file mode 100644 index 00000000000..cbaec1a9fe7 --- /dev/null +++ b/sys/arch/powerpc/mac/macintr.c @@ -0,0 +1,518 @@ +/* $OpenBSD: macintr.c,v 1.1 1999/11/08 23:46:01 rahnds Exp $ */ + +/*- + * Copyright (c) 1995 Per Fogelstrom + * Copyright (c) 1993, 1994 Charles M. Hannum. + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * William Jolitz and Don Ahn. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)isa.c 7.2 (Berkeley) 5/12/91 + */ +#include <sys/param.h> +#include <sys/proc.h> +#include <sys/user.h> +#include <sys/systm.h> +#include <sys/time.h> +#include <sys/kernel.h> +#include <sys/device.h> +#include <sys/malloc.h> + +#include <vm/vm.h> +#include <vm/vm_kern.h> + +#include <machine/intr.h> +#include <machine/psl.h> +#include <machine/pio.h> + +#define ICU_LEN 64 +#define LEGAL_IRQ(x) ((x >= 0) && (x < ICU_LEN)) + +static int intrtype[ICU_LEN], intrmask[ICU_LEN], intrlevel[ICU_LEN]; +static struct intrhand *intrhand[ICU_LEN]; +static int hwirq[ICU_LEN], virq[64]; +unsigned int imen = 0xffffffff; +int virq_max = 0; + +struct evcnt evirq[ICU_LEN*2]; + +static int fakeintr __P((void *)); +static char *intr_typename(int type); +static void intr_calculatemasks(); +static void enable_irq(int x); +static __inline int cntlzw(int x); + +extern u_int32_t *heathrow_FCR; + +#define HWIRQ_MAX 27 +#define HWIRQ_MASK 0x0fffffff + +#define INT_STATE_REG0 (interrupt_reg + 0x20) +#define INT_ENABLE_REG0 (interrupt_reg + 0x24) +#define INT_CLEAR_REG0 (interrupt_reg + 0x28) +#define INT_LEVEL_REG0 (interrupt_reg + 0x2c) +#define INT_STATE_REG1 (INT_STATE_REG0 - 0x10) +#define INT_ENABLE_REG1 (INT_ENABLE_REG0 - 0x10) +#define INT_CLEAR_REG1 (INT_CLEAR_REG0 - 0x10) +#define INT_LEVEL_REG1 (INT_LEVEL_REG0 - 0x10) + +int macintrmatch __P((struct device *, void *, void *)); +void macintrattach __P((struct device *, struct device *, void *)); + +u_int8_t *interrupt_reg; + +static int +fakeintr(arg) + void *arg; +{ + + return 0; +} + +/* + * Register an interrupt handler. + */ +void * +mac_intr_establish(irq, type, level, ih_fun, ih_arg) + int irq; + int type; + int level; + int (*ih_fun) __P((void *)); + void *ih_arg; +{ + struct intrhand **p, *q, *ih; + static struct intrhand fakehand; + extern int cold; + fakehand.ih_next = NULL; + fakehand.ih_fun = fakeintr; + +#if 0 +printf("mac_intr_establish, hI %d L %d ", irq, type); +printf("addr reg0 %x\n", INT_STATE_REG0); +#endif + + irq = mapirq(irq); +#if 0 +printf("vI %d ", irq); +#endif + + /* no point in sleeping unless someone can free memory. */ + ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK); + if (ih == NULL) + panic("intr_establish: can't malloc handler info"); + + if (!LEGAL_IRQ(irq) || type == IST_NONE) + panic("intr_establish: bogus irq or type"); + + switch (intrtype[irq]) { + case IST_NONE: + intrtype[irq] = type; + break; + case IST_EDGE: + case IST_LEVEL: + if (type == intrtype[irq]) + break; + case IST_PULSE: + if (type != IST_NONE) + panic("intr_establish: can't share %s with %s", + intr_typename(intrtype[irq]), + intr_typename(type)); + break; + } + + /* + * Figure out where to put the handler. + * This is O(N^2), but we want to preserve the order, and N is + * generally small. + */ + for (p = &intrhand[irq]; (q = *p) != NULL; p = &q->ih_next) + ; + + /* + * Actually install a fake handler momentarily, since we might be doing + * this with interrupts enabled and don't want the real routine called + * until masking is set up. + */ + fakehand.ih_level = level; + *p = &fakehand; + + intr_calculatemasks(); + + /* + * Poke the real handler in now. + */ + ih->ih_fun = ih_fun; + ih->ih_arg = ih_arg; + ih->ih_count = 0; + ih->ih_next = NULL; + ih->ih_level = level; + ih->ih_irq = irq; + *p = ih; + + return (ih); +} + +/* + * Deregister an interrupt handler. + */ +void +mac_intr_disestablish(arg) + void *arg; +{ + struct intrhand *ih = arg; + int irq = ih->ih_irq; + struct intrhand **p, *q; + + if (!LEGAL_IRQ(irq)) + panic("intr_disestablish: bogus irq"); + + /* + * Remove the handler from the chain. + * This is O(n^2), too. + */ + for (p = &intrhand[irq]; (q = *p) != NULL && q != ih; p = &q->ih_next) + ; + if (q) + *p = q->ih_next; + else + panic("intr_disestablish: handler not registered"); + free((void *)ih, M_DEVBUF); + + intr_calculatemasks(); + + if (intrhand[irq] == NULL) + intrtype[irq] = IST_NONE; +} + + +static char * +intr_typename(type) + int type; +{ + + switch (type) { + case IST_NONE : + return ("none"); + case IST_PULSE: + return ("pulsed"); + case IST_EDGE: + return ("edge-triggered"); + case IST_LEVEL: + return ("level-triggered"); + default: + panic("intr_typename: invalid type %d", type); +#if 1 /* XXX */ + return ("unknown"); +#endif + } +} +/* + * Recalculate the interrupt masks from scratch. + * We could code special registry and deregistry versions of this function that + * would be faster, but the code would be nastier, and we don't expect this to + * happen very much anyway. + */ +static void +intr_calculatemasks() +{ + int irq, level; + struct intrhand *q; + + /* First, figure out which levels each IRQ uses. */ + for (irq = 0; irq < ICU_LEN; irq++) { + register int levels = 0; + for (q = intrhand[irq]; q; q = q->ih_next) + levels |= 1 << q->ih_level; + intrlevel[irq] = levels; + } + + /* Then figure out which IRQs use each level. */ + for (level = 0; level < 5; level++) { + register int irqs = 0; + for (irq = 0; irq < ICU_LEN; irq++) + if (intrlevel[irq] & (1 << level)) + irqs |= 1 << irq; + imask[level] = irqs | SINT_MASK; + } + + /* + * There are tty, network and disk drivers that use free() at interrupt + * time, so imp > (tty | net | bio). + */ + imask[IPL_IMP] |= imask[IPL_TTY] | imask[IPL_NET] | imask[IPL_BIO]; + + /* + * Enforce a hierarchy that gives slow devices a better chance at not + * dropping data. + */ + imask[IPL_TTY] |= imask[IPL_NET] | imask[IPL_BIO]; + imask[IPL_NET] |= imask[IPL_BIO]; + + /* + * These are pseudo-levels. + */ + imask[IPL_NONE] = 0x00000000; + imask[IPL_HIGH] = 0xffffffff; + + /* And eventually calculate the complete masks. */ + for (irq = 0; irq < ICU_LEN; irq++) { + register int irqs = 1 << irq; + for (q = intrhand[irq]; q; q = q->ih_next) + irqs |= imask[q->ih_level]; + intrmask[irq] = irqs | SINT_MASK; + } + + /* Lastly, determine which IRQs are actually in use. */ + { + register int irqs = 0; + for (irq = 0; irq < ICU_LEN; irq++) { + if (intrhand[irq]) + irqs |= 1 << irq; + } + imen = ~irqs; + enable_irq(~imen); + } +} +static void +enable_irq(x) + int x; +{ + int state0, state1, v; + int irq; + + x &= HWIRQ_MASK; /* XXX Higher bits are software interrupts. */ + + state0 = state1 = 0; + while (x) { + v = 31 - cntlzw(x); + irq = hwirq[v]; + if (irq < 32) { + state0 |= 1 << irq; + } else { + state1 |= 1 << (irq - 32); + } + x &= ~(1 << v); + } + + if (heathrow_FCR) { + out32rb(INT_ENABLE_REG1, state1); + } + out32rb(INT_ENABLE_REG0, state0); +} +/* + * Map 64 irqs into 32 (bits). + */ +int +mapirq(irq) + int irq; +{ + int v; + + if (irq < 0 || irq >= 64) + panic("invalid irq"); + virq_max++; + v = virq_max; + if (v > HWIRQ_MAX) + panic("virq overflow"); + + hwirq[v] = irq; + virq[irq] = v; +#if 0 +printf("\nmapirq %x to %x\n", irq, v); +#endif + + return v; +} + +/* + * Count leading zeros. + */ +static __inline int +cntlzw(x) + int x; +{ + int a; + + __asm __volatile ("cntlzw %0,%1" : "=r"(a) : "r"(x)); + + return a; +} + +/* + * external interrupt handler + */ +void +mac_ext_intr() +{ + int i, irq = 0; + int o_imen, r_imen; + int pcpl; + struct intrhand *ih; + volatile unsigned long int_state; + + pcpl = splhigh(); /* Turn off all */ + +#if 0 +printf("mac_intr \n"); +#endif + int_state = read_irq(); + if (int_state == 0) + goto out; + +start: + irq = 31 - cntlzw(int_state); + + o_imen = imen; + r_imen = 1 << irq; + + if ((pcpl & r_imen) != 0) { + ipending |= r_imen; /* Masked! Mark this as pending */ + imen |= r_imen; + enable_irq(~imen); + } else { + ih = intrhand[irq]; + while (ih) { +#if 0 +printf("calling handler %x\n", ih->ih_fun); +#endif + (*ih->ih_fun)(ih->ih_arg); + ih = ih->ih_next; + } + +#ifdef UVM + uvmexp.intrs++; +#else +#endif + evirq[hwirq[irq]].ev_count++; + } + int_state &= ~r_imen; + if (int_state) + goto start; + +out: + splx(pcpl); /* Process pendings. */ +} + +void +mac_do_pending_int() +{ + struct intrhand *ih; + int irq; + int pcpl; + int hwpend; + int emsr, dmsr; + static int processing; + + if (processing) + return; + + processing = 1; + pcpl = splhigh(); /* Turn off all */ + asm volatile("mfmsr %0" : "=r"(emsr)); + dmsr = emsr & ~PSL_EE; + asm volatile("mtmsr %0" :: "r"(dmsr)); + + hwpend = ipending & ~pcpl; /* Do now unmasked pendings */ + imen &= ~hwpend; + enable_irq(~imen); + hwpend &= HWIRQ_MASK; + while (hwpend) { + irq = 31 - cntlzw(hwpend); + hwpend &= ~(1L << irq); + ih = intrhand[irq]; + while(ih) { + (*ih->ih_fun)(ih->ih_arg); + ih = ih->ih_next; + } + + evirq[hwirq[irq]].ev_count++; + } + + /*out32rb(INT_ENABLE_REG, ~imen);*/ + + do { + if((ipending & SINT_CLOCK) & ~pcpl) { + ipending &= ~SINT_CLOCK; + softclock(); + } + if((ipending & SINT_NET) & ~pcpl) { + extern int netisr; + int pisr = netisr; + netisr = 0; + ipending &= ~SINT_NET; + softnet(pisr); + } + } while (ipending & (SINT_NET|SINT_CLOCK) & ~cpl); + ipending &= pcpl; + cpl = pcpl; /* Don't use splx... we are here already! */ + asm volatile("mtmsr %0" :: "r"(emsr)); + processing = 0; +} + +int +read_irq() +{ + int rv = 0; + int state0, state1, p; + int state0save, state1save; + + state0 = in32rb(INT_STATE_REG0); + if (state0) + out32rb(INT_CLEAR_REG0, state0); + state0save = state0; + while (state0) { + p = 31 - cntlzw(state0); + rv |= 1 << virq[p]; + state0 &= ~(1 << p); + } + + if (heathrow_FCR) /* has heathrow? */ + state1 = in32rb(INT_STATE_REG1); + else + state1 = 0; + + if (state1) + out32rb(INT_CLEAR_REG1, state1); + state1save = state1; + while (state1) { + p = 31 - cntlzw(state1); + rv |= 1 << virq[p + 32]; + state1 &= ~(1 << p); + } +#if 0 +printf("mac_intr int_stat 0:%x 1:%x\n", state0save, state1save); +#endif + + /* 1 << 0 is invalid. */ + return rv & ~1; +} diff --git a/sys/arch/powerpc/mac/wdc_obio.c b/sys/arch/powerpc/mac/wdc_obio.c new file mode 100644 index 00000000000..be6cad3f2ef --- /dev/null +++ b/sys/arch/powerpc/mac/wdc_obio.c @@ -0,0 +1,270 @@ +/* $OpenBSD: wdc_obio.c,v 1.1 1999/11/08 23:46:01 rahnds Exp $ */ +/* $NetBSD: wdc_obio.c,v 1.4 1999/06/14 08:53:06 tsubai Exp $ */ + +/*- + * Copyright (c) 1998 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Charles M. Hannum and by Onno van der Linden. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/device.h> +#include <sys/malloc.h> + +#include <vm/vm.h> + +#include <machine/bus.h> +#include <machine/autoconf.h> + +#include <dev/ata/atavar.h> +#include <dev/ic/wdcvar.h> + +#include <powerpc/mac/dbdma.h> + +#define WDC_REG_NPORTS 8 +#define WDC_AUXREG_OFFSET 0x16 +#define WDC_DEFAULT_PIO_IRQ 13 /* XXX */ +#define WDC_DEFAULT_DMA_IRQ 2 /* XXX */ + +#define WDC_OPTIONS_DMA 0x01 + +/* + * XXX This code currently doesn't even try to allow 32-bit data port use. + */ + +struct wdc_obio_softc { + struct wdc_softc sc_wdcdev; + struct channel_softc *wdc_chanptr; + struct channel_softc wdc_channel; + dbdma_regmap_t *sc_dmareg; + dbdma_command_t *sc_dmacmd; +}; + +int wdc_obio_probe __P((struct device *, void *, void *)); +void wdc_obio_attach __P((struct device *, struct device *, void *)); + +struct cfattach wdc_obio_ca = { + sizeof(struct wdc_obio_softc), wdc_obio_probe, wdc_obio_attach +}; + +#if 0 +struct cfdriver wdc_cd = { + NULL, "wdc", DV_DULL +}; +#endif + + +static int wdc_obio_dma_init __P((void *, int, int, void *, size_t, int)); +static void wdc_obio_dma_start __P((void *, int, int, int)); +static int wdc_obio_dma_finish __P((void *, int, int, int)); + +int +wdc_obio_probe(parent, match, aux) + struct device *parent; + void *match; + void *aux; +{ + struct confargs *ca = aux; + char compat[32]; + + /* XXX should not use name */ + if (strcmp(ca->ca_name, "ATA") == 0 || + strcmp(ca->ca_name, "ata") == 0 || + strcmp(ca->ca_name, "ata0") == 0 || + strcmp(ca->ca_name, "ide") == 0) + return 1; + + bzero(compat, sizeof(compat)); + OF_getprop(ca->ca_node, "compatible", compat, sizeof(compat)); + if (strcmp(compat, "heathrow-ata") == 0) + return 1; + + return 0; +} + +void +wdc_obio_attach(parent, self, aux) + struct device *parent, *self; + void *aux; +{ + struct wdc_obio_softc *sc = (void *)self; + struct confargs *ca = aux; + struct channel_softc *chp = &sc->wdc_channel; + int intr; + int use_dma = 0; + bus_addr_t cmdbase; + bus_size_t cmdsize; + bus_addr_t ctlbase; + bus_size_t ctlsize; + + if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & WDC_OPTIONS_DMA) { + if (ca->ca_nreg >= 16 || ca->ca_nintr == -1) + use_dma = 1; /* XXX Don't work yet. */ + } + + if (ca->ca_nintr >= 4 && ca->ca_nreg >= 8) { + intr = ca->ca_intr[0]; + printf(" irq %d", intr); + } else if (ca->ca_nintr == -1) { + intr = WDC_DEFAULT_PIO_IRQ; + printf(" irq property not found; using %d", intr); + } else { + printf(": couldn't get irq property\n"); + return; + } + + if (use_dma) + printf(": DMA transfer"); + + printf("\n"); + + chp->cmd_iot = chp->ctl_iot = ca->ca_iot; + cmdbase = ca->ca_reg[0]; + cmdsize = ca->ca_reg[1]; + + if (bus_space_map(chp->cmd_iot, cmdbase, cmdsize, 0, &chp->cmd_ioh) || + bus_space_subregion(chp->cmd_iot, chp->cmd_ioh, + /* WDC_AUXREG_OFFSET<<4 */ 0x160, 1, &chp->ctl_ioh)) + { + printf("%s: couldn't map registers\n", + sc->sc_wdcdev.sc_dev.dv_xname); + return; + } +printf ("wdc_obio cmd_ioh %x ctl_ioh %x\n", chp->cmd_ioh, chp->ctl_ioh); + chp->data32iot = chp->cmd_iot; + chp->data32ioh = chp->cmd_ioh; + + mac_intr_establish(intr, IST_LEVEL, IPL_BIO, wdcintr, chp); + + if (use_dma) { + sc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20); + sc->sc_dmareg = mapiodev(ca->ca_baseaddr + ca->ca_reg[2], + ca->ca_reg[3]); + sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; + } + sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; + sc->sc_wdcdev.PIO_cap = 0; + sc->wdc_chanptr = chp; + sc->sc_wdcdev.channels = &sc->wdc_chanptr; + sc->sc_wdcdev.nchannels = 1; + sc->sc_wdcdev.dma_arg = sc; + sc->sc_wdcdev.dma_init = wdc_obio_dma_init; + sc->sc_wdcdev.dma_start = wdc_obio_dma_start; + sc->sc_wdcdev.dma_finish = wdc_obio_dma_finish; + chp->channel = 0; + chp->wdc = &sc->sc_wdcdev; + chp->ch_queue = malloc(sizeof(struct channel_queue), + M_DEVBUF, M_NOWAIT); + if (chp->ch_queue == NULL) { + printf("%s: can't allocate memory for command queue", + sc->sc_wdcdev.sc_dev.dv_xname); + return; + } + + wdcattach(chp); +} + +static int +wdc_obio_dma_init(v, channel, drive, databuf, datalen, read) + void *v; + void *databuf; + size_t datalen; + int read; +{ + struct wdc_obio_softc *sc = v; + vaddr_t va = (vaddr_t)databuf; + dbdma_command_t *cmdp; + u_int cmd, offset; + + cmdp = sc->sc_dmacmd; + cmd = read ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE; + + offset = va & PGOFSET; + + /* if va is not page-aligned, setup the first page */ + if (offset != 0) { + int rest = NBPG - offset; /* the rest of the page */ + + if (datalen > rest) { /* if continues to next page */ + DBDMA_BUILD(cmdp, cmd, 0, rest, vtophys(va), + DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, + DBDMA_BRANCH_NEVER); + datalen -= rest; + va += rest; + cmdp++; + } + } + + /* now va is page-aligned */ + while (datalen > NBPG) { + DBDMA_BUILD(cmdp, cmd, 0, NBPG, vtophys(va), + DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); + datalen -= NBPG; + va += NBPG; + cmdp++; + } + + /* the last page (datalen <= NBPG here) */ + cmd = read ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST; + DBDMA_BUILD(cmdp, cmd, 0, datalen, vtophys(va), + DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); + cmdp++; + + DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0, + DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); + + return 0; +} + +static void +wdc_obio_dma_start(v, channel, drive, read) + void *v; + int channel, drive; +{ + struct wdc_obio_softc *sc = v; + + dbdma_start(sc->sc_dmareg, sc->sc_dmacmd); +} + +static int +wdc_obio_dma_finish(v, channel, drive, read) + void *v; + int channel, drive; + int read; +{ + struct wdc_obio_softc *sc = v; + + dbdma_stop(sc->sc_dmareg); + return 0; +} |