summaryrefslogtreecommitdiff
path: root/sys/arch/sparc/dev/dmareg.h
diff options
context:
space:
mode:
Diffstat (limited to 'sys/arch/sparc/dev/dmareg.h')
-rw-r--r--sys/arch/sparc/dev/dmareg.h14
1 files changed, 9 insertions, 5 deletions
diff --git a/sys/arch/sparc/dev/dmareg.h b/sys/arch/sparc/dev/dmareg.h
index 3998581845a..c9e575a262f 100644
--- a/sys/arch/sparc/dev/dmareg.h
+++ b/sys/arch/sparc/dev/dmareg.h
@@ -1,4 +1,5 @@
-/* $NetBSD: dmareg.h,v 1.8 1996/04/22 02:34:58 abrown Exp $ */
+/* $OpenBSD: dmareg.h,v 1.4 1997/08/08 08:24:58 downsj Exp $ */
+/* $NetBSD: dmareg.h,v 1.10 1996/11/28 09:37:34 pk Exp $ */
/*
* Copyright (c) 1994 Peter Galbavy. All rights reserved.
@@ -38,19 +39,21 @@ struct dma_regs {
#define D_INT_EN 0x00000010 /* interrupt enable */
#define D_INVALIDATE 0x00000020 /* invalidate fifo */
#define D_SLAVE_ERR 0x00000040 /* slave access size error */
-#define D_DRAIN 0x00000040 /* drain fifo if DMAREV_1 */
+#define D_DRAIN 0x00000040 /* rev0,1,esc: drain fifo */
#define D_RESET 0x00000080 /* reset scsi */
#define D_WRITE 0x00000100 /* 1 = dev -> mem */
#define D_EN_DMA 0x00000200 /* enable DMA requests */
-#define D_R_PEND 0x00000400 /* something only on ver < 2 */
+#define D_R_PEND 0x00000400 /* rev0,1: request pending */
+#define D_ESC_BURST 0x00000800 /* DMA ESC: 16 byte bursts */
#define D_EN_CNT 0x00002000 /* enable byte counter */
#define D_TC 0x00004000 /* terminal count */
#define D_DSBL_CSR_DRN 0x00010000 /* disable fifo drain on csr */
#define D_DSBL_SCSI_DRN 0x00020000 /* disable fifo drain on reg */
#define D_BURST_SIZE 0x000c0000 /* sbus read/write burst size */
#define D_BURST_0 0x00080000 /* no bursts (SCSI-only) */
-#define D_BURST_16 0x00040000 /* 16-byte bursts */
-#define D_BURST_32 0x00000000 /* 32-byte bursts */
+#define D_BURST_16 0x00000000 /* 16-byte bursts */
+#define D_BURST_32 0x00040000 /* 32-byte bursts */
+#define D_AUTODRAIN 0x00040000 /* DMA ESC: Auto-drain */
#define D_DIAG 0x00100000 /* disable fifo drain on addr */
#define D_TWO_CYCLE 0x00200000 /* 2 clocks per transfer */
#define D_FASTER 0x00400000 /* 3 clocks per transfer */
@@ -62,6 +65,7 @@ struct dma_regs {
#define D_NA_LOADED 0x08000000 /* next address loaded */
#define D_DEV_ID 0xf0000000 /* device ID */
#define DMAREV_0 0x00000000 /* Sunray DMA */
+#define DMAREV_ESC 0x40000000 /* DMA ESC array */
#define DMAREV_1 0x80000000 /* 'DMA' */
#define DMAREV_PLUS 0x90000000 /* 'DMA+' */
#define DMAREV_2 0xa0000000 /* 'DMA2' */