diff options
Diffstat (limited to 'sys/arch/sparc/dev')
| -rw-r--r-- | sys/arch/sparc/dev/p9100.c | 22 | ||||
| -rw-r--r-- | sys/arch/sparc/dev/tctrl.c | 499 | ||||
| -rw-r--r-- | sys/arch/sparc/dev/tctrlvar.h | 45 | ||||
| -rw-r--r-- | sys/arch/sparc/dev/ts102reg.h | 322 |
4 files changed, 875 insertions, 13 deletions
diff --git a/sys/arch/sparc/dev/p9100.c b/sys/arch/sparc/dev/p9100.c index 497aaa76301..466dff38066 100644 --- a/sys/arch/sparc/dev/p9100.c +++ b/sys/arch/sparc/dev/p9100.c @@ -1,4 +1,4 @@ -/* $OpenBSD: p9100.c,v 1.2 1999/09/06 04:46:38 jason Exp $ */ +/* $OpenBSD: p9100.c,v 1.3 1999/09/07 02:58:49 jason Exp $ */ /* * Copyright (c) 1999 Jason L. Wright (jason@thought.net) @@ -61,6 +61,11 @@ #include <sparc/dev/btvar.h> #include <sparc/dev/sbusvar.h> +#include "tctrl.h" +#if NTCTRL > 0 +#include <sparc/dev/tctrlvar.h> +#endif + /* per-display variables */ struct p9100_softc { struct device sc_dev; /* base device */ @@ -406,6 +411,9 @@ p9100_set_video(sc, enable) else v &= ~SRTC1_VIDEN; sc->sc_ctl->ctl_vcr.srtc1 = v; +#if NTCTRL > 0 + tadpole_set_video(enable); +#endif } int @@ -443,16 +451,6 @@ p9100loadcmap(sc, start, ncolors) /* * Return the address that would map the given device at the given * offset, allowing for the given protection, or return -1 for error. - * - * The cg3 is mapped starting at 256KB, for pseudo-compatibility with - * the cg4 (which had an overlay plane in the first 128K and an enable - * plane in the next 128K). X11 uses only 256k+ region but tries to - * map the whole thing, so we repeatedly map the first 256K to the - * first page of the color screen. If someone tries to use the overlay - * and enable regions, they will get a surprise.... - * - * As well, mapping at an offset of 0x04000000 causes the cg3 to be - * mapped in flat mode without the cg4 emulation. */ int p9100mmap(dev, off, prot) @@ -460,8 +458,6 @@ p9100mmap(dev, off, prot) int off, prot; { struct p9100_softc *sc = pnozz_cd.cd_devs[minor(dev)]; -#define START (128*1024 + 128*1024) -#define NOOVERLAY (0x04000000) if (off & PGOFSET) panic("p9100mmap"); diff --git a/sys/arch/sparc/dev/tctrl.c b/sys/arch/sparc/dev/tctrl.c new file mode 100644 index 00000000000..b3a924d2095 --- /dev/null +++ b/sys/arch/sparc/dev/tctrl.c @@ -0,0 +1,499 @@ +/* $OpenBSD: tctrl.c,v 1.1 1999/09/07 02:58:50 jason Exp $ */ +/* $NetBSD: tctrl.c,v 1.2 1999/08/11 00:46:06 matt Exp $ */ + +/*- + * Copyright (c) 1998 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Matt Thomas. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/ioctl.h> +#include <sys/select.h> +#include <sys/tty.h> +#include <sys/proc.h> +#include <sys/user.h> +#include <sys/conf.h> +#include <sys/file.h> +#include <sys/uio.h> +#include <sys/kernel.h> +#include <sys/syslog.h> +#include <sys/types.h> +#include <sys/device.h> + +#include <machine/autoconf.h> +#include <machine/cpu.h> + +#include <sparc/dev/ts102reg.h> +#include <sparc/dev/tctrlvar.h> + +const char *tctrl_ext_statuses[16] = { + "main power available", + "internal battery attached", + "external battery attached", + "external VGA attached", + "external keyboard attached", + "external mouse attached", + "lid down", + "internal battery charging", + "external battery charging", + "internal battery discharging", + "external battery discharging", +}; + +struct tctrl_softc { + struct device sc_dev; + struct uctrl_regs *sc_regs; + struct intrhand sc_ih; + int sc_node; + unsigned int sc_junk; + unsigned int sc_ext_status; + unsigned int sc_pending; +#define TCTRL_SEND_BITPORT 0x0001 +#define TCTRL_SEND_POWEROFF 0x0002 +#define TCTRL_SEND_RD_EXT_STATUS 0x0004 +#define TCTRL_SEND_RD_EVENT_STATUS 0x0008 +#define TCTRL_SEND_BITPORT_NOP 0x0010 + enum { TCTRL_IDLE, TCTRL_ARGS, + TCTRL_ACK, TCTRL_DATA } sc_state; + u_int8_t sc_cmdbuf[16]; + u_int8_t sc_rspbuf[16]; + u_int8_t sc_bitport; + u_int8_t sc_tft_on; + u_int8_t sc_op; + u_int8_t sc_cmdoff; + u_int8_t sc_cmdlen; + u_int8_t sc_rspoff; + u_int8_t sc_rsplen; + + struct evcnt sc_intrcnt; /* interrupt counting */ +}; + +int tctrl_match __P((struct device *, void *, void *)); +void tctrl_attach __P((struct device *, struct device *, void *)); + +void tctrl_write_data __P((struct tctrl_softc *, u_int8_t)); +u_int8_t tctrl_read_data __P((struct tctrl_softc *)); +int tctrl_intr __P((void *)); +void tctrl_setup_bitport __P((struct tctrl_softc *, int)); +void tctrl_process_response __P((struct tctrl_softc *)); + +struct cfattach tctrl_ca = { + sizeof(struct tctrl_softc), tctrl_match, tctrl_attach +}; + +struct cfdriver tctrl_cd = { + NULL, "tctrl", DV_DULL +}; + +int +tctrl_match(parent, vcf, aux) + struct device *parent; + void *vcf; + void *aux; +{ + struct confargs *ca = aux; + struct romaux *ra = &ca->ca_ra; + + /* + * Tadpole 3GX/3GS uses "uctrl" for the Tadpole Microcontroller + * (who's interface is off the TS102 PCMCIA controller but there + * exists a OpenProm for microcontroller interface). + */ + if (strcmp("uctrl", ra->ra_name)) + return (0); + + return (1); +} + +void +tctrl_attach(parent, self, aux) + struct device *parent, *self; + void *aux; +{ + struct confargs *ca = aux; + struct tctrl_softc *sc = (void *)self; + int pri; + unsigned int i, v; + + /* + * We're living on a sbus slot that looks like an obio that + * looks like an sbus slot. + */ + if (ca->ca_ra.ra_nintr != 1) { + printf(": expected 1 interrupt, got %d\n", + ca->ca_ra.ra_nintr); + return; + } + pri = ca->ca_ra.ra_intr[0].int_pri; + + if (ca->ca_ra.ra_nreg != 1) { + printf(": expected 1 register, got %d\n", + ca->ca_ra.ra_nreg); + return; + } + sc->sc_regs = mapiodev(&(ca->ca_ra.ra_reg[0]), 0, + ca->ca_ra.ra_reg[0].rr_len); + + sc->sc_node = ca->ca_ra.ra_node; + + printf("\n"); + + sc->sc_tft_on = 1; + + /* clear any pending data. + */ + for (i = 0; i < 10000; i++) { + if ((TS102_UCTRL_STS_RXNE_STA & sc->sc_regs->stat) == 0) + break; + v = sc->sc_regs->data; + sc->sc_regs->stat = TS102_UCTRL_STS_RXNE_STA; + } + + sc->sc_ih.ih_fun = tctrl_intr; + sc->sc_ih.ih_arg = sc; + intr_establish(pri, &sc->sc_ih); + evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); + + /* See what the external status is + */ + sc->sc_pending |= TCTRL_SEND_RD_EXT_STATUS; + do { + tctrl_intr(sc); + } while (sc->sc_state != TCTRL_IDLE); + + if (sc->sc_ext_status != 0) { + const char *sep; + + printf("%s: ", sc->sc_dev.dv_xname); + v = sc->sc_ext_status; + for (i = 0, sep = ""; v != 0; i++, v >>= 1) { + if (v & 1) { + printf("%s%s", sep, tctrl_ext_statuses[i]); + sep = ", "; + } + } + printf("\n"); + } + + /* Get a current of the control bitport; + */ + sc->sc_pending |= TCTRL_SEND_BITPORT_NOP; + do { + tctrl_intr(sc); + } while (sc->sc_state != TCTRL_IDLE); + + sc->sc_regs->intr = TS102_UCTRL_INT_RXNE_REQ|TS102_UCTRL_INT_RXNE_MSK; +} + +int +tctrl_intr(void *arg) +{ + struct tctrl_softc *sc = arg; + unsigned int v, d; + int progress = 0; + + again: + /* find out the cause(s) of the interrupt */ + v = sc->sc_regs->stat; + + /* clear the cause(s) of the interrupt */ + sc->sc_regs->stat = v; + + v &= ~(TS102_UCTRL_STS_RXO_STA|TS102_UCTRL_STS_TXE_STA); + if (sc->sc_cmdoff >= sc->sc_cmdlen) { + v &= ~TS102_UCTRL_STS_TXNF_STA; + } + if ((v == 0) && (sc->sc_pending == 0 || sc->sc_state != TCTRL_IDLE)) { + return (progress); + } + + progress = 1; + if (v & TS102_UCTRL_STS_RXNE_STA) { + d = tctrl_read_data(sc); + switch (sc->sc_state) { + case TCTRL_IDLE: + if (d == 0xfa) { + sc->sc_pending |= TCTRL_SEND_RD_EVENT_STATUS; + } else { + printf("%s: (op=0x%02x): unexpected data (0x%02x)\n", + sc->sc_dev.dv_xname, sc->sc_op, d); + } + goto again; + case TCTRL_ACK: + if (d != 0xfe) { + printf("%s: (op=0x%02x): unexpected ack value (0x%02x)\n", + sc->sc_dev.dv_xname, sc->sc_op, d); + } +#if 0 + printf(" ack=0x%02x", d); +#endif + sc->sc_rsplen--; + sc->sc_rspoff = 0; + sc->sc_state = sc->sc_rsplen ? TCTRL_DATA : TCTRL_IDLE; +#if 0 + if (sc->sc_rsplen > 0) { + printf(" [data(%u)]", sc->sc_rsplen); + } else { + printf(" [idle]\n"); + } +#endif + goto again; + case TCTRL_DATA: + sc->sc_rspbuf[sc->sc_rspoff++] = d; +#if 0 + printf(" [%d]=0x%02x", sc->sc_rspoff-1, d); +#endif + if (sc->sc_rspoff == sc->sc_rsplen) { +#if 0 + printf(" [idle]\n"); +#endif + sc->sc_state = TCTRL_IDLE; + tctrl_process_response(sc); + } + goto again; + default: + printf("%s: (op=0x%02x): unexpected data (0x%02x) in state %d\n", + sc->sc_dev.dv_xname, sc->sc_op, d, sc->sc_state); + goto again; + } + } + if (sc->sc_state == TCTRL_IDLE) { + sc->sc_cmdoff = 0; + sc->sc_cmdlen = 0; + if (sc->sc_pending & TCTRL_SEND_POWEROFF) { + sc->sc_pending &= ~TCTRL_SEND_POWEROFF; + sc->sc_cmdbuf[0] = TS102_OP_ADMIN_POWER_OFF; + sc->sc_cmdlen = 1; + sc->sc_rsplen = 0; + } else if (sc->sc_pending & TCTRL_SEND_RD_EVENT_STATUS) { + sc->sc_pending &= ~TCTRL_SEND_RD_EVENT_STATUS; + sc->sc_cmdbuf[0] = TS102_OP_RD_EVENT_STATUS; + sc->sc_cmdlen = 1; + sc->sc_rsplen = 3; + } else if (sc->sc_pending & TCTRL_SEND_RD_EXT_STATUS) { + sc->sc_pending &= ~TCTRL_SEND_RD_EXT_STATUS; + sc->sc_cmdbuf[0] = TS102_OP_RD_EXT_STATUS; + sc->sc_cmdlen = 1; + sc->sc_rsplen = 3; + } else if (sc->sc_pending & TCTRL_SEND_BITPORT_NOP) { + sc->sc_pending &= ~TCTRL_SEND_BITPORT_NOP; + tctrl_setup_bitport(sc, 1); + } else if (sc->sc_pending & TCTRL_SEND_BITPORT) { + sc->sc_pending &= ~TCTRL_SEND_BITPORT; + tctrl_setup_bitport(sc, 0); + } + if (sc->sc_cmdlen > 0) { + sc->sc_regs->intr = + sc->sc_regs->intr | TS102_UCTRL_INT_TXNF_MSK + |TS102_UCTRL_INT_TXNF_REQ; + v = sc->sc_regs->stat; + } + } + if ((sc->sc_cmdoff < sc->sc_cmdlen) && (v & TS102_UCTRL_STS_TXNF_STA)) { + tctrl_write_data(sc, sc->sc_cmdbuf[sc->sc_cmdoff++]); +#if 0 + if (sc->sc_cmdoff == 1) { + printf("%s: op=0x%02x(l=%u)", sc->sc_dev.dv_xname, + sc->sc_cmdbuf[0], sc->sc_rsplen); + } else { + printf(" [%d]=0x%02x", sc->sc_cmdoff-1, + sc->sc_cmdbuf[sc->sc_cmdoff-1]); + } +#endif + if (sc->sc_cmdoff == sc->sc_cmdlen) { + sc->sc_state = sc->sc_rsplen ? TCTRL_ACK : TCTRL_IDLE; +#if 0 + printf(" %s", sc->sc_rsplen ? "[ack]" : "[idle]\n"); +#endif + if (sc->sc_cmdoff == 1) { + sc->sc_op = sc->sc_cmdbuf[0]; + } + sc->sc_regs->intr = + sc->sc_regs->intr & (~TS102_UCTRL_INT_TXNF_MSK + |TS102_UCTRL_INT_TXNF_REQ); + } else if (sc->sc_state == TCTRL_IDLE) { + sc->sc_op = sc->sc_cmdbuf[0]; + sc->sc_state = TCTRL_ARGS; +#if 0 + printf(" [args]"); +#endif + } + } + goto again; +} + +void +tctrl_setup_bitport(struct tctrl_softc *sc, int nop) +{ + if (nop) { + sc->sc_cmdbuf[0] = TS102_OP_CTL_BITPORT; + sc->sc_cmdbuf[1] = 0xff; + sc->sc_cmdbuf[2] = 0; + sc->sc_cmdlen = 3; + sc->sc_rsplen = 2; + } else { + if ((sc->sc_ext_status & TS102_EXT_STATUS_LID_DOWN) + || (!sc->sc_tft_on)) { + sc->sc_cmdbuf[2] = TS102_BITPORT_TFTPWR; + } else { + sc->sc_cmdbuf[2] = 0; + } + sc->sc_cmdbuf[0] = TS102_OP_CTL_BITPORT; + sc->sc_cmdbuf[1] = ~TS102_BITPORT_TFTPWR; + sc->sc_cmdlen = 3; + sc->sc_rsplen = 2; + } +} + +void +tctrl_process_response(struct tctrl_softc *sc) +{ + switch (sc->sc_op) { + case TS102_OP_RD_EXT_STATUS: { + sc->sc_ext_status = sc->sc_rspbuf[0] * 256 + sc->sc_rspbuf[1]; + break; + } + case TS102_OP_RD_EVENT_STATUS: { + unsigned int v = sc->sc_rspbuf[0] * 256 + sc->sc_rspbuf[1]; + if (v & TS102_EVENT_STATUS_SHUTDOWN_REQUEST) { + printf("%s: SHUTDOWN REQUEST!\n", sc->sc_dev.dv_xname); + } + if (v & TS102_EVENT_STATUS_VERY_LOW_POWER_WARNING) { + printf("%s: VERY LOW POWER WARNING!\n", sc->sc_dev.dv_xname); + } + if (v & TS102_EVENT_STATUS_LOW_POWER_WARNING) { + printf("%s: LOW POWER WARNING!\n", sc->sc_dev.dv_xname); + } + if (v & TS102_EVENT_STATUS_DC_STATUS_CHANGE) { + sc->sc_pending |= TCTRL_SEND_RD_EXT_STATUS; + printf("%s: main power %s\n", sc->sc_dev.dv_xname, + (sc->sc_ext_status & TS102_EXT_STATUS_MAIN_POWER_AVAILABLE) ? "removed" : "restored"); + } + if (v & TS102_EVENT_STATUS_LID_STATUS_CHANGE) { + sc->sc_pending |= TCTRL_SEND_RD_EXT_STATUS; + sc->sc_pending |= TCTRL_SEND_BITPORT; +#if 0 + printf("%s: lid %s\n", sc->sc_dev.dv_xname, + (sc->sc_ext_status & TS102_EXT_STATUS_LID_DOWN) ? "opened" : "closed"); +#endif + } + break; + } + case TS102_OP_CTL_BITPORT: + sc->sc_bitport = (sc->sc_rspbuf[0] & sc->sc_cmdbuf[1]) ^ sc->sc_cmdbuf[2]; + break; + default: + break; + } +} + +void +tadpole_powerdown(void) +{ + struct tctrl_softc *sc; + int i, s; + + if (tctrl_cd.cd_devs == NULL + || tctrl_cd.cd_ndevs == 0 + || tctrl_cd.cd_devs[0] == NULL) { + return; + } + + sc = (struct tctrl_softc *) tctrl_cd.cd_devs[0]; + s = splhigh(); + sc->sc_pending |= TCTRL_SEND_POWEROFF; + for (i = 0; i < 10000; i++) { + tctrl_intr(sc); + DELAY(1); + } + splx(s); +} + +void +tadpole_set_video(int enabled) +{ + struct tctrl_softc *sc; + int s; + + if (tctrl_cd.cd_devs == NULL + || tctrl_cd.cd_ndevs == 0 + || tctrl_cd.cd_devs[0] == NULL) { + return; + } + + sc = (struct tctrl_softc *) tctrl_cd.cd_devs[0]; + s = splhigh(); + if ((sc->sc_tft_on && !enabled) || (!sc->sc_tft_on && enabled)) { + sc->sc_tft_on = enabled; + if (sc->sc_ext_status & TS102_EXT_STATUS_LID_DOWN) { + splx(s); + return; + } + sc->sc_pending |= TCTRL_SEND_BITPORT; + tctrl_intr(sc); + } + splx(s); +} + +void +tctrl_write_data(sc, v) + struct tctrl_softc *sc; + u_int8_t v; +{ + unsigned int i; + + for (i = 0; i < 100; i++) { + if (sc->sc_regs->stat & TS102_UCTRL_STS_TXNF_STA) + break; + } + sc->sc_regs->data = v; +} + +u_int8_t +tctrl_read_data(sc) + struct tctrl_softc *sc; +{ + unsigned int i, v; + + for (i = 0; i < 100000; i++) { + if (sc->sc_regs->stat & TS102_UCTRL_STS_RXNE_STA) + break; + DELAY(1); + } + + v = sc->sc_regs->data; + sc->sc_regs->stat = TS102_UCTRL_STS_RXNE_STA; + return v; +} diff --git a/sys/arch/sparc/dev/tctrlvar.h b/sys/arch/sparc/dev/tctrlvar.h new file mode 100644 index 00000000000..e55067f6f1c --- /dev/null +++ b/sys/arch/sparc/dev/tctrlvar.h @@ -0,0 +1,45 @@ +/* $OpenBSD: tctrlvar.h,v 1.1 1999/09/07 02:58:50 jason Exp $ */ +/* $NetBSD: tctrlvar.h,v 1.1 1999/08/09 18:39:58 matt Exp $ */ + +/*- + * Copyright (c) 1998 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Matt Thomas. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _SPARC_DEV_TCTRLVAR_H +#define _SPARC_DEV_TCTRLVAR_H + +extern void tadpole_powerdown(void); +extern void tadpole_set_video(int enabled); + +#endif /* _SPARC_DEV_TCTRLVAR_H */ diff --git a/sys/arch/sparc/dev/ts102reg.h b/sys/arch/sparc/dev/ts102reg.h new file mode 100644 index 00000000000..3bd629c2b74 --- /dev/null +++ b/sys/arch/sparc/dev/ts102reg.h @@ -0,0 +1,322 @@ +/* $OpenBSD: ts102reg.h,v 1.1 1999/09/07 02:58:50 jason Exp $ */ +/* $NetBSD: ts102reg.h,v 1.2 1999/08/11 00:46:06 matt Exp $ */ + +/*- + * Copyright (c) 1998 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Matt Thomas. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _SPARC_DEV_TS102REG_H +#define _SPARC_DEV_TS102REG_H + +/* There are two separate register blocks within the TS102. The first + * gives access to PCMCIA card specific resources, and the second gives + * access to the microcontroller interface + */ +#define TS102_REG_CARD_A_INT 0x0000 /* Card A Interrupt Register */ +#define TS102_REG_CARD_A_STS 0x0004 /* Card A Status Register */ +#define TS102_REG_CARD_A_CTL 0x0008 /* Card A Control Register */ +#define TS102_REG_CARD_B_INT 0x0010 /* Card B Interrupt Register */ +#define TS102_REG_CARD_B_STS 0x0014 /* Card B Status Register */ +#define TS102_REG_CARD_B_CTL 0x0018 /* Card B Control Register */ + +struct uctrl_regs { + volatile u_int8_t intr; /* Microcontroller Interrupt Reg */ + volatile u_int8_t filler0[3]; + volatile u_int8_t data; /* Microcontroller Data Reg */ + volatile u_int8_t filler1[3]; + volatile u_int8_t stat; /* Microcontroller Status Reg */ + volatile u_int8_t filler2[3]; +}; + +/* TS102 Card Interrupt Register defintions. + * + * There is one 16-bit interrupt register for each card. Each register + * contains interrupt status (read) and clear (write) bits and an + * interrupt mask for each of the four interrupt sources. + * + * The request bit is the logical AND of the status and the mask bit, + * and indicated and an interrupt is being requested. The mask bits + * allow masking of individual interrupts. An interrupt is enabled when + * the mask is set to 1 and is clear by write a 1 to the associated + * request bit. + * + * The card interrupt register also contain the soft reset flag. + * Setting this bit to 1 will the SPARCbook 3 to be reset. + */ +#define TS102_CARD_INT_RQST_IRQ 0x0001 +#define TS102_CARD_INT_RQST_WP_STATUS_CHANGED 0x0002 +#define TS102_CARD_INT_RQST_BATTERY_STATUS_CHANGED 0x0004 +#define TS102_CARD_INT_RQST_CARDDETECT_STATUS_CHANGED 0x0008 +#define TS102_CARD_INT_STATUS_IRQ 0x0010 +#define TS102_CARD_INT_STATUS_WP_STATUS_CHANGED 0x0020 +#define TS102_CARD_INT_STATUS_BATTERY_STATUS_CHANGED 0x0040 +#define TS102_CARD_INT_STATUS_CARDDETECT_STATUS_CHANGED 0x0080 +#define TS102_CARD_INT_MASK_IRQ 0x0100 +#define TS102_CARD_INT_MASK_WP_STATUS 0x0200 +#define TS102_CARD_INT_MASK_BATTERY_STATUS 0x0400 +#define TS102_CARD_INT_MASK_CARDDETECT_STATUS 0x0800 +#define TS102_CARD_INT_SOFT_RESET 0x1000 + +/* TS102 Card Status Register definitions. The Card Status Register + * contains card status and control bit. + */ +#define TS102_CARD_STS_PRES 0x0001 /* Card Present (1) */ +#define TS102_CARD_STS_IO 0x0002 /* (1) I/O Card, (0) = Mem Card */ +#define TS102_CARD_STS_TYPE3 0x0004 /* Type-3 PCMCIA card (disk) */ +#define TS102_CARD_STS_VCC 0x0008 /* Vcc (0=5V, 1=3.3V) */ +#define TS102_CARD_STS_VPP1_MASK 0x0030 /* Programming Voltage Control2 */ +#define TS102_CARD_STS_VPP1_NC 0x0030 /* NC */ +#define TS102_CARD_STS_VPP1_VCC 0x0020 /* Vcc (3.3V or 5V) */ +#define TS102_CARD_STS_VPP1_VPP 0x0010 /* Vpp (12V) */ +#define TS102_CARD_STS_VPP1_0V 0x0000 /* 0V */ +#define TS102_CARD_STS_VPP2_MASK 0x00c0 /* Programming Voltage Control1 */ +#define TS102_CARD_STS_VPP2_NC 0x00c0 /* NC */ +#define TS102_CARD_STS_VPP2_VCC 0x0080 /* Vcc (3.3V or 5V) */ +#define TS102_CARD_STS_VPP2_VPP 0x0040 /* Vpp (12V) */ +#define TS102_CARD_STS_VPP2_0V 0x0000 /* 0V */ +#define TS102_CARD_STS_WP 0x0100 /* Write Protect (1) */ +#define TS102_CARD_STS_BVD_MASK 0x0600 /* Battery Voltage Detect */ +#define TS102_CARD_STS_BVD_GOOD 0x0600 /* Battery good */ +#define TS102_CARD_STS_BVD_LOW_OK 0x0400 /* Battery low, data OK */ +#define TS102_CARD_STS_BVD_LOW_SUSPECT1 0x0200 /* Battery low, data suspect */ +#define TS102_CARD_STS_BVD_LOW_SUSPECT0 0x0000 /* Battery low, data suspect */ +#define TS102_CARD_STS_LVL 0x0800 /* Level (1) / Edge */ +#define TS102_CARD_STS_RDY 0x1000 /* Ready (1) / Not Busy */ +#define TS102_CARD_STS_VCCEN 0x2000 /* Powered Up (0) */ +#define TS102_CARD_STS_RIEN 0x4000 /* Not Supported */ +#define TS102_CARD_STS_ACEN 0x8000 /* Access Enabled (1) */ + +/* TS102 Card Control Register definitions + */ +#define TS102_CARD_CTL_AA_MASK 0x0003 /* Attribute Address A[25:24] */ +#define TS102_CARD_CTL_IA_MASK 0x000c /* I/O Address A[25:24] */ +#define TS102_CARD_CTL_IA_BITPOS 2 /* */ +#define TS102_CARD_CTL_CES_MASK 0x0070 /* CE/address setup time */ +#define TS102_CARD_CTL_CES_BITPOS 4 /* n+1 clocks */ +#define TS102_CARD_CTL_OWE_MASK 0x0380 /* OE/WE width */ +#define TS102_CARD_CTL_OWE_BITPOS 7 /* n+2 clocks */ +#define TS102_CARD_CTL_CEH 0x0400 /* Chip enable hold time */ + /* (0) - 1 clock */ + /* (1) - 2 clocks */ +#define TS102_CARD_CTL_SBLE 0x0800 /* SBus little endian */ +#define TS102_CARD_CTL_PCMBE 0x1000 /* PCMCIA big endian */ +#define TS102_CARD_CTL_RAHD 0x2000 /* Read ahead enable */ +#define TS102_CARD_CTL_INCDIS 0x4000 /* Address increment disable */ +#define TS102_CARD_CTL_PWRD 0x8000 /* Power down */ + +/* Microcontroller Interrupt Register + */ +#define TS102_UCTRL_INT_TXE_REQ 0x01 /* transmit FIFO empty */ +#define TS102_UCTRL_INT_TXNF_REQ 0x02 /* transmit FIFO not full */ +#define TS102_UCTRL_INT_RXNE_REQ 0x04 /* receive FIFO not empty */ +#define TS102_UCTRL_INT_RXO_REQ 0x08 /* receive FIFO overflow */ +#define TS102_UCTRL_INT_TXE_MSK 0x10 /* transmit FIFO empty */ +#define TS102_UCTRL_INT_TXNF_MSK 0x20 /* transmit FIFO not full */ +#define TS102_UCTRL_INT_RXNE_MSK 0x40 /* receive FIFO not empty */ +#define TS102_UCTRL_INT_RXO_MSK 0x80 /* receive FIFO overflow */ + +/* TS102 Microcontroller Data Register (only 8 bits are significant). + */ +#define TS102_UCTRL_DATA_MASK 0xff + +/* TS102 Microcontroller Status Register. + * read 1 if asserted + * write 1 to clear + */ +#define TS102_UCTRL_STS_TXE_STA 0x01 /* transmit FIFO empty */ +#define TS102_UCTRL_STS_TXNF_STA 0x02 /* transmit FIFO not full */ +#define TS102_UCTRL_STS_RXNE_STA 0x04 /* receive FIFO not empty */ +#define TS102_UCTRL_STS_RXO_STA 0x08 /* receive FIFO overflow */ + +enum ts102_opcode { /* Argument Returned */ + TS102_OP_RD_SERIAL_NUM=0x01, /* none ack + 4 bytes */ + TS102_OP_RD_ETHER_ADDR=0x02, /* none ack + 6 bytes */ + TS102_OP_RD_HW_VERSION=0x03, /* none ack + 2 bytes */ + TS102_OP_RD_UCTLR_VERSION=0x04, /* none ack + 2 bytes */ + TS102_OP_RD_MAX_TEMP=0x05, /* none ack + 1 bytes */ + TS102_OP_RD_MIN_TEMP=0x07, /* none ack + 1 bytes */ + TS102_OP_RD_CURRENT_TEMP=0x06, /* none ack + 1 bytes */ + TS102_OP_RD_SYSTEM_VARIANT=0x08, /* none ack + 4 bytes */ + TS102_OP_RD_POWERON_CYCLES=0x09, /* none ack + 4 bytes */ + TS102_OP_RD_POWERON_SECONDS=0x0a, /* none ack + 4 bytes */ + TS102_OP_RD_RESET_STATUS=0x0b, /* none ack + 1 bytes */ +#define TS102_RESET_STATUS_RESERVED0 0x00 +#define TS102_RESET_STATUS_POWERON 0x01 +#define TS102_RESET_STATUS_KEYBOARD 0x02 +#define TS102_RESET_STATUS_WATCHDOG 0x03 +#define TS102_RESET_STATUS_TIMEOUT 0x04 +#define TS102_RESET_STATUS_SOFTWARE 0x05 +#define TS102_RESET_STATUS_BROWNOUT 0x06 +#define TS102_RESET_STATUS_RESERVED1 0x07 + TS102_OP_RD_EVENT_STATUS=0x0c, /* none ack + 2 bytes */ +#define TS102_EVENT_STATUS_SHUTDOWN_REQUEST 0x0001 +#define TS102_EVENT_STATUS_LOW_POWER_WARNING 0x0002 +#define TS102_EVENT_STATUS_VERY_LOW_POWER_WARNING 0x0004 +#define TS102_EVENT_STATUS_BATT_CHANGED 0x0008 +#define TS102_EVENT_STATUS_EXT_KEYBOARD_STATUS_CHANGE 0x0010 +#define TS102_EVENT_STATUS_EXT_MOUSE_STATUS_CHANGE 0x0020 +#define TS102_EVENT_STATUS_EXTERNAL_VGA_STATUS_CHANGE 0x0040 +#define TS102_EVENT_STATUS_LID_STATUS_CHANGE 0x0080 +#define TS102_EVENT_STATUS_MICROCONTROLLER_ERROR 0x0100 +#define TS102_EVENT_STATUS_RESERVED 0x0200 +#define TS102_EVENT_STATUS_EXT_BATT_STATUS_CHANGE 0x0400 +#define TS102_EVENT_STATUS_EXT_BATT_CHARGING_STATUS_CHANGE 0x0800 +#define TS102_EVENT_STATUS_EXT_BATT_LOW_POWER 0x1000 +#define TS102_EVENT_STATUS_DC_STATUS_CHANGE 0x2000 +#define TS102_EVENT_STATUS_CHARGING_STATUS_CHANGE 0x4000 +#define TS102_EVENT_STATUS_POWERON_BTN_PRESSED 0x8000 + TS102_OP_RD_REAL_TIME_CLK=0x0d, /* none ack + 7 bytes */ + TS102_OP_RD_EXT_VGA_PORT=0x0e, /* none ack + 1 bytes */ + TS102_OP_RD_UCTRL_ROM_CKSUM=0x0f, /* none ack + 2 bytes */ + TS102_OP_RD_ERROR_STATUS=0x10, /* none ack + 2 bytes */ +#define TS102_ERROR_STATUS_NO_ERROR 0x00 +#define TS102_ERROR_STATUS_COMMAND_ERROR 0x01 +#define TS102_ERROR_STATUS_EXECUTION_ERROR 0x02 +#define TS102_ERROR_STATUS_PHYSICAL_ERROR 0x04 + TS102_OP_RD_EXT_STATUS=0x11, /* none ack + 2 bytes */ +#define TS102_EXT_STATUS_MAIN_POWER_AVAILABLE 0x0001 +#define TS102_EXT_STATUS_INTERNAL_BATTERY_ATTACHED 0x0002 +#define TS102_EXT_STATUS_EXTERNAL_BATTERY_ATTACHED 0x0004 +#define TS102_EXT_STATUS_EXTERNAL_VGA_ATTACHED 0x0008 +#define TS102_EXT_STATUS_EXTERNAL_KEYBOARD_ATTACHED 0x0010 +#define TS102_EXT_STATUS_EXTERNAL_MOUSE_ATTACHED 0x0020 +#define TS102_EXT_STATUS_LID_DOWN 0x0040 +#define TS102_EXT_STATUS_INTERNAL_BATTERY_CHARGING 0x0080 +#define TS102_EXT_STATUS_EXTERNAL_BATTERY_CHARGING 0x0100 +#define TS102_EXT_STATUS_INTERNAL_BATTERY_DISCHARGING 0x0200 +#define TS102_EXT_STATUS_EXTERNAL_BATTERY_DISCHARGING 0x0400 + TS102_OP_RD_USER_CONFIG=0x12, /* none ack + 2 bytes */ + TS102_OP_RD_UCTRL_VLT=0x13, /* none ack + 1 bytes */ + TS102_OP_RD_INT_BATT_VLT=0x14, /* none ack + 1 bytes */ + TS102_OP_RD_DC_IN_VLT=0x15, /* none ack + 1 bytes */ + TS102_OP_RD_HORZ_PRT_VLT=0x16, /* none ack + 1 bytes */ + TS102_OP_RD_VERT_PTR_VLT=0x17, /* none ack + 1 bytes */ + TS102_OP_RD_INT_CHANGE_LEVEL=0x18, /* none ack + 1 bytes */ + TS102_OP_RD_EXT_CHARGE_LEVEL=0x19, /* none ack + 1 bytes */ + TS102_OP_RD_RTC_ALARM=0x1a, /* none ack + 7 bytes */ + TS102_OP_RD_EVENT_STATUS_NO_RESET=0x1b, /* none ack + 2 bytes */ + TS102_OP_RD_INT_KBD_LAYOUT=0x1c, /* none ack + 2 bytes */ + TS102_OP_RD_EXT_KBD_LAYOUT=0x1d, /* none ack + 2 bytes */ + TS102_OP_RD_EEPROM_STATUS=0x1e, /* none ack + 2 bytes */ +#define TS102_EEPROM_STATUS_FACTORY_AREA_CHECKSUM_FAIL 0x01 +#define TS102_EEPROM_STATUS_CONSUMER_AREA_CHECKSUM_FAIL 0x02 +#define TS102_EEPROM_STATUS_USER_AREA_CHECKSUM_FAIL 0x04 +#define TS102_EEPROM_STATUS_VPD_AREA_CHECKSUM_FAIL 0x08 + + /* Read/Write/Modify Commands + */ + TS102_OP_CTL_LCD=0x20, /* mask ack + 2 bytes */ +#define TS102_LCD_CAPS_LOCK 0x0001 +#define TS102_LCD_SCROLL_LOCK 0x0002 +#define TS102_LCD_NUMLOCK 0x0004 +#define TS102_LCD_DISK_ACTIVE 0x0008 +#define TS102_LCD_LAN_ACTIVE 0x0010 +#define TS102_LCD_WAN_ACTIVE 0x0020 +#define TS102_LCD_PCMCIA_ACTIVE 0x0040 +#define TS102_LCD_DC_OK 0x0080 +#define TS102_LCD_COMPOSE 0x0100 + TS102_OP_CTL_BITPORT=0x21, /* mask ack + 1 byte */ +#define TS102_BITPORT_TFTPWR 0x01 /* TFT power (low) */ +#define TS102_BITPORT_SYNCINVA 0x04 /* ext. monitor sync (low) */ +#define TS102_BITPORT_SYNCINVB 0x08 /* ext. monitor sync (low) */ +#define TS102_BITPORT_BP_DIS 0x10 /* no bootprom from pcmcia (high) */ + /* boot from pcmcia (low */ +#define TS102_BITPORT_ENCSYNC 0x20 /* enab composite sync (low) */ + TS102_OP_CTL_SPEAKER_VOLUME=0x23, /* mask ack + 1 byte */ + TS102_OP_CTL_TFT_BIRGHNESS=0x24, /* mask ack + 1 byte */ + TS102_OP_CTL_WATCHDOG=0x25, /* mask ack + 1 byte */ + TS102_OP_CTL_FCTRY_EEPROM=0x26, /* mask ack + 1 byte */ + TS102_OP_CTL_KDB_TIME_UNTL_RTP=0x28, /* mask ack + 1 byte */ + TS102_OP_CTL_KBD_TIME_BTWN_RPTS=0x29, /* mask ack + 1 byte */ + TS102_OP_CTL_TIMEZONE=0x2a, /* mask ack + 1 byte */ + TS102_OP_CTL_MARK_SPACE_RATIO=0x2b, /* mask ack + 1 byte */ + TS102_OP_CTL_DIAGNOSTIC_MODE=0x2e, /* mask ack + 1 byte */ +#define TS102_DIAGNOSTIC_MODE_CMD_DIAG_ON_LCD 0x01 +#define TS102_DIAGNOSTIC_MODE_KDB_MS_9600 0x02 + TS102_OP_CTL_SCREEN_CONTRAST=0x2f, /* mask ack + 1 byte */ + + /* Commands returning no status + */ + TS102_OP_CMD_RING_BELL=0x30, /* msb,lsb ack */ + TS102_OP_CMD_DIAGNOSTIC_STATUS=0x32, /* msb,lsb ack */ + TS102_OP_CMD_CLR_KEY_COMBO_TBL=0x33, /* none ack */ + TS102_OP_CMD_SOFTWARE_RESET=0x34, /* none ack */ + TS102_OP_CMD_SET_RTC=0x35, /* smhddmy ack */ + TS102_OP_CMD_RECAL_PTR=0x36, /* none ack */ + TS102_OP_CMD_SET_BELL_FREQ=0x37, /* msb,lsb ack */ + TS102_OP_CMD_SET_INT_BATT_RATE=0x39, /* charge-lvl ack */ + TS102_OP_CMD_SET_EXT_BATT_RATE=0x3a, /* charge-lvl ack */ + TS102_OP_CMD_SET_RTC_ALARM=0x3b, /* smhddmy ack */ + + /* Block transfer commands + */ + TS102_OP_BLK_RD_EEPROM=0x40, /* len off ack <data> */ + TS102_OP_BLK_WR_EEPROM=0x41, /* len off <data> ack */ + TS102_OP_BLK_WR_STATUS=0x42, /* len off <data> ack */ + TS102_OP_BLK_DEF_SPCL_CHAR=0x43, /* len off <data> ack */ +#define TS102_BLK_OFF_DEF_WAN1 0 +#define TS102_BLK_OFF_DEF_WAN2 1 +#define TS102_BLK_OFF_DEF_LAN1 2 +#define TS102_BLK_OFF_DEF_LAN2 3 +#define TS102_BLK_OFF_DEF_PCMCIA 4 +#define TS102_BLK_OFF_DEF_DC_GOOD 5 +#define TS102_BLK_OFF_DEF_BACKSLASH 6 + + /* Generic commands + */ + TS102_OP_GEN_DEF_KEY_COMBO_ENT=0x50, /* seq com-length ack */ + TS102_OP_GEN_DEF_STRING_TBL_ENT=0x51, /* str-code len <str> ack */ + TS102_OP_GEN_DEF_STS_CTRN_DISP=0x52, /* len <msg> ack */ + + /* Generic commands with optional status + */ + TS102_OP_GEN_STS_EMU_COMMAND=0x64, /* <command> ack */ + TS102_OP_GEN_STS_RD_EMU_REGISTER=0x65, /* reg ack + 1 byte */ + TS102_OP_GEN_STS_WR_EMU_REGISTER=0x66, /* reg,val ack */ + TS102_OP_GEN_STS_RD_EMU_RAM=0x67, /* addr ack + 1 byte */ + TS102_OP_GEN_STS_WR_EMU_RAM=0x68, /* addr,val ack */ + TS102_OP_GEN_STS_RD_BQ_REGISTER=0x69, /* reg ack + 1 byte */ + TS102_OP_GEN_STS_WR_BQ_REGISTER=0x6a, /* reg,val ack */ + + /* Administration commands + */ + TS102_OP_ADMIN_SET_USER_PASS=0x70, /* len <pass> ack */ + TS102_OP_ADMIN_VRFY_USER_PASS=0x71, /* len <pass> ack + status */ + TS102_OP_ADMIN_GET_SYSTEM_PASS=0x72, /* none ack + <7bytekey> */ + TS102_OP_ADMIN_VRFY_SYSTEM_PASS=0x73, /* len <pass> ack + status */ + TS102_OP_ADMIN_POWER_OFF=0x82, /* len <pass> none */ + TS102_OP_ADMIN_POWER_RESTART=0x83, /* msb,xx,lsb none */ +}; + +#endif /* _SPARC_DEV_TS102REG_H */ |