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Diffstat (limited to 'sys/arch/sparc64/include/lock.h')
-rw-r--r--sys/arch/sparc64/include/lock.h47
1 files changed, 1 insertions, 46 deletions
diff --git a/sys/arch/sparc64/include/lock.h b/sys/arch/sparc64/include/lock.h
index 5b3e63db804..ef6820871c7 100644
--- a/sys/arch/sparc64/include/lock.h
+++ b/sys/arch/sparc64/include/lock.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: lock.h,v 1.11 2017/05/27 15:11:03 mpi Exp $ */
+/* $OpenBSD: lock.h,v 1.12 2017/05/29 14:19:50 mpi Exp $ */
/*
* Copyright (c) 2012 Mark Kettenis <kettenis@openbsd.org>
*
@@ -18,49 +18,4 @@
#ifndef _MACHINE_LOCK_H_
#define _MACHINE_LOCK_H_
-#ifdef _KERNEL
-
-/*
- * On processors with multiple threads we force a thread switch.
- *
- * On UltraSPARC T2 and its successors, the optimal way to do this
- * seems to be to do three nop reads of %ccr. This works on
- * UltraSPARC T1 as well, even though three nop casx operations seem
- * to be slightly more optimal. Since these instructions are
- * effectively nops, executing them on earlier non-CMT processors is
- * harmless, so we make this the default.
- *
- * On SPARC T4 and later, we can use the processor-specific pause
- * instruction.
- *
- * On SPARC64 VI and its successors we execute the processor-specific
- * sleep instruction.
- */
-#define SPINLOCK_SPIN_HOOK \
-do { \
- __asm volatile( \
- "999: rd %%ccr, %%g0 \n" \
- " rd %%ccr, %%g0 \n" \
- " rd %%ccr, %%g0 \n" \
- " .section .sun4v_pause_patch, \"ax\" \n" \
- " .word 999b \n" \
- " .word 0xb7802080 ! pause 128 \n" \
- " .word 999b + 4 \n" \
- " nop \n" \
- " .word 999b + 8 \n" \
- " nop \n" \
- " .previous \n" \
- " .section .sun4u_mtp_patch, \"ax\" \n" \
- " .word 999b \n" \
- " .word 0x81b01060 ! sleep \n" \
- " .word 999b + 4 \n" \
- " nop \n" \
- " .word 999b + 8 \n" \
- " nop \n" \
- " .previous \n" \
- : : : "memory"); \
-} while (0)
-
-
-#endif /* _KERNEL */
#endif /* _MACHINE_LOCK_H_ */