diff options
Diffstat (limited to 'sys/arch/sparc64/include')
| -rw-r--r-- | sys/arch/sparc64/include/bsd_openprom.h | 327 | ||||
| -rw-r--r-- | sys/arch/sparc64/include/pmap.h | 188 | ||||
| -rw-r--r-- | sys/arch/sparc64/include/pte.h | 236 |
3 files changed, 751 insertions, 0 deletions
diff --git a/sys/arch/sparc64/include/bsd_openprom.h b/sys/arch/sparc64/include/bsd_openprom.h new file mode 100644 index 00000000000..ffd7d61d1c4 --- /dev/null +++ b/sys/arch/sparc64/include/bsd_openprom.h @@ -0,0 +1,327 @@ +/* $NetBSD: bsd_openprom.h,v 1.2 2000/03/13 23:52:34 soren Exp $ */ + +/* + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Jan-Simon Pendry. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)bsd_openprom.h 8.1 (Berkeley) 6/11/93 + */ + +/* + * Sun4m support by Aaron Brown, Harvard University. + * Changes Copyright (c) 1995 The President and Fellows of Harvard College. + * All rights reserved. + */ + +/* + * This file defines the interface between the kernel and the Openboot PROM. + * N.B.: this has been tested only on interface versions 0 and 2 (we have + * never seen interface version 1). + */ + +/* + * The v0 interface tells us what virtual memory to scan to avoid PMEG + * conflicts, but the v2 interface fails to do so, and we must `magically' + * know where the OPENPROM lives in virtual space. + */ +#define OPENPROM_STARTVADDR 0xffd00000 +#define OPENPROM_ENDVADDR 0xfff00000 + +#define OPENPROM_MAGIC 0x10010407 + +/* + * Version 0 PROM vector device operations (collected here to emphasise that + * they are deprecated). Open and close are obvious. Read and write are + * segregated according to the device type (block, network, or character); + * this is unnecessary and was eliminated from the v2 device operations, but + * we are stuck with it. + * + * Seek is probably only useful on tape devices, since the only character + * devices are the serial ports. + * + * Note that a v0 device name is always exactly two characters ("sd", "le", + * and so forth). + */ +struct v0devops { + int (*v0_open) __P((char *dev)); + int (*v0_close) __P((int d)); + int (*v0_rbdev) __P((int d, int nblks, int blkno, void *addr)); + int (*v0_wbdev) __P((int d, int nblks, int blkno, void *addr)); + int (*v0_wnet) __P((int d, int nbytes, void *addr)); + int (*v0_rnet) __P((int d, int nbytes, void *addr)); + int (*v0_rcdev) __P((int d, int nbytes, int, void *addr)); + int (*v0_wcdev) __P((int d, int nbytes, int, void *addr)); + int (*v0_seek) __P((int d, long offset, int whence)); +}; + +/* + * Version 2 device operations. Open takes a device `path' such as + * /sbus/le@0,c00000,0 or /sbus/esp@.../sd@0,0, which means it can open + * anything anywhere, without any magic translation. + * + * The memory allocator and map functions are included here even though + * they relate only indirectly to devices (e.g., mmap is good for mapping + * device memory, and drivers need to allocate space in which to record + * the device state). + */ +struct v2devops { + /* + * Convert an `instance handle' (acquired through v2_open()) to + * a `package handle', a.k.a. a `node'. + */ + int (*v2_fd_phandle) __P((int d)); + + /* Memory allocation and release. */ + void *(*v2_malloc) __P((caddr_t va, u_int sz)); + void (*v2_free) __P((caddr_t va, u_int sz)); + + /* Device memory mapper. */ + caddr_t (*v2_mmap) __P((caddr_t va, int asi, u_int pa, u_int sz)); + void (*v2_munmap) __P((caddr_t va, u_int sz)); + + /* Device open, close, etc. */ + int (*v2_open) __P((char *devpath)); + void (*v2_close) __P((int d)); + int (*v2_read) __P((int d, void *buf, int nbytes)); + int (*v2_write) __P((int d, void *buf, int nbytes)); + void (*v2_seek) __P((int d, int hi, int lo)); + + void (*v2_chain) __P((void)); /* ??? */ + void (*v2_release) __P((void)); /* ??? */ +}; + +/* + * The v0 interface describes memory regions with these linked lists. + * (The !$&@#+ v2 interface reformats these as properties, so that we + * have to extract them into local temporary memory and reinterpret them.) + */ +struct v0mlist { + struct v0mlist *next; + caddr_t addr; + u_int nbytes; +}; + +/* + * V0 gives us three memory lists: Total physical memory, VM reserved to + * the PROM, and available physical memory (which, presumably, is just the + * total minus any pages mapped in the PROM's VM region). We can find the + * reserved PMEGs by scanning the taken VM. Unfortunately, the V2 prom + * forgot to provide taken VM, and we are stuck with scanning ``magic'' + * addresses. + */ +struct v0mem { + struct v0mlist **v0_phystot; /* physical memory */ + struct v0mlist **v0_vmprom; /* VM used by PROM */ + struct v0mlist **v0_physavail; /* available physical memory */ +}; + +/* + * The version 0 PROM breaks up the string given to the boot command and + * leaves the decoded version behind. + */ +struct v0bootargs { + char *ba_argv[8]; /* argv format for boot string */ + char ba_args[100]; /* string space */ + char ba_bootdev[2]; /* e.g., "sd" for `b sd(...' */ + int ba_ctlr; /* controller # */ + int ba_unit; /* unit # */ + int ba_part; /* partition # */ + char *ba_kernel; /* kernel to boot, e.g., "vmunix" */ + void *ba_spare0; /* not decoded here XXX */ +}; + +/* + * The version 2 PROM interface uses the more general, if less convenient, + * approach of passing the boot strings unchanged. We also get open file + * numbers for stdin and stdout (keyboard and screen, or whatever), for use + * with the v2 device ops. + */ +struct v2bootargs { + char **v2_bootpath; /* V2: Path to boot device */ + char **v2_bootargs; /* V2: Boot args */ + int *v2_fd0; /* V2: Stdin descriptor */ + int *v2_fd1; /* V2: Stdout descriptor */ +}; + +/* + * The following structure defines the primary PROM vector interface. + * The Boot PROM hands the kernel a pointer to this structure in %o0. + * There are numerous substructures defined below. + */ +struct promvec { + /* Version numbers. */ + u_int pv_magic; /* Magic number */ + u_int pv_romvec_vers; /* interface version (0, 2) */ + u_int pv_plugin_vers; /* ??? */ + u_int pv_printrev; /* PROM rev # (* 10, e.g 1.9 = 19) */ + + /* Version 0 memory descriptors (see below). */ + struct v0mem pv_v0mem; /* V0: Memory description lists. */ + + /* Node operations (see below). */ + struct nodeops *pv_nodeops; /* node functions */ + + char **pv_bootstr; /* Boot command, eg sd(0,0,0)vmunix */ + + struct v0devops pv_v0devops; /* V0: device ops */ + + /* + * PROMDEV_* cookies. I fear these may vanish in lieu of fd0/fd1 + * (see below) in future PROMs, but for now they work fine. + */ + char *pv_stdin; /* stdin cookie */ + char *pv_stdout; /* stdout cookie */ +#define PROMDEV_KBD 0 /* input from keyboard */ +#define PROMDEV_SCREEN 0 /* output to screen */ +#define PROMDEV_TTYA 1 /* in/out to ttya */ +#define PROMDEV_TTYB 2 /* in/out to ttyb */ + + /* Blocking getchar/putchar. NOT REENTRANT! (grr) */ + int (*pv_getchar) __P((void)); + void (*pv_putchar) __P((int ch)); + + /* Non-blocking variants that return -1 on error. */ + int (*pv_nbgetchar) __P((void)); + int (*pv_nbputchar) __P((int ch)); + + /* Put counted string (can be very slow). */ + void (*pv_putstr) __P((char *str, int len)); + + /* Miscellany. */ + void (*pv_reboot) __P((char *bootstr)); + void (*pv_printf) __P((const char *fmt, ...)); + void (*pv_abort) __P((void)); /* L1-A abort */ + int *pv_ticks; /* Ticks since last reset */ + void (*pv_halt) __P((void)) __attribute__((noreturn));/* Halt! */ + void (**pv_synchook) __P((void)); /* "sync" command hook */ + + /* + * This eval's a FORTH string. Unfortunately, its interface + * changed between V0 and V2, which gave us much pain. + */ + union { + void (*v0_eval) __P((int len, char *str)); + void (*v2_eval) __P((char *str)); + } pv_fortheval; + + struct v0bootargs **pv_v0bootargs; /* V0: Boot args */ + + /* Extract Ethernet address from network device. */ + u_int (*pv_enaddr) __P((int d, char *enaddr)); + + struct v2bootargs pv_v2bootargs; /* V2: Boot args + std in/out */ + struct v2devops pv_v2devops; /* V2: device operations */ + + int pv_spare[15]; + + /* + * The following is machine-dependent. + * + * The sun4c needs a PROM function to set a PMEG for another + * context, so that the kernel can map itself in all contexts. + * It is not possible simply to set the context register, because + * contexts 1 through N may have invalid translations for the + * current program counter. The hardware has a mode in which + * all memory references go to the PROM, so the PROM can do it + * easily. + */ + void (*pv_setctxt) __P((int ctxt, caddr_t va, int pmeg)); +#if defined(SUN4M) && defined(notyet) + /* + * The following are V3 ROM functions to handle MP machines in the + * Sun4m series. They have undefined results when run on a uniprocessor! + */ + int (*pv_v3cpustart) __P((u_int module, u_int ctxtbl, + int context, caddr_t pc)); + int (*pv_v3cpustop) __P((u_int module)); + int (*pv_v3cpuidle) __P((u_int module)); + int (*pv_v3cpuresume) __P((u_int module)); +#endif +}; + +/* + * In addition to the global stuff defined in the PROM vectors above, + * the PROM has quite a collection of `nodes'. A node is described by + * an integer---these seem to be internal pointers, actually---and the + * nodes are arranged into an N-ary tree. Each node implements a fixed + * set of functions, as described below. The first two deal with the tree + * structure, allowing traversals in either breadth- or depth-first fashion. + * The rest deal with `properties'. + * + * A node property is simply a name/value pair. The names are C strings + * (NUL-terminated); the values are arbitrary byte strings (counted strings). + * Many values are really just C strings. Sometimes these are NUL-terminated, + * sometimes not, depending on the interface version; v0 seems to terminate + * and v2 not. Many others are simply integers stored as four bytes in + * machine order: you just get them and go. The third popular format is + * an `address', which is made up of one or more sets of three integers + * as defined below. + * + * N.B.: for the `next' functions, next(0) = first, and next(last) = 0. + * Whoever designed this part had good taste. On the other hand, these + * operation vectors are global, rather than per-node, yet the pointers + * are not in the openprom vectors but rather found by indirection from + * there. So the taste balances out. + */ +struct openprom_addr { + int oa_space; /* address space (may be relative) */ + u_int oa_base; /* address within space */ + u_int oa_size; /* extent (number of bytes) */ +}; + +struct nodeops { + /* + * Tree traversal. + */ + int (*no_nextnode) __P((int node)); /* next(node) */ + int (*no_child) __P((int node)); /* first child */ + + /* + * Property functions. Proper use of getprop requires calling + * proplen first to make sure it fits. Kind of a pain, but no + * doubt more convenient for the PROM coder. + */ + int (*no_proplen) __P((int node, caddr_t name)); + int (*no_getprop) __P((int node, caddr_t name, caddr_t val)); + int (*no_setprop) __P((int node, caddr_t name, caddr_t val, + int len)); + caddr_t (*no_nextprop) __P((int node, caddr_t name)); +}; + +void romhalt __P((void)) + __attribute__((__noreturn__)); +void romboot __P((char *)) + __attribute__((__noreturn__)); + +extern struct promvec *promvec; diff --git a/sys/arch/sparc64/include/pmap.h b/sys/arch/sparc64/include/pmap.h new file mode 100644 index 00000000000..1032af946e2 --- /dev/null +++ b/sys/arch/sparc64/include/pmap.h @@ -0,0 +1,188 @@ +/* $NetBSD: pmap.h,v 1.16 2001/04/22 23:19:30 thorpej Exp $ */ + +/*- + * Copyright (C) 1995, 1996 Wolfgang Solfrank. + * Copyright (C) 1995, 1996 TooLs GmbH. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by TooLs GmbH. + * 4. The name of TooLs GmbH may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE_PMAP_H_ +#define _MACHINE_PMAP_H_ + +#ifndef _LOCORE +#include <machine/pte.h> +#include <sys/queue.h> +#endif + +/* + * This scheme uses 2-level page tables. + * + * While we're still in 32-bit mode we do the following: + * + * offset: 13 bits + * 1st level: 1024 64-bit TTEs in an 8K page for 10 bits + * 2nd level: 512 32-bit pointers in the pmap for 9 bits + * ------- + * total: 32 bits + * + * In 64-bit mode the Spitfire and Blackbird CPUs support only + * 44-bit virtual addresses. All addresses between + * 0x0000 07ff ffff ffff and 0xffff f800 0000 0000 are in the + * "VA hole" and trap, so we don't have to track them. However, + * we do need to keep them in mind during PT walking. If they + * ever change the size of the address "hole" we need to rework + * all the page table handling. + * + * offset: 13 bits + * 1st level: 1024 64-bit TTEs in an 8K page for 10 bits + * 2nd level: 1024 64-bit pointers in an 8K page for 10 bits + * 3rd level: 1024 64-bit pointers in the segmap for 10 bits + * ------- + * total: 43 bits + * + * Of course, this means for 32-bit spaces we always have a (practically) + * wasted page for the segmap (only one entry used) and half a page wasted + * for the page directory. We still have need of one extra bit 8^(. + */ + +#define HOLESHIFT (43) + +#define PTSZ (NBPG/8) +#define PDSZ (PTSZ) +#define STSZ (PTSZ) + +#define PTSHIFT (13) +#define PDSHIFT (10+PTSHIFT) +#define STSHIFT (10+PDSHIFT) + +#define PTMASK (PTSZ-1) +#define PDMASK (PDSZ-1) +#define STMASK (STSZ-1) + +#ifndef _LOCORE + +/* + * Support for big page sizes. This maps the page size to the + * page bits. + */ +struct page_size_map { + u_int64_t mask; + u_int64_t code; +#ifdef DEBUG + u_int64_t use; +#endif +}; +extern struct page_size_map page_size_map[]; + +/* + * Pmap stuff + */ + +#define va_to_seg(v) (int)((((paddr_t)(v))>>STSHIFT)&STMASK) +#define va_to_dir(v) (int)((((paddr_t)(v))>>PDSHIFT)&PDMASK) +#define va_to_pte(v) (int)((((paddr_t)(v))>>PTSHIFT)&PTMASK) + +struct pmap { + int pm_ctx; /* Current context */ + int pm_refs; /* ref count */ + /* + * This contains 64-bit pointers to pages that contain + * 1024 64-bit pointers to page tables. All addresses + * are physical. + * + * !!! Only touch this through pseg_get() and pseg_set() !!! + */ + paddr_t pm_physaddr; /* physical address of pm_segs */ + int64_t *pm_segs; + struct simplelock pm_lock; +}; + +/* + * This comes from the PROM and is used to map prom entries. + */ +struct prom_map { + u_int64_t vstart; + u_int64_t vsize; + u_int64_t tte; +}; + +#define PMAP_NC 0x001 /* Set the E bit in the page */ +#define PMAP_NVC 0x002 /* Don't enable the virtual cache */ +#define PMAP_LITTLE 0x004 /* Map in little endian mode */ +/* Large page size hints -- we really should use another param to pmap_enter() */ +#define PMAP_8K 0x000 +#define PMAP_64K 0x008 /* Use 64K page */ +#define PMAP_512K 0x010 +#define PMAP_4M 0x018 +#define PMAP_SZ_TO_TTE(x) (((x)&0x018)<<58) +/* If these bits are different in va's to the same PA then there is an aliasing in the d$ */ +#define VA_ALIAS_MASK (1<<14) + +typedef struct pmap *pmap_t; + +/* + * Encode IO space for pmap_enter() + * + * Since sun4u machines don't have separate IO spaces, this is a noop. + */ +#define PMAP_IOENC(io) 0 + +#ifdef _KERNEL +extern struct pmap kernel_pmap_; +#define pmap_kernel() (&kernel_pmap_) + +int pmap_count_res __P((pmap_t pmap)); +/* int pmap_change_wiring __P((pmap_t pm, vaddr_t va, boolean_t wired)); */ +#define pmap_resident_count(pm) pmap_count_res((pm)) +#define pmap_from_phys_address(x,f) ((x)>>PGSHIFT) +#define pmap_phys_address(x) ((((paddr_t)(x))<<PGSHIFT)|PMAP_NC) +#define pmap_update() /* nothing (yet) */ + +void pmap_bootstrap __P((u_long kernelstart, u_long kernelend, u_int numctx)); +/* make sure all page mappings are modulo 16K to prevent d$ aliasing */ +#define PMAP_PREFER(pa, va) (*(va)+=(((*(va))^(pa))&(1<<(PGSHIFT+1)))) + +#define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */ + +/* SPARC specific? */ +void pmap_redzone __P((void)); +int pmap_dumpsize __P((void)); +int pmap_dumpmmu __P((int (*)__P((dev_t, daddr_t, caddr_t, size_t)), + daddr_t)); +int pmap_pa_exists __P((paddr_t)); +struct proc; +void switchexit __P((struct proc *)); + +/* SPARC64 specific */ +int ctx_alloc __P((struct pmap*)); +void ctx_free __P((struct pmap*)); + + +#endif /* _KERNEL */ +#endif /* _LOCORE */ +#endif /* _MACHINE_PMAP_H_ */ diff --git a/sys/arch/sparc64/include/pte.h b/sys/arch/sparc64/include/pte.h new file mode 100644 index 00000000000..08bda84ca39 --- /dev/null +++ b/sys/arch/sparc64/include/pte.h @@ -0,0 +1,236 @@ +/* $NetBSD: pte.h,v 1.7 2001/07/31 06:55:46 eeh Exp $ */ + +/* + * Copyright (c) 1996-1999 Eduardo Horvath + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +/* + * Address translation works as follows: + * + ** + * For sun4u: + * + * Take your pick; it's all S/W anyway. We'll start by emulating a sun4. + * Oh, here's the sun4u TTE for reference: + * + * struct sun4u_tte { + * u_int64 tag_g:1, (global flag) + * tag_ctxt:15, (context for mapping) + * tag_unassigned:6, + * tag_va:42; (virtual address bits<64:22>) + * u_int64 data_v:1, (valid bit) + * data_size:2, (page size [8K*8**<SIZE>]) + * data_nfo:1, (no-fault only) + * data_ie:1, (invert endianness [inefficient]) + * data_soft2:2, (reserved for S/W) + * data_pa:36, (physical address) + * data_soft:6, (reserved for S/W) + * data_lock:1, (lock into TLB) + * data_cacheable:2, (cacheability control) + * data_e:1, (explicit accesses only) + * data_priv:1, (privileged page) + * data_w:1, (writeable) + * data_g:1; (same as tag_g) + * }; + */ + +/* virtual address to virtual page number */ +#define VA_SUN4U_VPG(va) (((int)(va) >> 13) & 31) + +/* virtual address to offset within page */ +#define VA_SUN4U_OFF(va) (((int)(va)) & 0x1FFF) + +/* When we go to 64-bit VAs we need to handle the hole */ +#define VA_VPG(va) VA_SUN4U_VPG(va) +#define VA_OFF(va) VA_SUN4U_OFF(va) + +#define PG_SHIFT4U 13 +#define MMU_PAGE_ALIGN 8192 + +/* If you know where a tte is in the tsb, how do you find its va? */ +#define TSBVA(i) ((tsb[(i)].tag.f.tag_va<<22)|(((i)<<13)&0x3ff000)) + +#ifndef _LOCORE +/* + * This is the spitfire TTE. + * + * We could use bitmasks and shifts to construct this if + * we had a 64-bit compiler w/64-bit longs. Otherwise it's + * a real pain to do this in C. + */ +#if 0 +/* We don't use bitfeilds anyway. */ +struct sun4u_tag_fields { + u_int64_t tag_g:1, /* global flag */ + tag_ctxt:15, /* context for mapping */ + tag_unassigned:6, + tag_va:42; /* virtual address bits<64:22> */ +}; +union sun4u_tag { struct sun4u_tag_fields f; int64_t tag; }; +struct sun4u_data_fields { + u_int64_t data_v:1, /* valid bit */ + data_size:2, /* page size [8K*8**<SIZE>] */ + data_nfo:1, /* no-fault only */ + data_ie:1, /* invert endianness [inefficient] */ + data_soft2:2, /* reserved for S/W */ + data_pa:36, /* physical address */ + data_accessed:1,/* S/W accessed bit */ + data_modified:1,/* S/W modified bit */ + data_realw:1, /* S/W real writable bit (to manage modified) */ + data_tsblock:1, /* S/W TSB locked entry */ + data_exec:1, /* S/W Executable */ + data_onlyexec:1,/* S/W Executable only */ + data_lock:1, /* lock into TLB */ + data_cacheable:2, /* cacheability control */ + data_e:1, /* explicit accesses only */ + data_priv:1, /* privileged page */ + data_w:1, /* writeable */ + data_g:1; /* same as tag_g */ +}; +union sun4u_data { struct sun4u_data_fields f; int64_t data; }; +struct sun4u_tte { + union sun4u_tag tag; + union sun4u_data data; +}; +#else +struct sun4u_tte { + int64_t tag; + int64_t data; +}; +#endif +typedef struct sun4u_tte pte_t; + +/* Assembly routine to flush a mapping */ +extern void tlb_flush_pte __P((vaddr_t addr, int ctx)); +extern void tlb_flush_ctx __P((int ctx)); + +#endif /* _LOCORE */ + +/* TSB tag masks */ +#define CTX_MASK ((1<<13)-1) +#define TSB_TAG_CTX_SHIFT 48 +#define TSB_TAG_VA_SHIFT 22 +#define TSB_TAG_G 0x8000000000000000LL + +#define TSB_TAG_CTX(t) ((((int64_t)(t))>>TSB_TAG_CTX_SHIFT)&CTX_MASK) +#define TSB_TAG_VA(t) ((((int64_t)(t))<<TSB_TAG_VA_SHIFT)) +#define TSB_TAG(g,ctx,va) ((((u_int64_t)((g)!=0))<<63)|(((u_int64_t)(ctx)&CTX_MASK)<<TSB_TAG_CTX_SHIFT)|(((u_int64_t)va)>>TSB_TAG_VA_SHIFT)) + +/* Page sizes */ +#define PGSZ_8K 0 +#define PGSZ_64K 1 +#define PGSZ_512K 2 +#define PGSZ_4M 3 + +#define PGSZ_SHIFT 61 + +/* + * Why couldn't Sun pick better page sizes? + * + * Page sizes are 2**(12+(3*sz)), except for 8K which + * is 2**12+1 instead of 2**12. + */ +#define PG_SZ(s) (1<<(12+(s?(3*s):1))) +#define TLB_SZ(s) (((uint64_t)(s))<<PGSZ_SHIFT) + +/* TLB data masks */ +#define TLB_V 0x8000000000000000LL +#define TLB_8K TLB_SZ(PGSZ_8K) +#define TLB_64K TLB_SZ(PGSZ_64K) +#define TLB_512K TLB_SZ(PGSZ_512K) +#define TLB_4M TLB_SZ(PGSZ_4M) +#define TLB_SZ_MASK 0x6000000000000000LL +#define TLB_NFO 0x1000000000000000LL +#define TLB_IE 0x0800000000000000LL +#define TLB_SOFT2_MASK 0x07fe000000000000LL +#define TLB_DIAG_MASK 0x0001fe0000000000LL +#define TLB_PA_MASK 0x000001ffffffe000LL +#define TLB_SOFT_MASK 0x0000000000001f80LL +/* S/W bits */ +/* Access & TSB locked bits are swapped so I can set access w/one insn */ +/* #define TLB_ACCESS 0x0000000000001000LL */ +#define TLB_ACCESS 0x0000000000000200LL +#define TLB_MODIFY 0x0000000000000800LL +#define TLB_REAL_W 0x0000000000000400LL +/* #define TLB_TSB_LOCK 0x0000000000000200LL */ +#define TLB_TSB_LOCK 0x0000000000001000LL +#define TLB_EXEC 0x0000000000000100LL +#define TLB_EXEC_ONLY 0x0000000000000080LL +/* H/W bits */ +#define TLB_L 0x0000000000000040LL +#define TLB_CACHE_MASK 0x0000000000000030LL +#define TLB_CP 0x0000000000000020LL +#define TLB_CV 0x0000000000000010LL +#define TLB_E 0x0000000000000008LL +#define TLB_P 0x0000000000000004LL +#define TLB_W 0x0000000000000002LL +#define TLB_G 0x0000000000000001LL + +/* + * The following bits are used by locore so they should + * be duplicates of the above w/o the "long long" + */ +/* S/W bits */ +/* #define TTE_ACCESS 0x0000000000001000 */ +#define TTE_ACCESS 0x0000000000000200 +#define TTE_MODIFY 0x0000000000000800 +#define TTE_REAL_W 0x0000000000000400 +/* #define TTE_TSB_LOCK 0x0000000000000200 */ +#define TTE_TSB_LOCK 0x0000000000001000 +#define TTE_EXEC 0x0000000000000100 +#define TTE_EXEC_ONLY 0x0000000000000080 +/* H/W bits */ +#define TTE_L 0x0000000000000040 +#define TTE_CACHE_MASK 0x0000000000000030 +#define TTE_CP 0x0000000000000020 +#define TTE_CV 0x0000000000000010 +#define TTE_E 0x0000000000000008 +#define TTE_P 0x0000000000000004 +#define TTE_W 0x0000000000000002 +#define TTE_G 0x0000000000000001 + +#define TTE_DATA_BITS "\177\20" \ + "b\77V\0" "f\75\2SIZE\0" "b\77V\0" "f\75\2SIZE\0" \ + "=\0008K\0" "=\00164K\0" "=\002512K\0" "=\0034M\0" \ + "b\74NFO\0" "b\73IE\0" "f\62\10SOFT2\0" \ + "f\51\10DIAG\0" "f\15\33PA<40:13>\0" "f\7\5SOFT\0" \ + "b\6L\0" "b\5CP\0" "b\4CV\0" \ + "b\3E\0" "b\2P\0" "b\1W\0" "b\0G\0" + +#define TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \ +(((valid)?TLB_V:0LL)|TLB_SZ(sz)|(((u_int64_t)(pa))&TLB_PA_MASK)|\ +((cache)?((aliased)?TLB_CP:TLB_CACHE_MASK):TLB_E)|\ +((priv)?TLB_P:0LL)|((write)?TLB_W:0LL)|((g)?TLB_G:0LL)|((ie)?TLB_IE:0LL)) + +#define MMU_CACHE_VIRT 0x3 +#define MMU_CACHE_PHYS 0x2 +#define MMU_CACHE_NONE 0x0 + +/* This needs to be updated for sun4u IOMMUs */ +/* + * IOMMU PTE bits. + */ +#define IOPTE_PPN_MASK 0x07ffff00 +#define IOPTE_PPN_SHIFT 8 +#define IOPTE_RSVD 0x000000f1 +#define IOPTE_WRITE 0x00000004 +#define IOPTE_VALID 0x00000002 |