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-rw-r--r--sys/arch/mips64/include/cpu.h7
-rw-r--r--sys/arch/mips64/include/db_machdep.h12
-rw-r--r--sys/arch/mips64/mips64/db_machdep.c71
-rw-r--r--sys/arch/mips64/mips64/mips64_machdep.c62
4 files changed, 72 insertions, 80 deletions
diff --git a/sys/arch/mips64/include/cpu.h b/sys/arch/mips64/include/cpu.h
index 138675e4528..dadb80c45e6 100644
--- a/sys/arch/mips64/include/cpu.h
+++ b/sys/arch/mips64/include/cpu.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpu.h,v 1.96 2014/03/09 10:12:17 miod Exp $ */
+/* $OpenBSD: cpu.h,v 1.97 2014/03/21 23:05:41 miod Exp $ */
/*-
* Copyright (c) 1992, 1993
@@ -428,6 +428,11 @@ int guarded_write_4(paddr_t, uint32_t);
void MipsFPTrap(struct trap_frame *);
register_t MipsEmulateBranch(struct trap_frame *, vaddr_t, uint32_t, uint32_t);
+int classify_insn(uint32_t);
+#define INSNCLASS_NEUTRAL 0
+#define INSNCLASS_CALL 1
+#define INSNCLASS_BRANCH 2
+
/*
* Low level access routines to CPU registers
*/
diff --git a/sys/arch/mips64/include/db_machdep.h b/sys/arch/mips64/include/db_machdep.h
index 3f235c55fd5..b707ac376fe 100644
--- a/sys/arch/mips64/include/db_machdep.h
+++ b/sys/arch/mips64/include/db_machdep.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: db_machdep.h,v 1.14 2014/03/16 20:31:46 guenther Exp $ */
+/* $OpenBSD: db_machdep.h,v 1.15 2014/03/21 23:05:41 miod Exp $ */
/*
* Copyright (c) 1998-2003 Opsycon AB (www.opsycon.se)
@@ -58,15 +58,11 @@ db_addr_t next_instr_address(db_addr_t, boolean_t);
/*
* Test of instructions to see class.
*/
-#define IT_CALL 0x01
-#define IT_BRANCH 0x02
-
-#define inst_branch(i) (db_inst_type(i) == IT_BRANCH)
+#define inst_branch(i) (classify_insn(i) == INSNCLASS_BRANCH)
#define inst_trap_return(i) ((i) & 0)
-#define inst_call(i) (db_inst_type(i) == IT_CALL)
-#define inst_return(i) ((i) == 0x03e00008)
+#define inst_call(i) (classify_insn(i) == INSNCLASS_CALL)
+#define inst_return(i) ((i) == 0x03e00008)
-int db_inst_type(int);
void db_machine_init(void);
int db_enter_ddb(void);
diff --git a/sys/arch/mips64/mips64/db_machdep.c b/sys/arch/mips64/mips64/db_machdep.c
index 684d6edd389..2646400b31f 100644
--- a/sys/arch/mips64/mips64/db_machdep.c
+++ b/sys/arch/mips64/mips64/db_machdep.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: db_machdep.c,v 1.36 2012/09/29 21:37:03 miod Exp $ */
+/* $OpenBSD: db_machdep.c,v 1.37 2014/03/21 23:05:41 miod Exp $ */
/*
* Copyright (c) 1998-2003 Opsycon AB (www.opsycon.se)
@@ -378,75 +378,6 @@ next_instr_address(db_addr_t pc, boolean_t bd)
/*
- * Decode instruction and figure out type.
- */
-int
-db_inst_type(ins)
- int ins;
-{
- InstFmt inst;
- int ityp = 0;
-
- inst.word = ins;
- switch ((int)inst.JType.op) {
- case OP_SPECIAL:
- switch ((int)inst.RType.func) {
- case OP_JR:
- ityp = IT_BRANCH;
- break;
- case OP_JALR:
- case OP_SYSCALL:
- ityp = IT_CALL;
- break;
- }
- break;
-
- case OP_BCOND:
- switch ((int)inst.IType.rt) {
- case OP_BLTZ:
- case OP_BLTZL:
- case OP_BGEZ:
- case OP_BGEZL:
- ityp = IT_BRANCH;
- break;
-
- case OP_BLTZAL:
- case OP_BLTZALL:
- case OP_BGEZAL:
- case OP_BGEZALL:
- ityp = IT_CALL;
- break;
- }
- break;
-
- case OP_JAL:
- ityp = IT_CALL;
- break;
-
- case OP_J:
- case OP_BEQ:
- case OP_BEQL:
- case OP_BNE:
- case OP_BNEL:
- case OP_BLEZ:
- case OP_BLEZL:
- case OP_BGTZ:
- case OP_BGTZL:
- ityp = IT_BRANCH;
- break;
-
- case OP_COP1:
- switch (inst.RType.rs) {
- case OP_BC:
- ityp = IT_BRANCH;
- break;
- }
- break;
- }
- return (ityp);
-}
-
-/*
* MIPS machine dependent DDB commands.
*/
diff --git a/sys/arch/mips64/mips64/mips64_machdep.c b/sys/arch/mips64/mips64/mips64_machdep.c
index 138c625a734..cefac71775a 100644
--- a/sys/arch/mips64/mips64/mips64_machdep.c
+++ b/sys/arch/mips64/mips64/mips64_machdep.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: mips64_machdep.c,v 1.13 2014/03/09 10:12:17 miod Exp $ */
+/* $OpenBSD: mips64_machdep.c,v 1.14 2014/03/21 23:05:41 miod Exp $ */
/*
* Copyright (c) 2009, 2010, 2012 Miodrag Vallat.
@@ -52,6 +52,7 @@
#include <machine/autoconf.h>
#include <machine/cpu.h>
#include <mips64/mips_cpu.h>
+#include <mips64/mips_opcode.h>
#include <uvm/uvm.h>
@@ -491,3 +492,62 @@ resettodr()
if (cd->tod_set)
(*cd->tod_set)(cd->tod_cookie, &c);
}
+
+/*
+ * Decode instruction and figure out type.
+ */
+int
+classify_insn(uint32_t insn)
+{
+ InstFmt inst;
+
+ inst.word = insn;
+ switch (inst.JType.op) {
+ case OP_SPECIAL:
+ switch (inst.RType.func) {
+ case OP_JR:
+ return INSNCLASS_BRANCH;
+ case OP_JALR:
+ return INSNCLASS_CALL;
+ }
+ break;
+
+ case OP_BCOND:
+ switch (inst.IType.rt) {
+ case OP_BLTZ:
+ case OP_BLTZL:
+ case OP_BGEZ:
+ case OP_BGEZL:
+ return INSNCLASS_BRANCH;
+ case OP_BLTZAL:
+ case OP_BLTZALL:
+ case OP_BGEZAL:
+ case OP_BGEZALL:
+ return INSNCLASS_CALL;
+ }
+ break;
+
+ case OP_JAL:
+ return INSNCLASS_CALL;
+
+ case OP_J:
+ case OP_BEQ:
+ case OP_BEQL:
+ case OP_BNE:
+ case OP_BNEL:
+ case OP_BLEZ:
+ case OP_BLEZL:
+ case OP_BGTZ:
+ case OP_BGTZL:
+ return INSNCLASS_BRANCH;
+
+ case OP_COP1:
+ switch (inst.RType.rs) {
+ case OP_BC:
+ return INSNCLASS_BRANCH;
+ }
+ break;
+ }
+
+ return INSNCLASS_NEUTRAL;
+}