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-rw-r--r--sys/arch/hp300/hp300/locore.s120
-rw-r--r--sys/arch/mac68k/mac68k/bus_space.c3
-rw-r--r--sys/arch/mac68k/mac68k/locore.s65
-rw-r--r--sys/arch/mvme68k/mvme68k/locore.s136
4 files changed, 95 insertions, 229 deletions
diff --git a/sys/arch/hp300/hp300/locore.s b/sys/arch/hp300/hp300/locore.s
index 95c0709538f..eb6979559d0 100644
--- a/sys/arch/hp300/hp300/locore.s
+++ b/sys/arch/hp300/hp300/locore.s
@@ -1,4 +1,4 @@
-/* $OpenBSD: locore.s,v 1.55 2006/06/11 20:44:18 miod Exp $ */
+/* $OpenBSD: locore.s,v 1.56 2006/06/11 20:57:41 miod Exp $ */
/* $NetBSD: locore.s,v 1.91 1998/11/11 06:41:25 thorpej Exp $ */
/*
@@ -640,7 +640,7 @@ Lenab1:
addql #4,sp
Lenab2:
/* flush TLB and turn on caches */
- jbsr _C_LABEL(TBIA) | invalidate TLB
+ jbsr _ASM_LABEL(TBIA) | invalidate TLB
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
jeq Lnocache0 | yes, cache already on
movl #CACHE_ON,d0
@@ -1125,7 +1125,9 @@ Lbrkpt3:
movl sp@,sp | ... and sp
rte | all done
-/* Use common m68k sigreturn */
+/*
+ * Use common m68k sigreturn.
+ */
#include <m68k/m68k/sigreturn.s>
/*
@@ -1545,8 +1547,7 @@ Lsldone:
/*
* Invalidate entire TLB.
*/
-ENTRY(TBIA)
-_C_LABEL(_TBIA):
+ASENTRY_NOPROFILE(TBIA)
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
jne Lmotommu3 | no, skip
@@ -1568,11 +1569,7 @@ Lhpmmu6:
#if defined(M68K_MMU_HP)
MMUADDR(a0)
movl a0@(MMUTBINVAL),sp@- | do not ask me, this
- addql #4,sp | is how hpux does it
-#ifdef DEBUG
- tstl _ASM_LABEL(fullcflush)
- jne _C_LABEL(_DCIA) | XXX: invalidate entire cache
-#endif
+ addql #4,sp | is how HP-UX does it
#endif
rts
@@ -1580,10 +1577,6 @@ Lhpmmu6:
* Invalidate any TLB entry for given VA (TB Invalidate Single)
*/
ENTRY(TBIS)
-#ifdef DEBUG
- tstl _ASM_LABEL(fulltflush) | being conservative?
- jne _C_LABEL(_TBIA) | yes, flush entire TLB
-#endif
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
jne Lmotommu4 | no, skip
@@ -1633,10 +1626,6 @@ Lhpmmu5:
* Invalidate supervisor side of TLB
*/
ENTRY(TBIAS)
-#ifdef DEBUG
- tstl _ASM_LABEL(fulltflush) | being conservative?
- jne _C_LABEL(_TBIA) | yes, flush everything
-#endif
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
jne Lmotommu5 | no, skip
@@ -1661,21 +1650,14 @@ Lhpmmu7:
MMUADDR(a0)
movl #0x8000,d0 | more
movl d0,a0@(MMUTBINVAL) | HP magic
-#ifdef DEBUG
- tstl _ASM_LABEL(fullcflush)
- jne _C_LABEL(_DCIS) | XXX: invalidate entire sup. cache
-#endif
#endif
rts
+#if defined(COMPAT_HPUX)
/*
* Invalidate user side of TLB
*/
ENTRY(TBIAU)
-#ifdef DEBUG
- tstl _ASM_LABEL(fulltflush) | being conservative?
- jne _C_LABEL(_TBIA) | yes, flush everything
-#endif
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
jne Lmotommu6 | no, skip
@@ -1700,19 +1682,15 @@ Lhpmmu8:
MMUADDR(a0)
moveq #0,d0 | more
movl d0,a0@(MMUTBINVAL) | HP magic
-#ifdef DEBUG
- tstl _ASM_LABEL(fullcflush)
- jne _C_LABEL(_DCIU) | XXX: invalidate entire user cache
-#endif
#endif
rts
+#endif /* COMPAT_HPUX */
/*
* Invalidate instruction cache
*/
ENTRY(ICIA)
#if defined(M68040)
-ENTRY(ICPA)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
jne Lmotommu7 | no, skip
.word 0xf498 | cinva ic
@@ -1732,7 +1710,6 @@ Lmotommu7:
* and TBI*.
*/
ENTRY(DCIA)
-_C_LABEL(_DCIA):
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
jne Lmotommu8 | no, skip
@@ -1751,7 +1728,6 @@ Lnocache2:
rts
ENTRY(DCIS)
-_C_LABEL(_DCIS):
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
jne Lmotommu9 | no, skip
@@ -1770,7 +1746,6 @@ Lnocache3:
rts
ENTRY(DCIU)
-_C_LABEL(_DCIU):
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
jne LmotommuA | no, skip
@@ -1788,7 +1763,36 @@ Lnocache4:
#endif
rts
+#if defined(M68040) || defined(CACHE_HAVE_PAC)
+ENTRY(PCIA)
+#if defined(M68040)
+ cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
+ jne LmotommuB | no, skip
+ .word 0xf478 | cpusha dc
+ rts
+LmotommuB:
+#endif
+#if defined(CACHE_HAVE_PAC)
+ /*
+ * On non-68040 machines, PCIA() will only get invoked if
+ * ectype == EC_PHYS, thus we do not need to test anything.
+ */
+ movl #DC_CLEAR,d0
+ movc d0,cacr | invalidate on-chip d-cache
+ MMUADDR(a0)
+ andl #~MMU_CEN,a0@(MMUCMD) | disable cache in MMU control reg
+ orl #MMU_CEN,a0@(MMUCMD) | reenable cache in MMU control reg
+ rts
+#endif
+#endif
+
#if defined(M68040)
+ENTRY(ICPA)
+ .word 0xf498 | cinva ic
+ rts
+ENTRY(DCFA)
+ .word 0xf478 | cpusha dc
+ rts
ENTRY(ICPL)
movl sp@(4),a0 | address
.word 0xf488 | cinvl ic,a0@
@@ -1805,9 +1809,6 @@ ENTRY(DCPP)
movl sp@(4),a0 | address
.word 0xf450 | cinvp dc,a0@
rts
-ENTRY(DCPA)
- .word 0xf458 | cinva dc
- rts
ENTRY(DCFL)
movl sp@(4),a0 | address
.word 0xf468 | cpushl dc,a0@
@@ -1818,27 +1819,6 @@ ENTRY(DCFP)
rts
#endif
-ENTRY(PCIA)
-#if defined(M68040)
-ENTRY(DCFA)
- cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
- jne LmotommuB | no, skip
- .word 0xf478 | cpusha dc
- rts
-LmotommuB:
-#endif
-#if defined(M68K_MMU_MOTOROLA)
- movl #DC_CLEAR,d0
- movc d0,cacr | invalidate on-chip d-cache
- tstl _C_LABEL(ectype) | got external PAC?
- jge Lnocache6 | no, all done
- MMUADDR(a0)
- andl #~MMU_CEN,a0@(MMUCMD) | disable cache in MMU control reg
- orl #MMU_CEN,a0@(MMUCMD) | reenable cache in MMU control reg
-Lnocache6:
-#endif
- rts
-
ENTRY(ecacheon)
tstl _C_LABEL(ectype)
jeq Lnocache7
@@ -1904,22 +1884,6 @@ Lhpmmu9:
#endif
rts
-ENTRY(ploadw)
-#if defined(M68K_MMU_MOTOROLA)
- movl sp@(4),a0 | address to load
-#if defined(M68K_MMU_HP)
- tstl _C_LABEL(mmutype) | HP MMU?
- jeq Lploadwskp | yes, skip
-#endif
-#if defined(M68040)
- cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
- jeq Lploadwskp | yes, skip
-#endif
- ploadw #1,a0@ | pre-load translation
-Lploadwskp:
-#endif
- rts
-
/*
* Set processor priority level calls. Most are implemented with
* inline asm expansions. However, spl0 requires special handling
@@ -2161,11 +2125,3 @@ ASLOCAL(heartbeat)
ASLOCAL(beatstatus)
.long 0 | for determining a fast or slow throb
#endif
-
-#ifdef DEBUG
-ASGLOBAL(fulltflush)
- .long 0
-
-ASGLOBAL(fullcflush)
- .long 0
-#endif
diff --git a/sys/arch/mac68k/mac68k/bus_space.c b/sys/arch/mac68k/mac68k/bus_space.c
index 46403fcb3b9..e17bc0805be 100644
--- a/sys/arch/mac68k/mac68k/bus_space.c
+++ b/sys/arch/mac68k/mac68k/bus_space.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: bus_space.c,v 1.20 2006/01/17 00:08:36 miod Exp $ */
+/* $OpenBSD: bus_space.c,v 1.21 2006/06/11 20:57:44 miod Exp $ */
/* $NetBSD: bus_space.c,v 1.5 1999/03/26 23:41:30 mycroft Exp $ */
/*-
@@ -156,6 +156,7 @@ bus_mem_add_mapping(bpa, size, flags, bshp)
u_long pa, endpa;
vaddr_t va;
pt_entry_t *pte;
+ extern void TBIA(void);
pa = trunc_page(bpa);
endpa = round_page((bpa + size) - 1);
diff --git a/sys/arch/mac68k/mac68k/locore.s b/sys/arch/mac68k/mac68k/locore.s
index 51e98e059f9..c6c3158ac3f 100644
--- a/sys/arch/mac68k/mac68k/locore.s
+++ b/sys/arch/mac68k/mac68k/locore.s
@@ -1,4 +1,4 @@
-/* $OpenBSD: locore.s,v 1.52 2006/06/11 20:49:27 miod Exp $ */
+/* $OpenBSD: locore.s,v 1.53 2006/06/11 20:57:44 miod Exp $ */
/* $NetBSD: locore.s,v 1.103 1998/07/09 06:02:50 scottr Exp $ */
/*
@@ -1163,7 +1163,6 @@ Lsldone:
* Invalidate entire TLB.
*/
ENTRY(TBIA)
-__TBIA:
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
jne Lmotommu3 | no, skip
@@ -1185,10 +1184,6 @@ Ltbia851:
* Invalidate any TLB entry for given VA (TB Invalidate Single)
*/
ENTRY(TBIS)
-#ifdef DEBUG
- tstl _ASM_LABEL(fulltflush) | being conservative?
- jne _C_LABEL(_TBIA) | yes, flush entire TLB
-#endif
movl sp@(4),a0
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
@@ -1220,10 +1215,6 @@ Ltbis851:
* Invalidate supervisor side of TLB
*/
ENTRY(TBIAS)
-#ifdef DEBUG
- tstl _ASM_LABEL(fulltflush) | being conservative?
- jne _C_LABEL(_TBIA) | yes, flush everything
-#endif
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
jne Lmotommu5 | no, skip
@@ -1243,14 +1234,11 @@ Ltbias851:
movc d0,cacr | invalidate on-chip d-cache
rts
+#if defined(COMPAT_HPUX)
/*
* Invalidate user side of TLB
*/
ENTRY(TBIAU)
-#ifdef DEBUG
- tstl _ASM_LABEL(fulltflush) | being conservative?
- jne _C_LABEL(_TBIA) | yes, flush everything
-#endif
#if defined(M68040)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
jne Lmotommu6 | no, skip
@@ -1268,13 +1256,13 @@ Ltbiau851:
movl #DC_CLEAR,d0
movc d0,cacr | invalidate on-chip d-cache
rts
+#endif /* COMPAT_HPUX */
/*
* Invalidate instruction cache
*/
ENTRY(ICIA)
#if defined(M68040)
-ENTRY(ICPA)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
jne Lmotommu7 | no, skip
.word 0xf498 | cinva ic
@@ -1287,42 +1275,33 @@ Lmotommu7:
/*
* Invalidate data cache.
+ *
* NOTE: we do not flush 68030 on-chip cache as there are no aliasing
* problems with DC_WA. The only cases we have to worry about are context
* switch and TLB changes, both of which are handled "in-line" in resume
* and TBI*.
+ * Because of this, since there is no way on 68040 and 68060 to flush
+ * user and supervisor modes specfically, DCIS and DCIU are the same entry
+ * point as DCIA.
*/
ENTRY(DCIA)
-_C_LABEL(_DCIA):
-#if defined(M68040)
- cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
- jne Lmotommu8 | no, skip
- .word 0xf478 | cpusha dc
-Lmotommu8:
-#endif
- rts
-
ENTRY(DCIS)
-_C_LABEL(_DCIS):
-#if defined(M68040)
- cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
- jne Lmotommu9 | no, skip
- .word 0xf478 | cpusha dc
-Lmotommu9:
-#endif
- rts
-
ENTRY(DCIU)
-_C_LABEL(_DCIU):
#if defined(M68040)
- cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
- jne LmotommuA | no, skip
+ cmpl #MMU_68040,_C_LABEL(mmutype) | 68040 or 68060?
+ jgt 1f | no, skip
.word 0xf478 | cpusha dc
-LmotommuA:
+1:
#endif
rts
#ifdef M68040
+ENTRY(ICPA)
+ .word 0xf498 | cinva ic
+ rts
+ENTRY(DCFA)
+ .word 0xf478 | cpusha dc
+ rts
ENTRY(ICPL) /* invalidate instruction physical cache line */
movl sp@(4),a0 | address
.word 0xf488 | cinvl ic,a0@
@@ -1339,9 +1318,6 @@ ENTRY(DCPP) /* invalidate data physical cache page */
movl sp@(4),a0 | address
.word 0xf450 | cinvp dc,a0@
rts
-ENTRY(DCPA) /* invalidate instruction physical cache line */
- .word 0xf458 | cinva dc
- rts
ENTRY(DCFL) /* data cache flush line */
movl sp@(4),a0 | address
.word 0xf468 | cpushl dc,a0@
@@ -1354,7 +1330,6 @@ ENTRY(DCFP) /* data cache flush page */
ENTRY(PCIA)
#if defined(M68040)
-ENTRY(DCFA)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
jne LmotommuB | no, skip
.word 0xf478 | cpusha dc
@@ -1848,11 +1823,3 @@ GLOBAL(mac68k_vrsrc_cnt)
.long 0
GLOBAL(mac68k_vrsrc_vec)
.word 0, 0, 0, 0, 0, 0
-
-#ifdef DEBUG
-ASGLOBAL(fulltflush)
- .long 0
-
-ASGLOBAL(fullcflush)
- .long 0
-#endif
diff --git a/sys/arch/mvme68k/mvme68k/locore.s b/sys/arch/mvme68k/mvme68k/locore.s
index 3d753d72d03..b4d86c20ac5 100644
--- a/sys/arch/mvme68k/mvme68k/locore.s
+++ b/sys/arch/mvme68k/mvme68k/locore.s
@@ -1,4 +1,4 @@
-/* $OpenBSD: locore.s,v 1.51 2006/05/19 22:51:09 miod Exp $ */
+/* $OpenBSD: locore.s,v 1.52 2006/06/11 20:57:44 miod Exp $ */
/*
* Copyright (c) 1995 Theo de Raadt
@@ -518,7 +518,7 @@ Lenab1:
addql #4,sp
Lenab2:
/* flush TLB and turn on caches */
- jbsr _C_LABEL(TBIA) | invalidate TLB
+ jbsr _ASM_LABEL(TBIA) | invalidate TLB
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040 or 68060?
jle Lnocache0 | yes, cache already on
movl #CACHE_ON,d0
@@ -1432,8 +1432,7 @@ Lsldone:
/*
* Invalidate entire TLB.
*/
-ENTRY(TBIA)
-_C_LABEL(_TBIA):
+ASENTRY_NOPROFILE(TBIA)
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040 or 68060?
jle Ltbia040 | yes, goto Ltbia040
pflusha | flush entire TLB
@@ -1460,10 +1459,6 @@ Ltbiano60:
* Invalidate any TLB entry for given VA (TB Invalidate Single)
*/
ENTRY(TBIS)
-#ifdef DEBUG
- tstl _ASM_LABEL(fulltflush) | being conservative?
- jne _C_LABEL(_TBIA) | yes, flush entire TLB
-#endif
movl sp@(4),a0 | get addr to flush
cmpl #MMU_68040,_C_LABEL(mmutype) | 68040 or 68060 ?
jle Ltbis040 | yes, goto Ltbis040
@@ -1496,43 +1491,21 @@ Ltbisno60:
/*
* Invalidate supervisor side of TLB
*/
+#if defined(M68060)
ENTRY(TBIAS)
-#ifdef DEBUG
- tstl _ASM_LABEL(fulltflush) | being conservative?
- jne _C_LABEL(_TBIA) | yes, flush everything
-#endif
- cmpl #MMU_68040,_C_LABEL(mmutype) | 68040 or 68060 ?
- jle Ltbias040 | yes, goto Ltbias040
- tstl _C_LABEL(mmutype)
- jpl Lmc68851c | 68851?
- pflush #4,#4 | flush supervisor TLB entries
- movl #DC_CLEAR,d0
- movc d0,cacr | invalidate on-chip d-cache
- rts
-Lmc68851c:
- pflushs #4,#4 | flush supervisor TLB entries
- rts
-Ltbias040:
-| 68040 cannot specify supervisor/user on pflusha, so we flush all
+ | 68060 cannot specify supervisor/user on pflusha, so we flush all
.word 0xf518 | pflusha
-#ifdef M68060
- cmpl #MMU_68060,_C_LABEL(mmutype)
- jne Ltbiasno60
movc cacr,d0
orl #IC60_CABC,d0 | and clear all branch cache entries
movc d0,cacr
-Ltbiasno60:
-#endif
rts
+#endif
+#if defined(COMPAT_HPUX) || defined(M68060)
/*
* Invalidate user side of TLB
*/
ENTRY(TBIAU)
-#ifdef DEBUG
- tstl _ASM_LABEL(fulltflush) | being conservative?
- jne _C_LABEL(_TBIA) | yes, flush everything
-#endif
cmpl #MMU_68040,_C_LABEL(mmutype)
jle Ltbiau040
tstl _C_LABEL(mmutype)
@@ -1556,18 +1529,18 @@ Ltbiau040:
Ltbiauno60:
#endif
rts
+#endif /* defined(COMPAT_HPUX) || defined(M68060) */
/*
* Invalidate instruction cache
*/
ENTRY(ICIA)
#if defined(M68040) || defined(M68060)
-ENTRY(ICPA)
- cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
- jgt Lmotommu7 | no, skip
+ cmpl #MMU_68040,_C_LABEL(mmutype) | 68040 or 68060?
+ jgt 1f | no, skip
.word 0xf498 | cinva ic
rts
-Lmotommu7:
+1:
#endif
movl #IC_CLEAR,d0
movc d0,cacr | invalidate i-cache
@@ -1575,45 +1548,38 @@ Lmotommu7:
/*
* Invalidate data cache.
+ *
* NOTE: we do not flush 68030 on-chip cache as there are no aliasing
* problems with DC_WA. The only cases we have to worry about are context
* switch and TLB changes, both of which are handled "in-line" in resume
* and TBI*.
+ * Because of this, since there is no way on 68040 and 68060 to flush
+ * user and supervisor modes specfically, DCIS and DCIU are the same entry
+ * point as DCIA.
+ *
+ * On 68060, since we have disabled cache invalidation on pushes, we need
+ * an explicit cinva after the cpusha.
*/
ENTRY(DCIA)
-_C_LABEL(_DCIA):
-#if defined(M68040) || defined(M68060)
- cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
- jgt Lmotommu8 | no, skip
- .word 0xf478 | cpusha dc
- rts
-Lmotommu8:
-#endif
- rts
-
ENTRY(DCIS)
-_C_LABEL(_DCIS):
+ENTRY(DCIU)
#if defined(M68040) || defined(M68060)
- cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
- jgt Lmotommu9 | no, skip
+ cmpl #MMU_68040,_C_LABEL(mmutype) | 68040 or 68060?
+ jgt 1f | no, skip
.word 0xf478 | cpusha dc
- rts
-Lmotommu9:
+ jeq 1f
+ .word 0xf458 | cinva dc
+1:
#endif
rts
-ENTRY(DCIU)
-_C_LABEL(_DCIU):
#if defined(M68040) || defined(M68060)
- cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
- jgt LmotommuA | no, skip
- .word 0xf478 | cpusha dc
+ENTRY(ICPA)
+ .word 0xf498 | cinva ic
rts
-LmotommuA:
-#endif
+ENTRY(DCFA)
+ .word 0xf478 | cpusha dc
rts
-
-#if defined(M68040) || defined(M68060)
ENTRY(ICPL)
movl sp@(4),a0 | address
.word 0xf488 | cinvl ic,a0@
@@ -1630,9 +1596,6 @@ ENTRY(DCPP)
movl sp@(4),a0 | address
.word 0xf450 | cinvp dc,a0@
rts
-ENTRY(DCPA)
- .word 0xf458 | cinva dc
- rts
ENTRY(DCFL)
movl sp@(4),a0 | address
.word 0xf468 | cpushl dc,a0@
@@ -1643,19 +1606,6 @@ ENTRY(DCFP)
rts
#endif
-ENTRY(PCIA)
-#if defined(M68040) || defined(M68060)
-ENTRY(DCFA)
- cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
- jgt LmotommuB | no, skip
- .word 0xf478 | cpusha dc
- rts
-LmotommuB:
-#endif
- movl #DC_CLEAR,d0
- movc d0,cacr | invalidate on-chip d-cache
- rts
-
ENTRY(getsfc)
movc sfc,d0
rts
@@ -1667,16 +1617,19 @@ ENTRY(getdfc)
/*
* Load a new user segment table pointer.
*/
-ENTRY(loadustp) /* XXX - smurph */
+ENTRY(loadustp)
movl sp@(4),d0 | new USTP
moveq #PGSHIFT,d1
lsll d1,d0 | convert to addr
+#if defined(M68040) || defined(M68060)
+ cmpl #MMU_68040,_C_LABEL(mmutype)
#ifdef M68060
- cmpl #MMU_68060,_C_LABEL(mmutype) | 68040 or 68060?
- jeq Lldustp060 | yes, goto Lldustp060
+ jlt Lldustp060
#endif
- cmpl #MMU_68040,_C_LABEL(mmutype)
+#ifdef M68040
jeq Lldustp040
+#endif
+#endif
pflusha | flush entire TLB
lea _C_LABEL(protorp),a0 | CRP prototype
movl d0,a0@(4) | stash USTP
@@ -1690,17 +1643,13 @@ Lldustp060:
movc cacr,d1
orl #IC60_CUBC,d1 | clear user branch cache entries
movc d1,cacr
+ /* FALLTHROUGH */
#endif
Lldustp040:
.word 0xf518 | pflusha
.long 0x4e7b0806 | movec d0,URP
rts
-ENTRY(ploadw)
- movl sp@(4),a0 | address to load
- ploadw #1,a0@ | pre-load translation
- rts
-
/*
* Set processor priority level calls. Most are implemented with
* inline asm expansions. However, spl0 requires special handling
@@ -1735,8 +1684,8 @@ ENTRY(m68881_save)
#endif
tstb a0@ | null state frame?
jeq Lm68881sdone | yes, all done
- fmovem fp0-fp7,a0@(FPF_REGS) | save FP general registers
- fmovem fpcr/fpsr/fpi,a0@(FPF_FPCR) | save FP control registers
+ fmovem fp0-fp7,a0@(FPF_REGS) | save FP general registers
+ fmovem fpcr/fpsr/fpi,a0@(FPF_FPCR) | save FP control registers
Lm68881sdone:
rts
@@ -1744,7 +1693,7 @@ Lm68881sdone:
Lm68060fpsave:
tstb a0@(2) | null state frame?
jeq Lm68060sdone | yes, all done
- fmovem fp0-fp7,a0@(FPF_REGS) | save FP general registers
+ fmovem fp0-fp7,a0@(FPF_REGS) | save FP general registers
fmovem fpcr,a0@(FPF_FPCR) | save FP control registers
fmovem fpsr,a0@(FPF_FPSR)
fmovem fpi,a0@(FPF_FPI)
@@ -1881,11 +1830,4 @@ GLOBAL(intiolimit)
GLOBAL(extiobase)
.long 0 | KVA of base of external IO space
-#ifdef DEBUG
-ASGLOBAL(fulltflush)
- .long 0
-ASGLOBAL(fullcflush)
- .long 0
-#endif
-
#include <mvme68k/mvme68k/vectors.s>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-05 03:36:29 +0000