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-rw-r--r--sys/arch/powerpc/pci/macobio.c212
-rw-r--r--sys/arch/powerpc/pci/mpc106reg.h100
-rw-r--r--sys/arch/powerpc/pci/mpcpcibus.c173
-rw-r--r--sys/arch/powerpc/pci/pci_machdep.h8
-rw-r--r--sys/arch/powerpc/pci/pcibrvar.h10
5 files changed, 425 insertions, 78 deletions
diff --git a/sys/arch/powerpc/pci/macobio.c b/sys/arch/powerpc/pci/macobio.c
new file mode 100644
index 00000000000..f7d9de1b34b
--- /dev/null
+++ b/sys/arch/powerpc/pci/macobio.c
@@ -0,0 +1,212 @@
+/* $NetBSD: obio.c,v 1.6 1999/05/01 10:36:08 tsubai Exp $ */
+
+/*-
+ * Copyright (C) 1998 Internet Research Institute, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by
+ * Internet Research Institute, Inc.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/device.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+
+#include <dev/ofw/openfirm.h>
+
+#include <machine/bus.h>
+#include <machine/autoconf.h>
+
+static void obio_attach __P((struct device *, struct device *, void *));
+static int obio_match __P((struct device *, void *, void *));
+static int obio_print __P((void *, const char *));
+
+struct obio_softc {
+ struct device sc_dev;
+ int sc_node;
+ struct ppc_bus_space sc_membus_space;
+};
+struct cfdriver obio_cd = {
+ NULL, "macobio", DV_DULL,
+};
+
+
+struct cfattach obio_ca = {
+ sizeof(struct obio_softc), obio_match, obio_attach
+};
+
+int
+obio_match(parent, cf, aux)
+ struct device *parent;
+ void *cf;
+ void *aux;
+{
+ struct pci_attach_args *pa = aux;
+
+ if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_APPLE)
+ switch (PCI_PRODUCT(pa->pa_id)) {
+
+ case 0x02: /* gc */
+ case 0x07: /* ohare */
+ case 0x10: /* mac-io "Heathrow" */
+ case 0x17: /* mac-io "Paddington" */
+ return 1;
+ }
+
+ return 0;
+}
+
+#define HEATHROW_FCR_OFFSET 0x38
+u_int32_t *heathrow_FCR = NULL;
+
+void prog_switch (void *arg)
+{
+ Debugger();
+}
+
+/*
+ * Attach all the sub-devices we can find
+ */
+void
+obio_attach(parent, self, aux)
+ struct device *parent, *self;
+ void *aux;
+{
+ struct obio_softc *sc = (struct obio_softc *)self;
+ struct pci_attach_args *pa = aux;
+ struct confargs ca;
+ int node, child, namelen;
+ u_int32_t reg[20];
+ int32_t intr[5];
+ char name[32];
+
+ printf("obio ver %x\n", (PCI_PRODUCT(pa->pa_id)));
+
+ switch (PCI_PRODUCT(pa->pa_id)) {
+
+ /* XXX should not use name */
+ case 0x02:
+ node = OF_finddevice("/bandit/gc");
+ break;
+
+ case 0x07:
+ node = OF_finddevice("/bandit/ohare");
+ break;
+
+ case 0x10: /* heathrow */
+ case 0x17: /* paddington */
+ node = OF_finddevice("mac-io");
+ if (node == -1)
+ node = OF_finddevice("/pci/mac-io");
+ if (OF_getprop(node, "assigned-addresses", reg, sizeof(reg))
+ == (sizeof (reg[0]) * 5))
+ {
+ /* always ??? */
+ heathrow_FCR = mapiodev(reg[2] + HEATHROW_FCR_OFFSET,
+ 4);
+ printf("heathrow fcr, %x\n", heathrow_FCR);
+ }
+ break;
+
+ default:
+ printf("obio_attach: unknown obio controller\n");
+ return;
+ }
+ sc->sc_node = node;
+
+ if (OF_getprop(node, "assigned-addresses", reg, sizeof(reg)) < 12)
+ return;
+ ca.ca_baseaddr = reg[2];
+
+ sc->sc_membus_space.bus_base = ca.ca_baseaddr;
+ {
+ extern u_int32_t *interrupt_reg;
+ /* OK THIS IS AN UGLY HACK */
+ void mac_do_pending_int();
+ void mac_ext_intr();
+ typedef void (void_f) (void);
+ extern void_f *pending_int_f;
+
+ interrupt_reg = (void*)ca.ca_baseaddr;
+
+ install_extint(mac_ext_intr);
+ pending_int_f = mac_do_pending_int;
+
+ mac_intr_establish(0x14, IST_LEVEL, IPL_HIGH,
+ prog_switch, 0x14);
+ }
+
+ sc->sc_membus_space.bus_reverse = 1;
+
+ ca.ca_iot = &sc->sc_membus_space;
+
+ printf(": addr 0x%x\n", ca.ca_baseaddr);
+
+ for (child = OF_child(node); child; child = OF_peer(child)) {
+ namelen = OF_getprop(child, "name", name, sizeof(name));
+ if (namelen < 0)
+ continue;
+ if (namelen >= sizeof(name))
+ continue;
+
+ name[namelen] = 0;
+ ca.ca_name = name;
+ ca.ca_node = child;
+
+ ca.ca_nreg = OF_getprop(child, "reg", reg, sizeof(reg));
+ ca.ca_nintr = OF_getprop(child, "AAPL,interrupts", intr,
+ sizeof(intr));
+ if (ca.ca_nintr == -1)
+ ca.ca_nintr = OF_getprop(child, "interrupts", intr,
+ sizeof(intr));
+
+ ca.ca_reg = reg;
+ ca.ca_intr = intr;
+
+ config_found(self, &ca, obio_print);
+ }
+}
+
+int
+obio_print(aux, obio)
+ void *aux;
+ const char *obio;
+{
+ struct confargs *ca = aux;
+
+ if (obio)
+ printf("%s at %s", ca->ca_name, obio);
+
+ if (ca->ca_nreg > 0)
+ printf(" offset 0x%x", ca->ca_reg[0]);
+
+ return UNCONF;
+}
diff --git a/sys/arch/powerpc/pci/mpc106reg.h b/sys/arch/powerpc/pci/mpc106reg.h
index edc27ff5486..1a442cf606f 100644
--- a/sys/arch/powerpc/pci/mpc106reg.h
+++ b/sys/arch/powerpc/pci/mpc106reg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: mpc106reg.h,v 1.3 1998/10/09 02:09:19 rahnds Exp $ */
+/* $OpenBSD: mpc106reg.h,v 1.4 1999/11/08 23:49:00 rahnds Exp $ */
/*
* Copyright (c) 1997 Per Fogelstrom
@@ -38,95 +38,129 @@
#ifndef _MACHINE_MPC106REG_H_
#define _MACHINE_MPC106REG_H_
-/* Where we map the PCI memory space */
+/* Where we map the PCI memory space - MAP A*/
#define MPC106_V_PCI_MEM_SPACE 0xc0000000 /* Viritual */
#define MPC106_P_PCI_MEM_SPACE 0xc0000000 /* Physical */
-/* Where we map the PCI I/O space */
+/* Where we map the PCI I/O space - MAP A*/
#define MPC106_P_ISA_IO_SPACE 0x80000000
#define MPC106_V_ISA_IO_SPACE 0x80000000
#define MPC106_V_PCI_IO_SPACE 0x80000000
+#define MPC106_P_PCI_IO_SPACE 0x80000000
/* Where we map the config space */
#define MPC106_PCI_CONF_SPACE (MPC106_V_ISA_IO_SPACE + 0x00800000)
+/* Where we map the PCI memory space - MAP B*/
+#define MPC106_P_PCI_MEM_SPACE_MAP_B 0x80000000 /* Physical */
+
+/* Where we map the PCI I/O space - MAP B*/
+#define MPC106_P_PCI_IO_SPACE_MAP_B 0xf0000000
+
+/* Where we map the config space */
+#define MPC106_PCI_CONF_SPACE_MAP_B \
+ (MPC106_V_ISA_IO_SPACE_MAP_B + 0x00800000)
+
/* offsets from base pointer */
-#define MPC106_CONF_BASE (MPC106_V_ISA_IO_SPACE + 0x0cf8)
-#define MPC106_CONF_DATA (MPC106_V_ISA_IO_SPACE + 0x0cfc)
-#define MPC106_REGOFFS(x) ((x << 24) | 0x80)
+#define MPC106_REGOFFS(x) ((x) | 0x80000000)
/* Where PCI devices sees CPU memory. */
#define MPC106_PCI_CPUMEM 0x80000000
+#if 0
static __inline void
-mpc_cfg_write_1(reg, val)
+mpc_cfg_write_1(iot, ioh, reg, data)
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
u_int32_t reg;
u_int8_t val;
{
- out32(MPC106_CONF_BASE, MPC106_REGOFFS(reg));
- outb(MPC106_CONF_DATA + (reg & 3), val);
+ bus_space_write_4(iot, ioh, 0xcf8, MPC106_REGOFFS(reg));
+ bus_space_write_1(iot, ioh, 0xcfc, val);
+
+ u_int32_t addr;
+ int device;
+ int s;
+ int handle;
+ int tag = 0;
+ printf("mpc_cfg_write tag %x offset %x data %x\n", tag, offset, data);
+
+ device = (tag >> 11) & 0x1f;
+ addr = (0x800 << device) | (tag & 0x380) | MPC106_REGOFFS(reg);
+
+ handle = ppc_open_pci_bridge();
+ s = splhigh();
+
+ OF_call_method("config-l!", handle, 1, 1,
+ 0x80000000 | addr, &data);
+ splx(s);
+ ppc_close_pci_bridge(handle);
}
static __inline void
-mpc_cfg_write_2(reg, val)
+mpc_cfg_write_2(iot, ioh, reg, val)
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
u_int32_t reg;
u_int16_t val;
{
- u_int32_t _p_ = MPC106_CONF_DATA + (reg & 2);
-
- out32(MPC106_CONF_BASE, MPC106_REGOFFS(reg));
- __asm__ volatile("sthbrx %0, 0, %1\n" :: "r"(val), "r"(_p_));
- __asm__ volatile("sync"); __asm__ volatile("eieio");
+ bus_space_write_4(iot, ioh, 0xcf8, MPC106_REGOFFS(reg));
+ bus_space_write_2(iot, ioh, 0xcfc, val);
}
static __inline void
-mpc_cfg_write_4(reg, val)
+mpc_cfg_write_4(iot, ioh, reg, val)
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
u_int32_t reg;
u_int32_t val;
{
- u_int32_t _p_ = MPC106_CONF_DATA;
- out32(MPC106_CONF_BASE, MPC106_REGOFFS(reg));
- __asm__ volatile("stwbrx %0, 0, %1\n" :: "r"(val), "r"(_p_));
- __asm__ volatile("sync"); __asm__ volatile("eieio");
+ bus_space_write_4(iot, ioh, 0xcf8, MPC106_REGOFFS(reg));
+ bus_space_write_4(iot, ioh, 0xcfc, val);
}
+#endif
static __inline u_int8_t
-mpc_cfg_read_1(reg)
+mpc_cfg_read_1(iot, ioh, reg)
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
u_int32_t reg;
{
u_int8_t _v_;
- out32(MPC106_CONF_BASE, MPC106_REGOFFS(reg));
- _v_ = inb(MPC106_CONF_DATA);
+ bus_space_write_4(iot, ioh, 0xcf8, MPC106_REGOFFS(reg));
+ _v_ = bus_space_read_1(iot, ioh, 0xcfc);
return(_v_);
}
+#if 0
static __inline u_int16_t
-mpc_cfg_read_2(reg)
+mpc_cfg_read_2(iot, ioh, reg)
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
u_int32_t reg;
{
u_int16_t _v_;
- u_int32_t _p_ = MPC106_CONF_DATA + (reg & 2);
- out32(MPC106_CONF_BASE, MPC106_REGOFFS(reg));
- __asm__ volatile("lhbrx %0, 0, %1\n" : "=r"(_v_) : "r"(_p_));
- __asm__ volatile("sync"); __asm__ volatile("eieio");
+ bus_space_write_4(iot, ioh, 0xcf8, MPC106_REGOFFS(reg));
+ _v_ = bus_space_read_2(iot, ioh, 0xcfc);
return(_v_);
}
static __inline u_int32_t
-mpc_cfg_read_4(reg)
+mpc_cfg_read_4(iot, ioh, reg)
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh;
u_int32_t reg;
{
u_int32_t _v_;
- u_int32_t _p_ = MPC106_CONF_DATA;
- out32(MPC106_CONF_BASE, MPC106_REGOFFS(reg));
- __asm__ volatile("lwbrx %0, 0, %1\n" : "=r"(_v_) : "r"(_p_));
- __asm__ volatile("sync"); __asm__ volatile("eieio");
+ bus_space_write_4(iot, ioh, 0xcf8, MPC106_REGOFFS(reg));
+ _v_ = bus_space_read_4(iot, ioh, 0xcfc);
return(_v_);
}
+#endif
#define MPC106_PCI_VENDOR 0x00
#define MPC106_PCI_DEVICE 0x02
diff --git a/sys/arch/powerpc/pci/mpcpcibus.c b/sys/arch/powerpc/pci/mpcpcibus.c
index 69d3e43dc70..18fa6b7f103 100644
--- a/sys/arch/powerpc/pci/mpcpcibus.c
+++ b/sys/arch/powerpc/pci/mpcpcibus.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: mpcpcibus.c,v 1.9 1999/01/11 05:11:53 millert Exp $ */
+/* $OpenBSD: mpcpcibus.c,v 1.10 1999/11/08 23:49:00 rahnds Exp $ */
/*
* Copyright (c) 1997 Per Fogelstrom
@@ -47,11 +47,14 @@
#include <machine/autoconf.h>
#include <machine/bat.h>
+#if 0
#include <dev/isa/isareg.h>
#include <dev/isa/isavar.h>
+#endif
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
#include <powerpc/pci/pcibrvar.h>
#include <powerpc/pci/mpc106reg.h>
@@ -106,20 +109,43 @@ srom_crc32(
return crc;
}
-
int
mpcpcibrmatch(parent, match, aux)
struct device *parent;
void *match, *aux;
{
struct confargs *ca = aux;
+ int handle;
+ int found = 0;
+ int err;
+ unsigned int val;
if (strcmp(ca->ca_name, mpcpcibr_cd.cd_name) != 0)
- return (0);
+ return (found);
+
+ handle = ppc_open_pci_bridge();
+ if (handle != 0) {
+ err = OF_call_method("config-l@", handle, 1, 1,
+ 0x80000000, &val);
+ if (err == 0) {
+ switch (val) {
+ /* supported ppc-pci bridges */
+ case (PCI_VENDOR_MOT | ( PCI_PRODUCT_MOT_MPC105 <<16)):
+ case (PCI_VENDOR_MOT | ( PCI_PRODUCT_MOT_MPC106 <<16)):
+ found = 1;
+ break;
+ default:
+ found = 0;
+ }
+
+ }
+ }
+ ppc_close_pci_bridge(handle);
- return (1);
+ return found;
}
+int pci_map_a = 0;
void
mpcpcibrattach(parent, self, aux)
struct device *parent, *self;
@@ -128,6 +154,8 @@ mpcpcibrattach(parent, self, aux)
struct pcibr_softc *sc = (struct pcibr_softc *)self;
struct pcibr_config *lcp;
struct pcibus_attach_args pba;
+ int map;
+ char *bridge;
switch(system_type) {
case POWER4e:
@@ -157,35 +185,74 @@ mpcpcibrattach(parent, self, aux)
lcp->lc_pc.pc_intr_disestablish = mpc_intr_disestablish;
printf(": MPC106, Revision %x.\n",
- mpc_cfg_read_1(MPC106_PCI_REVID));
- mpc_cfg_write_2(MPC106_PCI_STAT, 0xff80); /* Reset status */
+ mpc_cfg_read_1(sc->sc_iobus_space, sc->ioh,
+ MPC106_PCI_REVID));
+#if 0
+ mpc_cfg_write_2(sc->sc_iobus_space, sc->ioh,
+ MPC106_PCI_STAT, 0xff80); /* Reset status */
+#endif
+ bridge = "MPC106";
break;
case OFWMACH:
case PWRSTK:
+ case APPL:
lcp = sc->sc_pcibr = &mpc_config;
-
{
- unsigned int addr;
- /* need to map 0xf0000000 also but cannot
- * because kernel uses that address space
+ int handle;
+ int err;
+ unsigned int val;
+ handle = ppc_open_pci_bridge();
+ /* if open fails something odd has happened,
+ * we did this before during probe...
*/
- for (addr = 0xc0000000;
- addr >= 0x80000000;
- addr -= 0x10000000)
- {
- /* we map it 1-1, cache inibited,
- * REALLY wish this could be cacheable
- * that is the reason to not use the bat.
- */
- addbatmap(addr, addr, BAT_I);
+ err = OF_call_method("config-l@", handle, 1, 1,
+ 0x80000000, &val);
+ if (err == 0) {
+ switch (val) {
+ /* supported ppc-pci bridges */
+ case (PCI_VENDOR_MOT | ( PCI_PRODUCT_MOT_MPC105 <<16)):
+ bridge = "MPC105";
+ break;
+ case (PCI_VENDOR_MOT | ( PCI_PRODUCT_MOT_MPC106 <<16)):
+ bridge = "MPC106";
+ break;
+ default:
+ ;
+ }
+
+ }
+
+ /* read the PICR1 register to find what
+ * address map is being used
+ */
+ err = OF_call_method("config-l@", handle, 1, 1,
+ 0x800000a8, &val);
+ if (val & 0x00010000) {
+ map = 1; /* map A */
+ pci_map_a = 1;
+ } else {
+ map = 0; /* map B */
+ pci_map_a = 0;
}
+
+ ppc_close_pci_bridge(handle);
}
- sc->sc_membus_space.bus_base = MPC106_V_PCI_MEM_SPACE;
- sc->sc_membus_space.bus_reverse = 1;
- sc->sc_iobus_space.bus_base = MPC106_V_PCI_IO_SPACE;
- sc->sc_iobus_space.bus_reverse = 1;
+
+ if (map == 1) {
+ sc->sc_membus_space.bus_base = MPC106_P_PCI_MEM_SPACE;
+ sc->sc_membus_space.bus_reverse = 1;
+ sc->sc_iobus_space.bus_base = MPC106_P_PCI_IO_SPACE;
+ sc->sc_iobus_space.bus_reverse = 1;
+ } else {
+ sc->sc_membus_space.bus_base =
+ MPC106_P_PCI_MEM_SPACE_MAP_B;
+ sc->sc_membus_space.bus_reverse = 1;
+ sc->sc_iobus_space.bus_base =
+ MPC106_P_PCI_IO_SPACE_MAP_B;
+ sc->sc_iobus_space.bus_reverse = 1;
+ }
lcp->lc_pc.pc_conf_v = lcp;
lcp->lc_pc.pc_attach_hook = mpc_attach_hook;
@@ -201,10 +268,27 @@ mpcpcibrattach(parent, self, aux)
lcp->lc_pc.pc_intr_string = mpc_intr_string;
lcp->lc_pc.pc_intr_establish = mpc_intr_establish;
lcp->lc_pc.pc_intr_disestablish = mpc_intr_disestablish;
+ if ( bus_space_map(&(sc->sc_iobus_space), 0, NBPG, 0,
+ &sc->ioh) != 0 )
+ {
+ panic("mpcpcibus: unable to map self\n");
+ }
- printf(": MPC106, Revision %x.\n",
- mpc_cfg_read_1(MPC106_PCI_REVID));
- mpc_cfg_write_2(MPC106_PCI_STAT, 0xff80); /* Reset status */
+
+ printf("iospace base %x ioh %x\n", sc->sc_iobus_space.bus_base,
+ sc->ioh);
+ printf(": %s, Revision %x. ", bridge, 0x999999);
+ if (map == 1) {
+ printf("Using Map A\n");
+ } else {
+ printf("Using Map B\n");
+ }
+#if 0
+ mpc_cfg_read_1(sc->sc_iobus_space, sc->ioh,
+ MPC106_PCI_REVID));
+ mpc_cfg_write_2(sc->sc_iobus_space, sc->ioh,
+ MPC106_PCI_STAT, 0xff80); /* Reset status */
+#endif
break;
default:
@@ -253,7 +337,7 @@ vtophys(p)
else {
pa = pmap_extract(vm_map_pmap(phys_map), va);
}
- return(pa | MPC106_PCI_CPUMEM);
+ return(pa | ((pci_map_a == 1) ? MPC106_PCI_CPUMEM : 0 ));
}
void
@@ -347,6 +431,7 @@ mpc_conf_read(cpv, tag, offset)
u_int32_t addr;
int device;
int s;
+ int handle;
if((tag >> 16) != 0)
return(~0);
@@ -358,15 +443,20 @@ mpc_conf_read(cpv, tag, offset)
device = (tag >> 11) & 0x1f;
if(device > 11)
return(~0); /* Outside config space */
+ printf("mpc_conf_read tag %x offset %x: ", tag, offset);
addr = (0x800 << device) | (tag & 0x380) | offset;
+ handle = ppc_open_pci_bridge();
s = splhigh();
- /* low 20 bits of address are in the actual address */
- data = in32rb(MPC106_PCI_CONF_SPACE | addr);
+ OF_call_method("config-l@", handle, 1, 1,
+ 0x80000000 | addr, &data);
splx(s);
+ ppc_close_pci_bridge(handle);
+ printf("data %x\n", data);
+
return(data);
}
@@ -380,16 +470,19 @@ mpc_conf_write(cpv, tag, offset, data)
u_int32_t addr;
int device;
int s;
+ int handle;
+ printf("mpc_conf_write tag %x offset %x data %x\n", tag, offset, data);
device = (tag >> 11) & 0x1f;
addr = (0x800 << device) | (tag & 0x380) | offset;
+ handle = ppc_open_pci_bridge();
s = splhigh();
- /* low 20 bits of address are in the actual address */
- out32rb(MPC106_PCI_CONF_SPACE | addr, data);
-
+ OF_call_method("config-l!", handle, 1, 1,
+ 0x80000000 | addr, &data);
splx(s);
+ ppc_close_pci_bridge(handle);
}
int
@@ -416,6 +509,8 @@ mpc_intr_map(lcv, bustag, buspin, line, ihp)
error = 1;
}
+#if 0
+ /* this hack belongs elsewhere */
if(system_type == POWER4e) {
pci_decompose_tag(pc, bustag, NULL, &device, NULL);
route = in32rb(MPC106_PCI_CONF_SPACE + 0x860);
@@ -457,6 +552,7 @@ mpc_intr_map(lcv, bustag, buspin, line, ihp)
isa_outb(0x04d1, lvl >> 8);
out32rb(MPC106_PCI_CONF_SPACE + 0x860, route);
}
+#endif
if(!error)
*ihp = line;
@@ -483,10 +579,11 @@ mpc_intr_establish(lcv, ih, level, func, arg, name)
void *arg;
char *name;
{
- if (ih == 0 || ih >= ICU_LEN || ih == 2)
- panic("pci_intr_establish: bogus handle 0x%x", ih);
-
+ printf("mpc_pintr_establish called for [%s]\n", name);
+ /*
return isabr_intr_establish(NULL, ih, IST_LEVEL, level, func, arg, name);
+ */
+ return NULL;
}
void
@@ -496,16 +593,18 @@ mpc_intr_disestablish(lcv, cookie)
/* XXX We should probably do something clever here.... later */
}
+#if 0
void
mpc_print_pci_stat()
{
u_int32_t stat;
- stat = mpc_cfg_read_4(MPC106_PCI_CMD);
+ stat = mpc_cfg_read_4(sc->sc_iobus_space, sc->ioh, MPC106_PCI_CMD);
printf("pci: status 0x%08x.\n", stat);
- stat = mpc_cfg_read_2(MPC106_PCI_STAT);
+ stat = mpc_cfg_read_2(sc->sc_iobus_space, sc->ioh, MPC106_PCI_STAT);
printf("pci: status 0x%04x.\n", stat);
}
+#endif
u_int32_t
pci_iack()
{
diff --git a/sys/arch/powerpc/pci/pci_machdep.h b/sys/arch/powerpc/pci/pci_machdep.h
index ea5c88e5dfa..01ed387d78d 100644
--- a/sys/arch/powerpc/pci/pci_machdep.h
+++ b/sys/arch/powerpc/pci/pci_machdep.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: pci_machdep.h,v 1.4 1998/08/06 15:04:01 pefo Exp $ */
+/* $OpenBSD: pci_machdep.h,v 1.5 1999/11/08 23:49:00 rahnds Exp $ */
/*
* Copyright (c) 1996 Carnegie-Mellon University.
@@ -34,15 +34,15 @@
/*
* Types provided to machine-independent PCI code
*/
-typedef struct p4e_pci_chipset *pci_chipset_tag_t;
+typedef struct ppc_pci_chipset *pci_chipset_tag_t;
typedef u_long pcitag_t;
typedef u_long pci_intr_handle_t;
/*
- * p4e-specific PCI structure and type definitions.
+ * ppc-specific PCI structure and type definitions.
* NOT TO BE USED DIRECTLY BY MACHINE INDEPENDENT CODE.
*/
-struct p4e_pci_chipset {
+struct ppc_pci_chipset {
void *pc_conf_v;
void (*pc_attach_hook) __P((struct device *,
struct device *, struct pcibus_attach_args *));
diff --git a/sys/arch/powerpc/pci/pcibrvar.h b/sys/arch/powerpc/pci/pcibrvar.h
index a5533a98de6..57f54fbd6a4 100644
--- a/sys/arch/powerpc/pci/pcibrvar.h
+++ b/sys/arch/powerpc/pci/pcibrvar.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: pcibrvar.h,v 1.2 1998/08/06 15:04:03 pefo Exp $ */
+/* $OpenBSD: pcibrvar.h,v 1.3 1999/11/08 23:49:00 rahnds Exp $ */
/*
* Copyright (c) 1997 Per Fogelstrom
@@ -35,15 +35,17 @@
struct pcibr_config {
bus_space_tag_t lc_iot;
bus_space_tag_t lc_memt;
- struct p4e_pci_chipset lc_pc;
+ struct ppc_pci_chipset lc_pc;
int pci_init_done;
};
struct pcibr_softc {
struct device sc_dev;
struct pcibr_config *sc_pcibr;
- struct p4e_bus_space sc_membus_space;
- struct p4e_bus_space sc_iobus_space;
+ struct ppc_bus_space sc_membus_space;
+ struct ppc_bus_space sc_iobus_space;
+ bus_space_handle_t ioh;
+
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 07:48:09 +0000