diff options
Diffstat (limited to 'sys/arch')
| -rw-r--r-- | sys/arch/mvme88k/conf/files.mvme88k | 6 | ||||
| -rw-r--r-- | sys/arch/mvme88k/ddb/db_interface.c | 11 | ||||
| -rw-r--r-- | sys/arch/mvme88k/dev/clock.c | 4 | ||||
| -rw-r--r-- | sys/arch/mvme88k/dev/if_ve.c | 4 | ||||
| -rw-r--r-- | sys/arch/mvme88k/dev/ssh.c | 4 | ||||
| -rw-r--r-- | sys/arch/mvme88k/dev/vs.c | 4 | ||||
| -rw-r--r-- | sys/arch/mvme88k/include/cmmu.h | 158 | ||||
| -rw-r--r-- | sys/arch/mvme88k/include/m88110.h | 316 | ||||
| -rw-r--r-- | sys/arch/mvme88k/include/m8820x.h | 105 | ||||
| -rw-r--r-- | sys/arch/mvme88k/mvme88k/cmmu.c | 762 | ||||
| -rw-r--r-- | sys/arch/mvme88k/mvme88k/locore_c_routines.c | 8 | ||||
| -rw-r--r-- | sys/arch/mvme88k/mvme88k/m197_cmmu.c | 800 | ||||
| -rw-r--r-- | sys/arch/mvme88k/mvme88k/m88110.c | 1085 | ||||
| -rw-r--r-- | sys/arch/mvme88k/mvme88k/m8820x.c (renamed from sys/arch/mvme88k/mvme88k/m18x_cmmu.c) | 1000 | ||||
| -rw-r--r-- | sys/arch/mvme88k/mvme88k/machdep.c | 13 | ||||
| -rw-r--r-- | sys/arch/mvme88k/mvme88k/pmap.c | 20 | ||||
| -rw-r--r-- | sys/arch/mvme88k/mvme88k/pmap_table.c | 5 | ||||
| -rw-r--r-- | sys/arch/mvme88k/mvme88k/process.S | 4 |
18 files changed, 1879 insertions, 2430 deletions
diff --git a/sys/arch/mvme88k/conf/files.mvme88k b/sys/arch/mvme88k/conf/files.mvme88k index d9e2a7510b2..88bafdcb011 100644 --- a/sys/arch/mvme88k/conf/files.mvme88k +++ b/sys/arch/mvme88k/conf/files.mvme88k @@ -1,4 +1,4 @@ -# $OpenBSD: files.mvme88k,v 1.18 2001/12/19 04:02:25 smurph Exp $ +# $OpenBSD: files.mvme88k,v 1.19 2001/12/22 09:49:38 smurph Exp $ # maxpartitions 16 @@ -88,8 +88,8 @@ file netns/ns_cksum.c ns file arch/mvme88k/mvme88k/autoconf.c file arch/mvme88k/mvme88k/conf.c file arch/mvme88k/mvme88k/cmmu.c -file arch/mvme88k/mvme88k/m18x_cmmu.c mvme187 | mvme188 -file arch/mvme88k/mvme88k/m197_cmmu.c mvme197 +file arch/mvme88k/mvme88k/m8820x.c mvme187 | mvme188 +file arch/mvme88k/mvme88k/m88110.c mvme197 file arch/mvme88k/mvme88k/disksubr.c file arch/mvme88k/mvme88k/dkbad.c file arch/mvme88k/mvme88k/eh.S diff --git a/sys/arch/mvme88k/ddb/db_interface.c b/sys/arch/mvme88k/ddb/db_interface.c index c58a5fca844..26cbda01048 100644 --- a/sys/arch/mvme88k/ddb/db_interface.c +++ b/sys/arch/mvme88k/ddb/db_interface.c @@ -1,4 +1,4 @@ -/* $OpenBSD: db_interface.c,v 1.23 2001/12/22 08:31:04 smurph Exp $ */ +/* $OpenBSD: db_interface.c,v 1.24 2001/12/22 09:49:39 smurph Exp $ */ /* * Mach Operating System * Copyright (c) 1993-1991 Carnegie Mellon University @@ -38,12 +38,11 @@ #include <uvm/uvm_extern.h> #include <machine/asm_macro.h> /* flush_pipeline() */ -#include <machine/m8820x.h> /* CMMU defs */ +#include <machine/cmmu.h> /* CMMU defs */ #include <machine/trap.h> /* current_thread() */ #include <machine/db_machdep.h> /* local ddb stuff */ #include <machine/bugio.h> /* bug routines */ #include <machine/locore.h> -#include <machine/mmu.h> #include <machine/cpu_number.h> #include <ddb/db_command.h> @@ -661,7 +660,9 @@ m88k_db_iflush(addr, have_addr, count, modif) char *modif; { addr = 0; +#ifdef may_be_removed cmmu_remote_set(addr, CMMU_SCR, 0, CMMU_FLUSH_CACHE_CBI_ALL); +#endif } /* flush dcache */ @@ -674,7 +675,9 @@ m88k_db_dflush(addr, have_addr, count, modif) char *modif; { addr = 0; +#ifdef may_be_removed cmmu_remote_set(addr, CMMU_SCR, 1, CMMU_FLUSH_CACHE_CBI_ALL); +#endif } /* probe my cache */ @@ -685,6 +688,7 @@ m88k_db_peek(addr, have_addr, count, modif) db_expr_t count; char *modif; { +#ifdef may_be_removed int pa12; int valmask; @@ -711,6 +715,7 @@ m88k_db_peek(addr, have_addr, count, modif) (unsigned)cmmu_remote_get(0, CMMU_CTP1, 0), (unsigned)cmmu_remote_get(0, CMMU_CTP2, 0), (unsigned)cmmu_remote_get(0, CMMU_CTP3, 0)); +#endif } diff --git a/sys/arch/mvme88k/dev/clock.c b/sys/arch/mvme88k/dev/clock.c index 15ff3fc734c..ebee2a4c254 100644 --- a/sys/arch/mvme88k/dev/clock.c +++ b/sys/arch/mvme88k/dev/clock.c @@ -1,4 +1,4 @@ -/* $OpenBSD: clock.c,v 1.16 2001/12/20 06:07:28 smurph Exp $ */ +/* $OpenBSD: clock.c,v 1.17 2001/12/22 09:49:39 smurph Exp $ */ /* * Copyright (c) 1999 Steve Murphree, Jr. * Copyright (c) 1995 Theo de Raadt @@ -96,7 +96,7 @@ #include <machine/autoconf.h> #include <machine/bugio.h> #include <machine/cpu.h> -#include <machine/mmu.h> /* DMA_CACHE_SYNC, etc... */ +#include <machine/cmmu.h> /* DMA_CACHE_SYNC, etc... */ #include "pcctwo.h" #if NPCCTWO > 0 #include <mvme88k/dev/pcctwofunc.h> diff --git a/sys/arch/mvme88k/dev/if_ve.c b/sys/arch/mvme88k/dev/if_ve.c index c8735e9e03e..66cf6fc8c43 100644 --- a/sys/arch/mvme88k/dev/if_ve.c +++ b/sys/arch/mvme88k/dev/if_ve.c @@ -1,4 +1,4 @@ -/* $OpenBSD: if_ve.c,v 1.13 2001/12/16 23:49:46 miod Exp $ */ +/* $OpenBSD: if_ve.c,v 1.14 2001/12/22 09:49:39 smurph Exp $ */ /*- * Copyright (c) 1999 Steve Murphree, Jr. * Copyright (c) 1982, 1992, 1993 @@ -71,7 +71,7 @@ #include <machine/autoconf.h> #include <machine/cpu.h> #include <machine/bugio.h> -#include <machine/mmu.h> /* DMA_CACHE_SYNC, etc... */ +#include <machine/cmmu.h> /* DMA_CACHE_SYNC, etc... */ #include <mvme88k/dev/if_vereg.h> #include <mvme88k/dev/if_vevar.h> diff --git a/sys/arch/mvme88k/dev/ssh.c b/sys/arch/mvme88k/dev/ssh.c index b407eb41ce9..631f48c6fdd 100644 --- a/sys/arch/mvme88k/dev/ssh.c +++ b/sys/arch/mvme88k/dev/ssh.c @@ -1,4 +1,4 @@ -/* $OpenBSD: ssh.c,v 1.10 2001/12/16 23:49:46 miod Exp $ */ +/* $OpenBSD: ssh.c,v 1.11 2001/12/22 09:49:39 smurph Exp $ */ /* * Copyright (c) 1994 Michael L. Hitch @@ -55,7 +55,7 @@ #include <uvm/uvm_pmap.h> #include <machine/autoconf.h> -#include <machine/mmu.h> +#include <machine/cmmu.h> #include <machine/pmap.h> #include <scsi/scsi_all.h> diff --git a/sys/arch/mvme88k/dev/vs.c b/sys/arch/mvme88k/dev/vs.c index 85de6f4fd2c..284061c3eb5 100644 --- a/sys/arch/mvme88k/dev/vs.c +++ b/sys/arch/mvme88k/dev/vs.c @@ -1,4 +1,4 @@ -/* $OpenBSD: vs.c,v 1.13 2001/12/16 23:49:46 miod Exp $ */ +/* $OpenBSD: vs.c,v 1.14 2001/12/22 09:49:39 smurph Exp $ */ /* * Copyright (c) 1999 Steve Murphree, Jr. @@ -61,7 +61,7 @@ #include <mvme88k/dev/vsreg.h> #include <mvme88k/dev/vsvar.h> #include <mvme88k/dev/vme.h> /* vme_findvec() */ -#include <machine/mmu.h> /* DMA_CACHE_SYNC, etc... */ +#include <machine/cmmu.h> /* DMA_CACHE_SYNC, etc... */ #else #include <mvme68k/dev/vsreg.h> #include <mvme68k/dev/vsvar.h> diff --git a/sys/arch/mvme88k/include/cmmu.h b/sys/arch/mvme88k/include/cmmu.h index cb81f1f55ad..4428ed13348 100644 --- a/sys/arch/mvme88k/include/cmmu.h +++ b/sys/arch/mvme88k/include/cmmu.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cmmu.h,v 1.9 2001/12/16 23:49:46 miod Exp $ */ +/* $OpenBSD: cmmu.h,v 1.10 2001/12/22 09:49:39 smurph Exp $ */ /* * Mach Operating System * Copyright (c) 1993-1992 Carnegie Mellon University @@ -28,6 +28,8 @@ #ifndef _MACHINE_CMMU_H_ #define _MACHINE_CMMU_H_ +#include <machine/mmu.h> + /* Area Description */ #define AREA_D_WT 0x00000200 /* write through */ #define AREA_D_G 0x00000080 /* global */ @@ -58,70 +60,106 @@ extern unsigned cpu_sets[MAX_CPUS]; extern int cpu_cmmu_ratio; extern unsigned number_cpus, master_cpu; extern unsigned cache_policy; +extern unsigned number_cpus; +extern unsigned master_cpu; extern int max_cpus, max_cmmus; -#ifdef CMMU_DEBUG -void show_apr(unsigned value); -void show_sctr(unsigned value); -#endif - -#ifdef DDB -void cmmu_show_translation(unsigned, unsigned, unsigned, int); -void cmmu_cache_state(unsigned, unsigned); -void show_cmmu_info(unsigned); -#endif - /* - * Prototypes from "mvme88k/mvme88k/cmmu.c" + * This lock protects the cmmu SAR and SCR's; other ports + * can be accessed without locking it + * + * May be used from "db_interface.c". */ - -unsigned cmmu_cpu_number(void); -unsigned cmmu_remote_get(unsigned cpu, unsigned r, unsigned data); -unsigned cmmu_get_idr(unsigned data); -void cmmu_init(void); -void cmmu_shutdown_now(void); -void cmmu_parity_enable(void); -void setup_board_config(void); -void setup_cmmu_config(void); -void cmmu_dump_config(void); -unsigned cmmu_get_by_mode(int cpu, int mode); -void cpu_configuration_print(int master); -void dma_cachectl(vm_offset_t va, int size, int op); -void cmmu_remote_set(unsigned cpu, unsigned r, unsigned data, unsigned x); -void cmmu_set_sapr(unsigned ap); -void cmmu_remote_set_sapr(unsigned cpu, unsigned ap); -void cmmu_set_uapr(unsigned ap); -void cmmu_flush_tlb(unsigned kernel, vm_offset_t vaddr, int size); -void cmmu_flush_remote_cache(int cpu, vm_offset_t physaddr, int size); -void cmmu_flush_cache(vm_offset_t physaddr, int size); -void cmmu_flush_remote_inst_cache(int cpu, vm_offset_t physaddr, int size); -void cmmu_flush_inst_cache(vm_offset_t physaddr, int size); -void cmmu_flush_remote_data_cache(int cpu, vm_offset_t physaddr, int size); -void cmmu_flush_data_cache(vm_offset_t physaddr, int size); - -void cmmu_pmap_activate( - unsigned cpu, - unsigned uapr, - batc_template_t i_batc[BATC_MAX], - batc_template_t d_batc[BATC_MAX]); - -void cmmu_flush_remote_tlb( - unsigned cpu, - unsigned kernel, - vm_offset_t vaddr, - int size); - -void cmmu_set_batc_entry( - unsigned cpu, - unsigned entry_no, - unsigned data, /* 1 = data, 0 = instruction */ - unsigned value); /* the value to stuff into the batc */ - -void cmmu_set_pair_batc_entry( - unsigned cpu, - unsigned entry_no, - unsigned value); /* the value to stuff into the batc */ +extern struct simplelock cmmu_cpu_lock; + +#define CMMU_LOCK simple_lock(&cmmu_cpu_lock) +#define CMMU_UNLOCK simple_unlock(&cmmu_cpu_lock) + +/* machine dependant cmmu function pointer structure */ +struct cmmu_p { + void (*cmmu_init_func) __P((void)); + void (*show_apr_func) __P((unsigned)); + void (*setup_board_config_func) __P((void)); + void (*setup_cmmu_config_func) __P((void)); + void (*cmmu_dump_config_func) __P((void)); + void (*cpu_configuration_print_func) __P((int)); + void (*cmmu_shutdown_now_func) __P((void)); + void (*cmmu_parity_enable_func) __P((void)); + unsigned (*cmmu_cpu_number_func) __P((void)); + unsigned (*cmmu_get_idr_func) __P((unsigned)); + void (*cmmu_set_sapr_func) __P((unsigned)); + void (*cmmu_remote_set_sapr_func) __P((unsigned, unsigned)); + void (*cmmu_set_uapr_func) __P((unsigned)); + void (*cmmu_set_batc_entry_func) __P((unsigned, unsigned, unsigned, unsigned)); + void (*cmmu_set_pair_batc_entry_func) __P((unsigned, unsigned, unsigned)); + void (*cmmu_flush_remote_tlb_func) __P((unsigned, unsigned, vm_offset_t, int)); + void (*cmmu_flush_tlb_func) __P((unsigned, vm_offset_t, int)); + void (*cmmu_pmap_activate_func) __P((unsigned, unsigned, + batc_template_t i_batc[BATC_MAX], + batc_template_t d_batc[BATC_MAX])); + void (*cmmu_flush_remote_cache_func) __P((int, vm_offset_t, int)); + void (*cmmu_flush_cache_func) __P((vm_offset_t, int)); + void (*cmmu_flush_remote_inst_cache_func) __P((int, vm_offset_t, int)); + void (*cmmu_flush_inst_cache_func) __P((vm_offset_t, int)); + void (*cmmu_flush_remote_data_cache_func) __P((int, vm_offset_t, int)); + void (*cmmu_flush_data_cache_func) __P((vm_offset_t, int)); + void (*dma_cachectl_func) __P((vm_offset_t, int, int)); +#ifdef DDB + unsigned (*cmmu_get_by_mode_func) __P((int, int)); + void (*cmmu_show_translation_func) __P((unsigned, unsigned, unsigned, int)); + void (*cmmu_cache_state_func) __P((unsigned, unsigned)); + void (*show_cmmu_info_func) __P((unsigned)); +#endif /* end if DDB */ +}; + +/* THE pointer! */ +extern struct cmmu_p *cmmu; + +extern struct cmmu_p cmmu88110; +extern struct cmmu_p cmmu8820x; + +/* The macros... */ +#define cmmu_init (cmmu->cmmu_init_func) +#define show_apr(ap) (cmmu->show_apr_func)(ap) +#define setup_board_config (cmmu->setup_board_config_func) +#define setup_cmmu_config (cmmu->setup_cmmu_config_func) +#define cmmu_dump_config (cmmu->cmmu_dump_config_func) +#define cpu_configuration_print(a) (cmmu->cpu_configuration_print_func)(a) +#define cmmu_shutdown_now (cmmu->cmmu_shutdown_now_func) +#define cmmu_parity_enable (cmmu->cmmu_parity_enable_func) +#define cmmu_cpu_number (cmmu->cmmu_cpu_number_func) +#define cmmu_get_idr(a) (cmmu->cmmu_get_idr_func)(a) +#define cmmu_set_sapr(a) (cmmu->cmmu_set_sapr_func)(a) +#define cmmu_remote_set_sapr(a, b) (cmmu->cmmu_remote_set_sapr_func)(a, b) +#define cmmu_set_uapr(a) (cmmu->cmmu_set_uapr_func)(a) +#define cmmu_set_batc_entry(a, b, c, d) (cmmu->cmmu_set_batc_entry_func)(a, b, c, d) +#define cmmu_set_pair_batc_entry(a, b, c) (cmmu->cmmu_set_pair_batc_entry_func)(a, b, c) +#define cmmu_flush_remote_tlb(a, b, c, d) (cmmu->cmmu_flush_remote_tlb_func)(a, b, c, d) +#define cmmu_flush_tlb(a, b, c) (cmmu->cmmu_flush_tlb_func)(a, b, c) +#define cmmu_pmap_activate(a, b, c, d) (cmmu->cmmu_pmap_activate_func)(a, b, c, d) +#define cmmu_flush_remote_cache(a, b, c) (cmmu->cmmu_flush_remote_cache_func)(a, b, c) +#define cmmu_flush_cache(a, b) (cmmu->cmmu_flush_cache_func)(a, b) +#define cmmu_flush_remote_inst_cache(a, b, c) (cmmu->cmmu_flush_remote_inst_cache_func)(a, b, c) +#define cmmu_flush_inst_cache(a, b) (cmmu->cmmu_flush_inst_cache_func)(a, b) +#define cmmu_flush_remote_data_cache(a, b, c) (cmmu->cmmu_flush_remote_data_cache_func)(a, b, c) +#define cmmu_flush_data_cache(a, b) (cmmu->cmmu_flush_data_cache_func)(a, b) +#define dma_cachectl(a, b, c) (cmmu->dma_cachectl_func)(a, b, c) +#ifdef DDB +#define cmmu_get_by_mode(a, b) (cmmu->cmmu_get_by_mode_func)(a, b) +#define cmmu_show_translation(a, b, c, d) (cmmu->cmmu_show_translation_func)(a, b, c, d) +#define cmmu_cache_state(a, b) (cmmu->cmmu_cache_state_func)(a, b) +#define show_cmmu_info(a) (cmmu->show_cmmu_info_func)(a) +#endif /* end if DDB */ #endif /* _LOCORE */ +#ifdef M88100 +#include <machine/m8820x.h> +#endif /* M88100 */ +#ifdef M88110 +#include <machine/m88110.h> +#include <machine/m88410.h> +#endif /* M88110 */ + #endif /* _MACHINE_CMMU_H_ */ + diff --git a/sys/arch/mvme88k/include/m88110.h b/sys/arch/mvme88k/include/m88110.h index 7be6627c784..2190b51aa25 100644 --- a/sys/arch/mvme88k/include/m88110.h +++ b/sys/arch/mvme88k/include/m88110.h @@ -1,16 +1,13 @@ -/* $OpenBSD: m88110.h,v 1.10 2001/12/16 23:49:46 miod Exp $ */ +/* $OpenBSD: m88110.h,v 1.11 2001/12/22 09:49:39 smurph Exp $ */ #ifndef __MACHINE_M88110_H__ #define __MACHINE_M88110_H__ +#include <uvm/uvm_extern.h> #ifndef _LOCORE # include <machine/mmu.h> /* batc_template_t */ #endif -#include <machine/board.h> -#include <machine/cmmu.h> -#include <uvm/uvm_extern.h> - /* * 88110 CMMU definitions */ @@ -79,6 +76,11 @@ #define CMMU_DCMD_INV_SATC 0x00A /* Invalidate All Supervisor ATCs */ #define CMMU_DCMD_INV_UATC 0x00B /* Invalidate All User ATCs */ +#define CMMU_DCTL_RSVD7 0x40000 /* Reserved */ +#define CMMU_DCTL_RSVD6 0x20000 /* Reserved */ +#define CMMU_DCTL_RSVD5 0x10000 /* Reserved */ +#define CMMU_DCTL_RSVD4 0x8000 /* Reserved */ +#define CMMU_DCTL_RSVD3 0x4000 /* Reserved */ #define CMMU_DCTL_XMEM 0x2000 /* store -> load sequence */ #define CMMU_DCTL_DEN 0x1000 /* Decoupled Cache Access Enable */ #define CMMU_DCTL_FWT 0x0800 /* Force Write Through */ @@ -88,6 +90,9 @@ #define CMMU_DCTL_FRZ1 0x0080 /* Data Cache Freeze Bank 1 */ #define CMMU_DCTL_HTEN 0x0040 /* Hardware Table Search Enable */ #define CMMU_DCTL_MEN 0x0020 /* Data MMU Enable */ +#define CMMU_DCTL_RSVD2 0x0010 /* Reserved */ +#define CMMU_DCTL_ADS 0x0008 /* Allocat Disable */ +#define CMMU_DCTL_RSVD1 0x0004 /* Reserved */ #define CMMU_DCTL_SEN 0x0002 /* Data Cache Snoop Enable */ #define CMMU_DCTL_CEN 0x0001 /* Data Cache Enable */ @@ -110,126 +115,205 @@ #define CMMU_DATA 1 #define CMMU_INST 0 +/* definitions for use of the BATC */ +#define BATC_512K (0x00 << 19) +#define BATC_1M (0x01 << 19) +#define BATC_2M (0x03 << 19) +#define BATC_4M (0x07 << 19) +#define BATC_8M (0x0F << 19) +#define BATC_16M (0x1F << 19) +#define BATC_32M (0x3F << 19) +#define BATC_64M (0x7F << 19) +#define BATC_ADDR_MASK 0xFFF80000 +#define BATC_ADDR_SHIFT 13 +#define BATC_LBA_SHIFT 19 +#define BATC_PBA_SHIFT 6 +#define BATC_SU 0x20 +#define BATC_WT 0x10 +#define BATC_G 0x08 +#define BATC_CI 0x04 +#define BATC_WP 0x02 +#define BATC_V 0x01 + +#define CLINE_MASK 0x1F +#define CLINE_SIZE (8 * 32) + #ifndef _LOCORE + /* - * Prototypes from "mvme88k/mvme88k/m197_cmmu.c" + * Prototypes from "mvme88k/mvme88k/m88110_cmmu.c" */ +void m88110_show_apr __P((unsigned)); +void m88110_show_sctr __P((unsigned)); +void m88110_setup_board_config __P((void)); +void m88110_setup_cmmu_config __P((void)); +void m88110_cmmu_dump_config __P((void)); +void m88110_cpu_configuration_print __P((int)); +void m88110_cmmu_shutdown_now __P((void)); +void m88110_cmmu_parity_enable __P((void)); +unsigned m88110_cmmu_cpu_number __P((void)); +unsigned m88110_cmmu_get_idr __P((unsigned)); +void m88110_cmmu_set_sapr __P((unsigned)); +void m88110_cmmu_remote_set_sapr __P((unsigned, unsigned)); +void m88110_cmmu_set_uapr __P((unsigned)); +void m88110_cmmu_set_batc_entry __P((unsigned, unsigned, unsigned, unsigned)); +void m88110_cmmu_set_pair_batc_entry __P((unsigned, unsigned, unsigned)); +void m88110_cmmu_flush_remote_tlb __P((unsigned, unsigned, vm_offset_t, int)); +void m88110_cmmu_flush_tlb __P((unsigned, vm_offset_t, int)); +void m88110_cmmu_pmap_activate __P((unsigned, unsigned, + batc_template_t i_batc[BATC_MAX], + batc_template_t d_batc[BATC_MAX])); +void m88110_cmmu_flush_remote_cache __P((int, vm_offset_t, int)); +void m88110_cmmu_flush_cache __P((vm_offset_t, int)); +void m88110_cmmu_flush_remote_inst_cache __P((int, vm_offset_t, int)); +void m88110_cmmu_flush_inst_cache __P((vm_offset_t, int)); +void m88110_cmmu_flush_remote_data_cache __P((int, vm_offset_t, int)); +void m88110_cmmu_flush_data_cache __P((vm_offset_t, int)); +void m88110_dma_cachectl __P((vm_offset_t, int, int)); -#ifdef DDB -void m197_cmmu_show_translation(unsigned, unsigned, unsigned, int); -void m197_cmmu_cache_state(unsigned, unsigned); -void m197_show_cmmu_info(unsigned); +#if DDB +unsigned m88110_cmmu_get_by_mode __P((int, int)); +void m88110_cmmu_show_translation __P((unsigned, unsigned, unsigned, int)); +void m88110_cmmu_cache_state __P((unsigned, unsigned)); +void m88110_show_cmmu_info __P((unsigned)); #endif -#ifdef CMMU_DEBUG -void m197_show_apr(unsigned value); -void m197_show_sctr(unsigned value); -#endif +void m88110_cmmu_init __P((void)); +int m88110_table_search __P((pmap_t, vm_offset_t, int, int, int)); -unsigned m197_cmmu_cpu_number(void); -unsigned m197_cmmu_remote_get(unsigned cpu, unsigned r, unsigned data); -unsigned m197_cmmu_get_idr(unsigned data); -void m197_cmmu_init(void); -void m197_cmmu_shutdown_now(void); -void m197_cmmu_parity_enable(void); -void m197_setup_board_config(void); -void m197_setup_cmmu_config(void); -void m197_cmmu_dump_config(void); -unsigned m197_cmmu_get_by_mode(int cpu, int mode); -void m197_cpu_configuration_print(int master); -void m197_dma_cachectl(vm_offset_t va, int size, int op); -void m197_cmmu_remote_set(unsigned cpu, unsigned r, unsigned data, unsigned x); -void m197_cmmu_set_sapr(unsigned ap); -void m197_cmmu_remote_set_sapr(unsigned cpu, unsigned ap); -void m197_cmmu_set_uapr(unsigned ap); -void m197_cmmu_flush_tlb(unsigned kernel, vm_offset_t vaddr, int size); -void m197_cmmu_flush_remote_cache(int cpu, vm_offset_t physaddr, int size); -void m197_cmmu_flush_cache(vm_offset_t physaddr, int size); -void m197_cmmu_flush_remote_inst_cache(int cpu, vm_offset_t physaddr, int size); -void m197_cmmu_flush_inst_cache(vm_offset_t physaddr, int size); -void m197_cmmu_flush_remote_data_cache(int cpu, vm_offset_t physaddr, int size); -void m197_cmmu_flush_data_cache(vm_offset_t physaddr, int size); - -void m197_cmmu_pmap_activate( - unsigned cpu, - unsigned uapr, - batc_template_t i_batc[BATC_MAX], - batc_template_t d_batc[BATC_MAX]); - -void m197_cmmu_flush_remote_tlb( - unsigned cpu, - unsigned kernel, - vm_offset_t vaddr, - int size); - -void m197_cmmu_set_batc_entry( - unsigned cpu, - unsigned entry_no, - unsigned data, /* 1 = data, 0 = instruction */ - unsigned value); /* the value to stuff into the batc */ - -void m197_cmmu_set_pair_batc_entry( - unsigned cpu, - unsigned entry_no, - unsigned value); /* the value to stuff into the batc */ - -int m197_table_search( - pmap_t map, - vm_offset_t virt, - int write, - int user, int data); - -void set_icmd (unsigned value); -void set_ictl (unsigned value); -void set_isar (unsigned value); -void set_isap (unsigned value); -void set_iuap (unsigned value); -void set_iir (unsigned value); -void set_ibp (unsigned value); -void set_ippu (unsigned value); -void set_ippl (unsigned value); -void set_isr (unsigned value); -void set_ilar (unsigned value); -void set_ipar (unsigned value); -void set_dcmd (unsigned value); -void set_dctl (unsigned value); -void set_dsar (unsigned value); -void set_dsap (unsigned value); -void set_duap (unsigned value); -void set_dir (unsigned value); -void set_dbp (unsigned value); -void set_dppu (unsigned value); -void set_dppl (unsigned value); -void set_dsr (unsigned value); -void set_dlar (unsigned value); -void set_dpar (unsigned value); +void set_icmd __P((unsigned value)); +void set_ictl __P((unsigned value)); +void set_isar __P((unsigned value)); +void set_isap __P((unsigned value)); +void set_iuap __P((unsigned value)); +void set_iir __P((unsigned value)); +void set_ibp __P((unsigned value)); +void set_ippu __P((unsigned value)); +void set_ippl __P((unsigned value)); +void set_isr __P((unsigned value)); +void set_ilar __P((unsigned value)); +void set_ipar __P((unsigned value)); +void set_dcmd __P((unsigned value)); +void set_dctl __P((unsigned value)); +void set_dsar __P((unsigned value)); +void set_dsap __P((unsigned value)); +void set_duap __P((unsigned value)); +void set_dir __P((unsigned value)); +void set_dbp __P((unsigned value)); +void set_dppu __P((unsigned value)); +void set_dppl __P((unsigned value)); +void set_dsr __P((unsigned value)); +void set_dlar __P((unsigned value)); +void set_dpar __P((unsigned value)); /* get routines */ -unsigned get_icmd (void); -unsigned get_ictl (void); -unsigned get_isar (void); -unsigned get_isap (void); -unsigned get_iuap (void); -unsigned get_iir (void); -unsigned get_ibp (void); -unsigned get_ippu (void); -unsigned get_ippl (void); -unsigned get_isr (void); -unsigned get_ilar (void); -unsigned get_ipar (void); -unsigned get_dcmd (void); -unsigned get_dctl (void); -unsigned get_dsar (void); -unsigned get_dsap (void); -unsigned get_duap (void); -unsigned get_dir (void); -unsigned get_dbp (void); -unsigned get_dppu (void); -unsigned get_dppl (void); -unsigned get_dsr (void); -unsigned get_dlar (void); -unsigned get_dpar (void); +unsigned get_icmd __P((void)); +unsigned get_ictl __P((void)); +unsigned get_isar __P((void)); +unsigned get_isap __P((void)); +unsigned get_iuap __P((void)); +unsigned get_iir __P((void)); +unsigned get_ibp __P((void)); +unsigned get_ippu __P((void)); +unsigned get_ippl __P((void)); +unsigned get_isr __P((void)); +unsigned get_ilar __P((void)); +unsigned get_ipar __P((void)); +unsigned get_dcmd __P((void)); +unsigned get_dctl __P((void)); +unsigned get_dsar __P((void)); +unsigned get_dsap __P((void)); +unsigned get_duap __P((void)); +unsigned get_dir __P((void)); +unsigned get_dbp __P((void)); +unsigned get_dppu __P((void)); +unsigned get_dppl __P((void)); +unsigned get_dsr __P((void)); +unsigned get_dlar __P((void)); +unsigned get_dpar __P((void)); -#endif /* _LOCORE */ +/* Cache inlines */ + +#define line_addr(x) (vm_offset_t)((x) & ~CLINE_MASK) +#define page_addr(x) (vm_offset_t)((x) & ~PAGE_MASK) + +static __inline__ void mc88110_flush_data_line(vm_offset_t x) +{ + unsigned dctl = get_dctl(); + if (dctl & CMMU_DCTL_CEN){ + set_dsar(line_addr(x)); + set_dcmd(CMMU_DCMD_FLUSH_LINE); + } +} +static __inline__ void mc88110_flush_data_page(vm_offset_t x) +{ + unsigned dctl = get_dctl(); + if (dctl & CMMU_DCTL_CEN){ + set_dsar(page_addr(x)); + set_dcmd(CMMU_DCMD_FLUSH_PG); + } +} + +static __inline__ void mc88110_flush_data(void) +{ + unsigned dctl = get_dctl(); + if (dctl & CMMU_DCTL_CEN){ + set_dsar(0x00); + set_dcmd(CMMU_DCMD_FLUSH_ALL); + } +} + +static __inline__ void mc88110_inval_data_line(vm_offset_t x) +{ + set_dsar(line_addr(x)); + set_dcmd(CMMU_DCMD_INV_LINE); +} + +static __inline__ void mc88110_inval_data(void) +{ + set_dsar(0x00); + set_dcmd(CMMU_DCMD_INV_ALL); +} + +static __inline__ void mc88110_sync_data_line(vm_offset_t x) +{ + unsigned dctl = get_dctl(); + if (dctl & CMMU_DCTL_CEN){ + set_dsar(line_addr(x)); + set_dcmd(CMMU_DCMD_FLUSH_LINE_INV); + } +} + +static __inline__ void mc88110_sync_data_page(vm_offset_t x) +{ + unsigned dctl = get_dctl(); + if (dctl & CMMU_DCTL_CEN){ + set_dsar(page_addr(x)); + set_dcmd(CMMU_DCMD_FLUSH_PG_INV); + } +} + +static __inline__ void mc88110_sync_data(void) +{ + unsigned dctl = get_dctl(); + if (dctl & CMMU_DCTL_CEN){ + set_dsar(0x00); + set_dcmd(CMMU_DCMD_FLUSH_ALL_INV); + } +} + +static __inline__ void mc88110_inval_inst_line(vm_offset_t x) +{ + set_isar(line_addr(x)); + set_icmd(CMMU_ICMD_INV_LINE); +} + +static __inline__ void mc88110_inval_inst(void) +{ + set_isar(0x00); + set_icmd(CMMU_ICMD_INV_ITIC); +} + +#endif /* _LOCORE */ #endif /* __MACHINE_M88110_H__ */ diff --git a/sys/arch/mvme88k/include/m8820x.h b/sys/arch/mvme88k/include/m8820x.h index 3b8c03ab510..64535a472dc 100644 --- a/sys/arch/mvme88k/include/m8820x.h +++ b/sys/arch/mvme88k/include/m8820x.h @@ -1,4 +1,4 @@ -/* $OpenBSD: m8820x.h,v 1.4 2001/12/22 07:35:43 smurph Exp $ */ +/* $OpenBSD: m8820x.h,v 1.5 2001/12/22 09:49:39 smurph Exp $ */ /* * Mach Operating System * Copyright (c) 1993-1992 Carnegie Mellon University @@ -30,15 +30,8 @@ */ -#ifndef __MACHINE_M882XX_H__ -#define __MACHINE_M882XX_H__ - -#ifndef _LOCORE -# include <machine/mmu.h> /* batc_template_t */ -#endif - -#include <machine/board.h> -#include <machine/cmmu.h> +#ifndef __MACHINE_M8820X_H__ +#define __MACHINE_M8820X_H__ /* * 88200 CMMU definitions @@ -133,65 +126,43 @@ #ifndef _LOCORE /* - * Prototypes from "mvme88k/mvme88k/m18x_cmmu.c" + * Prototypes from "mvme88k/mvme88k/m8820x.c" */ -#ifdef DDB -void m18x_cmmu_show_translation(unsigned, unsigned, unsigned, int); -void m18x_cmmu_cache_state(unsigned, unsigned); -void m18x_show_cmmu_info(unsigned); -#endif - -#ifdef CMMU_DEBUG -void m18x_show_apr(unsigned value); -void m18x_show_sctr(unsigned value); -#endif - -unsigned m18x_cmmu_cpu_number(void); -unsigned m18x_cmmu_remote_get(unsigned cpu, unsigned r, unsigned data); -unsigned m18x_cmmu_get_idr(unsigned data); -void m18x_cmmu_init(void); -void m18x_cmmu_shutdown_now(void); -void m18x_cmmu_parity_enable(void); -void m18x_setup_board_config(void); -void m18x_setup_cmmu_config(void); -void m18x_cmmu_dump_config(void); -unsigned m18x_cmmu_get_by_mode(int cpu, int mode); -void m18x_cpu_configuration_print(int master); -void m18x_dma_cachectl(vm_offset_t va, int size, int op); -void m18x_cmmu_remote_set(unsigned cpu, unsigned r, unsigned data, unsigned x); -void m18x_cmmu_set_sapr(unsigned ap); -void m18x_cmmu_remote_set_sapr(unsigned cpu, unsigned ap); -void m18x_cmmu_set_uapr(unsigned ap); -void m18x_cmmu_flush_tlb(unsigned kernel, vm_offset_t vaddr, int size); -void m18x_cmmu_flush_remote_cache(int cpu, vm_offset_t physaddr, int size); -void m18x_cmmu_flush_cache(vm_offset_t physaddr, int size); -void m18x_cmmu_flush_remote_inst_cache(int cpu, vm_offset_t physaddr, int size); -void m18x_cmmu_flush_inst_cache(vm_offset_t physaddr, int size); -void m18x_cmmu_flush_remote_data_cache(int cpu, vm_offset_t physaddr, int size); -void m18x_cmmu_flush_data_cache(vm_offset_t physaddr, int size); - -void m18x_cmmu_pmap_activate( - unsigned cpu, - unsigned uapr, +void m8820x_show_apr __P((unsigned)); +void m8820x_setup_board_config __P((void)); +void m8820x_setup_cmmu_config __P((void)); +void m8820x_cmmu_dump_config __P((void)); +void m8820x_cpu_configuration_print __P((int)); +void m8820x_cmmu_shutdown_now __P((void)); +void m8820x_cmmu_parity_enable __P((void)); +unsigned m8820x_cmmu_cpu_number __P((void)); +unsigned m8820x_cmmu_get_idr __P((unsigned)); +void m8820x_cmmu_set_sapr __P((unsigned)); +void m8820x_cmmu_remote_set_sapr __P((unsigned, unsigned)); +void m8820x_cmmu_set_uapr __P((unsigned)); +void m8820x_cmmu_set_batc_entry __P((unsigned, unsigned, unsigned, unsigned)); +void m8820x_cmmu_set_pair_batc_entry __P((unsigned, unsigned, unsigned)); +void m8820x_cmmu_flush_remote_tlb __P((unsigned, unsigned, vm_offset_t, int)); +void m8820x_cmmu_flush_tlb __P((unsigned, vm_offset_t, int)); +void m8820x_cmmu_pmap_activate __P((unsigned, unsigned, batc_template_t i_batc[BATC_MAX], - batc_template_t d_batc[BATC_MAX]); - -void m18x_cmmu_flush_remote_tlb( - unsigned cpu, - unsigned kernel, - vm_offset_t vaddr, - int size); - -void m18x_cmmu_set_batc_entry( - unsigned cpu, - unsigned entry_no, - unsigned data, /* 1 = data, 0 = instruction */ - unsigned value); /* the value to stuff into the batc */ + batc_template_t d_batc[BATC_MAX])); +void m8820x_cmmu_flush_remote_cache __P((int, vm_offset_t, int)); +void m8820x_cmmu_flush_cache __P((vm_offset_t, int)); +void m8820x_cmmu_flush_remote_inst_cache __P((int, vm_offset_t, int)); +void m8820x_cmmu_flush_inst_cache __P((vm_offset_t, int)); +void m8820x_cmmu_flush_remote_data_cache __P((int, vm_offset_t, int)); +void m8820x_cmmu_flush_data_cache __P((vm_offset_t, int)); +void m8820x_dma_cachectl __P((vm_offset_t, int, int)); + +#if DDB +unsigned m8820x_cmmu_get_by_mode __P((int, int)); +void m8820x_cmmu_show_translation __P((unsigned, unsigned, unsigned, int)); +void m8820x_cmmu_cache_state __P((unsigned, unsigned)); +void m8820x_show_cmmu_info __P((unsigned)); +#endif -void m18x_cmmu_set_pair_batc_entry( - unsigned cpu, - unsigned entry_no, - unsigned value); /* the value to stuff into the batc */ +void m8820x_cmmu_init __P((void)); #endif /* _LOCORE */ @@ -245,4 +216,4 @@ void m18x_cmmu_set_pair_batc_entry( #define NBSG (4*1024*1024) /* segment size */ -#endif /* __MACHINE_M882XX_H__ */ +#endif /* __MACHINE_M8820X_H__ */ diff --git a/sys/arch/mvme88k/mvme88k/cmmu.c b/sys/arch/mvme88k/mvme88k/cmmu.c index c54d8f7d4c6..3caee10274c 100644 --- a/sys/arch/mvme88k/mvme88k/cmmu.c +++ b/sys/arch/mvme88k/mvme88k/cmmu.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cmmu.c,v 1.18 2001/12/22 07:35:43 smurph Exp $ */ +/* $OpenBSD: cmmu.c,v 1.19 2001/12/22 09:49:39 smurph Exp $ */ /* * Copyright (c) 1998 Steve Murphree, Jr. * Copyright (c) 1996 Nivas Madhur @@ -60,18 +60,9 @@ #include <sys/param.h> #include <sys/types.h> #include <sys/simplelock.h> - -#include <machine/mmu.h> -#include <machine/board.h> #include <machine/cmmu.h> #include <machine/cpus.h> #include <machine/cpu_number.h> -#ifdef M88100 -#include <machine/m8820x.h> -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 -#include <machine/m88110.h> -#endif /* MVME197 */ /* * This lock protects the cmmu SAR and SCR's; other ports @@ -80,10 +71,6 @@ * May be used from "db_interface.c". */ struct simplelock cmmu_cpu_lock; - -#define CMMU_LOCK simple_lock(&cmmu_cpu_lock) -#define CMMU_UNLOCK simple_unlock(&cmmu_cpu_lock) - unsigned cache_policy = /*CACHE_INH*/ 0; unsigned cpu_sets[MAX_CPUS]; unsigned number_cpus = 0; @@ -91,751 +78,14 @@ unsigned master_cpu = 0; int max_cpus, max_cmmus; int cpu_cmmu_ratio; -#ifdef CMMU_DEBUG -void -show_apr(unsigned value) -{ - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_show_apr(value); - break; -#endif -#ifdef M88110 - case CPU_88110: - m197_show_apr(value); - break; -#endif - } -} - -void -show_sctr(unsigned value) -{ - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_show_sctr(value); - break; -#endif -#ifdef M88110 - case CPU_88110: - m197_show_sctr(value); - break; -#endif - } -} -#endif /* CMMU_DEBUG */ - -void -setup_board_config(void) -{ - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_setup_board_config(); - break; -#endif -#ifdef M88110 - case CPU_88110: - m197_setup_board_config(); - break; -#endif - } -} - -void -setup_cmmu_config(void) -{ - int cpu; - - for (cpu = 0; cpu < MAX_CPUS; cpu++) - cpu_sets[cpu] = 0; - - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_setup_cmmu_config(); - break; -#endif -#ifdef M88110 - case CPU_88110: - m197_setup_cmmu_config(); - break; -#endif - } -} - -void -cmmu_dump_config(void) -{ - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_cmmu_dump_config(); - break; -#endif -#ifdef M88110 - case CPU_88110: - m197_cmmu_dump_config(); - break; -#endif - } -} +struct cmmu_p *cmmu; -#ifdef DDB -/* - * Used by DDB for cache probe functions - */ -unsigned -cmmu_get_by_mode(int cpu, int mode) -{ - unsigned retval; - CMMU_LOCK; - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - retval = m18x_cmmu_get_by_mode(cpu, mode); - break; -#endif -#ifdef M88110 - case CPU_88110: - retval = m197_cmmu_get_by_mode(cpu, mode); - break; -#endif - } - CMMU_UNLOCK; - return retval; -} -#endif +void md_cmmu_flush_tlb __P((unsigned kernel, vm_offset_t vaddr, int size)); -/* - * Should only be called after the calling cpus knows its cpu - * number and master/slave status . Should be called first - * by the master, before the slaves are started. -*/ +/* This is here so that process.S doesn't have to decide the CPU type */ void -cpu_configuration_print(int master) -{ - CMMU_LOCK; - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_cpu_configuration_print(master); - break; -#endif -#ifdef M88110 - case CPU_88110: - m197_cpu_configuration_print(master); - break; -#endif - } - CMMU_UNLOCK; -} - -/* - * CMMU initialization routine - */ -void -cmmu_init(void) -{ - /* init the lock */ - simple_lock_init(&cmmu_cpu_lock); - - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_cmmu_init(); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - m197_cmmu_init(); - break; -#endif /* MVME197 */ - } -} - -/* - * Just before poweroff or reset.... - */ -void -cmmu_shutdown_now(void) -{ - CMMU_LOCK; - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_cmmu_shutdown_now(); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - m197_cmmu_shutdown_now(); - break; -#endif /* MVME197 */ - } - CMMU_UNLOCK; -} - -#define PARITY_ENABLE - -/* - * enable parity - */ -void -cmmu_parity_enable(void) -{ -#ifdef PARITY_ENABLE - CMMU_LOCK; - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_cmmu_parity_enable(); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - m197_cmmu_parity_enable(); - break; -#endif /* MVME197 */ - } - CMMU_UNLOCK; -#endif /* PARITY_ENABLE */ -} - -/* - * Find out the CPU number from accessing CMMU - * Better be at splhigh, or even better, with interrupts - * disabled. - */ -unsigned -cmmu_cpu_number(void) -{ - unsigned retval; - CMMU_LOCK; - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - retval = m18x_cmmu_cpu_number(); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - retval = m197_cmmu_cpu_number(); - break; -#endif /* MVME197 */ - } - CMMU_UNLOCK; - return retval; -} - -/** - ** Functions that actually modify CMMU registers. - **/ - -void -cmmu_remote_set(unsigned cpu, unsigned r, unsigned data, unsigned x) -{ - CMMU_LOCK; - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_cmmu_remote_set(cpu, r, data, x); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - m197_cmmu_remote_set(cpu, r, data, x); - break; -#endif /* MVME197 */ - } - CMMU_UNLOCK; -} - -/* - * cmmu_cpu_lock should be held when called if read - * the CMMU_SCR or CMMU_SAR. - */ -unsigned -cmmu_remote_get(unsigned cpu, unsigned r, unsigned data) -{ - unsigned retval; - CMMU_LOCK; - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - retval = m18x_cmmu_remote_get(cpu, r, data); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - retval = m197_cmmu_remote_get(cpu, r, data); - break; -#endif /* MVME197 */ - } - CMMU_UNLOCK; - return retval; -} - -/* Needs no locking - read only registers */ -unsigned -cmmu_get_idr(unsigned data) -{ - unsigned retval; - CMMU_LOCK; - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - retval = m18x_cmmu_get_idr(data); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - retval = m197_cmmu_get_idr(data); - break; -#endif /* MVME197 */ - } - CMMU_UNLOCK; - return retval; -} - -void -cmmu_set_sapr(unsigned ap) -{ - CMMU_LOCK; - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_cmmu_set_sapr(ap); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - m197_cmmu_set_sapr(ap); - break; -#endif /* MVME197 */ - } - CMMU_UNLOCK; -} - -void -cmmu_remote_set_sapr(unsigned cpu, unsigned ap) -{ - CMMU_LOCK; - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_cmmu_remote_set_sapr(cpu, ap); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - m197_cmmu_remote_set_sapr(cpu, ap); - break; -#endif /* MVME197 */ - } - CMMU_UNLOCK; -} - -void -cmmu_set_uapr(unsigned ap) -{ - register int s = splhigh(); - CMMU_LOCK; - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_cmmu_set_uapr(ap); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - m197_cmmu_set_uapr(ap); - break; -#endif /* MVME197 */ - } - CMMU_UNLOCK; - splx(s); -} - -/* - * Set batc entry number entry_no to value in - * the data or instruction cache depending on data. - * - * Except for the cmmu_init, this function, cmmu_set_pair_batc_entry, - * and cmmu_pmap_activate are the only functions which may set the - * batc values. - */ -void -cmmu_set_batc_entry( - unsigned cpu, - unsigned entry_no, - unsigned data, /* 1 = data, 0 = instruction */ - unsigned value) /* the value to stuff into the batc */ -{ - CMMU_LOCK; - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_cmmu_set_batc_entry(cpu, entry_no, data, value); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - m197_cmmu_set_batc_entry(cpu, entry_no, data, value); - break; -#endif /* MVME197 */ - } - CMMU_UNLOCK; -} - -/* - * Set batc entry number entry_no to value in - * the data and instruction cache for the named CPU. - */ -void -cmmu_set_pair_batc_entry( - unsigned cpu, - unsigned entry_no, - unsigned value) /* the value to stuff into the batc */ -{ - CMMU_LOCK; - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_cmmu_set_pair_batc_entry(cpu, entry_no, value); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - m197_cmmu_set_pair_batc_entry(cpu, entry_no, value); - break; -#endif /* MVME197 */ - } - CMMU_UNLOCK; -} - -/** - ** Functions that invalidate TLB entries. - **/ - -/* - * flush any tlb - * Some functionality mimiced in cmmu_pmap_activate. - */ -void -cmmu_flush_remote_tlb(unsigned cpu, unsigned kernel, vm_offset_t vaddr, int size) -{ - CMMU_LOCK; - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - m197_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size); - break; -#endif /* MVME197 */ - } - CMMU_UNLOCK; -} - -/* - * flush my personal tlb - */ -void -cmmu_flush_tlb(unsigned kernel, vm_offset_t vaddr, int size) +md_cmmu_flush_tlb(unsigned kernel, vm_offset_t vaddr, int size) { - int cpu; - cpu = cpu_number(); - cmmu_flush_remote_tlb(cpu, kernel, vaddr, size); + cmmu_flush_tlb(kernel, vaddr, size); } -/* - * New fast stuff for pmap_activate. - * Does what a few calls used to do. - * Only called from pmap.c's _pmap_activate(). - */ -void -cmmu_pmap_activate( - unsigned cpu, - unsigned uapr, - batc_template_t i_batc[BATC_MAX], - batc_template_t d_batc[BATC_MAX]) -{ - register int s = splhigh(); - CMMU_LOCK; - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_cmmu_pmap_activate(cpu, uapr, i_batc, d_batc); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - m197_cmmu_pmap_activate(cpu, uapr, i_batc, d_batc); - break; -#endif /* MVME197 */ - } - CMMU_UNLOCK; - splx(s); -} - -/** - ** Functions that invalidate caches. - ** - ** Cache invalidates require physical addresses. Care must be exercised when - ** using segment invalidates. This implies that the starting physical address - ** plus the segment length should be invalidated. A typical mistake is to - ** extract the first physical page of a segment from a virtual address, and - ** then expecting to invalidate when the pages are not physically contiguous. - ** - ** We don't push Instruction Caches prior to invalidate because they are not - ** snooped and never modified (I guess it doesn't matter then which form - ** of the command we use then). - **/ -/* - * flush both Instruction and Data caches - */ -void -cmmu_flush_remote_cache(int cpu, vm_offset_t physaddr, int size) -{ - CMMU_LOCK; - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_cmmu_flush_remote_cache(cpu, physaddr, size); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - m197_cmmu_flush_remote_cache(cpu, physaddr, size); - break; -#endif /* MVME197 */ - } - CMMU_UNLOCK; -} - -/* - * flush both Instruction and Data caches - */ -void -cmmu_flush_cache(vm_offset_t physaddr, int size) -{ - int cpu = cpu_number(); - cmmu_flush_remote_cache(cpu, physaddr, size); -} - -/* - * flush Instruction caches - */ -void -cmmu_flush_remote_inst_cache(int cpu, vm_offset_t physaddr, int size) -{ - CMMU_LOCK; - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_cmmu_flush_remote_inst_cache(cpu, physaddr, size); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - m197_cmmu_flush_remote_inst_cache(cpu, physaddr, size); - break; -#endif /* MVME197 */ - } - CMMU_UNLOCK; -} - -/* - * flush Instruction caches - */ -void -cmmu_flush_inst_cache(vm_offset_t physaddr, int size) -{ - int cpu; - cpu = cpu_number(); - cmmu_flush_remote_inst_cache(cpu, physaddr, size); -} - -void -cmmu_flush_remote_data_cache(int cpu, vm_offset_t physaddr, int size) -{ - CMMU_LOCK; - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_cmmu_flush_remote_data_cache(cpu, physaddr, size); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - m197_cmmu_flush_remote_data_cache(cpu, physaddr, size); - break; -#endif /* MVME197 */ - } - CMMU_UNLOCK; -} - -/* - * flush data cache - */ -void -cmmu_flush_data_cache(vm_offset_t physaddr, int size) -{ - int cpu; - cpu = cpu_number(); - cmmu_flush_remote_data_cache(cpu, physaddr, size); -} - -#if 0 -/* - * sync dcache (and icache too) - */ -void -cmmu_sync_cache(vm_offset_t physaddr, int size) -{ - CMMU_LOCK; - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_cmmu_sync_cache(physaddr, size); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - m197_cmmu_sync_cache(physaddr, size); - break; -#endif /* MVME197 */ - } - CMMU_UNLOCK; -} - -void -cmmu_sync_inval_cache(vm_offset_t physaddr, int size) -{ - CMMU_LOCK; - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_cmmu_sync_inval_cache(physaddr, size); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - m197_cmmu_sync_inval_cache(physaddr, size); - break; -#endif /* MVME197 */ - } - CMMU_UNLOCK; -} - -void -cmmu_inval_cache(vm_offset_t physaddr, int size) -{ - CMMU_LOCK; - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_cmmu_inval_cache(physaddr, size); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - m197_cmmu_inval_cache(physaddr, size); - break; -#endif /* MVME197 */ - } - CMMU_UNLOCK; -} -#endif - -void -dma_cachectl(vm_offset_t va, int size, int op) -{ - CMMU_LOCK; - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_dma_cachectl(va, size, op); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - m197_dma_cachectl(va, size, op); - break; -#endif /* MVME197 */ - } - CMMU_UNLOCK; -} - -#ifdef DDB - -/* - * Show (for debugging) how the given CMMU translates the given ADDRESS. - * If cmmu == -1, the data cmmu for the current cpu is used. - */ -void -cmmu_show_translation( - unsigned address, - unsigned supervisor_flag, - unsigned verbose_flag, - int cmmu_num) -{ - CMMU_LOCK; - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_cmmu_show_translation(address, supervisor_flag, - verbose_flag, cmmu_num); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - m197_cmmu_show_translation(address, supervisor_flag, - verbose_flag, cmmu_num); - break; -#endif /* MVME197 */ - } - CMMU_UNLOCK; -} - - -void -cmmu_cache_state(unsigned addr, unsigned supervisor_flag) -{ - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_cmmu_cache_state(addr, supervisor_flag); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - m197_cmmu_cache_state(addr, supervisor_flag); - break; -#endif /* MVME197 */ - } -} - -void -show_cmmu_info(unsigned addr) -{ - switch (cputyp) { -#ifdef M88100 - case CPU_88100: - m18x_show_cmmu_info(addr); - break; -#endif /* defined(MVME187) || defined(MVME188) */ -#ifdef M88110 - case CPU_88110: - m197_show_cmmu_info(addr); - break; -#endif /* MVME197 */ - } -} -#endif /* end if DDB */ diff --git a/sys/arch/mvme88k/mvme88k/locore_c_routines.c b/sys/arch/mvme88k/mvme88k/locore_c_routines.c index 279c9976299..4b4ea004b59 100644 --- a/sys/arch/mvme88k/mvme88k/locore_c_routines.c +++ b/sys/arch/mvme88k/mvme88k/locore_c_routines.c @@ -1,4 +1,4 @@ -/* $OpenBSD: locore_c_routines.c,v 1.18 2001/12/20 06:07:28 smurph Exp $ */ +/* $OpenBSD: locore_c_routines.c,v 1.19 2001/12/22 09:49:39 smurph Exp $ */ /* * Mach Operating System * Copyright (c) 1993-1991 Carnegie Mellon University @@ -34,14 +34,14 @@ #include <machine/cpu_number.h> /* cpu_number() */ #include <machine/board.h> /* m188 bit defines */ +#include <machine/cmmu.h> /* DMT_VALID */ #include <machine/asm.h> /* END_OF_VECTOR_LIST, etc. */ #include <machine/asm_macro.h> /* enable/disable interrupts */ -#include <machine/mmu.h> -#include <machine/cmmu.h> /* DMT_VALID */ #include <machine/cpu_number.h> /* cpu_number() */ #include <machine/locore.h> +#ifdef M88100 #include <machine/m88100.h> /* DMT_VALID */ -#include <machine/param.h> +#endif #ifdef DDB #include <ddb/db_output.h> /* db_printf() */ diff --git a/sys/arch/mvme88k/mvme88k/m197_cmmu.c b/sys/arch/mvme88k/mvme88k/m197_cmmu.c deleted file mode 100644 index 79db2aec28b..00000000000 --- a/sys/arch/mvme88k/mvme88k/m197_cmmu.c +++ /dev/null @@ -1,800 +0,0 @@ -/* $OpenBSD: m197_cmmu.c,v 1.13 2001/12/16 23:49:46 miod Exp $ */ -/* - * Copyright (c) 1998 Steve Murphree, Jr. - * Copyright (c) 1996 Nivas Madhur - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Nivas Madhur. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/* - * Mach Operating System - * Copyright (c) 1993-1991 Carnegie Mellon University - * Copyright (c) 1991 OMRON Corporation - * All Rights Reserved. - * - * Permission to use, copy, modify and distribute this software and its - * documentation is hereby granted, provided that both the copyright - * notice and this permission notice appear in all copies of the - * software, derivative works or modified versions, and any portions - * thereof, and that both notices appear in supporting documentation. - * - * CARNEGIE MELLON AND OMRON ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS IS" - * CONDITION. CARNEGIE MELLON AND OMRON DISCLAIM ANY LIABILITY OF ANY KIND - * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * - * Carnegie Mellon requests users of this software to return to - * - * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU - * School of Computer Science - * Carnegie Mellon University - * Pittsburgh PA 15213-3890 - * - * any improvements or extensions that they make and grant Carnegie the - * rights to redistribute these changes. - */ -#include <sys/param.h> -#include <sys/types.h> -#include <sys/simplelock.h> - -#include <machine/board.h> -#include <machine/cpus.h> -#include <machine/cpu_number.h> -#include <machine/locore.h> -#include <machine/m88110.h> -#include <machine/m88110_mmu.h> - -#ifdef DDB -#include <ddb/db_output.h> -#endif - -#ifdef DEBUG -#define DB_CMMU 0x4000 /* MMU debug */ -unsigned int debuglevel = 0; -#define dprintf(_L_,_X_) { if (debuglevel & (_L_)) { unsigned int psr = disable_interrupts_return_psr(); printf("%d: ", cpu_number()); printf _X_; set_psr(psr); } } -#else -#define dprintf(_L_,_X_) -#endif - -#undef SHADOW_BATC /* don't use BATCs for now XXX nivas */ - -/* - * CMMU(cpu,data) Is the cmmu struct for the named cpu's indicated cmmu. - * REGS(cpu,data) is the actual register structure. - */ - -#define CMMU(cpu, data) cpu_cmmu[(cpu)].pair[(data)?DATA_CMMU:INST_CMMU] -#define REGS(cpu, data) (*CMMU(cpu, data)->cmmu_regs) - -/* prototypes */ -void m197_cmmu_store __P((int, int, unsigned)); -int m197_cmmu_alive __P((int)); -unsigned m197_cmmu_get __P((int, int)); -void m197_cmmu_set __P((int, unsigned, int, int, int, int, vm_offset_t)); -int probe_mmu __P((vm_offset_t, int)); -void m197_cmmu_sync_cache __P((vm_offset_t, int)); -void m197_cmmu_sync_inval_cache __P((vm_offset_t, int)); -void m197_cmmu_inval_cache __P((vm_offset_t, int)); - -/* - * This lock protects the cmmu SAR and SCR's; other ports - * can be accessed without locking it - * - * May be used from "db_interface.c". - */ - -#ifdef CMMU_DEBUG -void -m197_show_apr(unsigned value) -{ - union apr_template apr_template; - apr_template.bits = value; - - printf("table @ 0x%x000", apr_template.field.st_base); - if (apr_template.field.wt) printf(", writethrough"); - if (apr_template.field.g) printf(", global"); - if (apr_template.field.ci) printf(", cache inhibit"); - if (apr_template.field.te) printf(", valid"); - else printf(", not valid"); - printf("\n"); -} - -void -m197_show_sctr(unsigned value) -{ - union { - unsigned bits; - struct { - unsigned :16, - pe: 1, - se: 1, - pr: 1, - :13; - } fields; - } sctr; - sctr.bits = value; - printf("%spe, %sse %spr]\n", - sctr.fields.pe ? "" : "!", - sctr.fields.se ? "" : "!", - sctr.fields.pr ? "" : "!"); -} -#endif - -void -m197_setup_board_config(void) -{ - /* dummy routine */ - m197_setup_cmmu_config(); - return; -} - -void -m197_setup_cmmu_config(void) -{ - /* we can print something here... */ - cpu_sets[0] = 1; /* This cpu installed... */ - return; -} - -void m197_cmmu_dump_config(void) -{ - /* dummy routine */ - return; -} - -void -m197_cmmu_store(int mmu, int reg, unsigned val) -{ -} - -int -m197_cmmu_alive(int mmu) -{ - return 1; -} - -unsigned -m197_cmmu_get(int mmu, int reg) -{ - return 0; -} - -/* - * This function is called by the MMU module and pokes values - * into the CMMU's registers. - */ -void -m197_cmmu_set(int reg, unsigned val, int flags, - int num, int mode, int access, vm_offset_t addr) -{ - return; -} - -#ifdef DDB -/* - * Used by DDB for cache probe functions - */ -unsigned m197_cmmu_get_by_mode(int cpu, int mode) -{ - return 0; -} -#endif - -/* - * Should only be called after the calling cpus knows its cpu - * number and master/slave status . Should be called first - * by the master, before the slaves are started. -*/ -void -m197_cpu_configuration_print(int master) -{ - int pid = read_processor_identification_register(); - int proctype = (pid & 0xff00) >> 8; - int procvers = (pid & 0xe) >> 1; - int cpu = cpu_number(); - struct simplelock print_lock; - - if (master) - simple_lock_init(&print_lock); - - simple_lock(&print_lock); - - printf("Processor %d: ", cpu); - if (proctype) - printf("Architectural Revision 0x%x UNKNOWN CPU TYPE Version 0x%x\n", - proctype, procvers); - else - printf("M88110 Version 0x%x\n", procvers); - - simple_unlock(&print_lock); - return; -} - -/* - * CMMU initialization routine - */ -void m197_load_patc(int entry, vm_offset_t vaddr, vm_offset_t paddr, int kernel); - -void -m197_cmmu_init(void) -{ - int i; - unsigned tmp; - extern void *kernel_sdt; - unsigned lba, pba, value; - - /* clear BATCs */ - for (i=0; i<8; i++) { - m197_cmmu_set_pair_batc_entry(0, i, 0); - } - /* clear PATCs */ - for (i=0; i<32; i++) { - m197_load_patc(i, 0, 0, 0); - } - set_ictl(CMMU_ICTL_DID /* Double instruction disable */ - | CMMU_ICTL_MEN - | CMMU_ICTL_HTEN); - - - set_dctl(CMMU_DCTL_MEN - | CMMU_DCTL_HTEN); - - set_icmd(CMMU_ICMD_INV_ITIC); /* clear instruction cache */ - set_dcmd(CMMU_DCMD_INV_ALL); /* clear data cache */ - - tmp = (0x00000 << 12) | /* segment table base address */ - AREA_D_WT | /* write through */ - AREA_D_G | /* global */ - ! AREA_D_TE ; /* not translation enable */ - - set_isap(tmp); - set_dsap(tmp); - - set_isr(0); - set_ilar(0); - set_ipar(0); - set_dsr(0); - set_dlar(0); - set_dpar(0); - - lba = pba = (unsigned)&kernel_sdt; - lba &= ~0x7FFFF; - pba = pba >> 13; - pba &= ~0x3F; - value = lba | pba | 0x20 | 0x01; - - m197_cmmu_set_pair_batc_entry(0, 0, value); - -} - -/* - * Just before poweroff or reset.... - */ -void -m197_cmmu_shutdown_now(void) -{ -} - -/* - * enable parity - */ -void -m197_cmmu_parity_enable(void) -{ -#ifdef PARITY_ENABLE -#endif /* PARITY_ENABLE */ -} - -/* - * Find out the CPU number from accessing CMMU - * Better be at splhigh, or even better, with interrupts - * disabled. - */ -#define ILLADDRESS U(0x0F000000) /* any faulty address */ - -unsigned -m197_cmmu_cpu_number(void) -{ - return 0; /* to make compiler happy */ -} - -/** - ** Functions that actually modify CMMU registers. - **/ -void -m197_cmmu_remote_set(unsigned cpu, unsigned r, unsigned data, unsigned x) -{ - panic("m197_cmmu_remote_set() called!"); -} - -/* - * cmmu_cpu_lock should be held when called if read - * the CMMU_SCR or CMMU_SAR. - */ -unsigned -m197_cmmu_remote_get(unsigned cpu, unsigned r, unsigned data) -{ - panic("m197_cmmu_remote_get() called!"); - return 0; -} - -/* Needs no locking - read only registers */ -unsigned -m197_cmmu_get_idr(unsigned data) -{ - return 0; /* todo */ -} - -int -probe_mmu(vm_offset_t va, int data) -{ - unsigned result; - if (data) { - set_dsar((unsigned)va); - set_dcmd(CMMU_DCMD_PRB_SUPR); - result = get_dsr(); - if (result & CMMU_DSR_PH) - return 1; - else - return 0; - } else { - set_isar((unsigned)va); - set_icmd(CMMU_ICMD_PRB_SUPR); - result = get_isr(); - if (result & CMMU_ISR_BH) - return 2; - else if (result & CMMU_ISR_PH) - return 1; - else - return 0; - } - return 0; -} - -void -m197_cmmu_set_sapr(unsigned ap) -{ - int result; - set_icmd(CMMU_ICMD_INV_SATC); - set_dcmd(CMMU_DCMD_INV_SATC); - /* load an entry pointing to seg table into PATC */ - /* Don't forget to set it valid */ - - m197_load_patc(0, (vm_offset_t)ap, (vm_offset_t)(ap | 0x1), 1); - if (!(result = probe_mmu((vm_offset_t) ap, 1))) { - printf("Didn't make it!!!!\n"); - return; - } else { - if (result == 2) - printf("area pointer is in BATC.\n"); - if (result == 1) - printf("area pointer is in PATC.\n"); - } - - set_isap(ap); - set_dsap(ap); -} - -void -m197_cmmu_remote_set_sapr(unsigned cpu, unsigned ap) -{ - m197_cmmu_set_sapr(ap); -} - -void -m197_cmmu_set_uapr(unsigned ap) -{ - set_iuap(ap); - set_duap(ap); -} - -/* - * Set batc entry number entry_no to value in - * the data or instruction cache depending on data. - * - * Except for the cmmu_init, this function, m197_cmmu_set_pair_batc_entry, - * and m197_cmmu_pmap_activate are the only functions which may set the - * batc values. - */ -void -m197_cmmu_set_batc_entry( - unsigned cpu, - unsigned entry_no, - unsigned data, /* 1 = data, 0 = instruction */ - unsigned value) /* the value to stuff */ -{ - if (data) { - set_dir(entry_no); - set_dbp(value); - } else { - set_iir(entry_no); - set_ibp(value); - } -} - -/* - * Set batc entry number entry_no to value in - * the data and instruction cache for the named CPU. - */ -void -m197_cmmu_set_pair_batc_entry(unsigned cpu, unsigned entry_no, unsigned value) -/* the value to stuff into the batc */ -{ - m197_cmmu_set_batc_entry(cpu, entry_no, 1, value); - m197_cmmu_set_batc_entry(cpu, entry_no, 0, value); -} - -/** - ** Functions that invalidate TLB entries. - **/ - -/* - * flush any tlb - * Some functionality mimiced in m197_cmmu_pmap_activate. - */ -void -m197_cmmu_flush_remote_tlb(unsigned cpu, unsigned kernel, vm_offset_t vaddr, int size) -{ - register int s = splhigh(); - if (kernel) { - set_icmd(CMMU_ICMD_INV_SATC); - set_dcmd(CMMU_DCMD_INV_SATC); - } else { - set_icmd(CMMU_ICMD_INV_UATC); - set_dcmd(CMMU_DCMD_INV_UATC); - } - splx(s); -} - -/* - * flush my personal tlb - */ -void -m197_cmmu_flush_tlb(unsigned kernel, vm_offset_t vaddr, int size) -{ - int cpu; - cpu = cpu_number(); - m197_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size); -} - -/* - * New fast stuff for pmap_activate. - * Does what a few calls used to do. - * Only called from pmap.c's _pmap_activate(). - */ -void -m197_cmmu_pmap_activate( - unsigned cpu, - unsigned uapr, - batc_template_t i_batc[BATC_MAX], - batc_template_t d_batc[BATC_MAX]) -{ - /* int entry_no;*/ - - m197_cmmu_set_uapr(uapr); - - /* - for (entry_no = 0; entry_no < 8; entry_no++) { - m197_cmmu_set_batc_entry(cpu, entry_no, 0, i_batc[entry_no].bits); - m197_cmmu_set_batc_entry(cpu, entry_no, 1, d_batc[entry_no].bits); - } - */ - /* - * Flush the user TLB. - * IF THE KERNEL WILL EVER CARE ABOUT THE BATC ENTRIES, - * THE SUPERVISOR TLBs SHOULB EE FLUSHED AS WELL. - */ - set_icmd(CMMU_ICMD_INV_UATC); - set_dcmd(CMMU_DCMD_INV_UATC); -} - -/** - ** Functions that invalidate caches. - ** - ** Cache invalidates require physical addresses. Care must be exercised when - ** using segment invalidates. This implies that the starting physical address - ** plus the segment length should be invalidated. A typical mistake is to - ** extract the first physical page of a segment from a virtual address, and - ** then expecting to invalidate when the pages are not physically contiguous. - ** - ** We don't push Instruction Caches prior to invalidate because they are not - ** snooped and never modified (I guess it doesn't matter then which form - ** of the command we use then). - **/ -/* - * flush both Instruction and Data caches - */ -void -m197_cmmu_flush_remote_cache(int cpu, vm_offset_t physaddr, int size) -{ - register int s = splhigh(); - set_icmd(CMMU_ICMD_INV_ITIC); - set_dcmd(CMMU_DCMD_FLUSH_ALL_INV); - splx(s); -} - -/* - * flush both Instruction and Data caches - */ -void -m197_cmmu_flush_cache(vm_offset_t physaddr, int size) -{ - int cpu = cpu_number(); - m197_cmmu_flush_remote_cache(cpu, physaddr, size); -} - -/* - * flush Instruction caches - */ -void -m197_cmmu_flush_remote_inst_cache(int cpu, vm_offset_t physaddr, int size) -{ - register int s = splhigh(); - - set_icmd(CMMU_ICMD_INV_ITIC); - - splx(s); -} - -/* - * flush Instruction caches - */ -void -m197_cmmu_flush_inst_cache(vm_offset_t physaddr, int size) -{ - int cpu; - cpu = cpu_number(); - m197_cmmu_flush_remote_inst_cache(cpu, physaddr, size); -} - -/* - * flush data cache - */ -void -m197_cmmu_flush_remote_data_cache(int cpu, vm_offset_t physaddr, int size) -{ - register int s = splhigh(); - set_dcmd(CMMU_DCMD_FLUSH_ALL_INV); - splx(s); -} - -/* - * flush data cache - */ -void -m197_cmmu_flush_data_cache(vm_offset_t physaddr, int size) -{ - int cpu; - cpu = cpu_number(); - m197_cmmu_flush_remote_data_cache(cpu, physaddr, size); -} - -/* - * sync dcache (and icache too) - */ -void -m197_cmmu_sync_cache(vm_offset_t physaddr, int size) -{ - register int s = splhigh(); - int cpu; - cpu = cpu_number(); - /* set_mmureg(CMMU_ICTL, CMMU_ICMD_INV_TIC); */ - set_dcmd(CMMU_DCMD_FLUSH_ALL); - - splx(s); -} - -void -m197_cmmu_sync_inval_cache(vm_offset_t physaddr, int size) -{ - register int s = splhigh(); - int cpu; - cpu = cpu_number(); - - set_dcmd(CMMU_DCMD_FLUSH_ALL_INV); - splx(s); -} - -void -m197_cmmu_inval_cache(vm_offset_t physaddr, int size) -{ - register int s = splhigh(); - int cpu; - cpu = cpu_number(); - set_icmd(CMMU_ICMD_INV_ITIC); - set_dcmd(CMMU_DCMD_INV_ALL); - splx(s); -} - -void -m197_dma_cachectl(vm_offset_t va, int size, int op) -{ - if (op == DMA_CACHE_SYNC) - m197_cmmu_sync_cache(kvtop(va), size); - else if (op == DMA_CACHE_SYNC_INVAL) - m197_cmmu_sync_inval_cache(kvtop(va), size); - else - m197_cmmu_inval_cache(kvtop(va), size); -} - -#ifdef DDB - - #define VV_EX_UNMOD 0 - #define VV_EX_MOD 1 - #define VV_SHARED_UNMOD 2 - #define VV_INVALID 3 - - #define D(UNION, LINE) \ - ((LINE) == 3 ? (UNION).field.d3 : \ - ((LINE) == 2 ? (UNION).field.d2 : \ - ((LINE) == 1 ? (UNION).field.d1 : \ - ((LINE) == 0 ? (UNION).field.d0 : ~0)))) - #define VV(UNION, LINE) \ - ((LINE) == 3 ? (UNION).field.vv3 : \ - ((LINE) == 2 ? (UNION).field.vv2 : \ - ((LINE) == 1 ? (UNION).field.vv1 : \ - ((LINE) == 0 ? (UNION).field.vv0 : ~0)))) - - - #undef VEQR_ADDR - #define VEQR_ADDR 0 - -/* - * Show (for debugging) how the given CMMU translates the given ADDRESS. - * If cmmu == -1, the data cmmu for the current cpu is used. - */ -void -m197_cmmu_show_translation(unsigned address, - unsigned supervisor_flag, - unsigned verbose_flag, - int cmmu_num) -{ - /* - * A virtual address is split into three fields. Two are used as - * indicies into tables (segment and page), and one is an offset into - * a page of memory. - */ - /* - union { - unsigned bits; - struct { - unsigned segment_table_index:10, - page_table_index:10, - page_offset:12; - } field; - } virtual_address; - */ - -#ifdef DDB - if (verbose_flag) - db_printf("-------------------------------------------\n"); -#endif -} - - -void -m197_cmmu_cache_state(unsigned addr, unsigned supervisor_flag) -{ - /* - static char *vv_name[4] = - {"exclu-unmod", "exclu-mod", "shared-unmod", "invalid"}; - */ -} - -void -m197_show_cmmu_info(unsigned addr) -{ - m197_cmmu_cache_state(addr, 1); -} -#endif /* end if DDB */ - -#define MSDTENT(addr, va) ((sdt_entry_t *)(addr + SDTIDX(va))) -#define MPDTENT(addr, va) ((sdt_entry_t *)(addr + PDTIDX(va))) -void -m197_load_patc(int entry, vm_offset_t vaddr, vm_offset_t paddr, int kernel) -{ - unsigned lpa, pfa, i; - - lpa = (unsigned)vaddr & 0xFFFFF000; - if (kernel) { - lpa |= 0x01; - } - pfa = (unsigned)paddr; - i = entry << 5; - set_iir(i); - set_ippu(lpa); - set_ippl(pfa); - set_dir(i); - set_dppu(lpa); - set_dppl(lpa); -} - -#define SDT_WP(sd_ptr) ((sd_ptr)->prot != 0) -#define SDT_SUP(sd_ptr) ((sd_ptr)->sup != 0) -#define PDT_WP(pte_ptr) ((pte_ptr)->prot != 0) -#define PDT_SUP(pte_ptr) ((pte_ptr)->sup != 0) - -int -m197_table_search(pmap_t map, vm_offset_t virt, int write, int kernel, int data) -{ - sdt_entry_t *sdt; - pt_entry_t *pte; - unsigned lpa, i; - static int entry_num = 0; - - if (map == (pmap_t)0) - panic("m197_table_search: pmap is NULL"); - - sdt = SDTENT(map, virt); - - /* - * Check whether page table exist or not. - */ - if (!SDT_VALID(sdt)) - return (4); /* seg fault */ - - /* OK, it's valid. Now check permissions. */ - if (!kernel) - if (SDT_SUP(sdt)) - return (6); /* Supervisor Violation */ - if (write) - if (SDT_WP(sdt)) - return (7); /* Write Violation */ - - pte = (pt_entry_t *)(((sdt + SDT_ENTRIES)->table_addr)<<PDT_SHIFT) + PDTIDX(virt); - - /* - * Check whether page frame exist or not. - */ - if (!PDT_VALID(pte)) - return (5); /* Page Fault */ - - /* OK, it's valid. Now check permissions. */ - if (!kernel) - if (PDT_SUP(sdt)) - return (6); /* Supervisor Violation */ - if (write) - if (PDT_WP(sdt)) - return (7); /* Write Violation */ - /* If we get here, load the PATC. */ - if (entry_num > 32) - entry_num = 0; - lpa = (unsigned)virt & 0xFFFFF000; - if (kernel) - lpa |= 0x01; - i = entry_num << 5; - if (data) { - set_dir(i); /* set PATC index */ - set_dppu(lpa); /* set logical address */ - set_dppl((unsigned)pte); /* set page fram address */ - } else { - set_iir(i); - set_ippu(lpa); - set_ippl((unsigned)pte); - } - return 0; -} diff --git a/sys/arch/mvme88k/mvme88k/m88110.c b/sys/arch/mvme88k/mvme88k/m88110.c new file mode 100644 index 00000000000..a0295b313b8 --- /dev/null +++ b/sys/arch/mvme88k/mvme88k/m88110.c @@ -0,0 +1,1085 @@ +/* $OpenBSD: m88110.c,v 1.4 2001/12/22 09:49:39 smurph Exp $ */ +/* + * Copyright (c) 1998 Steve Murphree, Jr. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Nivas Madhur. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* + * Mach Operating System + * Copyright (c) 1993-1991 Carnegie Mellon University + * Copyright (c) 1991 OMRON Corporation + * All Rights Reserved. + * + * Permission to use, copy, modify and distribute this software and its + * documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON AND OMRON ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON AND OMRON DISCLAIM ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ +#ifdef M88110 + +#include <sys/param.h> +#include <sys/types.h> +#include <sys/simplelock.h> +#include <machine/board.h> +#include <machine/cpus.h> +#include <machine/cpu_number.h> +#include <machine/cmmu.h> +#include <machine/locore.h> + +#define CMMU_DEBUG 1 + +#ifdef DEBUG +#define DB_CMMU 0x4000 /* MMU debug */ +unsigned int debuglevel = 0; +#define dprintf(_L_,_X_) { if (debuglevel & (_L_)) { unsigned int psr = disable_interrupts_return_psr(); printf("%d: ", cpu_number()); printf _X_; set_psr(psr); } } +#else +#define dprintf(_L_,_X_) +#endif + +#ifdef DDB +#include <ddb/db_output.h> /* db_printf() */ +#define DEBUG_MSG db_printf +#define STATIC +#else +#define DEBUG_MSG printf +#define STATIC static +#endif /* DDB */ + +/* kernel copy of PATC entries */ +unsigned patc_data_u[32]; +unsigned patc_data_l[32]; +unsigned patc_inst_u[32]; +unsigned patc_inst_l[32]; + +#define INST 0 +#define DATA 1 +#define BOTH 2 +#define KERN 1 +#define USER 0 + +/* FORWARDS */ +unsigned batc_val __P((unsigned phys, unsigned virt, unsigned prot)); +void patc_insert __P((unsigned upper, unsigned lower, int which)); +void patc_clear __P((void)); +void patc_sync __P((int which)); +void patc_load __P((int index, unsigned upper, unsigned lower, int which)); +void m88110_cmmu_sync_cache __P((vm_offset_t physaddr, int size)); +void m88110_cmmu_sync_inval_cache __P((vm_offset_t physaddr, int size)); +void m88110_cmmu_inval_cache __P((vm_offset_t physaddr, int size)); +int probe_mmu __P((vm_offset_t va, int data)); + +/* This is the function table for the mc88110 built-in CMMUs */ +struct cmmu_p cmmu88110 = { + m88110_cmmu_init, + m88110_show_apr, + m88110_setup_board_config, + m88110_setup_cmmu_config, + m88110_cmmu_dump_config, + m88110_cpu_configuration_print, + m88110_cmmu_shutdown_now, + m88110_cmmu_parity_enable, + m88110_cmmu_cpu_number, + m88110_cmmu_get_idr, + m88110_cmmu_set_sapr, + m88110_cmmu_remote_set_sapr, + m88110_cmmu_set_uapr, + m88110_cmmu_set_batc_entry, + m88110_cmmu_set_pair_batc_entry, + m88110_cmmu_flush_remote_tlb, + m88110_cmmu_flush_tlb, + m88110_cmmu_pmap_activate, + m88110_cmmu_flush_remote_cache, + m88110_cmmu_flush_cache, + m88110_cmmu_flush_remote_inst_cache, + m88110_cmmu_flush_inst_cache, + m88110_cmmu_flush_remote_data_cache, + m88110_cmmu_flush_data_cache, + m88110_dma_cachectl, +#ifdef DDB + m88110_cmmu_get_by_mode, + m88110_cmmu_show_translation, + m88110_cmmu_cache_state, + m88110_show_cmmu_info, +#endif /* end if DDB */ +}; + +void +patc_load(int index, unsigned upper, unsigned lower, int which) +{ + /* sanity check!!! */ + if (index > 31) { + panic("invalid PATC index %d!", index); + } + index = index << 5; + switch (which) { + case INST: + set_iir(index); + set_ippu(upper); + set_ippl(lower); + break; + case DATA: + set_dir(index); + set_dppu(upper); + set_dppl(lower); + break; + default: + panic("invalid PATC! Choose DATA or INST..."); + } +} + +void +patc_sync(int which) +{ + int i; + switch (which) { + case BOTH: + for (i=0; i<32; i++) { + patc_load(i, patc_data_u[i], patc_data_l[i], DATA); + patc_load(i, patc_inst_u[i], patc_inst_l[i], INST); + } + break; + case INST: + for (i=0; i<32; i++) { + patc_load(i, patc_inst_u[i], patc_inst_l[i], INST); + } + break; + case DATA: + for (i=0; i<32; i++) { + patc_load(i, patc_data_u[i], patc_data_l[i], DATA); + } + break; + } +} + +void +patc_clear(void) +{ + int i; + for (i=0; i<32; i++) { + patc_data_u[i] = 0; + patc_data_l[i] = 0; + patc_inst_u[i] = 0; + patc_inst_l[i] = 0; + } + patc_sync(BOTH); +} + +/* implement a FIFO on the PATC entries */ +void +patc_insert(unsigned upper, unsigned lower, int which) +{ + int i; + switch(which){ + case INST: + for (i=31; i>0; i--) { + patc_inst_u[i] = patc_inst_u[i-1]; + patc_inst_l[i] = patc_inst_l[i-1]; + } + patc_inst_u[0] = upper; + patc_inst_l[0] = lower; + patc_sync(INST); + break; + case DATA: + for (i=31; i>0; i--) { + patc_data_u[i] = patc_data_u[i-1]; + patc_data_l[i] = patc_data_l[i-1]; + } + patc_data_u[0] = upper; + patc_data_l[0] = lower; + patc_sync(DATA); + break; + case BOTH: + panic("patc_insert(): can't insert both INST and DATA."); + } +} + +unsigned +batc_val(unsigned phys, unsigned virt, unsigned prot) +{ + unsigned val = 0; + virt = (virt >> BATC_ADDR_SHIFT); + val |= (virt << BATC_LBA_SHIFT); + phys = (phys >> BATC_ADDR_SHIFT); + val |= (phys << BATC_PBA_SHIFT); + val |= prot; + return(val); +} + + +void +m88110_show_apr(unsigned value) +{ + union apr_template apr_template; + apr_template.bits = value; + + printf("table @ 0x%x000", apr_template.field.st_base); + if (apr_template.field.wt) printf(", writethrough"); + if (apr_template.field.g) printf(", global"); + if (apr_template.field.ci) printf(", cache inhibit"); + if (apr_template.field.te) printf(", valid"); + else printf(", not valid"); + printf("\n"); +} + +void +m88110_setup_board_config(void) +{ + /* dummy routine */ + m88110_setup_cmmu_config(); + return; +} + +void +m88110_setup_cmmu_config(void) +{ + /* we can print something here... */ + cpu_sets[0] = 1; /* This cpu installed... */ + return; +} + +void m88110_cmmu_dump_config(void) +{ + /* dummy routine */ + return; +} + +#ifdef DDB +/* + * Used by DDB for cache probe functions + */ +unsigned m88110_cmmu_get_by_mode(int cpu, int mode) +{ + CMMU_LOCK; + return 0; + CMMU_UNLOCK; +} +#endif + +/* + * Should only be called after the calling cpus knows its cpu + * number and master/slave status . Should be called first + * by the master, before the slaves are started. +*/ +void +m88110_cpu_configuration_print(int master) +{ + int pid = read_processor_identification_register(); + int proctype = (pid & 0xff00) >> 8; + int procvers = (pid & 0xe) >> 1; + int cpu = cpu_number(); + struct simplelock print_lock; + + CMMU_LOCK; + if (master) + simple_lock_init(&print_lock); + + simple_lock(&print_lock); + + printf("Processor %d: ", cpu); + if (proctype) + printf("Architectural Revision 0x%x UNKNOWN CPU TYPE Version 0x%x\n", + proctype, procvers); + else + printf("M88110 Version 0x%x\n", procvers); + + simple_unlock(&print_lock); + CMMU_UNLOCK; + return; +} + +/* + * CMMU initialization routine + */ +void m88110_load_patc(int entry, vm_offset_t vaddr, vm_offset_t paddr, int kernel); + +void +m88110_cmmu_init(void) +{ + int i; + + /* clear BATCs */ + for (i=0; i<8; i++) { + m88110_cmmu_set_pair_batc_entry(0, i, 0); + } + /* clear PATCs */ + patc_clear(); + + set_ictl(BATC_32M + | CMMU_ICTL_DID /* Double instruction disable */ + | CMMU_ICTL_MEN + | CMMU_ICTL_CEN + | CMMU_ICTL_BEN + | CMMU_ICTL_HTEN); + + set_dctl(BATC_32M + | CMMU_DCTL_MEN + | CMMU_DCTL_CEN + | CMMU_DCTL_SEN + | CMMU_DCTL_ADS + | CMMU_DCTL_HTEN); + + + mc88110_inval_inst(); /* clear instruction cache & TIC */ + mc88110_inval_data(); /* clear data cache */ + mc88410_inval(); /* clear external data cache */ + + set_dcmd(CMMU_DCMD_INV_SATC); /* invalidate ATCs */ + + set_isr(0); + set_ilar(0); + set_ipar(0); + set_dsr(0); + set_dlar(0); + set_dpar(0); +} + +/* + * Just before poweroff or reset.... + */ +void +m88110_cmmu_shutdown_now(void) +{ + CMMU_LOCK; + CMMU_UNLOCK; +} + +/* + * enable parity + */ +void +m88110_cmmu_parity_enable(void) +{ +#ifdef PARITY_ENABLE + CMMU_LOCK; + CMMU_UNLOCK; +#endif /* PARITY_ENABLE */ +} + +/* + * Find out the CPU number from accessing CMMU + * Better be at splhigh, or even better, with interrupts + * disabled. + */ +#define ILLADDRESS U(0x0F000000) /* any faulty address */ + +unsigned +m88110_cmmu_cpu_number(void) +{ + return 0; /* to make compiler happy */ +} + +/* Needs no locking - read only registers */ +unsigned +m88110_cmmu_get_idr(unsigned data) +{ + return 0; /* todo */ +} + +int +probe_mmu(vm_offset_t va, int data) +{ + unsigned result; + if (data) { + CMMU_LOCK; + set_dsar((unsigned)va); + set_dcmd(CMMU_DCMD_PRB_SUPR); + result = get_dsr(); + CMMU_UNLOCK; + if (result & CMMU_DSR_BH) + return 2; + else if (result & CMMU_DSR_PH) + return 1; + else + return 0; + } else { + CMMU_LOCK; + set_isar((unsigned)va); + set_icmd(CMMU_ICMD_PRB_SUPR); + result = get_isr(); + CMMU_UNLOCK; + if (result & CMMU_ISR_BH) + return 2; + else if (result & CMMU_ISR_PH) + return 1; + else + return 0; + } + return 0; +} + +void +m88110_cmmu_set_sapr(unsigned ap) +{ +#if 0 + int result; +#endif + unsigned ictl, dctl; + CMMU_LOCK; + + set_icmd(CMMU_ICMD_INV_SATC); + set_dcmd(CMMU_DCMD_INV_SATC); + + ictl = get_ictl(); + dctl = get_dctl(); + /* disabel translation */ + set_ictl((ictl &~ CMMU_ICTL_MEN)); + set_dctl((dctl &~ CMMU_DCTL_MEN)); + + set_isap(ap); + set_dsap(ap); + + patc_clear(); + + set_icmd(CMMU_ICMD_INV_UATC); + set_icmd(CMMU_ICMD_INV_SATC); + set_dcmd(CMMU_DCMD_INV_UATC); + set_dcmd(CMMU_DCMD_INV_SATC); + + /* restore MMU settings */ + set_ictl(ictl); + set_dctl(dctl); + + CMMU_UNLOCK; + return; +} + +void +m88110_cmmu_remote_set_sapr(unsigned cpu, unsigned ap) +{ + m88110_cmmu_set_sapr(ap); +} + +void +m88110_cmmu_set_uapr(unsigned ap) +{ + CMMU_LOCK; + set_iuap(ap); + set_duap(ap); + set_icmd(CMMU_ICMD_INV_UATC); + set_dcmd(CMMU_DCMD_INV_UATC); + mc88110_inval_inst(); + CMMU_UNLOCK; +} + +/* + * Set batc entry number entry_no to value in + * the data or instruction cache depending on data. + * + * Except for the cmmu_init, this function, m88110_cmmu_set_pair_batc_entry, + * and m88110_cmmu_pmap_activate are the only functions which may set the + * batc values. + */ +void +m88110_cmmu_set_batc_entry( + unsigned cpu, + unsigned entry_no, + unsigned data, /* 1 = data, 0 = instruction */ + unsigned value) /* the value to stuff */ +{ + CMMU_LOCK; + if (data) { + set_dir(entry_no); + set_dbp(value); + } else { + set_iir(entry_no); + set_ibp(value); + } + CMMU_UNLOCK; +} + +/* + * Set batc entry number entry_no to value in + * the data and instruction cache for the named CPU. + */ +void +m88110_cmmu_set_pair_batc_entry(unsigned cpu, unsigned entry_no, unsigned value) +/* the value to stuff into the batc */ +{ + m88110_cmmu_set_batc_entry(cpu, entry_no, 1, value); + m88110_cmmu_set_batc_entry(cpu, entry_no, 0, value); +} + +/** + ** Functions that invalidate TLB entries. + **/ + +/* + * flush any tlb + * Some functionality mimiced in m88110_cmmu_pmap_activate. + */ +void +m88110_cmmu_flush_remote_tlb(unsigned cpu, unsigned kernel, vm_offset_t vaddr, int size) +{ + register int s = splhigh(); + + CMMU_LOCK; + if (kernel) { + set_icmd(CMMU_ICMD_INV_SATC); + set_dcmd(CMMU_DCMD_INV_SATC); + } else { + set_icmd(CMMU_ICMD_INV_UATC); + set_dcmd(CMMU_DCMD_INV_UATC); + } + CMMU_UNLOCK; + + splx(s); +} + +/* + * flush my personal tlb + */ +void +m88110_cmmu_flush_tlb(unsigned kernel, vm_offset_t vaddr, int size) +{ + int cpu; + cpu = cpu_number(); + m88110_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size); +} + +/* + * New fast stuff for pmap_activate. + * Does what a few calls used to do. + * Only called from pmap.c's _pmap_activate(). + */ +void +m88110_cmmu_pmap_activate( + unsigned cpu, + unsigned uapr, + batc_template_t i_batc[BATC_MAX], + batc_template_t d_batc[BATC_MAX]) +{ + m88110_cmmu_set_uapr(uapr); + + /* + for (entry_no = 0; entry_no < 8; entry_no++) { + m88110_cmmu_set_batc_entry(cpu, entry_no, 0, i_batc[entry_no].bits); + m88110_cmmu_set_batc_entry(cpu, entry_no, 1, d_batc[entry_no].bits); + } + */ + /* + * Flush the user TLB. + * IF THE KERNEL WILL EVER CARE ABOUT THE BATC ENTRIES, + * THE SUPERVISOR TLBs SHOULB EE FLUSHED AS WELL. + */ + set_icmd(CMMU_ICMD_INV_UATC); + set_dcmd(CMMU_DCMD_INV_UATC); +} + +/** + ** Functions that invalidate caches. + ** + ** Cache invalidates require physical addresses. Care must be exercised when + ** using segment invalidates. This implies that the starting physical address + ** plus the segment length should be invalidated. A typical mistake is to + ** extract the first physical page of a segment from a virtual address, and + ** then expecting to invalidate when the pages are not physically contiguous. + ** + ** We don't push Instruction Caches prior to invalidate because they are not + ** snooped and never modified (I guess it doesn't matter then which form + ** of the command we use then). + **/ + +/* + * Care must be taken to avoid flushing the data cache when + * the data cache is not on! From the 0F92L Errata Documentation + * Package, Version 1.1 + */ + +/* + * flush both Instruction and Data caches + */ +void +m88110_cmmu_flush_remote_cache(int cpu, vm_offset_t physaddr, int size) +{ + register int s = splhigh(); + + mc88110_inval_inst(); + mc88110_flush_data(); + mc88410_flush(); + splx(s); +} + +/* + * flush both Instruction and Data caches + */ +void +m88110_cmmu_flush_cache(vm_offset_t physaddr, int size) +{ + int cpu = cpu_number(); + + m88110_cmmu_flush_remote_cache(cpu, physaddr, size); +} + +/* + * flush Instruction caches + */ +void +m88110_cmmu_flush_remote_inst_cache(int cpu, vm_offset_t physaddr, int size) +{ + register int s = splhigh(); + + mc88110_inval_inst(); + splx(s); +} + +/* + * flush Instruction caches + */ +void +m88110_cmmu_flush_inst_cache(vm_offset_t physaddr, int size) +{ + int cpu; + + cpu = cpu_number(); + m88110_cmmu_flush_remote_inst_cache(cpu, physaddr, size); +} + +/* + * flush data cache + */ +void +m88110_cmmu_flush_remote_data_cache(int cpu, vm_offset_t physaddr, int size) +{ + register int s = splhigh(); + + mc88110_flush_data(); + mc88410_flush(); + splx(s); +} + +/* + * flush data cache + */ +void +m88110_cmmu_flush_data_cache(vm_offset_t physaddr, int size) +{ + int cpu; + + cpu = cpu_number(); + m88110_cmmu_flush_remote_data_cache(cpu, physaddr, size); +} + +/* + * sync dcache (and icache too) + */ +void +m88110_cmmu_sync_cache(vm_offset_t physaddr, int size) +{ + register int s = splhigh(); + + mc88110_inval_inst(); + mc88110_flush_data(); + mc88410_flush(); + splx(s); +} + +void +m88110_cmmu_sync_inval_cache(vm_offset_t physaddr, int size) +{ + register int s = splhigh(); + + mc88110_sync_data(); + mc88410_sync(); + splx(s); +} + +void +m88110_cmmu_inval_cache(vm_offset_t physaddr, int size) +{ + register int s = splhigh(); + + mc88110_inval_inst(); + mc88110_inval_data(); + mc88410_inval(); + splx(s); +} + +void +m88110_dma_cachectl(vm_offset_t va, int size, int op) +{ + if (op == DMA_CACHE_SYNC) + m88110_cmmu_sync_cache(kvtop(va), size); + else if (op == DMA_CACHE_SYNC_INVAL) + m88110_cmmu_sync_inval_cache(kvtop(va), size); + else + m88110_cmmu_inval_cache(kvtop(va), size); +} + +#ifdef DDB + + #define VV_EX_UNMOD 0 + #define VV_EX_MOD 1 + #define VV_SHARED_UNMOD 2 + #define VV_INVALID 3 + + #define D(UNION, LINE) \ + ((LINE) == 3 ? (UNION).field.d3 : \ + ((LINE) == 2 ? (UNION).field.d2 : \ + ((LINE) == 1 ? (UNION).field.d1 : \ + ((LINE) == 0 ? (UNION).field.d0 : ~0)))) + #define VV(UNION, LINE) \ + ((LINE) == 3 ? (UNION).field.vv3 : \ + ((LINE) == 2 ? (UNION).field.vv2 : \ + ((LINE) == 1 ? (UNION).field.vv1 : \ + ((LINE) == 0 ? (UNION).field.vv0 : ~0)))) + + + #undef VEQR_ADDR + #define VEQR_ADDR 0 + +/* + * Show (for debugging) how the given CMMU translates the given ADDRESS. + * If cmmu == -1, the data cmmu for the current cpu is used. + */ +void +m88110_cmmu_show_translation(unsigned address, + unsigned supervisor_flag, + unsigned verbose_flag, + int cmmu_num) +{ + /* + * A virtual address is split into three fields. Two are used as + * indicies into tables (segment and page), and one is an offset into + * a page of memory. + */ + union { + unsigned bits; + struct { + unsigned segment_table_index:10, + page_table_index:10, + page_offset:12; + } field; + } virtual_address; + unsigned value; + unsigned result; + unsigned probeaddr; + + if (verbose_flag) + db_printf("-------------------------------------------\n"); + + if (supervisor_flag) + value = get_dsap(); + else + value = get_duap(); + + /******* SEE WHAT A PROBE SAYS (if not a thread) ***********/ + + set_dsar(address); + if (supervisor_flag) { + set_dcmd(CMMU_DCMD_PRB_SUPR); + } else { + set_dcmd(CMMU_DCMD_PRB_USER); + } + result = get_dsr(); + probeaddr = get_dsar(); + if (verbose_flag > 1) + DEBUG_MSG("probe of 0x%08x returns dsr=0x%08x\n", + address, result); + if (result & CMMU_DSR_PH || result & CMMU_DSR_BH) { + DEBUG_MSG("probe of 0x%08x returns phys=0x%x", + address, probeaddr); + if (result & CMMU_DSR_CP) DEBUG_MSG(", copyback err"); + if (result & CMMU_DSR_BE) DEBUG_MSG(", bus err"); + if (result & CMMU_DSR_TBE) DEBUG_MSG(", table search bus error"); + if (result & CMMU_DSR_SU) DEBUG_MSG(", sup prot"); + if (result & CMMU_DSR_WE) DEBUG_MSG(", write prot"); + if (result & CMMU_DSR_PH) DEBUG_MSG(", PATC"); + if (result & CMMU_DSR_BH) DEBUG_MSG(", BATC"); + } else { + DEBUG_MSG("probe of 0x%08x missed the ATCs"); +} + DEBUG_MSG(".\n"); + + /******* INTERPRET AREA DESCRIPTOR *********/ + { + union apr_template apr_template; + apr_template.bits = value; + if (verbose_flag > 1) { + DEBUG_MSG(" %cAPR is 0x%08x\n", + supervisor_flag ? 'S' : 'U', apr_template.bits); + } + DEBUG_MSG(" %cAPR: SegTbl: 0x%x000p", + supervisor_flag ? 'S' : 'U', apr_template.field.st_base); + if (apr_template.field.wt) DEBUG_MSG(", WTHRU"); + else DEBUG_MSG(", !wthru"); + if (apr_template.field.g) DEBUG_MSG(", GLOBAL"); + else DEBUG_MSG(", !global"); + if (apr_template.field.ci) DEBUG_MSG(", $INHIBIT"); + else DEBUG_MSG(", $ok"); + if (apr_template.field.te) DEBUG_MSG(", VALID"); + else DEBUG_MSG(", !valid"); + DEBUG_MSG(".\n"); + + /* if not valid, done now */ + if (apr_template.field.te == 0) { + DEBUG_MSG("<would report an error, valid bit not set>\n"); + return; + } + value = apr_template.field.st_base << 12; /* now point to seg page */ + } + + /* translate value from physical to virtual */ + if (verbose_flag) + DEBUG_MSG("[%x physical is %x virtual]\n", value, value + VEQR_ADDR); + value += VEQR_ADDR; + + virtual_address.bits = address; + + /****** ACCESS SEGMENT TABLE AND INTERPRET SEGMENT DESCRIPTOR *******/ + { + union sdt_entry_template std_template; + if (verbose_flag) + DEBUG_MSG("will follow to entry %d of page at 0x%x...\n", + virtual_address.field.segment_table_index, value); + value |= virtual_address.field.segment_table_index * + sizeof(struct sdt_entry); + + if (badwordaddr((vm_offset_t)value)) { + DEBUG_MSG("ERROR: unable to access page at 0x%08x.\n", value); + return; + } + + std_template.bits = *(unsigned *)value; + if (verbose_flag > 1) + DEBUG_MSG("SEG DESC @0x%x is 0x%08x\n", value, std_template.bits); + DEBUG_MSG("SEG DESC @0x%x: PgTbl: 0x%x000", + value, std_template.sdt_desc.table_addr); + if (std_template.sdt_desc.wt) DEBUG_MSG(", WTHRU"); + else DEBUG_MSG(", !wthru"); + if (std_template.sdt_desc.sup) DEBUG_MSG(", S-PROT"); + else DEBUG_MSG(", UserOk"); + if (std_template.sdt_desc.g) DEBUG_MSG(", GLOBAL"); + else DEBUG_MSG(", !global"); + if (std_template.sdt_desc.no_cache) DEBUG_MSG(", $INHIBIT"); + else DEBUG_MSG(", $ok"); + if (std_template.sdt_desc.prot) DEBUG_MSG(", W-PROT"); + else DEBUG_MSG(", WriteOk"); + if (std_template.sdt_desc.dtype) DEBUG_MSG(", VALID"); + else DEBUG_MSG(", !valid"); + DEBUG_MSG(".\n"); + + /* if not valid, done now */ + if (std_template.sdt_desc.dtype == 0) { + DEBUG_MSG("<would report an error, STD entry not valid>\n"); + return; + } + value = std_template.sdt_desc.table_addr << 12; + } + + /* translate value from physical to virtual */ + if (verbose_flag) + DEBUG_MSG("[%x physical is %x virtual]\n", value, value + VEQR_ADDR); + value += VEQR_ADDR; + + /******* PAGE TABLE *********/ + { + union pte_template pte_template; + if (verbose_flag) + DEBUG_MSG("will follow to entry %d of page at 0x%x...\n", + virtual_address.field.page_table_index, value); + value |= virtual_address.field.page_table_index * + sizeof(struct pt_entry); + + if (badwordaddr((vm_offset_t)value)) { + DEBUG_MSG("error: unable to access page at 0x%08x.\n", value); + + return; + } + + pte_template.bits = *(unsigned *)value; + if (verbose_flag > 1) + DEBUG_MSG("PAGE DESC @0x%x is 0x%08x.\n", value, pte_template.bits); + DEBUG_MSG("PAGE DESC @0x%x: page @%x000", + value, pte_template.pte.pfn); + if (pte_template.pte.wired) DEBUG_MSG(", WIRE"); + else DEBUG_MSG(", !wire"); + if (pte_template.pte.wt) DEBUG_MSG(", WTHRU"); + else DEBUG_MSG(", !wthru"); + if (pte_template.pte.sup) DEBUG_MSG(", S-PROT"); + else DEBUG_MSG(", UserOk"); + if (pte_template.pte.g) DEBUG_MSG(", GLOBAL"); + else DEBUG_MSG(", !global"); + if (pte_template.pte.ci) DEBUG_MSG(", $INHIBIT"); + else DEBUG_MSG(", $ok"); + if (pte_template.pte.modified) DEBUG_MSG(", MOD"); + else DEBUG_MSG(", !mod"); + if (pte_template.pte.pg_used) DEBUG_MSG(", USED"); + else DEBUG_MSG(", !used"); + if (pte_template.pte.prot) DEBUG_MSG(", W-PROT"); + else DEBUG_MSG(", WriteOk"); + if (pte_template.pte.dtype) DEBUG_MSG(", VALID"); + else DEBUG_MSG(", !valid"); + DEBUG_MSG(".\n"); + + /* if not valid, done now */ + if (pte_template.pte.dtype == 0) { + DEBUG_MSG("<would report an error, PTE entry not valid>\n"); + return; + } + + value = pte_template.pte.pfn << 12; + if (verbose_flag) + DEBUG_MSG("will follow to byte %d of page at 0x%x...\n", + virtual_address.field.page_offset, value); + value |= virtual_address.field.page_offset; + + if (badwordaddr((vm_offset_t)value)) { + DEBUG_MSG("error: unable to access page at 0x%08x.\n", value); + return; + } + } + + /* translate value from physical to virtual */ + if (verbose_flag) + DEBUG_MSG("[%x physical is %x virtual]\n", value, value + VEQR_ADDR); + value += VEQR_ADDR; + + DEBUG_MSG("WORD at 0x%x is 0x%08x.\n", value, *(unsigned *)value); +} + + +void +m88110_cmmu_cache_state(unsigned addr, unsigned supervisor_flag) +{ +#ifdef not_yet + static char *vv_name[4] = + {"exclu-unmod", "exclu-mod", "shared-unmod", "invalid"}; + int cmmu_num; +#endif +} + +void +m88110_show_cmmu_info(unsigned addr) +{ + m88110_cmmu_cache_state(addr, 1); +} +#endif /* end if DDB */ + +#define MSDTENT(addr, va) ((sdt_entry_t *)(addr + SDTIDX(va))) +#define MPDTENT(addr, va) ((sdt_entry_t *)(addr + PDTIDX(va))) +void +m88110_load_patc(int entry, vm_offset_t vaddr, vm_offset_t paddr, int kernel) +{ + unsigned long lpa, pfa, i; + + lpa = (unsigned)vaddr & 0xFFFFF000; + if (kernel) { + lpa |= 0x01; + } + pfa = (unsigned)paddr & 0xFFFFF000; + pfa |= 0x01; + i = entry << 5; + set_iir(i); + set_ippu(lpa); + set_ippl(pfa); + set_dir(i); + set_dppu(lpa); + set_dppl(lpa); +} + +#define SDT_WP(sd_ptr) ((sd_ptr)->prot != 0) +#define SDT_SUP(sd_ptr) ((sd_ptr)->sup != 0) +#define PDT_WP(pte_ptr) ((pte_ptr)->prot != 0) +#define PDT_SUP(pte_ptr) ((pte_ptr)->sup != 0) + +int +m88110_table_search(pmap_t map, vm_offset_t virt, int write, int kernel, int data) +{ + sdt_entry_t *sdt; + pt_entry_t *pte; + unsigned long lpa, i; + static unsigned int entry_num = 0; + + if (map == (pmap_t)0) + panic("m88110_table_search: pmap is NULL"); + + sdt = SDTENT(map, virt); + + /* + * Check whether page table exist or not. + */ + if (!SDT_VALID(sdt)) + return (4); /* seg fault */ + + /* OK, it's valid. Now check permissions. */ + if (!kernel && SDT_SUP(sdt)) + return (6); /* Supervisor Violation */ + if (write && SDT_WP(sdt)) + return (7); /* Write Violation */ + + pte = (pt_entry_t *)(((sdt + SDT_ENTRIES)->table_addr)<<PDT_SHIFT) + PDTIDX(virt); + /* + * Check whether page frame exist or not. + */ + if (!PDT_VALID(pte)) + return (5); /* Page Fault */ + + /* OK, it's valid. Now check permissions. */ + if (!kernel && PDT_SUP(pte)) + return (6); /* Supervisor Violation */ + if (write && PDT_WP(pte)) + return (7); /* Write Violation */ + /* If we get here, load the PATC. */ + entry_num++; + if (entry_num > 32) + entry_num = 0; + lpa = (unsigned)virt & 0xFFFFF000; + if (kernel) + lpa |= 0x01; + i = entry_num << 5; + if (data) { + set_dir(i); /* set PATC index */ + set_dppu(lpa); /* set logical address */ + set_dppl((unsigned)pte); /* set page fram address */ + } else { + set_iir(i); + set_ippu(lpa); + set_ippl((unsigned)pte); + } + return 0; +} + +#endif /* M88110 */ + + diff --git a/sys/arch/mvme88k/mvme88k/m18x_cmmu.c b/sys/arch/mvme88k/mvme88k/m8820x.c index 8a3bded4a00..003b67e5fc2 100644 --- a/sys/arch/mvme88k/mvme88k/m18x_cmmu.c +++ b/sys/arch/mvme88k/mvme88k/m8820x.c @@ -1,6 +1,6 @@ -/* $OpenBSD: m18x_cmmu.c,v 1.18 2001/12/22 07:35:43 smurph Exp $ */ +/* $OpenBSD: m8820x.c,v 1.9 2001/12/22 09:49:39 smurph Exp $ */ /* - * Copyright (c) 1998 Steve Murphree, Jr. + * Copyright (c) 2001 Steve Murphree, Jr. * Copyright (c) 1996 Nivas Madhur * All rights reserved. * @@ -57,6 +57,7 @@ * any improvements or extensions that they make and grant Carnegie the * rights to redistribute these changes. */ +#ifdef M88100 #include <sys/param.h> #include <sys/types.h> @@ -68,29 +69,27 @@ #include <machine/cpus.h> #include <machine/cpu_number.h> #include <machine/locore.h> -#include <machine/m8820x.h> -#ifdef DDB -#include <ddb/db_output.h> /* db_printf() */ -#endif /* DDB */ +#include <machine/cmmu.h> #ifdef DDB +#include <ddb/db_output.h> /* db_printf() */ #define DEBUG_MSG db_printf #else #define DEBUG_MSG printf #endif /* DDB */ + /* On some versions of 88200, page size flushes don't work. I am using * sledge hammer approach till I find for sure which ones are bad XXX nivas */ #define BROKEN_MMU_MASK -#define CMMU_DEBUG #ifdef DEBUG #define DB_CMMU 0x4000 /* MMU debug */ -unsigned int m18x_debuglevel = 0; +unsigned int m8820x_debuglevel = 0; #define dprintf(_L_,_X_) \ do { \ - if (m18x_debuglevel & (_L_)) { \ + if (m8820x_debuglevel & (_L_)) { \ unsigned int psr = disable_interrupts_return_psr(); \ printf("%d: ", cpu_number()); \ printf _X_; \ @@ -102,6 +101,41 @@ unsigned int m18x_debuglevel = 0; #endif #undef SHADOW_BATC /* don't use BATCs for now XXX nivas */ +/* This is the function table for the mc8820x CMMUs */ +struct cmmu_p cmmu8820x = { + m8820x_cmmu_init, + m8820x_show_apr, + m8820x_setup_board_config, + m8820x_setup_cmmu_config, + m8820x_cmmu_dump_config, + m8820x_cpu_configuration_print, + m8820x_cmmu_shutdown_now, + m8820x_cmmu_parity_enable, + m8820x_cmmu_cpu_number, + m8820x_cmmu_get_idr, + m8820x_cmmu_set_sapr, + m8820x_cmmu_remote_set_sapr, + m8820x_cmmu_set_uapr, + m8820x_cmmu_set_batc_entry, + m8820x_cmmu_set_pair_batc_entry, + m8820x_cmmu_flush_remote_tlb, + m8820x_cmmu_flush_tlb, + m8820x_cmmu_pmap_activate, + m8820x_cmmu_flush_remote_cache, + m8820x_cmmu_flush_cache, + m8820x_cmmu_flush_remote_inst_cache, + m8820x_cmmu_flush_inst_cache, + m8820x_cmmu_flush_remote_data_cache, + m8820x_cmmu_flush_data_cache, + m8820x_dma_cachectl, +#ifdef DDB + m8820x_cmmu_get_by_mode, + m8820x_cmmu_show_translation, + m8820x_cmmu_cache_state, + m8820x_show_cmmu_info, +#endif /* end if DDB */ +}; + struct cmmu_regs { /* base + $000 */volatile unsigned idr; /* base + $004 */volatile unsigned scr; @@ -133,7 +167,7 @@ struct cmmu_regs { /* base + $8B0 */volatile unsigned cssp3; }; -struct cmmu { +struct m8820x_cmmu { struct cmmu_regs *cmmu_regs; /* CMMU "base" area */ unsigned char cmmu_cpu; /* cpu number it is attached to */ unsigned char which; /* either INST_CMMU || DATA_CMMU */ @@ -174,25 +208,17 @@ error("ack gag barf!"); int vme188_config; -/* prototypes */ -void m18x_setup_cmmu_config __P((void)); -void m18x_setup_board_config __P((void)); -#if defined(CMMU_DEBUG) -void m18x_show_apr __P((unsigned value)); -void m18x_show_sctr __P((unsigned value)); -#endif -unsigned m18x_cmmu_get __P((int mmu, int reg)); -void m18x_cmmu_set __P((int reg, unsigned val, int flags, int num, - int mode, int access, vm_offset_t addr)); -void m18x_cmmu_sync_cache __P((vm_offset_t physaddr, int size)); -void m18x_cmmu_sync_inval_cache __P((vm_offset_t physaddr, int size)); -void m18x_cmmu_inval_cache __P((vm_offset_t physaddr, int size)); -int m18x_cmmu_alive __P((int)); -void m18x_cmmu_store __P((int, int, unsigned)); - -#ifdef CMMU_DEBUG +/* local prototypes */ +unsigned m8820x_cmmu_get __P((int mmu, int reg)); +void m8820x_cmmu_store __P((int, int, unsigned)); +void m8820x_cmmu_set __P((int, unsigned, int, int, int, int, vm_offset_t)); +void m8820x_cmmu_sync_cache __P((vm_offset_t, int)); +void m8820x_cmmu_sync_inval_cache __P((vm_offset_t, int)); +void m8820x_cmmu_inval_cache __P((vm_offset_t, int)); +int m8820x_cmmu_alive __P((int)); + void -m18x_show_apr(value) +m8820x_show_apr(value) unsigned value; { union apr_template apr_template; @@ -207,28 +233,6 @@ m18x_show_apr(value) printf("\n"); } -void -m18x_show_sctr(value) - unsigned value; -{ - union { - unsigned bits; - struct { - unsigned :16, - pe: 1, - se: 1, - pr: 1, - :13; - } fields; - } sctr; - sctr.bits = value; - printf("%spe, %sse %spr]\n", - sctr.fields.pe ? "" : "!", - sctr.fields.se ? "" : "!", - sctr.fields.pr ? "" : "!"); -} -#endif - /*---------------------------------------------------------------- * The cmmu.c module was initially designed for the Omron Luna 88K * layout consisting of 4 CPUs with 2 CMMUs each, one for data @@ -285,7 +289,8 @@ struct board_config { int supported; int ncpus; int ncmmus; -} bd_config[] = { +} bd_config[] = +{ /* sup, CPU MMU */ { 1, 4, 8}, /* 4P128 - 4P512 */ { 1, 2, 8}, /* 2P128 - 2P512 */ @@ -309,7 +314,8 @@ struct board_config { * Structure for accessing MMUS properly. */ -struct cmmu cmmu[MAX_CMMUS] = { +struct m8820x_cmmu m8820x_cmmu[MAX_CMMUS] = +{ /* addr cpu mode access alive addr mask */ {(void *)VME_CMMU_I0, -1, INST_CMMU, CMMU_ACS_BOTH, @@ -331,11 +337,11 @@ struct cmmu cmmu[MAX_CMMUS] = { }; struct cpu_cmmu { - struct cmmu *pair[2]; + struct m8820x_cmmu *pair[2]; } cpu_cmmu[MAX_CPUS]; void -m18x_setup_board_config() +m8820x_setup_board_config() { volatile unsigned long *whoami; @@ -343,26 +349,26 @@ m18x_setup_board_config() switch (brdtyp) { #ifdef MVME187 case BRD_187: - vme188_config = 10; /* There is no WHOAMI reg on MVME1x7 - fake it... */ - cmmu[0].cmmu_regs = (void *)SBC_CMMU_I; - cmmu[0].cmmu_cpu = 0; - cmmu[1].cmmu_regs = (void *)SBC_CMMU_D; - cmmu[1].cmmu_cpu = 0; - cmmu[2].cmmu_regs = (void *)NULL; - cmmu[3].cmmu_regs = (void *)NULL; - cmmu[4].cmmu_regs = (void *)NULL; - cmmu[5].cmmu_regs = (void *)NULL; - cmmu[6].cmmu_regs = (void *)NULL; - cmmu[7].cmmu_regs = (void *)NULL; + vme188_config = 10; /* There is no WHOAMI reg on MVME187 - fake it... */ + m8820x_cmmu[0].cmmu_regs = (void *)SBC_CMMU_I; + m8820x_cmmu[0].cmmu_cpu = 0; + m8820x_cmmu[1].cmmu_regs = (void *)SBC_CMMU_D; + m8820x_cmmu[1].cmmu_cpu = 0; + m8820x_cmmu[2].cmmu_regs = (void *)NULL; + m8820x_cmmu[3].cmmu_regs = (void *)NULL; + m8820x_cmmu[4].cmmu_regs = (void *)NULL; + m8820x_cmmu[5].cmmu_regs = (void *)NULL; + m8820x_cmmu[6].cmmu_regs = (void *)NULL; + m8820x_cmmu[7].cmmu_regs = (void *)NULL; max_cpus = 1; max_cmmus = 2; break; -#endif /* defined(MVME187) */ +#endif /* MVME187 */ #ifdef MVME188 case BRD_188: whoami = (volatile unsigned long *)MVME188_WHOAMI; vme188_config = (*whoami & 0xf0) >> 4; - dprintf(DB_CMMU,("m18x_setup_board_config: WHOAMI @ 0x%08x holds value 0x%08x vme188_config = %d\n", + dprintf(DB_CMMU,("m8820x_setup_board_config: WHOAMI @ 0x%08x holds value 0x%08x vme188_config = %d\n", whoami, *whoami, vme188_config)); max_cpus = bd_config[vme188_config].ncpus; max_cmmus = bd_config[vme188_config].ncmmus; @@ -380,7 +386,7 @@ m18x_setup_board_config() case 1: printf("MVME%x board configuration #%X: %d CPUs %d CMMUs\n", cputyp, vme188_config, max_cpus, max_cmmus); - m18x_setup_cmmu_config(); + m8820x_setup_cmmu_config(); break; default: panic("UNKNOWN MVME%x board configuration: WHOAMI = 0x%02x", cputyp, *whoami); @@ -395,7 +401,7 @@ m18x_setup_board_config() * motorola/m88k/m88100/cmmu.c module. */ void -m18x_setup_cmmu_config() +m8820x_setup_cmmu_config() { register int num, cmmu_num; #ifdef MVME188 @@ -404,25 +410,26 @@ m18x_setup_cmmu_config() volatile unsigned long *pcnfb; #endif - dprintf(DB_CMMU,("m18x_setup_cmmu_config: initializing with %d CPU(s) and %d CMMU(s)\n", + dprintf(DB_CMMU,("m8820x_setup_cmmu_config: initializing with %d CPU(s) and %d CMMU(s)\n", max_cpus, max_cmmus)); /* * Probe for available MMUs */ for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) - if (!badwordaddr((vm_offset_t)cmmu[cmmu_num].cmmu_regs)) { + if (!badwordaddr((vm_offset_t)m8820x_cmmu[cmmu_num].cmmu_regs)) { union cpupid id; - id.cpupid = cmmu[cmmu_num].cmmu_regs->idr; - if (id.m88200.type != M88200_ID && id.m88200.type != M88204_ID) { + id.cpupid = m8820x_cmmu[cmmu_num].cmmu_regs->idr; + if (id.m88200.type != M88200_ID && + id.m88200.type != M88204_ID) { printf("WARNING: non M8820x circuit found at CMMU address 0x%08x\n", - cmmu[cmmu_num].cmmu_regs); + m8820x_cmmu[cmmu_num].cmmu_regs); continue; } - cmmu[cmmu_num].cmmu_alive = CMMU_ALIVE; - dprintf(DB_CMMU,("m18x_setup_cmmu_config: CMMU %d found at 0x%08x\n", - cmmu_num, cmmu[cmmu_num].cmmu_regs)); + m8820x_cmmu[cmmu_num].cmmu_alive = CMMU_ALIVE; + dprintf(DB_CMMU,("m8820x_setup_cmmu_config: CMMU %d found at 0x%08x\n", + cmmu_num, m8820x_cmmu[cmmu_num].cmmu_regs)); } /* @@ -436,13 +443,13 @@ m18x_setup_cmmu_config() for (i = 0; i < cpu_cmmu_ratio; i++) { dprintf(DB_CMMU,("cmmu_init: testing CMMU %d for CPU %d\n", num*cpu_cmmu_ratio+i, num)); - if (!m18x_cmmu_alive(num*cpu_cmmu_ratio + i)) { + if (!m8820x_cmmu_alive(num*cpu_cmmu_ratio + i)) { printf("CMMU %d attached to CPU %d is not working\n"); - panic("m18x_setup_cmmu_config"); + panic("m8820x_setup_cmmu_config"); } } cpu_sets[num] = 1; /* This cpu installed... */ - id.cpupid = cmmu[num*cpu_cmmu_ratio].cmmu_regs->idr; + id.cpupid = m8820x_cmmu[num*cpu_cmmu_ratio].cmmu_regs->idr; if (id.m88200.type == M88204_ID) printf("CPU%d is attached with %d MC88204 CMMUs\n", @@ -455,7 +462,7 @@ m18x_setup_cmmu_config() for (num = 0; num < max_cpus; num++) { cpu_cmmu_strategy[num].inst &= CMMU_SPLIT_MASK; cpu_cmmu_strategy[num].data &= CMMU_SPLIT_MASK; - dprintf(DB_CMMU,("m18x_setup_cmmu_config: CPU %d inst strat %d data strat %d\n", + dprintf(DB_CMMU,("m8820x_setup_cmmu_config: CPU %d inst strat %d data strat %d\n", num, cpu_cmmu_strategy[num].inst, cpu_cmmu_strategy[num].data)); } @@ -466,7 +473,7 @@ m18x_setup_cmmu_config() case CONFIG_0: case CONFIG_5: case CONFIG_A: - dprintf(DB_CMMU,("m18x_setup_cmmu_config: resetting strategies\n")); + dprintf(DB_CMMU,("m8820x_setup_cmmu_config: resetting strategies\n")); for (num = 0; num < max_cpus; num++) cpu_cmmu_strategy[num].inst = cpu_cmmu_strategy[num].data = CMMU_SPLIT_ADDRESS; @@ -482,7 +489,7 @@ m18x_setup_cmmu_config() val2 = (cpu_cmmu_strategy[1].inst << 2) | cpu_cmmu_strategy[1].data; *pcnfa = val1; *pcnfb = val2; - dprintf(DB_CMMU,("m18x_setup_cmmu_config: 2P128: PCNFA = 0x%x, PCNFB = 0x%x\n", val1, val2)); + dprintf(DB_CMMU,("m8820x_setup_cmmu_config: 2P128: PCNFA = 0x%x, PCNFB = 0x%x\n", val1, val2)); break; case CONFIG_2: pcnfa = (volatile unsigned long *)MVME188_PCNFA; @@ -491,46 +498,46 @@ m18x_setup_cmmu_config() val2 = (cpu_cmmu_strategy[0].data << 2) | cpu_cmmu_strategy[0].data; *pcnfa = val1; *pcnfb = val2; - dprintf(DB_CMMU,("m18x_setup_cmmu_config: 1P128: PCNFA = 0x%x, PCNFB = 0x%x\n", val1, val2)); + dprintf(DB_CMMU,("m8820x_setup_cmmu_config: 1P128: PCNFA = 0x%x, PCNFB = 0x%x\n", val1, val2)); break; case CONFIG_6: pcnfa = (volatile unsigned long *)MVME188_PCNFA; val1 = (cpu_cmmu_strategy[0].inst << 2) | cpu_cmmu_strategy[0].data; *pcnfa = val1; - dprintf(DB_CMMU,("m18x_setup_cmmu_config: 1P64: PCNFA = 0x%x\n", val1)); + dprintf(DB_CMMU,("m8820x_setup_cmmu_config: 1P64: PCNFA = 0x%x\n", val1)); break; #endif /* MVME188 */ default: - panic("m18x_setup_cmmu_config"); + panic("m8820x_setup_cmmu_config"); break; } #ifdef MVME188 - dprintf(DB_CMMU,("m18x_setup_cmmu_config: PCNFA = 0x%x, PCNFB = 0x%x\n", *pcnfa, *pcnfb)); + dprintf(DB_CMMU,("m8820x_setup_cmmu_config: PCNFA = 0x%x, PCNFB = 0x%x\n", *pcnfa, *pcnfb)); #endif /* MVME188 */ /* * Calculate the CMMU<->CPU connections */ for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) { - cmmu[cmmu_num].cmmu_cpu = + m8820x_cmmu[cmmu_num].cmmu_cpu = (int) (((float) cmmu_num) * ((float) max_cpus) / ((float) max_cmmus)); - dprintf(DB_CMMU,("m18x_setup_cmmu_config: CMMU %d connected with CPU %d\n", - cmmu_num, cmmu[cmmu_num].cmmu_cpu)); + dprintf(DB_CMMU,("m8820x_setup_cmmu_config: CMMU %d connected with CPU %d\n", + cmmu_num, m8820x_cmmu[cmmu_num].cmmu_cpu)); } /* - * Now set cmmu[].cmmu_access and addr + * Now set m8820x_cmmu[].cmmu_access and addr */ for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) { /* * We don't set up anything for the hardwired configurations. */ if (cpu_cmmu_ratio == 2) { - cmmu[cmmu_num].cmmu_addr = - cmmu[cmmu_num].cmmu_addr_mask = 0; - cmmu[cmmu_num].cmmu_addr_match = 1; - cmmu[cmmu_num].cmmu_access = CMMU_ACS_BOTH; + m8820x_cmmu[cmmu_num].cmmu_addr = + m8820x_cmmu[cmmu_num].cmmu_addr_mask = 0; + m8820x_cmmu[cmmu_num].cmmu_addr_match = 1; + m8820x_cmmu[cmmu_num].cmmu_access = CMMU_ACS_BOTH; continue; } @@ -538,33 +545,33 @@ m18x_setup_cmmu_config() * First we set the address/mask pairs for the exact address * matches. */ - switch ((cmmu[cmmu_num].which == INST_CMMU) ? - cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].inst : - cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].data) { + switch ((m8820x_cmmu[cmmu_num].which == INST_CMMU) ? + cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].inst : + cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].data) { case CMMU_SPLIT_ADDRESS: - cmmu[cmmu_num].cmmu_addr = ((cmmu_num & 0x2) ^ 0x2) << 11; - cmmu[cmmu_num].cmmu_addr_mask = CMMU_A12_MASK; - cmmu[cmmu_num].cmmu_addr_match = 1; + m8820x_cmmu[cmmu_num].cmmu_addr = ((cmmu_num & 0x2) ^ 0x2) << 11; + m8820x_cmmu[cmmu_num].cmmu_addr_mask = CMMU_A12_MASK; + m8820x_cmmu[cmmu_num].cmmu_addr_match = 1; break; case CMMU_SPLIT_SPV: - cmmu[cmmu_num].cmmu_addr = - cmmu[cmmu_num].cmmu_addr_mask = 0; - cmmu[cmmu_num].cmmu_addr_match = 1; + m8820x_cmmu[cmmu_num].cmmu_addr = + m8820x_cmmu[cmmu_num].cmmu_addr_mask = 0; + m8820x_cmmu[cmmu_num].cmmu_addr_match = 1; break; case CMMU_SPLIT_SRAM_ALL: - cmmu[cmmu_num].cmmu_addr = CMMU_SRAM; - cmmu[cmmu_num].cmmu_addr_mask = CMMU_SRAM_MASK; - cmmu[cmmu_num].cmmu_addr_match = (cmmu_num & 0x2) ? 1 : 0; + m8820x_cmmu[cmmu_num].cmmu_addr = CMMU_SRAM; + m8820x_cmmu[cmmu_num].cmmu_addr_mask = CMMU_SRAM_MASK; + m8820x_cmmu[cmmu_num].cmmu_addr_match = (cmmu_num & 0x2) ? 1 : 0; break; case CMMU_SPLIT_SRAM_SPV: if (cmmu_num & 0x2) { - cmmu[cmmu_num].cmmu_addr = CMMU_SRAM; - cmmu[cmmu_num].cmmu_addr_mask = CMMU_SRAM_MASK; + m8820x_cmmu[cmmu_num].cmmu_addr = CMMU_SRAM; + m8820x_cmmu[cmmu_num].cmmu_addr_mask = CMMU_SRAM_MASK; } else { - cmmu[cmmu_num].cmmu_addr = - cmmu[cmmu_num].cmmu_addr_mask = 0; + m8820x_cmmu[cmmu_num].cmmu_addr = + m8820x_cmmu[cmmu_num].cmmu_addr_mask = 0; } - cmmu[cmmu_num].cmmu_addr_match = 1; + m8820x_cmmu[cmmu_num].cmmu_addr_match = 1; break; } @@ -575,26 +582,26 @@ m18x_setup_cmmu_config() * NOT TESTED!!! - em */ if (cpu_cmmu_ratio > 4) { - cmmu[cmmu_num].cmmu_addr |= ((cmmu_num & 0x4) ^ 0x4) << 12; - cmmu[cmmu_num].cmmu_addr_mask |= CMMU_A14_MASK; + m8820x_cmmu[cmmu_num].cmmu_addr |= ((cmmu_num & 0x4) ^ 0x4) << 12; + m8820x_cmmu[cmmu_num].cmmu_addr_mask |= CMMU_A14_MASK; } /* * Next we cope with the various access modes. */ - switch ((cmmu[cmmu_num].which == INST_CMMU) ? - cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].inst : - cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].data) { + switch ((m8820x_cmmu[cmmu_num].which == INST_CMMU) ? + cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].inst : + cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].data) { case CMMU_SPLIT_SPV: - cmmu[cmmu_num].cmmu_access = + m8820x_cmmu[cmmu_num].cmmu_access = (cmmu_num & 0x2 ) ? CMMU_ACS_USER : CMMU_ACS_SUPER; break; case CMMU_SPLIT_SRAM_SPV: - cmmu[cmmu_num].cmmu_access = + m8820x_cmmu[cmmu_num].cmmu_access = (cmmu_num & 0x2 ) ? CMMU_ACS_SUPER : CMMU_ACS_BOTH; break; default: - cmmu[cmmu_num].cmmu_access = CMMU_ACS_BOTH; + m8820x_cmmu[cmmu_num].cmmu_access = CMMU_ACS_BOTH; break; } } @@ -611,7 +618,7 @@ static char *cmmu_strat_string[] = { #endif void -m18x_cmmu_dump_config() +m8820x_cmmu_dump_config() { #ifdef MVME188 volatile unsigned long *pcnfa; @@ -625,7 +632,7 @@ m18x_cmmu_dump_config() #ifdef MVME187 case BRD_187: DEBUG_MSG("VME1x7 split mode\n\n"); -#endif /* defined(MVME187) */ +#endif /* MVME187 */ #ifdef MVME188 case BRD_188: pcnfa = (volatile unsigned long *)MVME188_PCNFA; @@ -634,17 +641,17 @@ m18x_cmmu_dump_config() for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) { DEBUG_MSG("CMMU #%d: %s CMMU for CPU %d:\n Strategy: %s\n %s access addr 0x%08x mask 0x%08x match %s\n", cmmu_num, - (cmmu[cmmu_num].which == INST_CMMU) ? "inst" : "data", - cmmu[cmmu_num].cmmu_cpu, - cmmu_strat_string[(cmmu[cmmu_num].which == INST_CMMU) ? - cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].inst : - cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].data], - (cmmu[cmmu_num].cmmu_access == CMMU_ACS_BOTH) ? "User and spv" : - ((cmmu[cmmu_num].cmmu_access == CMMU_ACS_USER) ? "User " : + (m8820x_cmmu[cmmu_num].which == INST_CMMU) ? "inst" : "data", + m8820x_cmmu[cmmu_num].cmmu_cpu, + cmmu_strat_string[(m8820x_cmmu[cmmu_num].which == INST_CMMU) ? + cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].inst : + cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].data], + (m8820x_cmmu[cmmu_num].cmmu_access == CMMU_ACS_BOTH) ? "User and spv" : + ((m8820x_cmmu[cmmu_num].cmmu_access == CMMU_ACS_USER) ? "User " : "Supervisor "), - cmmu[cmmu_num].cmmu_addr, - cmmu[cmmu_num].cmmu_addr_mask, - cmmu[cmmu_num].cmmu_addr_match ? "TRUE" : "FALSE"); + m8820x_cmmu[cmmu_num].cmmu_addr, + m8820x_cmmu[cmmu_num].cmmu_addr_mask, + m8820x_cmmu[cmmu_num].cmmu_addr_match ? "TRUE" : "FALSE"); } #endif /* MVME188 */ } @@ -652,25 +659,25 @@ m18x_cmmu_dump_config() /* To be implemented as a macro for speedup - XXX-em */ void -m18x_cmmu_store(mmu, reg, val) +m8820x_cmmu_store(mmu, reg, val) int mmu, reg; unsigned val; { - *(volatile unsigned *)(reg + (char *)(cmmu[mmu].cmmu_regs)) = val; + *(volatile unsigned *)(reg + (char*)(m8820x_cmmu[mmu].cmmu_regs)) = val; } int -m18x_cmmu_alive(mmu) +m8820x_cmmu_alive(mmu) int mmu; { - return (cmmu[mmu].cmmu_alive == CMMU_ALIVE); + return (m8820x_cmmu[mmu].cmmu_alive == CMMU_ALIVE); } unsigned -m18x_cmmu_get(mmu, reg) +m8820x_cmmu_get(mmu, reg) int mmu, reg; { - return *(volatile unsigned *)(reg + (char*)(cmmu[mmu].cmmu_regs)); + return *(volatile unsigned *)(reg + (char*)(m8820x_cmmu[mmu].cmmu_regs)); } /* @@ -678,7 +685,7 @@ m18x_cmmu_get(mmu, reg) * into the CMMU's registers. */ void -m18x_cmmu_set(reg, val, flags, num, mode, access, addr) +m8820x_cmmu_set(reg, val, flags, num, mode, access, addr) int reg; unsigned val; int flags, num, mode, access; @@ -692,7 +699,7 @@ m18x_cmmu_set(reg, val, flags, num, mode, access, addr) * Simply store the value away. */ /* assert(num < max_cmmus); */ - m18x_cmmu_store(num, reg, val); + m8820x_cmmu_store(num, reg, val); return; } @@ -702,19 +709,19 @@ m18x_cmmu_set(reg, val, flags, num, mode, access, addr) */ for (mmu = num*cpu_cmmu_ratio; mmu < (num+1)*cpu_cmmu_ratio; mmu++) { if (((flags & MODE_VAL)) && - (cmmu[mmu].which != mode)) + (m8820x_cmmu[mmu].which != mode)) continue; if (((flags & ACCESS_VAL)) && - (cmmu[mmu].cmmu_access != access) && - (cmmu[mmu].cmmu_access != CMMU_ACS_BOTH)) + (m8820x_cmmu[mmu].cmmu_access != access) && + (m8820x_cmmu[mmu].cmmu_access != CMMU_ACS_BOTH)) continue; if (flags & ADDR_VAL) { - if (((addr & cmmu[mmu].cmmu_addr_mask) == cmmu[mmu].cmmu_addr) - != cmmu[mmu].cmmu_addr_match) { + if (((addr & m8820x_cmmu[mmu].cmmu_addr_mask) == m8820x_cmmu[mmu].cmmu_addr) + != m8820x_cmmu[mmu].cmmu_addr_match) { continue; } } - m18x_cmmu_store(mmu, reg, val); + m8820x_cmmu_store(mmu, reg, val); } } @@ -723,17 +730,17 @@ m18x_cmmu_set(reg, val, flags, num, mode, access, addr) * Used by DDB for cache probe functions */ unsigned -m18x_cmmu_get_by_mode(cpu, mode) +m8820x_cmmu_get_by_mode(cpu, mode) int cpu, mode; { register int mmu; for (mmu = cpu*cpu_cmmu_ratio; mmu < (cpu+1)*cpu_cmmu_ratio; mmu++) - if (cmmu[mmu].which == mode) + if (m8820x_cmmu[mmu].which == mode) return mmu; printf("can't figure out first %s CMMU for CPU %d\n", (mode == DATA_CMMU) ? "data" : "instruction", cpu); - panic("m18x_cmmu_get_by_mode"); + panic("m8820x_cmmu_get_by_mode"); /* NOTREACHED */ return(0); } @@ -756,7 +763,7 @@ static char *mmutypes[8] = { * by the master, before the slaves are started. */ void -m18x_cpu_configuration_print(master) +m8820x_cpu_configuration_print(master) int master; { int pid = read_processor_identification_register(); @@ -783,14 +790,14 @@ m18x_cpu_configuration_print(master) #endif for (mmu = cpu*cpu_cmmu_ratio; mmu < (cpu+1)*cpu_cmmu_ratio; mmu++) { - int idr = m18x_cmmu_get(mmu, CMMU_IDR); + int idr = m8820x_cmmu_get(mmu, CMMU_IDR); int mmuid = (0xe00000 & idr)>>21; printf(" %s %s Cache: ", - (cmmu[mmu].cmmu_access == CMMU_ACS_BOTH) ? "Spv and User" : - ((cmmu[mmu].cmmu_access == CMMU_ACS_USER) ? "User " : + (m8820x_cmmu[mmu].cmmu_access == CMMU_ACS_BOTH) ? "Spv and User" : + ((m8820x_cmmu[mmu].cmmu_access == CMMU_ACS_USER) ? "User " : "Supervisor "), - (cmmu[mmu].which == INST_CMMU) ? "Instruction" : + (m8820x_cmmu[mmu].which == INST_CMMU) ? "Instruction" : "Data "); if (mmutypes[mmuid][0] == 'U') printf("Type 0x%x ", mmuid); @@ -807,7 +814,7 @@ m18x_cpu_configuration_print(master) * CMMU initialization routine */ void -m18x_cmmu_init() +m8820x_cmmu_init() { unsigned tmp, cmmu_num; union cpupid id; @@ -818,33 +825,33 @@ m18x_cmmu_init() } for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++){ - if (m18x_cmmu_alive(cmmu_num)) { - id.cpupid = cmmu[cmmu_num].cmmu_regs->idr; + if (m8820x_cmmu_alive(cmmu_num)) { + id.cpupid = m8820x_cmmu[cmmu_num].cmmu_regs->idr; - cpu_cmmu[cmmu[cmmu_num].cmmu_cpu].pair[cmmu[cmmu_num].which] = - &cmmu[cmmu_num]; + cpu_cmmu[m8820x_cmmu[cmmu_num].cmmu_cpu].pair[m8820x_cmmu[cmmu_num].which] = + &m8820x_cmmu[cmmu_num]; /* * Reset cache data.... * as per M88200 Manual (2nd Ed.) section 3.11. */ for (tmp = 0; tmp < 255; tmp++) { - cmmu[cmmu_num].cmmu_regs->sar = tmp << 4; - cmmu[cmmu_num].cmmu_regs->cssp = 0x3f0ff000; + m8820x_cmmu[cmmu_num].cmmu_regs->sar = tmp << 4; + m8820x_cmmu[cmmu_num].cmmu_regs->cssp = 0x3f0ff000; } /* 88204 has additional cache to clear */ if (id.m88200.type == M88204_ID) { for (tmp = 0; tmp < 255; tmp++) { - cmmu[cmmu_num].cmmu_regs->sar = tmp<<4; - cmmu[cmmu_num].cmmu_regs->cssp1 = 0x3f0ff000; + m8820x_cmmu[cmmu_num].cmmu_regs->sar = tmp<<4; + m8820x_cmmu[cmmu_num].cmmu_regs->cssp1 = 0x3f0ff000; } for (tmp = 0; tmp < 255; tmp++) { - cmmu[cmmu_num].cmmu_regs->sar = tmp<<4; - cmmu[cmmu_num].cmmu_regs->cssp2 = 0x3f0ff000; + m8820x_cmmu[cmmu_num].cmmu_regs->sar = tmp<<4; + m8820x_cmmu[cmmu_num].cmmu_regs->cssp2 = 0x3f0ff000; } for (tmp = 0; tmp < 255; tmp++) { - cmmu[cmmu_num].cmmu_regs->sar = tmp<<4; - cmmu[cmmu_num].cmmu_regs->cssp3 = 0x3f0ff000; + m8820x_cmmu[cmmu_num].cmmu_regs->sar = tmp<<4; + m8820x_cmmu[cmmu_num].cmmu_regs->cssp3 = 0x3f0ff000; } } @@ -856,7 +863,7 @@ m18x_cmmu_init() ! CMMU_SCTR_PE | /* not parity enable */ ! CMMU_SCTR_SE | /* not snoop enable */ ! CMMU_SCTR_PR ; /* not priority arbitration */ - cmmu[cmmu_num].cmmu_regs->sctr = tmp; + m8820x_cmmu[cmmu_num].cmmu_regs->sctr = tmp; tmp = (0x00000 << 12) | /* segment table base address */ @@ -864,31 +871,31 @@ m18x_cmmu_init() AREA_D_G | /* global */ AREA_D_CI | /* cache inhibit */ ! AREA_D_TE ; /* not translation enable */ - cmmu[cmmu_num].cmmu_regs->sapr = - cmmu[cmmu_num].cmmu_regs->uapr = tmp; + m8820x_cmmu[cmmu_num].cmmu_regs->sapr = + m8820x_cmmu[cmmu_num].cmmu_regs->uapr = tmp; #ifdef SHADOW_BATC - cmmu[cmmu_num].batc[0] = - cmmu[cmmu_num].batc[1] = - cmmu[cmmu_num].batc[2] = - cmmu[cmmu_num].batc[3] = - cmmu[cmmu_num].batc[4] = - cmmu[cmmu_num].batc[5] = - cmmu[cmmu_num].batc[6] = - cmmu[cmmu_num].batc[7] = 0; + m8820x_cmmu[cmmu_num].batc[0] = + m8820x_cmmu[cmmu_num].batc[1] = + m8820x_cmmu[cmmu_num].batc[2] = + m8820x_cmmu[cmmu_num].batc[3] = + m8820x_cmmu[cmmu_num].batc[4] = + m8820x_cmmu[cmmu_num].batc[5] = + m8820x_cmmu[cmmu_num].batc[6] = + m8820x_cmmu[cmmu_num].batc[7] = 0; #endif - cmmu[cmmu_num].cmmu_regs->bwp[0] = - cmmu[cmmu_num].cmmu_regs->bwp[1] = - cmmu[cmmu_num].cmmu_regs->bwp[2] = - cmmu[cmmu_num].cmmu_regs->bwp[3] = - cmmu[cmmu_num].cmmu_regs->bwp[4] = - cmmu[cmmu_num].cmmu_regs->bwp[5] = - cmmu[cmmu_num].cmmu_regs->bwp[6] = - cmmu[cmmu_num].cmmu_regs->bwp[7] = 0; - cmmu[cmmu_num].cmmu_regs->scr = CMMU_FLUSH_CACHE_INV_ALL; - cmmu[cmmu_num].cmmu_regs->scr = CMMU_FLUSH_SUPER_ALL; - cmmu[cmmu_num].cmmu_regs->scr = CMMU_FLUSH_USER_ALL; + m8820x_cmmu[cmmu_num].cmmu_regs->bwp[0] = + m8820x_cmmu[cmmu_num].cmmu_regs->bwp[1] = + m8820x_cmmu[cmmu_num].cmmu_regs->bwp[2] = + m8820x_cmmu[cmmu_num].cmmu_regs->bwp[3] = + m8820x_cmmu[cmmu_num].cmmu_regs->bwp[4] = + m8820x_cmmu[cmmu_num].cmmu_regs->bwp[5] = + m8820x_cmmu[cmmu_num].cmmu_regs->bwp[6] = + m8820x_cmmu[cmmu_num].cmmu_regs->bwp[7] = 0; + m8820x_cmmu[cmmu_num].cmmu_regs->scr = CMMU_FLUSH_CACHE_INV_ALL; + m8820x_cmmu[cmmu_num].cmmu_regs->scr = CMMU_FLUSH_SUPER_ALL; + m8820x_cmmu[cmmu_num].cmmu_regs->scr = CMMU_FLUSH_USER_ALL; } } /* @@ -913,12 +920,12 @@ m18x_cmmu_init() ! CMMU_SCTR_PE | /* not parity enable */ ! CMMU_SCTR_PR ; /* not priority arbitration */ } - m18x_cmmu_set(CMMU_SCTR, tmp, 0, cpu, DATA_CMMU, 0, 0); - m18x_cmmu_set(CMMU_SCTR, tmp, 0, cpu, INST_CMMU, 0, 0); + m8820x_cmmu_set(CMMU_SCTR, tmp, 0, cpu, DATA_CMMU, 0, 0); + m8820x_cmmu_set(CMMU_SCTR, tmp, 0, cpu, INST_CMMU, 0, 0); - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL, ACCESS_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL, ACCESS_VAL, cpu, DATA_CMMU, CMMU_ACS_SUPER, 0); - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL, ACCESS_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL, ACCESS_VAL, cpu, INST_CMMU, CMMU_ACS_SUPER, 0); } @@ -943,13 +950,13 @@ m18x_cmmu_init() /* REGS(cpu, INST_CMMU).sapr = tmp; */ - m18x_cmmu_set(CMMU_SAPR, tmp, MODE_VAL, + m8820x_cmmu_set(CMMU_SAPR, tmp, MODE_VAL, cpu, INST_CMMU, 0, 0); /* REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_SUPER_ALL; */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL, ACCESS_VAL|MODE_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL, ACCESS_VAL|MODE_VAL, cpu, DATA_CMMU, CMMU_ACS_SUPER, 0); } } @@ -958,11 +965,12 @@ m18x_cmmu_init() * Just before poweroff or reset.... */ void -m18x_cmmu_shutdown_now() +m8820x_cmmu_shutdown_now() { unsigned tmp; unsigned cmmu_num; + CMMU_LOCK; /* * Now set some state as we like... */ @@ -978,7 +986,7 @@ m18x_cmmu_shutdown_now() ! CMMU_SCTR_PR ; /* priority arbitration */ } - cmmu[cmmu_num].cmmu_regs->sctr = tmp; + m8820x_cmmu[cmmu_num].cmmu_regs->sctr = tmp; tmp = (0x00000 << 12) | /* segment table base address */ @@ -987,9 +995,10 @@ m18x_cmmu_shutdown_now() AREA_D_CI | /* cache inhibit */ ! AREA_D_TE ; /* translation disable */ - cmmu[cmmu_num].cmmu_regs->sapr = tmp; - cmmu[cmmu_num].cmmu_regs->uapr = tmp; + m8820x_cmmu[cmmu_num].cmmu_regs->sapr = tmp; + m8820x_cmmu[cmmu_num].cmmu_regs->uapr = tmp; } + CMMU_UNLOCK; } #define PARITY_ENABLE @@ -997,23 +1006,25 @@ m18x_cmmu_shutdown_now() * enable parity */ void -m18x_cmmu_parity_enable() +m8820x_cmmu_parity_enable() { #ifdef PARITY_ENABLE register int cmmu_num; + CMMU_LOCK; for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) { - if (m18x_cmmu_alive(cmmu_num)) { + if (m8820x_cmmu_alive(cmmu_num)) { register unsigned val1 = - m18x_cmmu_get(cmmu_num, CMMU_SCTR); + m8820x_cmmu_get(cmmu_num, CMMU_SCTR); /* - cmmu[cmmu_num].cmmu_regs->sctr |= CMMU_SCTR_PE; + m8820x_cmmu[cmmu_num].cmmu_regs->sctr |= CMMU_SCTR_PE; */ - m18x_cmmu_set(CMMU_SCTR, val1 | CMMU_SCTR_PE, + m8820x_cmmu_set(CMMU_SCTR, val1 | CMMU_SCTR_PE, NUM_CMMU, cmmu_num, 0, 0, 0); } } + CMMU_UNLOCK; #endif /* PARITY_ENABLE */ } @@ -1025,18 +1036,19 @@ m18x_cmmu_parity_enable() #define ILLADDRESS U(0x0F000000) /* any faulty address */ unsigned -m18x_cmmu_cpu_number() +m8820x_cmmu_cpu_number() { register unsigned cmmu_no; int i; + CMMU_LOCK; for (i=0; i < 10; i++) { /* clear CMMU p-bus status registers */ for (cmmu_no = 0; cmmu_no < MAX_CMMUS; cmmu_no++) { - if (cmmu[cmmu_no].cmmu_alive == CMMU_AVAILABLE && - cmmu[cmmu_no].which == DATA_CMMU) - cmmu[cmmu_no].cmmu_regs->pfSTATUSr = 0; + if (m8820x_cmmu[cmmu_no].cmmu_alive == CMMU_AVAILABLE && + m8820x_cmmu[cmmu_no].which == DATA_CMMU) + m8820x_cmmu[cmmu_no].cmmu_regs->pfSTATUSr = 0; } /* access faulting address */ @@ -1044,28 +1056,28 @@ m18x_cmmu_cpu_number() /* check which CMMU reporting the fault */ for (cmmu_no = 0; cmmu_no < MAX_CMMUS; cmmu_no++) { - if (cmmu[cmmu_no].cmmu_alive == CMMU_AVAILABLE && - cmmu[cmmu_no].which == DATA_CMMU && - cmmu[cmmu_no].cmmu_regs->pfSTATUSr & 0x70000) { - if (cmmu[cmmu_no].cmmu_regs->pfSTATUSr & 0x70000) { - cmmu[cmmu_no].cmmu_regs->pfSTATUSr = 0; /* to be clean */ - cmmu[cmmu_no].cmmu_alive = CMMU_MARRIED; - return cmmu[cmmu_no].cmmu_cpu; + if (m8820x_cmmu[cmmu_no].cmmu_alive == CMMU_AVAILABLE && + m8820x_cmmu[cmmu_no].which == DATA_CMMU && + m8820x_cmmu[cmmu_no].cmmu_regs->pfSTATUSr & 0x70000) { + if (m8820x_cmmu[cmmu_no].cmmu_regs->pfSTATUSr & 0x70000) { + m8820x_cmmu[cmmu_no].cmmu_regs->pfSTATUSr = 0; /* to be clean */ + m8820x_cmmu[cmmu_no].cmmu_alive = CMMU_MARRIED; + return m8820x_cmmu[cmmu_no].cmmu_cpu; } } } } - panic("m18x_cmmu_cpu_number: could not determine my cpu number"); + panic("m8820x_cmmu_cpu_number: could not determine my cpu number"); + CMMU_UNLOCK; return 0; /* to make compiler happy */ } +#if 0 /* * Functions that actually modify CMMU registers. */ - void -m18x_cmmu_remote_set(cpu, r, data, x) - unsigned cpu, r, data, x; +m8820x_cmmu_remote_set(unsigned cpu, unsigned r, unsigned data, unsigned x) { *(volatile unsigned *)(r + (char*)®S(cpu,data)) = x; } @@ -1075,15 +1087,15 @@ m18x_cmmu_remote_set(cpu, r, data, x) * the CMMU_SCR or CMMU_SAR. */ unsigned -m18x_cmmu_remote_get(cpu, r, data) - unsigned cpu, r, data; +m8820x_cmmu_remote_get(unsigned cpu, unsigned r, unsigned data) { return (*(volatile unsigned *)(r + (char*)®S(cpu,data))); } +#endif /* Needs no locking - read only registers */ unsigned -m18x_cmmu_get_idr(data) +m8820x_cmmu_get_idr(data) unsigned data; { int cpu; @@ -1092,71 +1104,65 @@ m18x_cmmu_get_idr(data) } void -m18x_cmmu_set_sapr(ap) +m8820x_cmmu_set_sapr(ap) unsigned ap; { int cpu; cpu = cpu_number(); + CMMU_LOCK; if (cache_policy & CACHE_INH) ap |= AREA_D_CI; - /* - REGS(cpu, INST_CMMU).sapr = ap; - REGS(cpu, DATA_CMMU).sapr = ap; - */ - m18x_cmmu_set(CMMU_SAPR, ap, ACCESS_VAL, + m8820x_cmmu_set(CMMU_SAPR, ap, ACCESS_VAL, cpu, 0, CMMU_ACS_SUPER, 0); + CMMU_UNLOCK; } void -m18x_cmmu_remote_set_sapr(cpu, ap) +m8820x_cmmu_remote_set_sapr(cpu, ap) unsigned cpu, ap; { + CMMU_LOCK; if (cache_policy & CACHE_INH) ap |= AREA_D_CI; - - /* - REGS(cpu, INST_CMMU).sapr = ap; - REGS(cpu, DATA_CMMU).sapr = ap; - */ - m18x_cmmu_set(CMMU_SAPR, ap, ACCESS_VAL, + m8820x_cmmu_set(CMMU_SAPR, ap, ACCESS_VAL, cpu, 0, CMMU_ACS_SUPER, 0); + CMMU_UNLOCK; } void -m18x_cmmu_set_uapr(ap) +m8820x_cmmu_set_uapr(ap) unsigned ap; { + register int s = splhigh(); int cpu; + cpu = cpu_number(); - /* this functionality also mimiced in m18x_cmmu_pmap_activate() */ - /* - REGS(cpu, INST_CMMU).uapr = ap; - REGS(cpu, DATA_CMMU).uapr = ap; - */ - m18x_cmmu_set(CMMU_UAPR, ap, ACCESS_VAL, + CMMU_LOCK; + /* this functionality also mimiced in m8820x_cmmu_pmap_activate() */ + m8820x_cmmu_set(CMMU_UAPR, ap, ACCESS_VAL, cpu, 0, CMMU_ACS_USER, 0); + CMMU_UNLOCK; + splx(s); } /* * Set batc entry number entry_no to value in * the data or instruction cache depending on data. * - * Except for the cmmu_init, this function, m18x_cmmu_set_pair_batc_entry, - * and m18x_cmmu_pmap_activate are the only functions which may set the + * Except for the cmmu_init, this function, m8820x_cmmu_set_pair_batc_entry, + * and m8820x_cmmu_pmap_activate are the only functions which may set the * batc values. */ void -m18x_cmmu_set_batc_entry(cpu, entry_no, data, value) +m8820x_cmmu_set_batc_entry(cpu, entry_no, data, value) unsigned cpu, entry_no; unsigned data; /* 1 = data, 0 = instruction */ unsigned value; /* the value to stuff into the batc */ { - /* - REGS(cpu,data).bwp[entry_no] = value; - */ - m18x_cmmu_set(CMMU_BWP(entry_no), value, MODE_VAL|ACCESS_VAL, + CMMU_LOCK; + m8820x_cmmu_set(CMMU_BWP(entry_no), value, MODE_VAL|ACCESS_VAL, cpu, data, CMMU_ACS_USER, 0); #ifdef SHADOW_BATC CMMU(cpu,data)->batc[entry_no] = value; @@ -1165,6 +1171,7 @@ m18x_cmmu_set_batc_entry(cpu, entry_no, data, value) REGS(cpu,data).scr = CMMU_FLUSH_SUPER_ALL; REGS(cpu,data).scr = CMMU_FLUSH_USER_ALL; #endif + CMMU_UNLOCK; } /* @@ -1172,23 +1179,17 @@ m18x_cmmu_set_batc_entry(cpu, entry_no, data, value) * the data and instruction cache for the named CPU. */ void -m18x_cmmu_set_pair_batc_entry(cpu, entry_no, value) +m8820x_cmmu_set_pair_batc_entry(cpu, entry_no, value) unsigned cpu, entry_no; unsigned value; /* the value to stuff into the batc */ { - - /* - REGS(cpu,DATA_CMMU).bwp[entry_no] = value; - */ - m18x_cmmu_set(CMMU_BWP(entry_no), value, MODE_VAL|ACCESS_VAL, + CMMU_LOCK; + m8820x_cmmu_set(CMMU_BWP(entry_no), value, MODE_VAL|ACCESS_VAL, cpu, DATA_CMMU, CMMU_ACS_USER, 0); #ifdef SHADOW_BATC CMMU(cpu,DATA_CMMU)->batc[entry_no] = value; #endif - /* - REGS(cpu,INST_CMMU).bwp[entry_no] = value; - */ - m18x_cmmu_set(CMMU_BWP(entry_no), value, MODE_VAL|ACCESS_VAL, + m8820x_cmmu_set(CMMU_BWP(entry_no), value, MODE_VAL|ACCESS_VAL, cpu, INST_CMMU, CMMU_ACS_USER, 0); #ifdef SHADOW_BATC CMMU(cpu,INST_CMMU)->batc[entry_no] = value; @@ -1200,6 +1201,7 @@ m18x_cmmu_set_pair_batc_entry(cpu, entry_no, value) REGS(cpu,DATA_CMMU).scr = CMMU_FLUSH_SUPER_ALL; REGS(cpu,DATA_CMMU).scr = CMMU_FLUSH_USER_ALL; #endif + CMMU_UNLOCK; } /* @@ -1208,46 +1210,31 @@ m18x_cmmu_set_pair_batc_entry(cpu, entry_no, value) /* * flush any tlb - * Some functionality mimiced in m18x_cmmu_pmap_activate. + * Some functionality mimiced in m8820x_cmmu_pmap_activate. */ void -m18x_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size) +m8820x_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size) unsigned cpu, kernel; vm_offset_t vaddr; int size; { register int s = splhigh(); + CMMU_LOCK; if (cpu > max_cpus) { cpu = cpu_number(); } if ((unsigned)size > PAGE_SIZE) { - /* - REGS(cpu, INST_CMMU).scr = - REGS(cpu, DATA_CMMU).scr = - kernel ? CMMU_FLUSH_SUPER_ALL : CMMU_FLUSH_USER_ALL; - */ - - m18x_cmmu_set(CMMU_SCR, kernel ? CMMU_FLUSH_SUPER_ALL : CMMU_FLUSH_USER_ALL, ACCESS_VAL, + m8820x_cmmu_set(CMMU_SCR, kernel ? CMMU_FLUSH_SUPER_ALL : CMMU_FLUSH_USER_ALL, ACCESS_VAL, cpu, 0, kernel ? CMMU_ACS_SUPER : CMMU_ACS_USER, 0); } else { /* a page or smaller */ - /* - REGS(cpu, INST_CMMU).sar = (unsigned)vaddr; - REGS(cpu, DATA_CMMU).sar = (unsigned)vaddr; - */ - m18x_cmmu_set(CMMU_SAR, vaddr, ADDR_VAL|ACCESS_VAL, + m8820x_cmmu_set(CMMU_SAR, vaddr, ADDR_VAL|ACCESS_VAL, cpu, 0, kernel ? CMMU_ACS_SUPER : CMMU_ACS_USER, vaddr); - - /* - REGS(cpu, INST_CMMU).scr = - REGS(cpu, DATA_CMMU).scr = - kernel ? CMMU_FLUSH_SUPER_PAGE : CMMU_FLUSH_USER_PAGE; - */ - m18x_cmmu_set(CMMU_SCR, kernel ? CMMU_FLUSH_SUPER_PAGE : CMMU_FLUSH_USER_PAGE, ADDR_VAL|ACCESS_VAL, + m8820x_cmmu_set(CMMU_SCR, kernel ? CMMU_FLUSH_SUPER_PAGE : CMMU_FLUSH_USER_PAGE, ADDR_VAL|ACCESS_VAL, cpu, 0, kernel ? CMMU_ACS_SUPER : CMMU_ACS_USER, vaddr); } - + CMMU_UNLOCK; splx(s); } @@ -1255,14 +1242,14 @@ m18x_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size) * flush my personal tlb */ void -m18x_cmmu_flush_tlb(kernel, vaddr, size) +m8820x_cmmu_flush_tlb(kernel, vaddr, size) unsigned kernel; vm_offset_t vaddr; int size; { int cpu; cpu = cpu_number(); - m18x_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size); + m8820x_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size); } /* @@ -1271,30 +1258,22 @@ m18x_cmmu_flush_tlb(kernel, vaddr, size) * Only called from pmap.c's _pmap_activate(). */ void -m18x_cmmu_pmap_activate(cpu, uapr, i_batc, d_batc) +m8820x_cmmu_pmap_activate(cpu, uapr, i_batc, d_batc) unsigned cpu, uapr; batc_template_t i_batc[BATC_MAX]; batc_template_t d_batc[BATC_MAX]; { int entry_no; + CMMU_LOCK; - - /* the following is from m18x_cmmu_set_uapr */ - /* - REGS(cpu, INST_CMMU).uapr = uapr; - REGS(cpu, DATA_CMMU).uapr = uapr; - */ - m18x_cmmu_set(CMMU_UAPR, uapr, ACCESS_VAL, + /* the following is from m8820x_cmmu_set_uapr */ + m8820x_cmmu_set(CMMU_UAPR, uapr, ACCESS_VAL, cpu, 0, CMMU_ACS_USER, 0); for (entry_no = 0; entry_no < BATC_MAX; entry_no++) { - /* - REGS(cpu,INST_CMMU).bwp[entry_no] = i_batc[entry_no].bits; - REGS(cpu,DATA_CMMU).bwp[entry_no] = d_batc[entry_no].bits; - */ - m18x_cmmu_set(CMMU_BWP(entry_no), i_batc[entry_no].bits, MODE_VAL|ACCESS_VAL, + m8820x_cmmu_set(CMMU_BWP(entry_no), i_batc[entry_no].bits, MODE_VAL|ACCESS_VAL, cpu, INST_CMMU, CMMU_ACS_USER, 0); - m18x_cmmu_set(CMMU_BWP(entry_no), d_batc[entry_no].bits, MODE_VAL|ACCESS_VAL, + m8820x_cmmu_set(CMMU_BWP(entry_no), d_batc[entry_no].bits, MODE_VAL|ACCESS_VAL, cpu, DATA_CMMU, CMMU_ACS_USER, 0); #ifdef SHADOW_BATC CMMU(cpu,INST_CMMU)->batc[entry_no] = i_batc[entry_no].bits; @@ -1302,18 +1281,14 @@ m18x_cmmu_pmap_activate(cpu, uapr, i_batc, d_batc) #endif } - /* * Flush the user TLB. * IF THE KERNEL WILL EVER CARE ABOUT THE BATC ENTRIES, * THE SUPERVISOR TLBs SHOULB EE FLUSHED AS WELL. */ - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_USER_ALL; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_USER_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_USER_ALL, ACCESS_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_USER_ALL, ACCESS_VAL, cpu, 0, CMMU_ACS_USER, 0); + CMMU_UNLOCK; } /* @@ -1334,72 +1309,41 @@ m18x_cmmu_pmap_activate(cpu, uapr, i_batc, d_batc) * flush both Instruction and Data caches */ void -m18x_cmmu_flush_remote_cache(cpu, physaddr, size) +m8820x_cmmu_flush_remote_cache(cpu, physaddr, size) int cpu; vm_offset_t physaddr; int size; { register int s = splhigh(); - + CMMU_LOCK; #if !defined(BROKEN_MMU_MASK) if (size < 0 || size > NBSG ) { - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, 0, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, 0, cpu, 0, 0, 0); } else if (size <= 16) { - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, ADDR_VAL, cpu, 0, 0, (unsigned)physaddr); - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE , ADDR_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE , ADDR_VAL, cpu, 0, 0, (unsigned)physaddr); } else if (size <= NBPG) { - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, ADDR_VAL, cpu, 0, 0, (unsigned)physaddr); - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE , ADDR_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE , ADDR_VAL, cpu, 0, 0, (unsigned)physaddr); } else { - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, 0, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, 0, cpu, 0, 0, 0); - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_SEGMENT, 0, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_SEGMENT, 0, cpu, 0, 0, 0); } #else - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, 0, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, 0, cpu, 0, 0, 0); #endif /* !BROKEN_MMU_MASK */ + CMMU_UNLOCK; splx(s); } @@ -1407,77 +1351,53 @@ m18x_cmmu_flush_remote_cache(cpu, physaddr, size) * flush both Instruction and Data caches */ void -m18x_cmmu_flush_cache(physaddr, size) +m8820x_cmmu_flush_cache(physaddr, size) vm_offset_t physaddr; int size; { int cpu = cpu_number(); - m18x_cmmu_flush_remote_cache(cpu, physaddr, size); + m8820x_cmmu_flush_remote_cache(cpu, physaddr, size); } /* * flush Instruction caches */ void -m18x_cmmu_flush_remote_inst_cache(cpu, physaddr, size) +m8820x_cmmu_flush_remote_inst_cache(cpu, physaddr, size) int cpu; vm_offset_t physaddr; int size; { register int s = splhigh(); - - + CMMU_LOCK; #if !defined(BROKEN_MMU_MASK) if (size < 0 || size > NBSG ) { - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, cpu, INST_CMMU, 0, 0); } else if (size <= 16) { - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr); - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL|ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr); } else if (size <= NBPG) { - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr); - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL|ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr); } else { - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL, cpu, INST_CMMU, 0, 0); - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL, cpu, INST_CMMU, 0, 0); } #else - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, cpu, INST_CMMU, 0, 0); #endif /* !BROKEN_MMU_MASK */ + CMMU_UNLOCK; splx(s); } @@ -1485,67 +1405,51 @@ m18x_cmmu_flush_remote_inst_cache(cpu, physaddr, size) * flush Instruction caches */ void -m18x_cmmu_flush_inst_cache(physaddr, size) +m8820x_cmmu_flush_inst_cache(physaddr, size) vm_offset_t physaddr; int size; { int cpu; cpu = cpu_number(); - m18x_cmmu_flush_remote_inst_cache(cpu, physaddr, size); + m8820x_cmmu_flush_remote_inst_cache(cpu, physaddr, size); } void -m18x_cmmu_flush_remote_data_cache(cpu, physaddr, size) +m8820x_cmmu_flush_remote_data_cache(cpu, physaddr, size) int cpu; vm_offset_t physaddr; int size; { register int s = splhigh(); + CMMU_LOCK; #if !defined(BROKEN_MMU_MASK) if (size < 0 || size > NBSG ) { - /* - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, cpu, DATA_CMMU, 0, 0); } else if (size <= 16) { - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL|ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr); } else if (size <= NBPG) { - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL|ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr); } else { - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL, cpu, DATA_CMMU, 0, 0); - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL, cpu, DATA_CMMU, 0, 0); } #else - /* - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, cpu, DATA_CMMU, 0, 0); #endif /* !BROKEN_MMU_MASK */ + CMMU_UNLOCK; splx(s); } @@ -1553,274 +1457,184 @@ m18x_cmmu_flush_remote_data_cache(cpu, physaddr, size) * flush data cache */ void -m18x_cmmu_flush_data_cache(physaddr, size) +m8820x_cmmu_flush_data_cache(physaddr, size) vm_offset_t physaddr; int size; { int cpu; cpu = cpu_number(); - m18x_cmmu_flush_remote_data_cache(cpu, physaddr, size); + m8820x_cmmu_flush_remote_data_cache(cpu, physaddr, size); } /* * sync dcache (and icache too) */ void -m18x_cmmu_sync_cache(physaddr, size) +m8820x_cmmu_sync_cache(physaddr, size) vm_offset_t physaddr; int size; { register int s = splhigh(); int cpu; + + CMMU_LOCK; cpu = cpu_number(); #if !defined(BROKEN_MMU_MASK) if (size < 0 || size > NBSG ) { - /* - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CB_ALL; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL, cpu, DATA_CMMU, 0, 0); - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL, cpu, INST_CMMU, 0, 0); } else if (size <= 16) { - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CB_LINE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_LINE, MODE_VAL, + m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_LINE, MODE_VAL, cpu, INST_CMMU, 0, 0); - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_LINE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_LINE, MODE_VAL, + m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_LINE, MODE_VAL, cpu, DATA_CMMU, 0, 0); } else if (size <= NBPG) { - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CB_PAGE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_PAGE, MODE_VAL, + m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_PAGE, MODE_VAL, cpu, INST_CMMU, 0, 0); - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_PAGE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_PAGE, MODE_VAL, + m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_PAGE, MODE_VAL, cpu, DATA_CMMU, 0, 0); } else { - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CB_SEGMENT; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_SEGMENT, MODE_VAL, + m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_SEGMENT, MODE_VAL, cpu, INST_CMMU, 0, 0); - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_SEGMENT; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_SEGMENT, MODE_VAL, + m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_SEGMENT, MODE_VAL, cpu, DATA_CMMU, 0, 0); } #else - /* - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_ALL; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL, cpu, DATA_CMMU, 0, 0); - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL, cpu, INST_CMMU, 0, 0); #endif /* !BROKEN_MMU_MASK */ splx(s); + CMMU_UNLOCK; } void -m18x_cmmu_sync_inval_cache(physaddr, size) +m8820x_cmmu_sync_inval_cache(physaddr, size) vm_offset_t physaddr; int size; { register int s = splhigh(); int cpu; cpu = cpu_number(); + CMMU_LOCK; #if !defined(BROKEN_MMU_MASK) if (size < 0 || size > NBSG ) { - /* - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, cpu, DATA_CMMU, 0, 0); - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, cpu, INST_CMMU, 0, 0); } else if (size <= 16) { - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL, + m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL, cpu, INST_CMMU, 0, 0); - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL, + m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL, cpu, DATA_CMMU, 0, 0); } else if (size <= NBPG) { - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL, + m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL, cpu, INST_CMMU, 0, 0); - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL, + m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL, cpu, DATA_CMMU, 0, 0); } else { - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL, + m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL, cpu, INST_CMMU, 0, 0); - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL, + m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL, cpu, DATA_CMMU, 0, 0); } #else - /* - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, cpu, DATA_CMMU, 0, 0); - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL, cpu, INST_CMMU, 0, 0); #endif /* !BROKEN_MMU_MASK */ + CMMU_UNLOCK; splx(s); } void -m18x_cmmu_inval_cache(physaddr, size) +m8820x_cmmu_inval_cache(physaddr, size) vm_offset_t physaddr; int size; { register int s = splhigh(); int cpu; cpu = cpu_number(); + CMMU_LOCK; #if !defined(BROKEN_MMU_MASK) if (size < 0 || size > NBSG ) { - /* - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_INV_ALL; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_INV_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL, cpu, DATA_CMMU, 0, 0); - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL, cpu, INST_CMMU, 0, 0); } else if (size <= 16) { - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_INV_LINE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_LINE, MODE_VAL, + m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_LINE, MODE_VAL, cpu, INST_CMMU, 0, 0); - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_INV_LINE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_LINE, MODE_VAL, + m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_LINE, MODE_VAL, cpu, DATA_CMMU, 0, 0); } else if (size <= NBPG) { - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_INV_PAGE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_PAGE, MODE_VAL, + m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_PAGE, MODE_VAL, cpu, INST_CMMU, 0, 0); - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_INV_PAGE; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_PAGE, MODE_VAL, + m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_PAGE, MODE_VAL, cpu, DATA_CMMU, 0, 0); } else { - /* - REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr; - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_INV_SEGMENT; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_SEGMENT, MODE_VAL, + m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_SEGMENT, MODE_VAL, cpu, INST_CMMU, 0, 0); - /* - REGS(cpu, INST_CMMU).sar = (unsigned)physaddr; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_INV_SEGMENT; - */ - m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, + m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr); - m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_SEGMENT, MODE_VAL, + m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_SEGMENT, MODE_VAL, cpu, DATA_CMMU, 0, 0); } #else - /* - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_INV_ALL; - REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_INV_ALL; - */ - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL, cpu, DATA_CMMU, 0, 0); - m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL, + m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL, cpu, INST_CMMU, 0, 0); #endif /* !BROKEN_MMU_MASK */ - + CMMU_UNLOCK; splx(s); } void -m18x_dma_cachectl(va, size, op) +m8820x_dma_cachectl(va, size, op) vm_offset_t va; int size, op; { @@ -1834,11 +1648,11 @@ m18x_dma_cachectl(va, size, op) count = size; if (op == DMA_CACHE_SYNC) - m18x_cmmu_sync_cache(kvtop(va), count); + m8820x_cmmu_sync_cache(kvtop(va), count); else if (op == DMA_CACHE_SYNC_INVAL) - m18x_cmmu_sync_inval_cache(kvtop(va), count); + m8820x_cmmu_sync_inval_cache(kvtop(va), count); else - m18x_cmmu_inval_cache(kvtop(va), count); + m8820x_cmmu_inval_cache(kvtop(va), count); va = (vm_offset_t)((int)va + count); size -= count; @@ -1846,11 +1660,11 @@ m18x_dma_cachectl(va, size, op) #else if (op == DMA_CACHE_SYNC) - m18x_cmmu_sync_cache(kvtop(va), size); + m8820x_cmmu_sync_cache(kvtop(va), size); else if (op == DMA_CACHE_SYNC_INVAL) - m18x_cmmu_sync_inval_cache(kvtop(va), size); + m8820x_cmmu_sync_inval_cache(kvtop(va), size); else - m18x_cmmu_inval_cache(kvtop(va), size); + m8820x_cmmu_inval_cache(kvtop(va), size); #endif /* !BROKEN_MMU_MASK */ } @@ -1930,7 +1744,7 @@ union batcu { * If cmmu == -1, the data cmmu for the current cpu is used. */ void -m18x_cmmu_show_translation(address, supervisor_flag, verbose_flag, cmmu_num) +m8820x_cmmu_show_translation(address, supervisor_flag, verbose_flag, cmmu_num) unsigned address, supervisor_flag, verbose_flag; int cmmu_num; { @@ -1999,7 +1813,7 @@ m18x_cmmu_show_translation(address, supervisor_flag, verbose_flag, cmmu_num) DEBUG_MSG("ack! can't figure my own data cmmu number.\n"); return; } - cmmu_num = cpu_cmmu[cpu].pair[DATA_CMMU] - cmmu; + cmmu_num = cpu_cmmu[cpu].pair[DATA_CMMU] - m8820x_cmmu; if (verbose_flag) DEBUG_MSG("The data cmmu for cpu#%d is cmmu#%d.\n", 0, cmmu_num); @@ -2010,7 +1824,7 @@ m18x_cmmu_show_translation(address, supervisor_flag, verbose_flag, cmmu_num) return; } - if (cmmu[cmmu_num].cmmu_alive == 0) { + if (m8820x_cmmu[cmmu_num].cmmu_alive == 0) { DEBUG_MSG("warning: cmmu %d is not alive.\n", cmmu_num); #if 0 return; @@ -2018,24 +1832,24 @@ m18x_cmmu_show_translation(address, supervisor_flag, verbose_flag, cmmu_num) } if (!verbose_flag) { - if (!(cmmu[cmmu_num].cmmu_regs->sctr & CMMU_SCTR_SE)) + if (!(m8820x_cmmu[cmmu_num].cmmu_regs->sctr & CMMU_SCTR_SE)) DEBUG_MSG("WARNING: snooping not enabled for CMMU#%d.\n", cmmu_num); } else { int i; for (i=0; i<MAX_CMMUS; i++) - if ((i == cmmu_num || cmmu[i].cmmu_alive) && - (verbose_flag>1 || !(cmmu[i].cmmu_regs->sctr&CMMU_SCTR_SE))) { + if ((i == cmmu_num || m8820x_cmmu[i].cmmu_alive) && + (verbose_flag>1 || !(m8820x_cmmu[i].cmmu_regs->sctr&CMMU_SCTR_SE))) { DEBUG_MSG("CMMU#%d (cpu %d %s) snooping %s\n", i, - cmmu[i].cmmu_cpu, cmmu[i].which ? "data" : "inst", - (cmmu[i].cmmu_regs->sctr & CMMU_SCTR_SE) ? "on":"OFF"); + m8820x_cmmu[i].cmmu_cpu, m8820x_cmmu[i].which ? "data" : "inst", + (m8820x_cmmu[i].cmmu_regs->sctr & CMMU_SCTR_SE) ? "on":"OFF"); } } if (supervisor_flag) - value = cmmu[cmmu_num].cmmu_regs->sapr; + value = m8820x_cmmu[cmmu_num].cmmu_regs->sapr; else - value = cmmu[cmmu_num].cmmu_regs->uapr; + value = m8820x_cmmu[cmmu_num].cmmu_regs->uapr; } @@ -2046,7 +1860,7 @@ m18x_cmmu_show_translation(address, supervisor_flag, verbose_flag, cmmu_num) int i; union batcu batc; for (i = 0; i < 8; i++) { - batc.bits = cmmu[cmmu_num].batc[i]; + batc.bits = m8820x_cmmu[cmmu_num].batc[i]; if (batc.field.v == 0) { if (verbose_flag>1) DEBUG_MSG("cmmu #%d batc[%d] invalid.\n", cmmu_num, i); @@ -2070,7 +1884,7 @@ m18x_cmmu_show_translation(address, supervisor_flag, verbose_flag, cmmu_num) #endif /* 0 */ { union ssr ssr; - struct cmmu_regs *cmmu_regs = cmmu[cmmu_num].cmmu_regs; + struct cmmu_regs *cmmu_regs = m8820x_cmmu[cmmu_num].cmmu_regs; cmmu_regs->sar = address; cmmu_regs->scr = supervisor_flag ? CMMU_PROBE_SUPER : CMMU_PROBE_USER; ssr.bits = cmmu_regs->ssr; @@ -2265,7 +2079,7 @@ m18x_cmmu_show_translation(address, supervisor_flag, verbose_flag, cmmu_num) } void -m18x_cmmu_cache_state(addr, supervisor_flag) +m8820x_cmmu_cache_state(addr, supervisor_flag) unsigned addr, supervisor_flag; { static char *vv_name[4] = @@ -2277,12 +2091,12 @@ m18x_cmmu_cache_state(addr, supervisor_flag) union cssp cssp; struct cmmu_regs *R; unsigned tag, line; - if (!cmmu[cmmu_num].cmmu_alive) + if (!m8820x_cmmu[cmmu_num].cmmu_alive) continue; - R = cmmu[cmmu_num].cmmu_regs; + R = m8820x_cmmu[cmmu_num].cmmu_regs; DEBUG_MSG("cmmu #%d %s cmmu for cpu %d.\n", cmmu_num, - cmmu[cmmu_num].which ? "data" : "inst", - cmmu[cmmu_num].cmmu_cpu); + m8820x_cmmu[cmmu_num].which ? "data" : "inst", + m8820x_cmmu[cmmu_num].cmmu_cpu); R->sar = addr; R->scr = supervisor_flag ? CMMU_PROBE_SUPER : CMMU_PROBE_USER; @@ -2319,20 +2133,22 @@ m18x_cmmu_cache_state(addr, supervisor_flag) } +#endif /* DDB */ + void -m18x_show_cmmu_info(addr) +m8820x_show_cmmu_info(addr) unsigned addr; { int cmmu_num; - m18x_cmmu_cache_state(addr, 1); + m8820x_cmmu_cache_state(addr, 1); for (cmmu_num = 0; cmmu_num < MAX_CMMUS; cmmu_num++) - if (cmmu[cmmu_num].cmmu_alive) { + if (m8820x_cmmu[cmmu_num].cmmu_alive) { DEBUG_MSG("cmmu #%d %s cmmu for cpu %d: ", cmmu_num, - cmmu[cmmu_num].which ? "data" : "inst", - cmmu[cmmu_num].cmmu_cpu); - m18x_cmmu_show_translation(addr, 1, 0, cmmu_num); + m8820x_cmmu[cmmu_num].which ? "data" : "inst", + m8820x_cmmu[cmmu_num].cmmu_cpu); + m8820x_cmmu_show_translation(addr, 1, 0, cmmu_num); } } -#endif /* DDB */ +#endif /* M88100 */ diff --git a/sys/arch/mvme88k/mvme88k/machdep.c b/sys/arch/mvme88k/mvme88k/machdep.c index 9365076d0bb..b92c53827b6 100644 --- a/sys/arch/mvme88k/mvme88k/machdep.c +++ b/sys/arch/mvme88k/mvme88k/machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: machdep.c,v 1.79 2001/12/22 07:35:43 smurph Exp $ */ +/* $OpenBSD: machdep.c,v 1.80 2001/12/22 09:49:39 smurph Exp $ */ /* * Copyright (c) 1998, 1999, 2000, 2001 Steve Murphree, Jr. * Copyright (c) 1996 Nivas Madhur @@ -85,16 +85,17 @@ #include <machine/board.h> #include <machine/bug.h> #include <machine/bugio.h> -#include <machine/cmmu.h> +#include <machine/cmmu.h> /* CMMU stuff */ #include <machine/cpu.h> #include <machine/cpu_number.h> #include <machine/kcore.h> #include <machine/locore.h> -#include <machine/m88100.h> /* DMT_VALID */ -#include <machine/m8820x.h> /* CMMU stuff */ #include <machine/prom.h> #include <machine/reg.h> #include <machine/trap.h> +#ifdef M88100 +#include <machine/m88100.h> /* DMT_VALID */ +#endif #include <dev/cons.h> @@ -224,7 +225,6 @@ caddr_t allocsys __P((caddr_t)); */ char machine[] = MACHINE; /* cpu "architecture" */ char cpu_model[120]; -extern unsigned master_cpu; struct bugenv bugargs; @@ -2358,6 +2358,7 @@ mvme_bootstrap() switch (brdtyp) { #ifdef MVME188 case BRD_188: + cmmu = &cmmu8820x; md.interrupt_func = &m188_ext_int; md.intr_mask = NULL; md.intr_ipl = NULL; @@ -2371,6 +2372,7 @@ mvme_bootstrap() #endif /* MVME188 */ #ifdef MVME187 case BRD_187: + cmmu = &cmmu8820x; md.interrupt_func = &m187_ext_int; md.intr_mask = (u_char *)M187_IMASK; md.intr_ipl = (u_char *)M187_ILEVEL; @@ -2379,6 +2381,7 @@ mvme_bootstrap() #endif /* MVME187 */ #ifdef MVME197 case BRD_197: + cmmu = &cmmu88110; md.interrupt_func = &m197_ext_int; md.intr_mask = (u_char *)M197_IMASK; md.intr_ipl = (u_char *)M197_ILEVEL; diff --git a/sys/arch/mvme88k/mvme88k/pmap.c b/sys/arch/mvme88k/mvme88k/pmap.c index 5d8e742cac0..1988b41357a 100644 --- a/sys/arch/mvme88k/mvme88k/pmap.c +++ b/sys/arch/mvme88k/mvme88k/pmap.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pmap.c,v 1.56 2001/12/22 07:35:43 smurph Exp $ */ +/* $OpenBSD: pmap.c,v 1.57 2001/12/22 09:49:39 smurph Exp $ */ /* * Copyright (c) 1996 Nivas Madhur * All rights reserved. @@ -59,11 +59,9 @@ #include <uvm/uvm.h> #include <machine/asm_macro.h> -#include <machine/mmu.h> #include <machine/board.h> #include <machine/cmmu.h> #include <machine/cpu_number.h> -#include <machine/m8820x.h> /* CMMU stuff */ #include <machine/pmap_table.h> #include <machine/pte.h> @@ -430,7 +428,6 @@ pt_entry_t * pmap_pte(pmap_t map, vm_offset_t virt) { sdt_entry_t *sdt; - #ifdef DIAGNOSTIC /*XXX will this change if physical memory is not contiguous? */ /* take a look at PDTIDX XXXnivas */ @@ -511,8 +508,9 @@ pmap_expand_kmap(vm_offset_t virt, vm_prot_t prot) return (PT_ENTRY_NULL); } kpdt_free = kpdt_free->next; - + /* physical table */ ((sdt_entry_template_t *)sdt)->bits = kpdt_ent->phys | aprot | DT_VALID; + /* virtual table */ ((sdt_entry_template_t *)(sdt + SDT_ENTRIES))->bits = (vm_offset_t)kpdt_ent | aprot | DT_VALID; (unsigned)(kpdt_ent->phys) = 0; (unsigned)(kpdt_ent->next) = 0; @@ -3808,32 +3806,32 @@ cache_flush_loop(int mode, vm_offset_t pa, int size) case FLUSH_CACHE: /* All caches, all CPUs */ ncpus = max_cpus; - cfunc = cmmu_flush_remote_cache; + cfunc = cmmu->cmmu_flush_remote_cache_func; break; case FLUSH_CODE_CACHE: /* Instruction caches, all CPUs */ ncpus = max_cpus; - cfunc = cmmu_flush_remote_inst_cache; + cfunc = cmmu->cmmu_flush_remote_inst_cache_func; break; case FLUSH_DATA_CACHE: /* Data caches, all CPUs */ ncpus = max_cpus; - cfunc = cmmu_flush_remote_data_cache; + cfunc = cmmu->cmmu_flush_remote_data_cache_func; break; case FLUSH_LOCAL_CACHE: /* Both caches, my CPU */ ncpus = 1; - cfunc = cmmu_flush_remote_cache; + cfunc = cmmu->cmmu_flush_remote_cache_func; break; case FLUSH_LOCAL_CODE_CACHE: /* Instruction cache, my CPU */ ncpus = 1; - cfunc = cmmu_flush_remote_inst_cache; + cfunc = cmmu->cmmu_flush_remote_inst_cache_func; break; case FLUSH_LOCAL_DATA_CACHE: /* Data cache, my CPU */ ncpus = 1; - cfunc = cmmu_flush_remote_data_cache; + cfunc = cmmu->cmmu_flush_remote_data_cache_func; break; } diff --git a/sys/arch/mvme88k/mvme88k/pmap_table.c b/sys/arch/mvme88k/mvme88k/pmap_table.c index 8ff56db77f5..69d50549b3f 100644 --- a/sys/arch/mvme88k/mvme88k/pmap_table.c +++ b/sys/arch/mvme88k/mvme88k/pmap_table.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pmap_table.c,v 1.13 2001/12/22 07:35:43 smurph Exp $ */ +/* $OpenBSD: pmap_table.c,v 1.14 2001/12/22 09:49:39 smurph Exp $ */ /* * Mach Operating System @@ -30,8 +30,7 @@ #include <sys/systm.h> #include <sys/types.h> #include <machine/board.h> -#include <sys/param.h> -#include <machine/m8820x.h> /* CMMU stuff */ +#include <machine/cmmu.h> /* CMMU stuff */ #include <uvm/uvm_extern.h> #include <machine/pmap_table.h> /* pmap_table.h*/ diff --git a/sys/arch/mvme88k/mvme88k/process.S b/sys/arch/mvme88k/mvme88k/process.S index 86b984059d3..46600092ba0 100644 --- a/sys/arch/mvme88k/mvme88k/process.S +++ b/sys/arch/mvme88k/mvme88k/process.S @@ -1,4 +1,4 @@ -/* $OpenBSD: process.S,v 1.14 2001/12/16 23:49:47 miod Exp $ */ +/* $OpenBSD: process.S,v 1.15 2001/12/22 09:49:39 smurph Exp $ */ /* * Copyright (c) 1996 Nivas Madhur * All rights reserved. @@ -265,7 +265,7 @@ Lswnochg: subu r31, r31,48 /* r2 = 1 : kernel ? user, r3 = address, r4 = size */ /* cmmu_flush_tlb(0, 0, 0xffff) */ - bsr.n _cmmu_flush_tlb + bsr.n _md_cmmu_flush_tlb or r4, r0, 0xffff /* cmmu_flush_tlb flushes entire tlb */ /* for sizes > 4096 */ addu r31, r31,48 |