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path: root/sys/dev/cardbus/if_ral_cardbus.c
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Diffstat (limited to 'sys/dev/cardbus/if_ral_cardbus.c')
-rw-r--r--sys/dev/cardbus/if_ral_cardbus.c11
1 files changed, 7 insertions, 4 deletions
diff --git a/sys/dev/cardbus/if_ral_cardbus.c b/sys/dev/cardbus/if_ral_cardbus.c
index 9cb140c703b..33ac332ff10 100644
--- a/sys/dev/cardbus/if_ral_cardbus.c
+++ b/sys/dev/cardbus/if_ral_cardbus.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: if_ral_cardbus.c,v 1.16 2010/03/27 20:04:03 jsg Exp $ */
+/* $OpenBSD: if_ral_cardbus.c,v 1.17 2010/03/27 21:40:13 jsg Exp $ */
/*-
* Copyright (c) 2005-2007
@@ -94,6 +94,7 @@ struct ral_cardbus_softc {
bus_size_t sc_mapsize;
pcireg_t sc_bar_val;
int sc_intrline;
+ pci_chipset_tag_t sc_pc;
};
int ral_cardbus_match(struct device *, void *, void *);
@@ -171,6 +172,7 @@ ral_cardbus_attach(struct device *parent, struct device *self, void *aux)
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
csc->sc_intrline = ca->ca_intrline;
+ csc->sc_pc = ca->ca_pc;
/* power management hooks */
sc->sc_enable = ral_cardbus_enable;
@@ -284,11 +286,12 @@ ral_cardbus_setup(struct ral_cardbus_softc *csc)
{
cardbus_devfunc_t ct = csc->sc_ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
+ pci_chipset_tag_t pc = csc->sc_pc;
cardbus_function_tag_t cf = ct->ct_cf;
pcireg_t reg;
/* program the BAR */
- cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_BASE0_REG,
+ pci_conf_write(pc, csc->sc_tag, CARDBUS_BASE0_REG,
csc->sc_bar_val);
/* make sure the right access type is on the cardbus bridge */
@@ -296,9 +299,9 @@ ral_cardbus_setup(struct ral_cardbus_softc *csc)
(*cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
/* enable the appropriate bits in the PCI CSR */
- reg = cardbus_conf_read(cc, cf, csc->sc_tag,
+ reg = pci_conf_read(pc, csc->sc_tag,
PCI_COMMAND_STATUS_REG);
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
- cardbus_conf_write(cc, cf, csc->sc_tag, PCI_COMMAND_STATUS_REG,
+ pci_conf_write(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG,
reg);
}