diff options
Diffstat (limited to 'sys/dev/fdt')
| -rw-r--r-- | sys/dev/fdt/rkclock.c | 188 | ||||
| -rw-r--r-- | sys/dev/fdt/rkclock_clocks.h | 46 |
2 files changed, 228 insertions, 6 deletions
diff --git a/sys/dev/fdt/rkclock.c b/sys/dev/fdt/rkclock.c index ef0a6e9cc4a..b638c4a3be0 100644 --- a/sys/dev/fdt/rkclock.c +++ b/sys/dev/fdt/rkclock.c @@ -1,4 +1,4 @@ -/* $OpenBSD: rkclock.c,v 1.64 2023/02/13 19:19:29 kettenis Exp $ */ +/* $OpenBSD: rkclock.c,v 1.65 2023/02/15 14:06:43 kettenis Exp $ */ /* * Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org> * @@ -420,6 +420,32 @@ rkclock_lookup(struct rkclock_softc *sc, uint32_t idx) } uint32_t +rkclock_external_frequency(const char *name) +{ + char buf[64] = {}; + int len, node; + + /* + * Hunt through the device tree to find a fixed-rate clock + * that has the requested clock output signal name. This may + * be too simple. + */ + node = OF_peer(0); + for (node = OF_child(node); node != 0; node = OF_peer(node)) { + len = OF_getproplen(node, "clock-output-names"); + if (len <= 0 || len > sizeof(buf)) + continue; + OF_getprop(node, "clock-output-names", buf, sizeof(buf)); + if (strcmp(buf, name) != 0) + continue; + if (OF_is_compatible(node, "fixed-clock")) + return OF_getpropint(node, "clock-frequency", 0); + } + + return 0; +} + +uint32_t rkclock_div_con(struct rkclock_softc *sc, const struct rkclock *clk, uint32_t mux, uint32_t freq) { @@ -3006,6 +3032,17 @@ rk3399_pmu_reset(void *cookie, uint32_t *cells, int on) const struct rkclock rk3568_clocks[] = { { + RK3568_ACLK_PHP, RK3568_CRU_CLKSEL_CON(30), + SEL(1, 0), 0, + { RK3568_GPLL_300M, RK3568_GPLL_200M, + RK3568_GPLL_100M, RK3568_XIN24M } + }, + { + RK3568_PCLK_PHP, RK3568_CRU_CLKSEL_CON(30), + 0, DIV(7, 4), + { RK3568_ACLK_PHP } + }, + { RK3568_CLK_SDMMC0, RK3568_CRU_CLKSEL_CON(30), SEL(10, 8), 0, { RK3568_XIN24M, RK3568_GPLL_400M, RK3568_GPLL_300M, @@ -3018,6 +3055,65 @@ const struct rkclock rk3568_clocks[] = { RK3568_CPLL_100M, RK3568_CPLL_50M, RK3568_CLK_OSC0_DIV_750K } }, { + RK3568_ACLK_GMAC0, 0, 0, 0, + { RK3568_ACLK_PHP } + }, + { + RK3568_PCLK_GMAC0, 0, 0, 0, + { RK3568_PCLK_PHP } + }, + { + RK3568_CLK_MAC0_2TOP, RK3568_CRU_CLKSEL_CON(31), + SEL(9, 8), 0, + { RK3568_CPLL_125M, RK3568_CPLL_50M, + RK3568_CPLL_25M, RK3568_XIN24M } + }, + { + RK3568_CLK_MAC0_REFOUT, 0, 0, 0, + { RK3568_CLK_MAC0_2TOP } + }, + { + RK3568_CLK_GMAC0_PTP_REF, RK3568_CRU_CLKSEL_CON(31), + SEL(13, 12), 0, + { RK3568_CPLL_62P5M, RK3568_GPLL_100M, + RK3568_CPLL_50M, RK3568_XIN24M } + }, + { + RK3568_ACLK_USB, RK3568_CRU_CLKSEL_CON(32), + SEL(1, 0), 0, + { RK3568_GPLL_300M, RK3568_GPLL_200M, + RK3568_GPLL_100M, RK3568_XIN24M } + }, + { + RK3568_PCLK_USB, RK3568_CRU_CLKSEL_CON(32), + 0, DIV(7, 4), + { RK3568_ACLK_USB } + }, + { + RK3568_ACLK_GMAC1, 0, 0, 0, + { RK3568_ACLK_USB } + }, + { + RK3568_PCLK_GMAC1, 0, 0, 0, + { RK3568_PCLK_USB } + }, + { + RK3568_CLK_MAC1_2TOP, RK3568_CRU_CLKSEL_CON(33), + SEL(9, 8), 0, + { RK3568_CPLL_125M, RK3568_CPLL_50M, + RK3568_CPLL_25M, RK3568_XIN24M } + }, + { + RK3568_CLK_MAC1_REFOUT, 0, 0, 0, + { RK3568_CLK_MAC1_2TOP } + }, + { + RK3568_CLK_GMAC1_PTP_REF, RK3568_CRU_CLKSEL_CON(33), + SEL(13, 12), 0, + { RK3568_CPLL_62P5M, RK3568_GPLL_100M, + RK3568_CPLL_50M, RK3568_XIN24M } + }, + { RK3568_CLK_TSADC_TSEN, RK3568_CRU_CLKSEL_CON(51), SEL(5, 4), DIV(2, 0), { RK3568_XIN24M, RK3568_GPLL_100M, RK3568_CPLL_100M } @@ -3098,11 +3194,68 @@ const struct rkclock rk3568_clocks[] = { { RK3568_CLK_I2C } }, { + RK3568_SCLK_GMAC0, RK3568_CRU_CLKSEL_CON(31), + SEL(2, 2), 0, + { RK3568_CLK_MAC0_2TOP, RK3568_GMAC0_CLKIN } + }, + { + RK3568_SCLK_GMAC0_RGMII_SPEED, RK3568_CRU_CLKSEL_CON(31), + SEL(5, 4), 0, + { RK3568_SCLK_GMAC0, RK3568_SCLK_GMAC0, + RK3568_SCLK_GMAC0_DIV_50, RK3568_SCLK_GMAC0_DIV_5 } + }, + { + RK3568_SCLK_GMAC0_RMII_SPEED, RK3568_CRU_CLKSEL_CON(31), + SEL(3, 3), 0, + { RK3568_SCLK_GMAC0_DIV_20, RK3568_SCLK_GMAC0_DIV_2 } + }, + { + RK3568_SCLK_GMAC0_RX_TX, RK3568_CRU_CLKSEL_CON(31), + SEL(1, 0), 0, + { RK3568_SCLK_GMAC0_RGMII_SPEED, RK3568_SCLK_GMAC0_RMII_SPEED } + }, + { + RK3568_SCLK_GMAC1, RK3568_CRU_CLKSEL_CON(33), + SEL(2, 2), 0, + { RK3568_CLK_MAC1_2TOP, RK3568_GMAC1_CLKIN } + }, + { + RK3568_SCLK_GMAC1_RGMII_SPEED, RK3568_CRU_CLKSEL_CON(33), + SEL(5, 4), 0, + { RK3568_SCLK_GMAC1, RK3568_SCLK_GMAC1, + RK3568_SCLK_GMAC1_DIV_50, RK3568_SCLK_GMAC1_DIV_5 } + }, + { + RK3568_SCLK_GMAC1_RMII_SPEED, RK3568_CRU_CLKSEL_CON(33), + SEL(3, 3), 0, + { RK3568_SCLK_GMAC1_DIV_20, RK3568_SCLK_GMAC1_DIV_2 } + }, + { + RK3568_SCLK_GMAC1_RX_TX, RK3568_CRU_CLKSEL_CON(33), + SEL(1, 0), 0, + { RK3568_SCLK_GMAC1_RGMII_SPEED, RK3568_SCLK_GMAC1_RMII_SPEED } + }, + { + RK3568_CPLL_125M, RK3568_CRU_CLKSEL_CON(80), + 0, DIV(4, 0), + { RK3568_PLL_CPLL } + }, + { + RK3568_CPLL_62P5M, RK3568_CRU_CLKSEL_CON(80), + 0, DIV(12, 8), + { RK3568_PLL_CPLL } + }, + { RK3568_CPLL_50M, RK3568_CRU_CLKSEL_CON(81), 0, DIV(4, 0), { RK3568_PLL_CPLL } }, { + RK3568_CPLL_25M, RK3568_CRU_CLKSEL_CON(81), + 0, DIV(13, 8), + { RK3568_PLL_CPLL } + }, + { RK3568_CPLL_100M, RK3568_CRU_CLKSEL_CON(82), 0, DIV(4, 0), { RK3568_PLL_CPLL } @@ -3118,6 +3271,11 @@ const struct rkclock rk3568_clocks[] = { { RK3568_PLL_GPLL } }, { + RK3568_GPLL_200M, RK3568_CRU_CLKSEL_CON(76), + 0, DIV(4, 0), + { RK3568_PLL_GPLL } + }, + { RK3568_GPLL_100M, RK3568_CRU_CLKSEL_CON(77), 0, DIV(4, 0), { RK3568_PLL_GPLL } @@ -3251,6 +3409,34 @@ rk3568_get_frequency(void *cookie, uint32_t *cells) case RK3568_PLL_VPLL: return rk3328_get_pll(sc, RK3568_CRU_VPLL_CON(0)); break; + case RK3568_SCLK_GMAC0_DIV_50: + idx = RK3568_SCLK_GMAC0; + return rk3568_get_frequency(sc, &idx) / 50; + case RK3568_SCLK_GMAC0_DIV_5: + idx = RK3568_SCLK_GMAC0; + return rk3568_get_frequency(sc, &idx) / 5; + case RK3568_SCLK_GMAC0_DIV_20: + idx = RK3568_SCLK_GMAC0; + return rk3568_get_frequency(sc, &idx) / 20; + case RK3568_SCLK_GMAC0_DIV_2: + idx = RK3568_SCLK_GMAC0; + return rk3568_get_frequency(sc, &idx) / 2; + case RK3568_SCLK_GMAC1_DIV_50: + idx = RK3568_SCLK_GMAC1; + return rk3568_get_frequency(sc, &idx) / 50; + case RK3568_SCLK_GMAC1_DIV_5: + idx = RK3568_SCLK_GMAC1; + return rk3568_get_frequency(sc, &idx) / 5; + case RK3568_SCLK_GMAC1_DIV_20: + idx = RK3568_SCLK_GMAC1; + return rk3568_get_frequency(sc, &idx) / 20; + case RK3568_SCLK_GMAC1_DIV_2: + idx = RK3568_SCLK_GMAC1; + return rk3568_get_frequency(sc, &idx) / 2; + case RK3568_GMAC0_CLKIN: + return rkclock_external_frequency("gmac0_clkin"); + case RK3568_GMAC1_CLKIN: + return rkclock_external_frequency("gmac1_clkin"); case RK3568_XIN24M: return 24000000; default: diff --git a/sys/dev/fdt/rkclock_clocks.h b/sys/dev/fdt/rkclock_clocks.h index 15ba3dc8473..3df0603e7e5 100644 --- a/sys/dev/fdt/rkclock_clocks.h +++ b/sys/dev/fdt/rkclock_clocks.h @@ -283,8 +283,22 @@ #define RK3568_PLL_VPLL 5 #define RK3568_PLL_NPLL 6 +#define RK3568_ACLK_PHP 173 +#define RK3568_PCLK_PHP 175 #define RK3568_CLK_SDMMC0 177 #define RK3568_CLK_SDMMC1 179 +#define RK3568_ACLK_GMAC0 180 +#define RK3568_PCLK_GMAC0 181 +#define RK3568_CLK_MAC0_2TOP 182 +#define RK3568_CLK_MAC0_REFOUT 184 +#define RK3568_CLK_GMAC0_PTP_REF 185 +#define RK3568_ACLK_USB 186 +#define RK3568_PCLK_USB 188 +#define RK3568_ACLK_GMAC1 195 +#define RK3568_PCLK_GMAC1 196 +#define RK3568_CLK_MAC1_2TOP 197 +#define RK3568_CLK_MAC1_REFOUT 199 +#define RK3568_CLK_GMAC1_PTP_REF 200 #define RK3568_CLK_TSADC_TSEN 272 #define RK3568_CLK_TSADC 273 #define RK3568_SCLK_UART1 287 @@ -302,14 +316,36 @@ #define RK3568_CLK_I2C3 332 #define RK3568_CLK_I2C4 334 #define RK3568_CLK_I2C5 336 - +#define RK3568_SCLK_GMAC0 386 +#define RK3568_SCLK_GMAC0_RGMII_SPEED 387 +#define RK3568_SCLK_GMAC0_RMII_SPEED 388 +#define RK3568_SCLK_GMAC0_RX_TX 389 +#define RK3568_SCLK_GMAC1 390 +#define RK3568_SCLK_GMAC1_RGMII_SPEED 391 +#define RK3568_SCLK_GMAC1_RMII_SPEED 392 +#define RK3568_SCLK_GMAC1_RX_TX 393 + +#define RK3568_CPLL_125M 413 +#define RK3568_CPLL_62P5M 414 #define RK3568_CPLL_50M 415 +#define RK3568_CPLL_25M 416 #define RK3568_CPLL_100M 417 -#define RK3568_GPLL_400M 1019 -#define RK3568_GPLL_300M 1020 -#define RK3568_GPLL_100M 1021 -#define RK3568_CLK_OSC0_DIV_750K 1022 +#define RK3568_SCLK_GMAC0_DIV_50 1008 +#define RK3568_SCLK_GMAC0_DIV_5 1009 +#define RK3568_SCLK_GMAC0_DIV_20 1010 +#define RK3568_SCLK_GMAC0_DIV_2 1011 +#define RK3568_SCLK_GMAC1_DIV_50 1012 +#define RK3568_SCLK_GMAC1_DIV_5 1013 +#define RK3568_SCLK_GMAC1_DIV_20 1014 +#define RK3568_SCLK_GMAC1_DIV_2 1015 +#define RK3568_GPLL_400M 1016 +#define RK3568_GPLL_300M 1017 +#define RK3568_GPLL_200M 1018 +#define RK3568_GPLL_100M 1019 +#define RK3568_CLK_OSC0_DIV_750K 1020 +#define RK3568_GMAC0_CLKIN 1021 +#define RK3568_GMAC1_CLKIN 1022 #define RK3568_XIN24M 1023 /* PMUCRU */ |