diff options
Diffstat (limited to 'sys/dev/ic/aic7xxxreg.h')
| -rw-r--r-- | sys/dev/ic/aic7xxxreg.h | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/sys/dev/ic/aic7xxxreg.h b/sys/dev/ic/aic7xxxreg.h index 1b52c8bcb59..8f9751421bf 100644 --- a/sys/dev/ic/aic7xxxreg.h +++ b/sys/dev/ic/aic7xxxreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: aic7xxxreg.h,v 1.4 1996/11/28 23:27:45 niklas Exp $ */ +/* $OpenBSD: aic7xxxreg.h,v 1.5 1997/04/10 22:52:19 deraadt Exp $ */ /* $NetBSD: aic7xxxreg.h,v 1.4 1996/10/08 03:04:04 gibbs Exp $ */ /* * Aic7xxx register and scratch ram definitions. @@ -34,7 +34,7 @@ /* * This header is shared by the sequencer code and the kernel level driver. * - * All page numbers refer to the Adaptec AIC-7770 Data Book availible from + * All page numbers refer to the Adaptec AIC-7770 Data Book available from * Adaptec's Technical Documents Department 1-800-934-2766 */ @@ -104,7 +104,7 @@ #define P_STATUS 0xc0 #define P_MESGIN 0xe0 /* - * SCSI Contol Signal Write Register (p. 3-16). + * SCSI Control Signal Write Register (p. 3-16). * Writing to this register modifies the control signals on the bus. Only * those signals that are allowed in the current mode (Initiator/Target) are * asserted. @@ -142,18 +142,18 @@ /* * SCSI Latched Data (p. 3-19). - * Read/Write latchs used to transfer data on the SCSI bus during + * Read/Write latches used to transfer data on the SCSI bus during * Automatic or Manual PIO mode. SCSIDATH can be used for the - * upper byte of a 16bit wide asyncronouse data phase transfer. + * upper byte of a 16bit wide asynchronous data phase transfer. */ #define SCSIDATL 0x006 #define SCSIDATH 0x007 /* * SCSI Transfer Count (pp. 3-19,20) - * These registers count down the number of bytes transfered + * These registers count down the number of bytes transferred * across the SCSI bus. The counter is decremented only once - * the data has been safely transfered. SDONE in SSTAT0 is + * the data has been safely transferred. SDONE in SSTAT0 is * set when STCNT goes to 0 */ #define STCNT 0x008 @@ -244,7 +244,7 @@ * transfered on the SCSI bus. They are counted up in the same * manner as STCNT is counted down. SHADDR should always be used * to determine the address of the last byte transfered since HADDR - * can be squewed by write ahead. + * can be skewed by write-ahead. */ #define SHADDR 0x014 #define SHADDR0 0x014 @@ -329,7 +329,7 @@ /* * Host Address (p. 3-48) * This register contains the address of the byte about - * to be transfered across the host bus. + * to be transferred across the host bus. */ #define HADDR 0x088 #define HADDR0 0x088 @@ -384,7 +384,7 @@ /* * Host Control (p. 3-47) R/W - * Overal host control of the device. + * Overall host control of the device. */ #define HCNTRL 0x087 /* UNUSED 0x80 */ @@ -520,7 +520,7 @@ * The two reserved bytes at SCBARRAY+1[23] are expected to be set to * zero. Bit 3 in SCBARRAY+0 is used as an internal flag to indicate * whether or not to DMA an SCB from host ram. This flag prevents the - * "re-fetching" of transactions that are requed because the target is + * "re-fetching" of transactions that are requeued because the target is * busy with another command. We also use bits 6 & 7 to indicate whether * or not to initiate SDTR or WDTR repectively when starting this command. */ @@ -643,7 +643,7 @@ #define TARG_SCRATCH 0x020 /* - * The sequencer will stick the frist byte of any rejected message here so + * The sequencer will stick the first byte of any rejected message here so * we can see what is getting thrown away. Extended messages put the * extended message type in REJBYTE_EXT. */ @@ -702,7 +702,7 @@ * this card. */ #define COMP_SCBCOUNT 0x048 /* - * Two's compliment of SCBCOUNT + * Two's complement of SCBCOUNT */ #define QCNTMASK 0x049 /* * Mask of bits to test against |