diff options
Diffstat (limited to 'sys/dev/ic/ar5210reg.h')
| -rw-r--r-- | sys/dev/ic/ar5210reg.h | 378 |
1 files changed, 189 insertions, 189 deletions
diff --git a/sys/dev/ic/ar5210reg.h b/sys/dev/ic/ar5210reg.h index 79e67105360..992027e8ff9 100644 --- a/sys/dev/ic/ar5210reg.h +++ b/sys/dev/ic/ar5210reg.h @@ -1,7 +1,7 @@ -/* $OpenBSD: ar5210reg.h,v 1.1 2004/11/02 03:01:16 reyk Exp $ */ +/* $OpenBSD: ar5210reg.h,v 1.2 2004/11/02 14:05:49 reyk Exp $ */ /* - * Copyright (c) 2004 Reyk Floeter <reyk@vantronix.net>. + * Copyright (c) 2004 Reyk Floeter <reyk@vantronix.net>. * * All rights reserved. * @@ -64,12 +64,12 @@ * Configuration and status register */ #define AR5K_AR5210_CFG 0x0014 -#define AR5K_AR5210_CFG_SWTD 0x00000001 -#define AR5K_AR5210_CFG_SWTB 0x00000002 -#define AR5K_AR5210_CFG_SWRD 0x00000004 -#define AR5K_AR5210_CFG_SWRB 0x00000008 -#define AR5K_AR5210_CFG_SWRG 0x00000010 -#define AR5K_AR5210_CFG_EEBS 0x00000200 +#define AR5K_AR5210_CFG_SWTD 0x00000001 +#define AR5K_AR5210_CFG_SWTB 0x00000002 +#define AR5K_AR5210_CFG_SWRD 0x00000004 +#define AR5K_AR5210_CFG_SWRB 0x00000008 +#define AR5K_AR5210_CFG_SWRG 0x00000010 +#define AR5K_AR5210_CFG_EEBS 0x00000200 #define AR5K_AR5210_CFG_TXCNT 0x00007800 #define AR5K_AR5210_CFG_TXCNT_S 11 #define AR5K_AR5210_CFG_TXFSTAT 0x00008000 @@ -78,30 +78,30 @@ /* * Interrupt service register */ -#define AR5K_AR5210_ISR 0x001c +#define AR5K_AR5210_ISR 0x001c #define AR5K_AR5210_ISR_RXOK 0x00000001 #define AR5K_AR5210_ISR_RXDESC 0x00000002 -#define AR5K_AR5210_ISR_RXERR 0x00000004 -#define AR5K_AR5210_ISR_RXNOFRM 0x00000008 +#define AR5K_AR5210_ISR_RXERR 0x00000004 +#define AR5K_AR5210_ISR_RXNOFRM 0x00000008 #define AR5K_AR5210_ISR_RXEOL 0x00000120 -#define AR5K_AR5210_ISR_RXORN 0x00000020 -#define AR5K_AR5210_ISR_TXOK 0x00000040 -#define AR5K_AR5210_ISR_TXDESC 0x00000080 -#define AR5K_AR5210_ISR_TXERR 0x00000100 -#define AR5K_AR5210_ISR_TXNOFRM 0x00000200 -#define AR5K_AR5210_ISR_TXEOL 0x00000400 -#define AR5K_AR5210_ISR_TXURN 0x00000800 -#define AR5K_AR5210_ISR_MIB 0x00001000 -#define AR5K_AR5210_ISR_SWI 0x00002000 -#define AR5K_AR5210_ISR_RXPHY 0x00004000 -#define AR5K_AR5210_ISR_RXKCM 0x00008000 -#define AR5K_AR5210_ISR_SWBA 0x00010000 -#define AR5K_AR5210_ISR_BRSSI 0x00020000 -#define AR5K_AR5210_ISR_BMISS 0x00040000 -#define AR5K_AR5210_ISR_MCABT 0x00100000 -#define AR5K_AR5210_ISR_SSERR 0x00200000 -#define AR5K_AR5210_ISR_DPERR 0x00400000 -#define AR5K_AR5210_ISR_GPIO 0x01000000 +#define AR5K_AR5210_ISR_RXORN 0x00000020 +#define AR5K_AR5210_ISR_TXOK 0x00000040 +#define AR5K_AR5210_ISR_TXDESC 0x00000080 +#define AR5K_AR5210_ISR_TXERR 0x00000100 +#define AR5K_AR5210_ISR_TXNOFRM 0x00000200 +#define AR5K_AR5210_ISR_TXEOL 0x00000400 +#define AR5K_AR5210_ISR_TXURN 0x00000800 +#define AR5K_AR5210_ISR_MIB 0x00001000 +#define AR5K_AR5210_ISR_SWI 0x00002000 +#define AR5K_AR5210_ISR_RXPHY 0x00004000 +#define AR5K_AR5210_ISR_RXKCM 0x00008000 +#define AR5K_AR5210_ISR_SWBA 0x00010000 +#define AR5K_AR5210_ISR_BRSSI 0x00020000 +#define AR5K_AR5210_ISR_BMISS 0x00040000 +#define AR5K_AR5210_ISR_MCABT 0x00100000 +#define AR5K_AR5210_ISR_SSERR 0x00200000 +#define AR5K_AR5210_ISR_DPERR 0x00400000 +#define AR5K_AR5210_ISR_GPIO 0x01000000 #define AR5K_AR5210_ISR_FATAL ( \ AR5K_AR5210_ISR_MCABT | AR5K_AR5210_ISR_SSERR | \ AR5K_AR5210_ISR_DPERR | AR5K_AR5210_ISR_RXORN \ @@ -110,37 +110,37 @@ /* * Interrupt mask register */ -#define AR5K_AR5210_IMR 0x0020 -#define AR5K_AR5210_IMR_RXOK 0x00000001 -#define AR5K_AR5210_IMR_RXDESC 0x00000002 -#define AR5K_AR5210_IMR_RXERR 0x00000004 -#define AR5K_AR5210_IMR_RXNOFRM 0x00000008 -#define AR5K_AR5210_IMR_RXEOL 0x00000010 -#define AR5K_AR5210_IMR_RXORN 0x00000020 -#define AR5K_AR5210_IMR_TXOK 0x00000040 -#define AR5K_AR5210_IMR_TXDESC 0x00000080 -#define AR5K_AR5210_IMR_TXERR 0x00000100 -#define AR5K_AR5210_IMR_TXNOFRM 0x00000200 -#define AR5K_AR5210_IMR_TXEOL 0x00000400 -#define AR5K_AR5210_IMR_TXURN 0x00000800 -#define AR5K_AR5210_IMR_MIB 0x00001000 -#define AR5K_AR5210_IMR_SWI 0x00002000 -#define AR5K_AR5210_IMR_RXPHY 0x00004000 -#define AR5K_AR5210_IMR_RXKCM 0x00008000 -#define AR5K_AR5210_IMR_SWBA 0x00010000 -#define AR5K_AR5210_IMR_BRSSI 0x00020000 -#define AR5K_AR5210_IMR_BMISS 0x00040000 -#define AR5K_AR5210_IMR_MCABT 0x00100000 -#define AR5K_AR5210_IMR_SSERR 0x00200000 -#define AR5K_AR5210_IMR_DPERR 0x00400000 -#define AR5K_AR5210_IMR_GPIO 0x01000000 +#define AR5K_AR5210_IMR 0x0020 +#define AR5K_AR5210_IMR_RXOK 0x00000001 +#define AR5K_AR5210_IMR_RXDESC 0x00000002 +#define AR5K_AR5210_IMR_RXERR 0x00000004 +#define AR5K_AR5210_IMR_RXNOFRM 0x00000008 +#define AR5K_AR5210_IMR_RXEOL 0x00000010 +#define AR5K_AR5210_IMR_RXORN 0x00000020 +#define AR5K_AR5210_IMR_TXOK 0x00000040 +#define AR5K_AR5210_IMR_TXDESC 0x00000080 +#define AR5K_AR5210_IMR_TXERR 0x00000100 +#define AR5K_AR5210_IMR_TXNOFRM 0x00000200 +#define AR5K_AR5210_IMR_TXEOL 0x00000400 +#define AR5K_AR5210_IMR_TXURN 0x00000800 +#define AR5K_AR5210_IMR_MIB 0x00001000 +#define AR5K_AR5210_IMR_SWI 0x00002000 +#define AR5K_AR5210_IMR_RXPHY 0x00004000 +#define AR5K_AR5210_IMR_RXKCM 0x00008000 +#define AR5K_AR5210_IMR_SWBA 0x00010000 +#define AR5K_AR5210_IMR_BRSSI 0x00020000 +#define AR5K_AR5210_IMR_BMISS 0x00040000 +#define AR5K_AR5210_IMR_MCABT 0x00100000 +#define AR5K_AR5210_IMR_SSERR 0x00200000 +#define AR5K_AR5210_IMR_DPERR 0x00400000 +#define AR5K_AR5210_IMR_GPIO 0x01000000 /* * Interrupt enable register */ #define AR5K_AR5210_IER 0x0024 -#define AR5K_AR5210_IER_DISABLE 0x00000000 -#define AR5K_AR5210_IER_ENABLE 0x00000001 +#define AR5K_AR5210_IER_DISABLE 0x00000000 +#define AR5K_AR5210_IER_ENABLE 0x00000001 /* * Beacon control register @@ -148,25 +148,25 @@ #define AR5K_AR5210_BCR 0x0028 #define AR5K_AR5210_BCR_AP 0x00000000 #define AR5K_AR5210_BCR_ADHOC 0x00000001 -#define AR5K_AR5210_BCR_BDMAE 0x00000002 -#define AR5K_AR5210_BCR_TQ1FV 0x00000004 -#define AR5K_AR5210_BCR_TQ1V 0x00000008 -#define AR5K_AR5210_BCR_BCGET 0x00000010 +#define AR5K_AR5210_BCR_BDMAE 0x00000002 +#define AR5K_AR5210_BCR_TQ1FV 0x00000004 +#define AR5K_AR5210_BCR_TQ1V 0x00000008 +#define AR5K_AR5210_BCR_BCGET 0x00000010 /* * Beacon status register */ -#define AR5K_AR5210_BSR 0x002c -#define AR5K_AR5210_BSR_BDLYSW 0x00000001 -#define AR5K_AR5210_BSR_BDLYDMA 0x00000002 -#define AR5K_AR5210_BSR_TXQ1F 0x00000004 -#define AR5K_AR5210_BSR_ATIMDLY 0x00000008 -#define AR5K_AR5210_BSR_SNPBCMD 0x00000100 -#define AR5K_AR5210_BSR_SNPBDMAE 0x00000200 -#define AR5K_AR5210_BSR_SNPTQ1FV 0x00000400 -#define AR5K_AR5210_BSR_SNPTQ1V 0x00000800 -#define AR5K_AR5210_BSR_SNAPPEDBCRVALID 0x00001000 -#define AR5K_AR5210_BSR_SWBA_CNT 0x00ff0000 +#define AR5K_AR5210_BSR 0x002c +#define AR5K_AR5210_BSR_BDLYSW 0x00000001 +#define AR5K_AR5210_BSR_BDLYDMA 0x00000002 +#define AR5K_AR5210_BSR_TXQ1F 0x00000004 +#define AR5K_AR5210_BSR_ATIMDLY 0x00000008 +#define AR5K_AR5210_BSR_SNPBCMD 0x00000100 +#define AR5K_AR5210_BSR_SNPBDMAE 0x00000200 +#define AR5K_AR5210_BSR_SNPTQ1FV 0x00000400 +#define AR5K_AR5210_BSR_SNPTQ1V 0x00000800 +#define AR5K_AR5210_BSR_SNAPPEDBCRVALID 0x00001000 +#define AR5K_AR5210_BSR_SWBA_CNT 0x00ff0000 /* * DMA size definitions @@ -185,27 +185,27 @@ typedef enum { /* * Transmit configuration register */ -#define AR5K_AR5210_TXCFG 0x0030 -#define AR5K_AR5210_TXCFG_SDMAMR 0x00000007 -#define AR5K_AR5210_TXCFG_TXFSTP 0x00000008 -#define AR5K_AR5210_TXCFG_TXFULL 0x00000070 -#define AR5K_AR5210_TXCFG_TXCONT_EN 0x00000080 +#define AR5K_AR5210_TXCFG 0x0030 +#define AR5K_AR5210_TXCFG_SDMAMR 0x00000007 +#define AR5K_AR5210_TXCFG_TXFSTP 0x00000008 +#define AR5K_AR5210_TXCFG_TXFULL 0x00000070 +#define AR5K_AR5210_TXCFG_TXCONT_EN 0x00000080 /* * Receive configuration register */ -#define AR5K_AR5210_RXCFG 0x0034 -#define AR5K_AR5210_RXCFG_SDMAMW 0x00000007 -#define AR5K_AR5210_RXCFG_ZLFDMA 0x00000010 +#define AR5K_AR5210_RXCFG 0x0034 +#define AR5K_AR5210_RXCFG_SDMAMW 0x00000007 +#define AR5K_AR5210_RXCFG_ZLFDMA 0x00000010 /* * MIB control register */ #define AR5K_AR5210_MIBC 0x0040 #define AR5K_AR5210_MIBC_COW 0x00000001 -#define AR5K_AR5210_MIBC_FMC 0x00000002 -#define AR5K_AR5210_MIBC_CMC 0x00000004 -#define AR5K_AR5210_MIBC_MCS 0x00000008 +#define AR5K_AR5210_MIBC_FMC 0x00000002 +#define AR5K_AR5210_MIBC_CMC 0x00000004 +#define AR5K_AR5210_MIBC_MCS 0x00000008 /* * Timeout prescale register @@ -227,28 +227,28 @@ typedef enum { */ #define AR5K_AR5210_RPGTO 0x0050 -/* - * Receive frame count limit register +/* + * Receive frame count limit register */ #define AR5K_AR5210_RFCNT 0x0054 -#define AR5K_AR5210_RFCNT_RFCL 0x0000000f +#define AR5K_AR5210_RFCNT_RFCL 0x0000000f /* - * Misc settings/status register + * Misc settings/status register */ #define AR5K_AR5210_MISC 0x0058 -#define AR5K_AR5210_MISC_LED_DECAY 0x001c0000 -#define AR5K_AR5210_MISC_LED_BLINK 0x00e00000 +#define AR5K_AR5210_MISC_LED_DECAY 0x001c0000 +#define AR5K_AR5210_MISC_LED_BLINK 0x00e00000 /* * Reset control register */ #define AR5K_AR5210_RC 0x4000 -#define AR5K_AR5210_RC_PCU 0x00000001 -#define AR5K_AR5210_RC_DMA 0x00000002 -#define AR5K_AR5210_RC_MAC 0x00000004 -#define AR5K_AR5210_RC_PHY 0x00000008 -#define AR5K_AR5210_RC_PCI 0x00000010 +#define AR5K_AR5210_RC_PCU 0x00000001 +#define AR5K_AR5210_RC_DMA 0x00000002 +#define AR5K_AR5210_RC_MAC 0x00000004 +#define AR5K_AR5210_RC_PHY 0x00000008 +#define AR5K_AR5210_RC_PCI 0x00000010 #define AR5K_AR5210_RC_CHIP ( \ AR5K_AR5210_RC_PCU | AR5K_AR5210_RC_DMA | \ AR5K_AR5210_RC_MAC | AR5K_AR5210_RC_PHY \ @@ -258,11 +258,11 @@ typedef enum { * Sleep control register */ #define AR5K_AR5210_SCR 0x4004 -#define AR5K_AR5210_SCR_SLDUR 0x0000ffff -#define AR5K_AR5210_SCR_SLE 0x00030000 -#define AR5K_AR5210_SCR_SLE_WAKE 0x00000000 -#define AR5K_AR5210_SCR_SLE_SLP 0x00010000 -#define AR5K_AR5210_SCR_SLE_ALLOW 0x00020000 +#define AR5K_AR5210_SCR_SLDUR 0x0000ffff +#define AR5K_AR5210_SCR_SLE 0x00030000 +#define AR5K_AR5210_SCR_SLE_WAKE 0x00000000 +#define AR5K_AR5210_SCR_SLE_SLP 0x00010000 +#define AR5K_AR5210_SCR_SLE_ALLOW 0x00020000 /* * Interrupt pending register @@ -274,34 +274,34 @@ typedef enum { * Sleep force register */ #define AR5K_AR5210_SFR 0x400c -#define AR5K_AR5210_SFR_SF 0x00000001 +#define AR5K_AR5210_SFR_SF 0x00000001 /* * PCI configuration register */ #define AR5K_AR5210_PCICFG 0x4010 -#define AR5K_AR5210_PCICFG_EEAE 0x00000001 -#define AR5K_AR5210_PCICFG_CLKRUNEN 0x00000004 -#define AR5K_AR5210_PCICFG_LED_PEND 0x00000020 -#define AR5K_AR5210_PCICFG_LED_ACT 0x00000040 -#define AR5K_AR5210_PCICFG_SL_INTEN 0x00000800 -#define AR5K_AR5210_PCICFG_LED_BCTL 0x00001000 -#define AR5K_AR5210_PCICFG_SL_INPEN 0x00002800 -#define AR5K_AR5210_PCICFG_SPWR_DN 0x00010000 +#define AR5K_AR5210_PCICFG_EEAE 0x00000001 +#define AR5K_AR5210_PCICFG_CLKRUNEN 0x00000004 +#define AR5K_AR5210_PCICFG_LED_PEND 0x00000020 +#define AR5K_AR5210_PCICFG_LED_ACT 0x00000040 +#define AR5K_AR5210_PCICFG_SL_INTEN 0x00000800 +#define AR5K_AR5210_PCICFG_LED_BCTL 0x00001000 +#define AR5K_AR5210_PCICFG_SL_INPEN 0x00002800 +#define AR5K_AR5210_PCICFG_SPWR_DN 0x00010000 /* * "General Purpose Input/Output" (GPIO) control register */ #define AR5K_AR5210_GPIOCR 0x4014 -#define AR5K_AR5210_GPIOCR_INT_ENA 0x00008000 -#define AR5K_AR5210_GPIOCR_INT_SELL 0x00000000 -#define AR5K_AR5210_GPIOCR_INT_SELH 0x00010000 -#define AR5K_AR5210_GPIOCR_IN(n) (0 << ((n) * 2)) -#define AR5K_AR5210_GPIOCR_OUT0(n) (1 << ((n) * 2)) -#define AR5K_AR5210_GPIOCR_OUT1(n) (2 << ((n) * 2)) -#define AR5K_AR5210_GPIOCR_OUT(n) (3 << ((n) * 2)) -#define AR5K_AR5210_GPIOCR_ALL(n) (3<< ((n) * 2)) -#define AR5K_AR5210_GPIOCR_INT_SEL(n) ((n) << 12) +#define AR5K_AR5210_GPIOCR_INT_ENA 0x00008000 +#define AR5K_AR5210_GPIOCR_INT_SELL 0x00000000 +#define AR5K_AR5210_GPIOCR_INT_SELH 0x00010000 +#define AR5K_AR5210_GPIOCR_IN(n) (0 << ((n) * 2)) +#define AR5K_AR5210_GPIOCR_OUT0(n) (1 << ((n) * 2)) +#define AR5K_AR5210_GPIOCR_OUT1(n) (2 << ((n) * 2)) +#define AR5K_AR5210_GPIOCR_OUT(n) (3 << ((n) * 2)) +#define AR5K_AR5210_GPIOCR_ALL(n) (3<< ((n) * 2)) +#define AR5K_AR5210_GPIOCR_INT_SEL(n) ((n) << 12) #define AR5K_AR5210_NUM_GPIO 6 @@ -323,22 +323,22 @@ typedef enum { #define AR5K_AR5210_SREV_ID_M 0x000000ff #define AR5K_AR5210_SREV_FPGA 1 #define AR5K_AR5210_SREV_PHYPLUS 2 -#define AR5K_AR5210_SREV_PHYPLUS_MS 3 +#define AR5K_AR5210_SREV_PHYPLUS_MS 3 #define AR5K_AR5210_SREV_CRETE 4 -#define AR5K_AR5210_SREV_CRETE_MS 5 -#define AR5K_AR5210_SREV_CRETE_MS23 7 -#define AR5K_AR5210_SREV_CRETE_23 8 +#define AR5K_AR5210_SREV_CRETE_MS 5 +#define AR5K_AR5210_SREV_CRETE_MS23 7 +#define AR5K_AR5210_SREV_CRETE_23 8 /* * EEPROM access registers */ -#define AR5K_AR5210_EEPROM_BASE 0x6000 -#define AR5K_AR5210_EEPROM_RDATA 0x6800 -#define AR5K_AR5210_EEPROM_STATUS 0x6c00 -#define AR5K_AR5210_EEPROM_STAT_RDERR 0x0001 -#define AR5K_AR5210_EEPROM_STAT_RDDONE 0x0002 -#define AR5K_AR5210_EEPROM_STAT_WRERR 0x0004 -#define AR5K_AR5210_EEPROM_STAT_WRDONE 0x0008 +#define AR5K_AR5210_EEPROM_BASE 0x6000 +#define AR5K_AR5210_EEPROM_RDATA 0x6800 +#define AR5K_AR5210_EEPROM_STATUS 0x6c00 +#define AR5K_AR5210_EEPROM_STAT_RDERR 0x0001 +#define AR5K_AR5210_EEPROM_STAT_RDDONE 0x0002 +#define AR5K_AR5210_EEPROM_STAT_WRERR 0x0004 +#define AR5K_AR5210_EEPROM_STAT_WRDONE 0x0008 /* * AR5210 EEPROM data registers @@ -370,15 +370,15 @@ typedef enum { * Second station id register (MAC address in upper 16 bits) */ #define AR5K_AR5210_STA_ID1 0x8004 -#define AR5K_AR5210_STA_ID1_AP 0x00010000 -#define AR5K_AR5210_STA_ID1_ADHOC 0x00020000 -#define AR5K_AR5210_STA_ID1_PWR_SV 0x00040000 -#define AR5K_AR5210_STA_ID1_NO_KEYSRCH 0x00080000 -#define AR5K_AR5210_STA_ID1_NO_PSPOLL 0x00100000 -#define AR5K_AR5210_STA_ID1_PCF 0x00200000 -#define AR5K_AR5210_STA_ID1_DESC_ANTENNA 0x00400000 -#define AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA 0x00800000 -#define AR5K_AR5210_STA_ID1_ACKCTS_6MB 0x01000000 +#define AR5K_AR5210_STA_ID1_AP 0x00010000 +#define AR5K_AR5210_STA_ID1_ADHOC 0x00020000 +#define AR5K_AR5210_STA_ID1_PWR_SV 0x00040000 +#define AR5K_AR5210_STA_ID1_NO_KEYSRCH 0x00080000 +#define AR5K_AR5210_STA_ID1_NO_PSPOLL 0x00100000 +#define AR5K_AR5210_STA_ID1_PCF 0x00200000 +#define AR5K_AR5210_STA_ID1_DESC_ANTENNA 0x00400000 +#define AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA 0x00800000 +#define AR5K_AR5210_STA_ID1_ACKCTS_6MB 0x01000000 /* * First BSSID register (MAC address, lower 32bits) @@ -391,7 +391,7 @@ typedef enum { * AID: Association ID */ #define AR5K_AR5210_BSS_ID1 0x800c -#define AR5K_AR5210_BSS_ID1_AID 0xffff0000 +#define AR5K_AR5210_BSS_ID1_AID 0xffff0000 #define AR5K_AR5210_BSS_ID1_AID_S 16 /* @@ -403,29 +403,29 @@ typedef enum { * ACK/CTS timeout register */ #define AR5K_AR5210_TIME_OUT 0x8014 -#define AR5K_AR5210_TIME_OUT_ACK 0x00001fff +#define AR5K_AR5210_TIME_OUT_ACK 0x00001fff #define AR5K_AR5210_TIME_OUT_ACK_S 0 -#define AR5K_AR5210_TIME_OUT_CTS 0x1fff0000 +#define AR5K_AR5210_TIME_OUT_CTS 0x1fff0000 #define AR5K_AR5210_TIME_OUT_CTS_S 16 /* * RSSI threshold register */ #define AR5K_AR5210_RSSI_THR 0x8018 -#define AR5K_AR5210_RSSI_THR_BM_THR 0x00000700 +#define AR5K_AR5210_RSSI_THR_BM_THR 0x00000700 #define AR5K_AR5210_RSSI_THR_BM_THR_S 8 /* * Retry limit register */ #define AR5K_AR5210_RETRY_LMT 0x801c -#define AR5K_AR5210_RETRY_LMT_SH_RETRY 0x0000000f +#define AR5K_AR5210_RETRY_LMT_SH_RETRY 0x0000000f #define AR5K_AR5210_RETRY_LMT_SH_RETRY_S 0 -#define AR5K_AR5210_RETRY_LMT_LG_RETRY 0x000000f0 +#define AR5K_AR5210_RETRY_LMT_LG_RETRY 0x000000f0 #define AR5K_AR5210_RETRY_LMT_LG_RETRY_S 4 -#define AR5K_AR5210_RETRY_LMT_SSH_RETRY 0x00003f00 +#define AR5K_AR5210_RETRY_LMT_SSH_RETRY 0x00003f00 #define AR5K_AR5210_RETRY_LMT_SSH_RETRY_S 8 -#define AR5K_AR5210_RETRY_LMT_SLG_RETRY 0x000fc000 +#define AR5K_AR5210_RETRY_LMT_SLG_RETRY 0x000fc000 #define AR5K_AR5210_RETRY_LMT_SLG_RETRY_S 14 #define AR5K_AR5210_RETRY_LMT_CW_MIN 0x3ff00000 #define AR5K_AR5210_RETRY_LMT_CW_MIN_S 20 @@ -434,85 +434,85 @@ typedef enum { * Transmit latency register */ #define AR5K_AR5210_USEC 0x8020 -#define AR5K_AR5210_USEC_1 0x0000007f +#define AR5K_AR5210_USEC_1 0x0000007f #define AR5K_AR5210_USEC_1_S 0 -#define AR5K_AR5210_USEC_32 0x00003f80 +#define AR5K_AR5210_USEC_32 0x00003f80 #define AR5K_AR5210_USEC_32_S 7 -#define AR5K_AR5210_USEC_TX_LATENCY 0x000fc000 +#define AR5K_AR5210_USEC_TX_LATENCY 0x000fc000 #define AR5K_AR5210_USEC_TX_LATENCY_S 14 -#define AR5K_AR5210_USEC_RX_LATENCY 0x03f00000 +#define AR5K_AR5210_USEC_RX_LATENCY 0x03f00000 #define AR5K_AR5210_USEC_RX_LATENCY_S 20 /* * PCU beacon control register */ #define AR5K_AR5210_BEACON 0x8024 -#define AR5K_AR5210_BEACON_PERIOD 0x0000ffff +#define AR5K_AR5210_BEACON_PERIOD 0x0000ffff #define AR5K_AR5210_BEACON_PERIOD_S 0 -#define AR5K_AR5210_BEACON_TIM 0x007f0000 +#define AR5K_AR5210_BEACON_TIM 0x007f0000 #define AR5K_AR5210_BEACON_TIM_S 16 -#define AR5K_AR5210_BEACON_EN 0x00800000 -#define AR5K_AR5210_BEACON_RESET_TSF 0x01000000 +#define AR5K_AR5210_BEACON_EN 0x00800000 +#define AR5K_AR5210_BEACON_RESET_TSF 0x01000000 /* * CFP period register */ -#define AR5K_AR5210_CFP_PERIOD 0x8028 +#define AR5K_AR5210_CFP_PERIOD 0x8028 /* * Next beacon time register */ -#define AR5K_AR5210_TIMER0 0x802c +#define AR5K_AR5210_TIMER0 0x802c /* * Next DMA beacon alert register */ -#define AR5K_AR5210_TIMER1 0x8030 +#define AR5K_AR5210_TIMER1 0x8030 /* * Next software beacon alert register */ -#define AR5K_AR5210_TIMER2 0x8034 +#define AR5K_AR5210_TIMER2 0x8034 /* * Next ATIM window time register */ -#define AR5K_AR5210_TIMER3 0x8038 +#define AR5K_AR5210_TIMER3 0x8038 /* * First inter frame spacing register (IFS) */ #define AR5K_AR5210_IFS0 0x8040 -#define AR5K_AR5210_IFS0_SIFS 0x000007ff +#define AR5K_AR5210_IFS0_SIFS 0x000007ff #define AR5K_AR5210_IFS0_SIFS_S 0 -#define AR5K_AR5210_IFS0_DIFS 0x007ff800 +#define AR5K_AR5210_IFS0_DIFS 0x007ff800 #define AR5K_AR5210_IFS0_DIFS_S 11 /* * Second inter frame spacing register (IFS) */ #define AR5K_AR5210_IFS1 0x8044 -#define AR5K_AR5210_IFS1_PIFS 0x00000fff +#define AR5K_AR5210_IFS1_PIFS 0x00000fff #define AR5K_AR5210_IFS1_PIFS_S 0 -#define AR5K_AR5210_IFS1_EIFS 0x03fff000 +#define AR5K_AR5210_IFS1_EIFS 0x03fff000 #define AR5K_AR5210_IFS1_EIFS_S 12 -#define AR5K_AR5210_IFS1_CS_EN 0x04000000 +#define AR5K_AR5210_IFS1_CS_EN 0x04000000 /* * CFP duration register */ -#define AR5K_AR5210_CFP_DUR 0x8048 +#define AR5K_AR5210_CFP_DUR 0x8048 /* * Receive filter register */ -#define AR5K_AR5210_RX_FILTER 0x804c -#define AR5K_AR5210_RX_FILTER_UNICAST 0x00000001 -#define AR5K_AR5210_RX_FILTER_MULTICAST 0x00000002 -#define AR5K_AR5210_RX_FILTER_BROADCAST 0x00000004 -#define AR5K_AR5210_RX_FILTER_CONTROL 0x00000008 -#define AR5K_AR5210_RX_FILTER_BEACON 0x00000010 -#define AR5K_AR5210_RX_FILTER_PROMISC 0x00000020 +#define AR5K_AR5210_RX_FILTER 0x804c +#define AR5K_AR5210_RX_FILTER_UNICAST 0x00000001 +#define AR5K_AR5210_RX_FILTER_MULTICAST 0x00000002 +#define AR5K_AR5210_RX_FILTER_BROADCAST 0x00000004 +#define AR5K_AR5210_RX_FILTER_CONTROL 0x00000008 +#define AR5K_AR5210_RX_FILTER_BEACON 0x00000010 +#define AR5K_AR5210_RX_FILTER_PROMISC 0x00000020 /* * Multicast filter register (lower 32 bits) @@ -527,7 +527,7 @@ typedef enum { /* * Transmit mask register (lower 32 bits) */ -#define AR5K_AR5210_TX_MASK0 0x8058 +#define AR5K_AR5210_TX_MASK0 0x8058 /* * Transmit mask register (higher 16 bits) @@ -548,20 +548,20 @@ typedef enum { * PCU control register */ #define AR5K_AR5210_DIAG_SW 0x8068 -#define AR5K_AR5210_DIAG_SW_DIS_WEP_ACK 0x00000001 -#define AR5K_AR5210_DIAG_SW_DIS_ACK 0x00000002 -#define AR5K_AR5210_DIAG_SW_DIS_CTS 0x00000004 -#define AR5K_AR5210_DIAG_SW_DIS_ENC 0x00000008 -#define AR5K_AR5210_DIAG_SW_DIS_DEC 0x00000010 -#define AR5K_AR5210_DIAG_SW_DIS_TX 0x00000020 -#define AR5K_AR5210_DIAG_SW_DIS_RX 0x00000040 -#define AR5K_AR5210_DIAG_SW_LOOP_BACK 0x00000080 -#define AR5K_AR5210_DIAG_SW_CORR_FCS 0x00000100 -#define AR5K_AR5210_DIAG_SW_CHAN_INFO 0x00000200 -#define AR5K_AR5210_DIAG_SW_EN_SCRAM_SEED 0x00000400 -#define AR5K_AR5210_DIAG_SW_SCVRAM_SEED 0x0003f800 -#define AR5K_AR5210_DIAG_SW_DIS_SEQ_INC 0x00040000 -#define AR5K_AR5210_DIAG_SW_FRAME_NV0 0x00080000 +#define AR5K_AR5210_DIAG_SW_DIS_WEP_ACK 0x00000001 +#define AR5K_AR5210_DIAG_SW_DIS_ACK 0x00000002 +#define AR5K_AR5210_DIAG_SW_DIS_CTS 0x00000004 +#define AR5K_AR5210_DIAG_SW_DIS_ENC 0x00000008 +#define AR5K_AR5210_DIAG_SW_DIS_DEC 0x00000010 +#define AR5K_AR5210_DIAG_SW_DIS_TX 0x00000020 +#define AR5K_AR5210_DIAG_SW_DIS_RX 0x00000040 +#define AR5K_AR5210_DIAG_SW_LOOP_BACK 0x00000080 +#define AR5K_AR5210_DIAG_SW_CORR_FCS 0x00000100 +#define AR5K_AR5210_DIAG_SW_CHAN_INFO 0x00000200 +#define AR5K_AR5210_DIAG_SW_EN_SCRAM_SEED 0x00000400 +#define AR5K_AR5210_DIAG_SW_SCVRAM_SEED 0x0003f800 +#define AR5K_AR5210_DIAG_SW_DIS_SEQ_INC 0x00040000 +#define AR5K_AR5210_DIAG_SW_FRAME_NV0 0x00080000 /* * TSF (clock) register (lower 32 bits) @@ -582,15 +582,15 @@ typedef enum { * Retry count register */ #define AR5K_AR5210_RETRY_CNT 0x8084 -#define AR5K_AR5210_RETRY_CNT_SSH 0x0000003f -#define AR5K_AR5210_RETRY_CNT_SLG 0x00000fc0 +#define AR5K_AR5210_RETRY_CNT_SSH 0x0000003f +#define AR5K_AR5210_RETRY_CNT_SLG 0x00000fc0 /* * Back-off status register */ #define AR5K_AR5210_BACKOFF 0x8088 -#define AR5K_AR5210_BACKOFF_CW 0x000003ff -#define AR5K_AR5210_BACKOFF_CNT 0x03ff0000 +#define AR5K_AR5210_BACKOFF_CW 0x000003ff +#define AR5K_AR5210_BACKOFF_CNT 0x03ff0000 /* * NAV register (current) @@ -635,7 +635,7 @@ typedef enum { #define AR5K_AR5210_KEYTABLE_SIZE 64 #define AR5K_AR5210_KEYCACHE_SIZE 8 -/* +/* * PHY register */ #define AR5K_AR5210_PHY(_n) (0x9800 + ((_n) << 2)) |