diff options
Diffstat (limited to 'sys/dev/ic/z8530reg.h')
| -rw-r--r-- | sys/dev/ic/z8530reg.h | 87 |
1 files changed, 54 insertions, 33 deletions
diff --git a/sys/dev/ic/z8530reg.h b/sys/dev/ic/z8530reg.h index f035900ac95..9e47c07f00c 100644 --- a/sys/dev/ic/z8530reg.h +++ b/sys/dev/ic/z8530reg.h @@ -1,5 +1,5 @@ -/* $OpenBSD: z8530reg.h,v 1.3 1996/10/31 01:01:42 niklas Exp $ */ -/* $NetBSD: z8530reg.h,v 1.5 1996/01/24 19:21:40 gwr Exp $ */ +/* $OpenBSD: z8530reg.h,v 1.4 1996/11/28 23:27:56 niklas Exp $ */ +/* $NetBSD: z8530reg.h,v 1.7 1996/10/23 00:32:31 gwr Exp $ */ /* * Copyright (c) 1992, 1993 @@ -64,22 +64,12 @@ * registers 2 and 9 across both channels, and reads registers 2 and 3 * differently for the two channels. We can, however, ignore this much * of the time. - */ -#if 0 /* Example only! */ -/* - * The layout of this structure is hardware-dependent! - * Define these in some machine-dependent place. - */ -struct zschan { - volatile u_char zc_csr; /* ctrl, status, or reg. number */ - volatile u_char zc_data; /* data or numbered register */ -}; -struct zsdevice { - struct zschan zs_chan[2]; -}; -#endif /* Example only! */ - -/* + * + * This file also includes flags for the Z85C30 and Z85230 enhanced scc. + * The CMOS 8530 includes extra SDLC functionality, and is used in a + * number of Macs (often in the Z85C80, an 85C30 combined w/ a SCSI + * controller). -wrs + * * Some of the names in this files were chosen to make the hsis driver * work unchanged (which means that they will match some in SunOS). * @@ -88,9 +78,7 @@ struct zsdevice { * framing error (missing stop bit, etc) * end of frame (in synchronous modes) * parity error (when `parity error is S.C.' is set) - */ - -/* + * * Registers with only a single `numeric value' get a name. * Other registers hold bits and are only numbered; the bit * definitions imply the register number (see below). @@ -101,8 +89,15 @@ struct zsdevice { */ #define ZSRR_IVEC 2 /* interrupt vector (channel 0) */ #define ZSRR_IPEND 3 /* interrupt pending (ch. 0 only) */ +#define ZSRR_TXSYNC 6 /* sync transmit char (monosync mode) */ +#define ZSRR_RXSYNC 7 /* sync receive char (monosync mode) */ +#define ZSRR_SYNCLO 6 /* sync low byte (bisync mode) */ +#define ZSRR_SYNCHI 7 /* sync high byte (bisync mode) */ +#define ZSRR_SDLC_ADDR 6 /* SDLC address (SDLC mode) */ +#define ZSRR_SDLC_FLAG 7 /* SDLC flag 0x7E (SDLC mode) */ #define ZSRR_BAUDLO 12 /* baud rate generator (low half) */ #define ZSRR_BAUDHI 13 /* baud rate generator (high half) */ +#define ZSRR_ENHANCED 14 /* read address of WR7' - yes, it's not 7!*/ #define ZSWR_IVEC 2 /* interrupt vector (shared) */ #define ZSWR_TXSYNC 6 /* sync transmit char (monosync mode) */ @@ -113,6 +108,7 @@ struct zsdevice { #define ZSWR_SDLC_FLAG 7 /* SDLC flag 0x7E (SDLC mode) */ #define ZSWR_BAUDLO 12 /* baud rate generator (low half) */ #define ZSWR_BAUDHI 13 /* baud rate generator (high half) */ +#define ZSWR_ENHANCED 7 /* write address of WR7' */ /* * Registers 0 through 7 may be written with any one of the 8 command @@ -186,6 +182,7 @@ struct zsdevice { #define ZSWR3_RX_7 0x40 /* receive 7 bits per char */ #define ZSWR3_RX_6 0x80 /* receive 6 bits per char */ #define ZSWR3_RX_8 0xc0 /* receive 8 bits per char */ +#define ZSWR3_RXSIZE 0xc0 /* receive char size mask */ #define ZSWR3_HFC 0x20 /* hardware flow control */ #define ZSWR3_HUNT 0x10 /* enter hunt mode */ @@ -202,19 +199,23 @@ struct zsdevice { #define ZSWR4_CLK_X16 0x40 /* clock divisor = 16 */ #define ZSWR4_CLK_X32 0x80 /* clock divisor = 32 */ #define ZSWR4_CLK_X64 0xc0 /* clock divisor = 64 */ +#define ZSWR4_CLK_MASK 0xc0 /* clock divisor mask */ #define ZSWR4_MONOSYNC 0x00 /* 8 bit sync char (sync only) */ #define ZSWR4_BISYNC 0x10 /* 16 bit sync char (sync only) */ -#define ZSWR4_SDLC 0x20 /* SDLC mode */ +#define ZSWR4_SDLC 0x20 /* SDLC mode */ #define ZSWR4_EXTSYNC 0x30 /* external sync mode */ +#define ZSWR4_SYNC_MASK 0x30 /* sync mode bit mask */ -#define ZSWR4_SYNCMODE 0x00 /* one of the above sync modes */ -#define ZSWR4_ONESB 0x04 /* 1 stop bit */ -#define ZSWR4_1P5SB 0x08 /* 1.5 stop bits (clk cannot be 1x) */ -#define ZSWR4_TWOSB 0x0c /* 2 stop bits */ +#define ZSWR4_SYNCMODE 0x00 /* no stop bit (sync mode only) */ +#define ZSWR4_ONESB 0x04 /* 1 stop bit */ +#define ZSWR4_1P5SB 0x08 /* 1.5 stop bits (clk cannot be 1x) */ +#define ZSWR4_TWOSB 0x0c /* 2 stop bits */ +#define ZSWR4_SBMASK 0x0c /* mask of all stop bits */ -#define ZSWR4_EVENP 0x02 /* check for even parity */ +#define ZSWR4_EVENP 0x02 /* check for even parity */ #define ZSWR4_PARENB 0x01 /* enable parity checking */ +#define ZSWR4_PARMASK 0x03 /* mask of all parity bits */ /* * Bits in Write Register 5 (`Transmit Parameter and Controls'). @@ -227,6 +228,7 @@ struct zsdevice { #define ZSWR5_TX_7 0x20 /* transmit 7 bits */ #define ZSWR5_TX_6 0x40 /* transmit 6 bits */ #define ZSWR5_TX_8 0x60 /* transmit 8 bits */ +#define ZSWR5_TXSIZE 0x60 /* transmit char size mask */ #define ZSWR5_BREAK 0x10 /* send break (continuous 0s) */ #define ZSWR5_TX_ENABLE 0x08 /* enable transmitter */ @@ -242,6 +244,21 @@ struct zsdevice { #endif /* + * Bits in Write Register 7' (ZSWR_ENHANCED above). This register is + * only available on the 85230. Dispite the fact it contains flags + * and not a single value, the register was named as it is read + * via RR14. Weird. + */ + /* 0x80 unused */ +#define ZSWR7P_EXTEND_READ 0x40 /* modify read map; make most regs readable */ +#define ZSWR7P_TX_FIFO 0x20 /* change level for Tx FIFO empty int */ +#define ZSWR7P_DTR_TIME 0x10 /* modifies deact. speed of /DTR//REQ */ +#define ZSWR7P_RX_FIFO 0x08 /* Rx FIFO int on 1/2 full? */ +#define ZSWR7P_RTS_DEACT 0x04 /* automatically deassert RTS */ +#define ZSWR7P_AUTO_EOM_RESET 0x02 /* automatically reset EMO/Tx Underrun */ +#define ZSWR7P_AUTO_TX_FLAG 0x01 /* Auto send SDLC flag at transmit start */ + +/* * Bits in Write Register 9 (`Master Interrupt Control'). Bits 7 & 6 * are taken as a unit and indicate the type of reset; 00 means no reset * (and is not defined here). @@ -249,7 +266,7 @@ struct zsdevice { #define ZSWR9_HARD_RESET 0xc0 /* force hardware reset */ #define ZSWR9_A_RESET 0x80 /* reset channel A (0) */ #define ZSWR9_B_RESET 0x40 /* reset channel B (1) */ - /* 0x20 unused */ +#define ZSWR9_SOFT_INTAC 0x20 /* Not in NMOS version */ #define ZSWR9_STATUS_HIGH 0x10 /* status in high bits of intr vec */ #define ZSWR9_MASTER_IE 0x08 /* master interrupt enable */ @@ -282,13 +299,13 @@ struct zsdevice { */ #define ZSWR11_XTAL 0x80 /* have xtal between RTxC* and SYNC* */ /* (else have TTL oscil. on RTxC*) */ -#define ZSWR11_RXCLK_RTXC 0x00 /* recv clock taken from TRxC* pin */ +#define ZSWR11_RXCLK_RTXC 0x00 /* recv clock taken from RTxC* pin */ #define ZSWR11_RXCLK_TRXC 0x20 /* recv clock taken from TRxC* pin */ #define ZSWR11_RXCLK_BAUD 0x40 /* recv clock taken from BRG */ #define ZSWR11_RXCLK_DPLL 0x60 /* recv clock taken from DPLL */ -#define ZSWR11_TXCLK_RTXC 0x00 /* xmit clock taken from TRxC* pin */ -#define ZSWR11_TXCLK_TRXC 0x08 /* xmit clock taken from RTxC* pin */ +#define ZSWR11_TXCLK_RTXC 0x00 /* xmit clock taken from RTxC* pin */ +#define ZSWR11_TXCLK_TRXC 0x08 /* xmit clock taken from TRxC* pin */ #define ZSWR11_TXCLK_BAUD 0x10 /* xmit clock taken from BRG */ #define ZSWR11_TXCLK_DPLL 0x18 /* xmit clock taken from DPLL */ @@ -349,15 +366,19 @@ struct zsdevice { * Bits in Write Register 15 (`External/Status Interrupt Control'). * Most of these cause status interrupts whenever the corresponding * bit or pin changes state (i.e., any rising or falling edge). + * + * NOTE: ZSWR15_SDLC_FIFO & ZSWR15_ENABLE_ENHANCED should not be + * set on an NMOS 8530. Also, ZSWR15_ENABLE_ENHANCED is only + * available on the 85230. */ #define ZSWR15_BREAK_IE 0x80 /* enable break/abort status int */ #define ZSWR15_TXUEOM_IE 0x40 /* enable TX underrun/EOM status int */ #define ZSWR15_CTS_IE 0x20 /* enable CTS* pin status int */ #define ZSWR15_SYNCHUNT_IE 0x10 /* enable SYNC* pin/hunt status int */ #define ZSWR15_DCD_IE 0x08 /* enable DCD* pin status int */ - /* 0x04 unused, must be zero */ +#define ZSWR15_SDLC_FIFO 0x04 /* enable SDLC FIFO enhancements */ #define ZSWR15_ZERO_COUNT_IE 0x02 /* enable BRG-counter = 0 status int */ - /* 0x01 unused, must be zero */ +#define ZSWR15_ENABLE_ENHANCED 0x01 /* enable writing WR7' at reg 7 */ /* * Bits in Read Register 0 (`Transmit/Receive Buffer Status and External |