diff options
Diffstat (limited to 'sys/dev/ic')
| -rw-r--r-- | sys/dev/ic/z8530.doc | 76 | ||||
| -rw-r--r-- | sys/dev/ic/z8530reg.h | 24 | ||||
| -rw-r--r-- | sys/dev/ic/z8530sc.c | 326 | ||||
| -rw-r--r-- | sys/dev/ic/z8530sc.h | 111 | ||||
| -rw-r--r-- | sys/dev/ic/z8530tty.c | 1042 |
5 files changed, 1564 insertions, 15 deletions
diff --git a/sys/dev/ic/z8530.doc b/sys/dev/ic/z8530.doc new file mode 100644 index 00000000000..ba0c5afb1da --- /dev/null +++ b/sys/dev/ic/z8530.doc @@ -0,0 +1,76 @@ +$NetBSD: z8530.doc,v 1.1 1996/01/24 01:07:21 gwr Exp $ + +Here are the results of my reorganization work on the zs driver. +Everything compiles and appears to work. + +Enjoy! +Gordon Ross + +---------------------------------------------------------------- +This design has a "zs controller" named "zsc" with three +flavors of child drivers that can be attached above it. +The three child drivers are: + zstty: normal RS-232 line + kbd: sun keyboard + ms: sun mouse + +Note that the machine-dependent parts are: + arch/sun3/include/z8530var.h + arch/sun3/dev/zs.c +(replicate those for new systems) + +The Sun hardware dependent parts (Sun3 and SPARC) are: + kd* sun keyboard/display console stuff + event* sun "firm event" stuff + +---------------------------------------------------------------- +Here is how the autoconfig looks on a sun3: + +zsc0 at obio0 addr 0x0 level 6 softpri 3 +kbd0 at zsc0 channel 0 +ms0 at zsc0 channel 1 +zsc1 at obio0 addr 0x20000 level 6 softpri 3 +zstty0 at zsc1 channel 0 (console) +zstty1 at zsc1 channel 1 + + +---------------------------------------------------------------- +Config lines: + +In any config file (i.e. GENERIC, NEW_ZS, ...) +Note {kbd,ms} are sun-specific. + +# +# New console (zs) stuff +# +zsc0 at obio? addr ? +zsc1 at obio? addr ? +kbd0 at zsc0 channel 0 +ms0 at zsc0 channel 1 +zstty* at zsc? channel ? + + +---------------------------------------------------------------- +In conf/files.sun3 + +# +# Console (zs) related stuff +# +device zsc at obio {channel = -1} +file arch/sun3/dev/zs.c zsc needs-flag +file dev/ic/z8530sc.c zsc + +device zstty at zsc: tty +file dev/ic/z8530tty.c zstty needs-flag + +define zsevent +file dev/sun/event.c zsevent + +device kbd at zsc: zsevent +file dev/sun/kbd.c kbd needs-flag +file dev/sun/kbd_tables.c kbd +file arch/sun3/dev/kd.c kbd + +device ms at zsc: zsevent +file dev/sun/ms.c ms needs-flag + diff --git a/sys/dev/ic/z8530reg.h b/sys/dev/ic/z8530reg.h index 30abf6206b2..a973bd6420e 100644 --- a/sys/dev/ic/z8530reg.h +++ b/sys/dev/ic/z8530reg.h @@ -1,4 +1,4 @@ -/* $NetBSD: z8530reg.h,v 1.4 1995/08/20 13:24:05 leo Exp $ */ +/* $NetBSD: z8530reg.h,v 1.5 1996/01/24 19:21:40 gwr Exp $ */ /* * Copyright (c) 1992, 1993 @@ -64,25 +64,19 @@ * differently for the two channels. We can, however, ignore this much * of the time. */ -#ifndef LOCORE +#if 0 /* Example only! */ +/* + * The layout of this structure is hardware-dependent! + * Define these in some machine-dependent place. + */ struct zschan { -#if (BYTE_ORDER == BIG_ENDIAN) && !defined(atari) - volatile u_char zc_csr; /* ctrl,status, and indirect access */ - u_char zc_xxx0; - volatile u_char zc_data; /* data */ - u_char zc_xxx1; -#else - u_char zc_xxx0; - volatile u_char zc_csr; /* ctrl,status, and indirect access */ - u_char zc_xxx1; - volatile u_char zc_data; /* data */ -#endif + volatile u_char zc_csr; /* ctrl, status, or reg. number */ + volatile u_char zc_data; /* data or numbered register */ }; - struct zsdevice { struct zschan zs_chan[2]; }; -#endif +#endif /* Example only! */ /* * Some of the names in this files were chosen to make the hsis driver diff --git a/sys/dev/ic/z8530sc.c b/sys/dev/ic/z8530sc.c new file mode 100644 index 00000000000..7b7ef11d4aa --- /dev/null +++ b/sys/dev/ic/z8530sc.c @@ -0,0 +1,326 @@ +/* $NetBSD: z8530sc.c,v 1.1 1996/01/24 01:07:23 gwr Exp $ */ + +/* + * Copyright (c) 1994 Gordon W. Ross + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This software was developed by the Computer Systems Engineering group + * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and + * contributed to Berkeley. + * + * All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Lawrence Berkeley Laboratory. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)zs.c 8.1 (Berkeley) 7/19/93 + */ + +/* + * Zilog Z8530 Dual UART driver (common part) + * + * This file contains the machine-independent parts of the + * driver common to tty and keyboard/mouse sub-drivers. + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/proc.h> +#include <sys/device.h> +#include <sys/conf.h> +#include <sys/file.h> +#include <sys/ioctl.h> +#include <sys/tty.h> +#include <sys/time.h> +#include <sys/kernel.h> +#include <sys/syslog.h> + +#include <dev/ic/z8530reg.h> +#include <machine/z8530var.h> + +int +zs_break(cs, set) + struct zs_chanstate *cs; + int set; +{ + int s; + + s = splzs(); + if (set) { + cs->cs_preg[5] |= ZSWR5_BREAK; + cs->cs_creg[5] |= ZSWR5_BREAK; + } else { + cs->cs_preg[5] &= ~ZSWR5_BREAK; + cs->cs_creg[5] &= ~ZSWR5_BREAK; + } + ZS_WRITE(cs, 5, cs->cs_creg[5]); + splx(s); +} + + +/* + * Compute the current baud rate given a ZSCC channel. + */ +int +zs_getspeed(cs) + struct zs_chanstate *cs; +{ + int tconst; + + tconst = ZS_READ(cs, 12); + tconst |= ZS_READ(cs, 13) << 8; + return (TCONST_TO_BPS(cs->cs_pclk_div16, tconst)); +} + +/* + * drain on-chip fifo + */ +void +zs_iflush(cs) + struct zs_chanstate *cs; +{ + u_char c, rr0, rr1; + + for (;;) { + /* Is there input available? */ + rr0 = *(cs->cs_reg_csr); + ZS_DELAY(); + if ((rr0 & ZSRR0_RX_READY) == 0) + break; + + /* Read the data. */ + c = *(cs->cs_reg_data); + ZS_DELAY(); + + /* Need to read status register too? */ + rr1 = ZS_READ(cs, 1); + if (rr1 & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE)) { + /* Clear the receive error. */ + *(cs->cs_reg_csr) = ZSWR0_RESET_ERRORS; + ZS_DELAY(); + } + } +} + + +/* + * Write the given register set to the given zs channel in the proper order. + * The channel must not be transmitting at the time. The receiver will + * be disabled for the time it takes to write all the registers. + * Call this with interrupts disabled. + */ +void +zs_loadchannelregs(cs) + struct zs_chanstate *cs; +{ + u_char *reg; + int i; + + /* Copy "pending" regs to "current" */ + bcopy((caddr_t)cs->cs_preg, (caddr_t)cs->cs_creg, 16); + reg = cs->cs_creg; /* current regs */ + + *(cs->cs_reg_csr) = ZSM_RESET_ERR; /* XXX: reset error condition */ + ZS_DELAY(); + +#if 1 + /* + * XXX: Is this really a good idea? + * XXX: Should go elsewhere! -gwr + */ + zs_iflush(cs); /* XXX */ +#endif + + /* baud clock divisor, stop bits, parity */ + ZS_WRITE(cs, 4, reg[4]); + + /* misc. TX/RX control bits */ + ZS_WRITE(cs, 10, reg[10]); + + /* char size, enable (RX/TX) */ + ZS_WRITE(cs, 3, reg[3] & ~ZSWR3_RX_ENABLE); + ZS_WRITE(cs, 5, reg[5] & ~ZSWR5_TX_ENABLE); + + /* interrupt enables: TX, TX, STATUS */ + ZS_WRITE(cs, 1, reg[1]); + +#if 0 + /* + * Registers 2 and 9 are special because they are + * actually common to both channels, but must be + * programmed through channel A. The "zsc" attach + * function takes care of setting these registers + * and they should not be touched thereafter. + */ + /* interrupt vector */ + ZS_WRITE(cs, 2, reg[2]); + /* master interrupt control */ + ZS_WRITE(cs, 9, reg[9]); +#endif + + /* clock mode control */ + ZS_WRITE(cs, 11, reg[11]); + + /* baud rate (lo/hi) */ + ZS_WRITE(cs, 12, reg[12]); + ZS_WRITE(cs, 13, reg[13]); + + /* Misc. control bits */ + ZS_WRITE(cs, 14, reg[14]); + + /* which lines cause status interrupts */ + ZS_WRITE(cs, 15, reg[15]); + + /* char size, enable (RX/TX)*/ + ZS_WRITE(cs, 3, reg[3]); + ZS_WRITE(cs, 5, reg[5]); +} + + +/* + * ZS hardware interrupt. Scan all ZS channels. NB: we know here that + * channels are kept in (A,B) pairs. + * + * Do just a little, then get out; set a software interrupt if more + * work is needed. + * + * We deliberately ignore the vectoring Zilog gives us, and match up + * only the number of `reset interrupt under service' operations, not + * the order. + */ +int +zsc_intr_hard(arg) + void *arg; +{ + register struct zsc_softc *zsc = arg; + register struct zs_chanstate *cs_a; + register struct zs_chanstate *cs_b; + register int rval, soft; + register u_char rr3; + + cs_a = &zsc->zsc_cs[0]; + cs_b = &zsc->zsc_cs[1]; + rval = 0; + soft = 0; + + /* Note: only channel A has an RR3 */ + rr3 = ZS_READ(cs_a, 3); + + /* Handle receive interrupts first. */ + if (rr3 & ZSRR3_IP_A_RX) + (*cs_a->cs_ops->zsop_rxint)(cs_a); + if (rr3 & ZSRR3_IP_B_RX) + (*cs_b->cs_ops->zsop_rxint)(cs_b); + + /* Handle transmit done interrupts. */ + if (rr3 & ZSRR3_IP_A_TX) + (*cs_a->cs_ops->zsop_txint)(cs_a); + if (rr3 & ZSRR3_IP_B_TX) + (*cs_b->cs_ops->zsop_txint)(cs_b); + + /* Handle status interrupts. */ + if (rr3 & ZSRR3_IP_A_STAT) + (*cs_a->cs_ops->zsop_stint)(cs_a); + if (rr3 & ZSRR3_IP_B_STAT) + (*cs_b->cs_ops->zsop_stint)(cs_b); + + /* Clear interrupt. */ + if (rr3 & (ZSRR3_IP_A_RX | ZSRR3_IP_A_TX | ZSRR3_IP_A_STAT)) { + *(cs_a->cs_reg_csr) = ZSWR0_CLR_INTR; + ZS_DELAY(); + rval |= 1; + } + if (rr3 & (ZSRR3_IP_B_RX | ZSRR3_IP_B_TX | ZSRR3_IP_B_STAT)) { + *(cs_b->cs_reg_csr) = ZSWR0_CLR_INTR; + ZS_DELAY(); + rval |= 2; + } + + if ((cs_a->cs_softreq) || (cs_b->cs_softreq)) + { + /* This is a machine-dependent function. */ + zsc_req_softint(zsc); + } + + return (rval); +} + + +/* + * ZS software interrupt. Scan all channels for deferred interrupts. + */ +int +zsc_intr_soft(arg) + void *arg; +{ + register struct zsc_softc *zsc = arg; + register struct zs_chanstate *cs; + register int req, rval, s, unit; + + rval = 0; + for (unit = 0; unit < 2; unit++) { + cs = &zsc->zsc_cs[unit]; + + s = splzs(); + req = cs->cs_softreq; + cs->cs_softreq = 0; + splx(s); + + if (req) { + (*cs->cs_ops->zsop_softint)(cs); + rval = 1; + } + } + return (rval); +} + + +static int +zsnull_intr(cs) + struct zs_chanstate *cs; +{ + ZS_WRITE(cs, 1, 0); + ZS_WRITE(cs, 15, 0); +} + +static int +zsnull_softint(cs) + struct zs_chanstate *cs; +{ +} + +struct zsops zsops_null = { + zsnull_intr, /* receive char available */ + zsnull_intr, /* external/status */ + zsnull_intr, /* xmit buffer empty */ + zsnull_softint, /* process software interrupt */ +}; diff --git a/sys/dev/ic/z8530sc.h b/sys/dev/ic/z8530sc.h new file mode 100644 index 00000000000..57ec9c4dc91 --- /dev/null +++ b/sys/dev/ic/z8530sc.h @@ -0,0 +1,111 @@ +/* $NetBSD: z8530sc.h,v 1.1 1996/01/24 01:07:24 gwr Exp $ */ + +/* + * Copyright (c) 1994 Gordon W. Ross + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This software was developed by the Computer Systems Engineering group + * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and + * contributed to Berkeley. + * + * All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Lawrence Berkeley Laboratory. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)zsvar.h 8.1 (Berkeley) 6/11/93 + */ + + +/* + * Function vector - per channel + */ +struct zsops { + int (*zsop_rxint)(); /* receive char available */ + int (*zsop_stint)(); /* external/status */ + int (*zsop_txint)(); /* xmit buffer empty */ + int (*zsop_softint)(); /* process software interrupt */ +}; + +extern struct zsops zsops_null; + + +/* + * Software state, per zs channel. + */ +struct zs_chanstate { + + /* Pointers to the device registers. */ + volatile u_char *cs_reg_csr; /* ctrl, status, and reg. number. */ + volatile u_char *cs_reg_data; /* data or numbered register */ + + int cs_channel; /* sub-unit number */ + void *cs_private; /* sub-driver data pointer */ + struct zsops *cs_ops; + + int cs_pclk_div16; /* PCLK / 16 */ + int cs_defspeed; /* default baud rate (from PROM) */ + + /* + * We must keep a copy of the write registers as they are + * mostly write-only and we sometimes need to set and clear + * individual bits (e.g., in WR3). Not all of these are + * needed but 16 bytes is cheap and this makes the addressing + * simpler. Unfortunately, we can only write to some registers + * when the chip is not actually transmitting, so whenever + * we are expecting a `transmit done' interrupt the preg array + * is allowed to `get ahead' of the current values. In a + * few places we must change the current value of a register, + * rather than (or in addition to) the pending value; for these + * cs_creg[] contains the current value. + */ + u_char cs_creg[16]; /* current values */ + u_char cs_preg[16]; /* pending values */ + + u_char cs_heldchange; /* change pending (creg != preg) */ + u_char cs_rr0; /* last rr0 processed */ + + char cs_softreq; /* need soft interrupt call */ + char cs__spare; +}; + +struct zsc_softc { + struct device zsc_dev; /* required first: base device */ + struct zs_chanstate zsc_cs[2]; /* channel A and B soft state */ +}; + +struct zsc_attach_args { + int channel; /* two serial channels per zsc */ + int hwflags; +}; +#define ZS_HWFLAG_CONSOLE 1 + diff --git a/sys/dev/ic/z8530tty.c b/sys/dev/ic/z8530tty.c new file mode 100644 index 00000000000..276ceb0cd1c --- /dev/null +++ b/sys/dev/ic/z8530tty.c @@ -0,0 +1,1042 @@ +/* $NetBSD: z8530tty.c,v 1.1 1996/01/24 01:07:25 gwr Exp $ */ + +/* + * Copyright (c) 1994 Gordon W. Ross + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This software was developed by the Computer Systems Engineering group + * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and + * contributed to Berkeley. + * + * All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Lawrence Berkeley Laboratory. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)zs.c 8.1 (Berkeley) 7/19/93 + */ + +/* + * Zilog Z8530 Dual UART driver (tty interface) + * + * This is the "slave" driver that will be attached to + * the "zsc" driver for plain "tty" async. serial lines. + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/proc.h> +#include <sys/device.h> +#include <sys/conf.h> +#include <sys/file.h> +#include <sys/ioctl.h> +#include <sys/tty.h> +#include <sys/time.h> +#include <sys/kernel.h> +#include <sys/syslog.h> + +#include <dev/ic/z8530reg.h> +#include <machine/z8530var.h> + +#ifdef KGDB +extern int zs_check_kgdb(); +#endif + +/* + * Allow the MD var.h to override the default CFLAG so that + * console messages during boot come out with correct parity. + */ +#ifndef ZSTTY_DEF_CFLAG +#define ZSTTY_DEF_CFLAG TTYDEF_CFLAG +#endif + +/* + * How many input characters we can buffer. + * The port-specific var.h may override this. + * Note: must be a power of two! + */ +#ifndef ZSTTY_RING_SIZE +#define ZSTTY_RING_SIZE 1024 +#endif +#define ZSTTY_RING_MASK (ZSTTY_RING_SIZE-1) + +struct zstty_softc { + struct device zst_dev; /* required first: base device */ + struct tty *zst_tty; + struct zs_chanstate *zst_cs; + + int zst_hwflags; /* see z8530var.h */ + int zst_swflags; /* TIOCFLAG_SOFTCAR, ... <ttycom.h> */ + + /* Flags to communicate with zstty_softint() */ + volatile int zst_intr_flags; +#define INTR_RX_OVERRUN 1 +#define INTR_TX_EMPTY 2 +#define INTR_ST_CHECK 4 + + /* + * The transmit byte count and address are used for pseudo-DMA + * output in the hardware interrupt code. PDMA can be suspended + * to get pending changes done; heldtbc is used for this. It can + * also be stopped for ^S; this sets TS_TTSTOP in tp->t_state. + */ + int zst_tbc; /* transmit byte count */ + caddr_t zst_tba; /* transmit buffer address */ + int zst_heldtbc; /* held tbc while xmission stopped */ + + /* + * Printing an overrun error message often takes long enough to + * cause another overrun, so we only print one per second. + */ + long zst_rotime; /* time of last ring overrun */ + long zst_fotime; /* time of last fifo overrun */ + + /* + * The receive ring buffer. + */ + u_int zst_rbget; /* ring buffer `get' index */ + volatile u_int zst_rbput; /* ring buffer `put' index */ + u_short zst_rbuf[ZSTTY_RING_SIZE]; /* rr1, data pairs */ +}; + + +/* Definition of the driver for autoconfig. */ +static int zstty_match(struct device *, void *, void *); +static void zstty_attach(struct device *, struct device *, void *); + +struct cfdriver zsttycd = { + NULL, "zstty", zstty_match, zstty_attach, + DV_TTY, sizeof(struct zstty_softc), NULL, +}; + +struct zsops zsops_tty; + +/* Routines called from other code. */ +cdev_decl(zs); /* open, close, read, write, ioctl, stop, ... */ + +static void zsstart(struct tty *); +static int zsparam(struct tty *, struct termios *); +static void zs_modem(struct zstty_softc *zst, int onoff); + +/* + * zstty_match: how is this zs channel configured? + */ +int +zstty_match(parent, match, aux) + struct device *parent; + void *match, *aux; +{ + struct cfdata *cf = match; + struct zsc_attach_args *args = aux; + + /* Exact match is better than wildcard. */ + if (cf->cf_loc[0] == args->channel) + return 2; + + /* This driver accepts wildcard. */ + if (cf->cf_loc[0] == -1) + return 1; + + return 0; +} + +void +zstty_attach(parent, self, aux) + struct device *parent, *self; + void *aux; + +{ + struct zsc_softc *zsc = (void *) parent; + struct zstty_softc *zst = (void *) self; + struct zsc_attach_args *args = aux; + struct zs_chanstate *cs; + struct cfdata *cf; + struct tty *tp; + int channel, tty_unit; + dev_t dev; + + cf = zst->zst_dev.dv_cfdata; + tty_unit = cf->cf_unit; + channel = args->channel; + cs = &zsc->zsc_cs[channel]; + cs->cs_private = zst; + cs->cs_ops = &zsops_tty; + + zst->zst_cs = cs; + zst->zst_swflags = cf->cf_flags; /* softcar, etc. */ + zst->zst_hwflags = args->hwflags; + dev = makedev(ZSTTY_MAJOR, tty_unit); + + if (zst->zst_swflags) + printf(" flags 0x%x", zst->zst_swflags); + + if (zst->zst_hwflags & ZS_HWFLAG_CONSOLE) + printf(" (console)"); + else { +#ifdef KGDB + /* + * Allow kgdb to "take over" this port. If this port is + * NOT the kgdb port, zs_check_kgdb() will return zero. + * If it IS the kgdb port, it will print "kgdb,...\n" + * and then return non-zero. + */ + if (zs_check_kgdb(cs, dev)) { + /* + * This is the kgdb port (exclusive use) + * so skip the normal attach code. + */ + return; + } +#endif + } + printf("\n"); + + tp = zst->zst_tty = ttymalloc(); + tp->t_dev = dev; + tp->t_oproc = zsstart; + tp->t_param = zsparam; + tp->t_sc = zst; /* XXX - Quick access! */ + + /* + * Hardware init + */ + if (zst->zst_hwflags & ZS_HWFLAG_CONSOLE) { + /* This unit is the console. */ + zst->zst_swflags |= TIOCFLAG_SOFTCAR; + /* Call _param so interrupts get enabled. */ + cs->cs_defspeed = zs_getspeed(cs); + tp->t_ispeed = cs->cs_defspeed; + tp->t_ospeed = cs->cs_defspeed; + tp->t_cflag = ZSTTY_DEF_CFLAG; + (void) zsparam(tp, &tp->t_termios); + } else { + /* Not the console; may need reset. */ + int reset, s; + reset = (channel == 0) ? + ZSWR9_A_RESET : ZSWR9_B_RESET; + s = splzs(); + ZS_WRITE(cs, 9, reset); + splx(s); + } + + /* + * Initialize state of modem control lines (DTR). + * If softcar is set, turn on DTR now and leave it. + * otherwise, turn off DTR now, and raise in open. + * (Keeps modem from answering too early.) + */ + zs_modem(zst, (zst->zst_swflags & TIOCFLAG_SOFTCAR) ? 1 : 0); +} + + +/* + * Return pointer to our tty. + */ +struct tty * +zstty(dev) + dev_t dev; +{ + struct zstty_softc *zst; + int unit = minor(dev); + +#ifdef DIAGNOSTIC + if (unit >= zsttycd.cd_ndevs) + panic("zstty"); +#endif + zst = zsttycd.cd_devs[unit]; + return (zst->zst_tty); +} + + +/* + * Open a zs serial (tty) port. + */ +int +zsopen(dev, flags, mode, p) + dev_t dev; + int flags; + int mode; + struct proc *p; +{ + register struct tty *tp; + register struct zs_chanstate *cs; + struct zstty_softc *zst; + int error, s, unit; + + unit = minor(dev); + if (unit >= zsttycd.cd_ndevs) + return (ENXIO); + zst = zsttycd.cd_devs[unit]; + if (zst == NULL) + return (ENXIO); + tp = zst->zst_tty; + cs = zst->zst_cs; + + /* If KGDB took the line, then tp==NULL */ + if (tp == NULL) + return (EBUSY); + + /* It's simpler to do this up here. */ + if (((tp->t_state & (TS_ISOPEN | TS_XCLUDE)) + == (TS_ISOPEN | TS_XCLUDE)) + && (p->p_ucred->cr_uid != 0) ) + { + return (EBUSY); + } + + s = spltty(); + + if ((tp->t_state & TS_ISOPEN) == 0) { + /* First open. */ + ttychars(tp); + tp->t_iflag = TTYDEF_IFLAG; + tp->t_oflag = TTYDEF_OFLAG; + tp->t_cflag = ZSTTY_DEF_CFLAG; + if (zst->zst_swflags & TIOCFLAG_CLOCAL) + tp->t_cflag |= CLOCAL; + if (zst->zst_swflags & TIOCFLAG_CRTSCTS) + tp->t_cflag |= CRTSCTS; + if (zst->zst_swflags & TIOCFLAG_MDMBUF) + tp->t_cflag |= MDMBUF; + tp->t_lflag = TTYDEF_LFLAG; + tp->t_ispeed = tp->t_ospeed = cs->cs_defspeed; + (void) zsparam(tp, &tp->t_termios); + ttsetwater(tp); + /* Flush any pending input. */ + zst->zst_rbget = zst->zst_rbput; + zs_iflush(cs); /* XXX */ + /* Turn on DTR */ + zs_modem(zst, 1); + if (zst->zst_swflags & TIOCFLAG_SOFTCAR) { + tp->t_state |= TS_CARR_ON; + } + } + error = 0; + + /* Wait for carrier. */ + for (;;) { + register int rr0; + + /* Might never get status intr if carrier already on. */ + rr0 = *(cs->cs_reg_csr); + ZS_DELAY(); + if (rr0 & ZSRR0_DCD) { + tp->t_state |= TS_CARR_ON; + break; + } + + if ((tp->t_state & TS_CARR_ON) || + (tp->t_cflag & CLOCAL) || + (flags & O_NONBLOCK) ) + { + break; + } + + tp->t_state |= TS_WOPEN; + error = ttysleep(tp, (caddr_t)&tp->t_rawq, + TTIPRI | PCATCH, ttopen, 0); + if (error) { + if ((tp->t_state & TS_ISOPEN) == 0) { + /* Never get here with softcar */ + zs_modem(zst, 0); + tp->t_state &= ~TS_WOPEN; + ttwakeup(tp); + } + break; + } + } + + splx(s); + + if (error == 0) + error = linesw[tp->t_line].l_open(dev, tp); + + return (error); +} + +/* + * Close a zs serial port. + */ +int +zsclose(dev, flags, mode, p) + dev_t dev; + int flags; + int mode; + struct proc *p; +{ + struct zstty_softc *zst; + register struct zs_chanstate *cs; + register struct tty *tp; + struct zsinfo *zi; + int hup, s; + + zst = zsttycd.cd_devs[minor(dev)]; + cs = zst->zst_cs; + tp = zst->zst_tty; + + /* XXX This is for cons.c. */ + if ((tp->t_state & TS_ISOPEN) == 0) + return 0; + + (*linesw[tp->t_line].l_close)(tp, flags); + hup = tp->t_cflag & HUPCL; + if (zst->zst_swflags & TIOCFLAG_SOFTCAR) + hup = 0; + if (hup) { + zs_modem(zst, 0); + /* hold low for 1 second */ + (void) tsleep((caddr_t)cs, TTIPRI, ttclos, hz); + } + if (cs->cs_creg[5] & ZSWR5_BREAK) { + zs_break(cs, 0); + } + /* XXX - turn off interrupts? */ + + ttyclose(tp); + return (0); +} + +/* + * Read/write zs serial port. + */ +int +zsread(dev, uio, flags) + dev_t dev; + struct uio *uio; + int flags; +{ + register struct zstty_softc *zst; + register struct tty *tp; + + zst = zsttycd.cd_devs[minor(dev)]; + tp = zst->zst_tty; + return (linesw[tp->t_line].l_read(tp, uio, flags)); +} + +int +zswrite(dev, uio, flags) + dev_t dev; + struct uio *uio; + int flags; +{ + register struct zstty_softc *zst; + register struct tty *tp; + + zst = zsttycd.cd_devs[minor(dev)]; + tp = zst->zst_tty; + return (linesw[tp->t_line].l_write(tp, uio, flags)); +} + +#define TIOCFLAG_ALL (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | \ + TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF ) + +int +zsioctl(dev, cmd, data, flag, p) + dev_t dev; + u_long cmd; + caddr_t data; + int flag; + struct proc *p; +{ + register struct zstty_softc *zst; + register struct zs_chanstate *cs; + register struct tty *tp; + register int error, tmp; + + zst = zsttycd.cd_devs[minor(dev)]; + cs = zst->zst_cs; + tp = zst->zst_tty; + + error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); + if (error >= 0) + return (error); + error = ttioctl(tp, cmd, data, flag, p); + if (error >= 0) + return (error); + + switch (cmd) { + + case TIOCSBRK: + zs_break(cs, 1); + break; + + case TIOCCBRK: + zs_break(cs, 0); + break; + + case TIOCGFLAGS: + *(int *)data = zst->zst_swflags; + break; + + case TIOCSFLAGS: + error = suser(p->p_ucred, &p->p_acflag); + if (error != 0) + return (EPERM); + tmp = *(int *)data; + /* Check for random bits... */ + if (tmp & ~TIOCFLAG_ALL) + return(EINVAL); + /* Silently enforce softcar on the console. */ + if (zst->zst_hwflags & ZS_HWFLAG_CONSOLE) + tmp |= TIOCFLAG_SOFTCAR; + /* These flags take effect during open. */ + zst->zst_swflags = tmp; + break; + + case TIOCSDTR: + zs_modem(zst, 1); + break; + + case TIOCCDTR: + zs_modem(zst, 0); + break; + + case TIOCMSET: + case TIOCMBIS: + case TIOCMBIC: + case TIOCMGET: + default: + return (ENOTTY); + } + return (0); +} + +/* + * Start or restart transmission. + */ +static void +zsstart(tp) + register struct tty *tp; +{ + register struct zstty_softc *zst; + register struct zs_chanstate *cs; + register int s, nch; + + zst = tp->t_sc; + cs = zst->zst_cs; + + s = spltty(); + + /* + * If currently active or delaying, no need to do anything. + */ + if (tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) + goto out; + + /* + * If there are sleepers, and output has drained below low + * water mark, awaken. + */ + if (tp->t_outq.c_cc <= tp->t_lowat) { + if (tp->t_state & TS_ASLEEP) { + tp->t_state &= ~TS_ASLEEP; + wakeup((caddr_t)&tp->t_outq); + } + selwakeup(&tp->t_wsel); + } + + nch = ndqb(&tp->t_outq, 0); /* XXX */ + if (nch) { + register char *p = tp->t_outq.c_cf; + + /* mark busy, enable tx done interrupts, & send first byte */ + tp->t_state |= TS_BUSY; + (void) splzs(); + + cs->cs_preg[1] |= ZSWR1_TIE; + cs->cs_creg[1] |= ZSWR1_TIE; + ZS_WRITE(cs, 1, cs->cs_creg[1]); + *(cs->cs_reg_data) = *p; + ZS_DELAY(); + zst->zst_tba = p + 1; + zst->zst_tbc = nch - 1; + } else { + /* + * Nothing to send, turn off transmit done interrupts. + * This is useful if something is doing polled output. + */ + (void) splzs(); + cs->cs_preg[1] &= ~ZSWR1_TIE; + cs->cs_creg[1] &= ~ZSWR1_TIE; + ZS_WRITE(cs, 1, cs->cs_creg[1]); + } +out: + splx(s); +} + +/* + * Stop output, e.g., for ^S or output flush. + */ +int +zsstop(tp, flag) + struct tty *tp; + int flag; +{ + register struct zstty_softc *zst; + register struct zs_chanstate *cs; + register int s; + + zst = tp->t_sc; + cs = zst->zst_cs; + + s = splzs(); + if (tp->t_state & TS_BUSY) { + /* + * Device is transmitting; must stop it. + */ + zst->zst_tbc = 0; + if ((tp->t_state & TS_TTSTOP) == 0) + tp->t_state |= TS_FLUSH; + } + splx(s); + return (0); +} + +/* + * Set ZS tty parameters from termios. + * XXX - Should just copy the whole termios after + * making sure all the changes could be done. + * XXX - Only whack the UART when params change... + */ +static int +zsparam(tp, t) + register struct tty *tp; + register struct termios *t; +{ + register struct zstty_softc *zst; + register struct zs_chanstate *cs; + register int s, bps, cflag, tconst; + u_char tmp3, tmp4, tmp5, reset; + + zst = tp->t_sc; + cs = zst->zst_cs; + + /* + * Because PCLK is only run at 4.9 MHz, the fastest we + * can go is 51200 baud (this corresponds to TC=1). + * This is somewhat unfortunate as there is no real + * reason we should not be able to handle higher rates. + */ + bps = t->c_ospeed; + if (bps < 0 || (t->c_ispeed && t->c_ispeed != bps)) + return (EINVAL); + if (bps == 0) { + /* stty 0 => drop DTR and RTS */ + zs_modem(zst, 0); + return (0); + } + tconst = BPS_TO_TCONST(cs->cs_pclk_div16, bps); + if (tconst < 0) + return (EINVAL); + + /* Convert back to make sure we can do it. */ + bps = TCONST_TO_BPS(cs->cs_pclk_div16, tconst); + if (bps != t->c_ospeed) + return (EINVAL); + tp->t_ispeed = tp->t_ospeed = bps; + + cflag = t->c_cflag; + tp->t_cflag = cflag; + + /* + * Block interrupts so that state will not + * be altered until we are done setting it up. + */ + s = splzs(); + + /* + * Initial values in cs_preg are set before + * our attach routine is called. The master + * interrupt enable is handled by zsc.c + */ + + cs->cs_preg[12] = tconst; + cs->cs_preg[13] = tconst >> 8; + + switch (cflag & CSIZE) { + case CS5: + tmp3 = ZSWR3_RX_5; + tmp5 = ZSWR5_TX_5; + break; + case CS6: + tmp3 = ZSWR3_RX_6; + tmp5 = ZSWR5_TX_6; + break; + case CS7: + tmp3 = ZSWR3_RX_7; + tmp5 = ZSWR5_TX_7; + break; + case CS8: + default: + tmp3 = ZSWR3_RX_8; + tmp5 = ZSWR5_TX_8; + break; + } + + /* + * Output hardware flow control on the chip is horrendous: if + * carrier detect drops, the receiver is disabled. Hence we + * can only do this when the carrier is on. + */ + tmp3 |= ZSWR3_RX_ENABLE; + if (cflag & CCTS_OFLOW) { + if (*(cs->cs_reg_csr) & ZSRR0_DCD) + tmp3 |= ZSWR3_HFC; + ZS_DELAY(); + } + + cs->cs_preg[3] = tmp3; + cs->cs_preg[5] = tmp5 | ZSWR5_TX_ENABLE | ZSWR5_DTR | ZSWR5_RTS; + + tmp4 = ZSWR4_CLK_X16 | (cflag & CSTOPB ? ZSWR4_TWOSB : ZSWR4_ONESB); + if ((cflag & PARODD) == 0) + tmp4 |= ZSWR4_EVENP; + if (cflag & PARENB) + tmp4 |= ZSWR4_PARENB; + cs->cs_preg[4] = tmp4; + + /* + * If nothing is being transmitted, set up new current values, + * else mark them as pending. + */ + if (cs->cs_heldchange == 0) { + if (tp->t_state & TS_BUSY) { + zst->zst_heldtbc = zst->zst_tbc; + zst->zst_tbc = 0; + cs->cs_heldchange = 1; + } else { + zs_loadchannelregs(cs); + } + } + splx(s); + return (0); +} + +/* + * Raise or lower modem control (DTR/RTS) signals. If a character is + * in transmission, the change is deferred. + */ +static void +zs_modem(zst, onoff) + struct zstty_softc *zst; + int onoff; +{ + struct zs_chanstate *cs; + struct tty *tp; + int s, bis, and; + + cs = zst->zst_cs; + tp = zst->zst_tty; + + if (onoff) { + bis = ZSWR5_DTR | ZSWR5_RTS; + and = ~0; + } else { + bis = 0; + and = ~(ZSWR5_DTR | ZSWR5_RTS); + } + s = splzs(); + cs->cs_preg[5] = (cs->cs_preg[5] | bis) & and; + if (cs->cs_heldchange == 0) { + if (tp->t_state & TS_BUSY) { + zst->zst_heldtbc = zst->zst_tbc; + zst->zst_tbc = 0; + cs->cs_heldchange = 1; + } else { + cs->cs_creg[5] = (cs->cs_creg[5] | bis) & and; + ZS_WRITE(cs, 5, cs->cs_creg[5]); + } + } + splx(s); +} + + +/**************************************************************** + * Interface to the lower layer (zscc) + ****************************************************************/ + +static int +zstty_rxint(cs) + register struct zs_chanstate *cs; +{ + register struct zstty_softc *zst; + register put, put_next; + register u_char c, rr0, rr1; + + zst = cs->cs_private; + put = zst->zst_rbput; + +nextchar: + /* Read the input data ASAP. */ + c = *(cs->cs_reg_data); + ZS_DELAY(); + + /* Save the status register too. */ + rr1 = ZS_READ(cs, 1); + + if (rr1 & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE)) { + /* Clear the receive error. */ + *(cs->cs_reg_csr) = ZSWR0_RESET_ERRORS; + ZS_DELAY(); + } + + zst->zst_rbuf[put] = (c << 8) | rr1; + put_next = (put + 1) & ZSTTY_RING_MASK; + + /* Would overrun if increment makes (put==get). */ + if (put_next == zst->zst_rbget) { + zst->zst_intr_flags |= INTR_RX_OVERRUN; + } else { + /* OK, really increment. */ + put = put_next; + } + + /* Keep reading until the FIFO is empty. */ + rr0 = *(cs->cs_reg_csr); + ZS_DELAY(); + if (rr0 & ZSRR0_RX_READY) + goto nextchar; + + /* Done reading. */ + zst->zst_rbput = put; + + /* Ask for softint() call. */ + cs->cs_softreq = 1; + return(1); +} + +static int +zstty_txint(cs) + register struct zs_chanstate *cs; +{ + register struct zstty_softc *zst; + register int count, rval; + + zst = cs->cs_private; + count = zst->zst_tbc; + + if (count > 0) { + /* Send the next char. */ + *(cs->cs_reg_data) = *zst->zst_tba++; + ZS_DELAY(); + zst->zst_tbc = --count; + rval = 0; + } else { + /* Nothing more to send. */ + *(cs->cs_reg_csr) = ZSWR0_RESET_TXINT; + ZS_DELAY(); + zst->zst_intr_flags |= INTR_TX_EMPTY; + rval = 1; /* want softcall */ + } + + cs->cs_softreq = rval; + return (rval); +} + +static int +zstty_stint(cs) + register struct zs_chanstate *cs; +{ + register struct zstty_softc *zst; + register int rr0; + + zst = cs->cs_private; + + rr0 = *(cs->cs_reg_csr); + ZS_DELAY(); + + *(cs->cs_reg_csr) = ZSWR0_RESET_STATUS; + ZS_DELAY(); + + if ((rr0 & ZSRR0_BREAK) && + (zst->zst_hwflags & ZS_HWFLAG_CONSOLE)) + { + zs_abort(); + return (0); + } + + zst->zst_intr_flags |= INTR_ST_CHECK; + /* Ask for softint() call. */ + cs->cs_softreq = 1; + return (1); +} + +/* + * Print out a ring or fifo overrun error message. + */ +static void +zsoverrun(zst, ptime, what) + struct zstty_softc *zst; + long *ptime; + char *what; +{ + + if (*ptime != time.tv_sec) { + *ptime = time.tv_sec; + log(LOG_WARNING, "%s: %s overrun\n", + zst->zst_dev.dv_xname, what); + } +} + +static int +zstty_softint(cs) + struct zs_chanstate *cs; +{ + register struct zstty_softc *zst; + register struct linesw *line; + register struct tty *tp; + register int get, c, s; + int intr_flags; + register u_short ring_data; + register u_char rr0, rr1; + + zst = cs->cs_private; + tp = zst->zst_tty; + line = &linesw[tp->t_line]; + + /* Atomically get and clear flags. */ + s = splzs(); + intr_flags = zst->zst_intr_flags; + zst->zst_intr_flags = 0; + splx(s); + + if (intr_flags & INTR_RX_OVERRUN) { + /* May turn this on again below. */ + intr_flags &= ~INTR_RX_OVERRUN; + zsoverrun(zst, "ring"); + } + + /* + * Copy data from the receive ring into the tty layer. + */ + get = zst->zst_rbget; + while (get != zst->zst_rbput) { + ring_data = zst->zst_rbuf[get]; + get = (get + 1) & ZSTTY_RING_MASK; + + if (ring_data & ZSRR1_DO) + intr_flags |= INTR_RX_OVERRUN; + /* low byte of ring_data is rr1 */ + c = (ring_data >> 8) & 0xff; + if (ring_data & ZSRR1_FE) + c |= TTY_FE; + if (ring_data & ZSRR1_PE) + c |= TTY_PE; + + line->l_rint(c, tp); + } + zst->zst_rbget = get; + + /* If set, it is from the loop above. */ + if (intr_flags & INTR_RX_OVERRUN) { + zsoverrun(zst, "fifo"); + } + + if (intr_flags & INTR_TX_EMPTY) { + /* + * Transmit done. Change registers and resume, + * or just clear BUSY. + */ + if (cs->cs_heldchange) { + s = splzs(); + rr0 = *(cs->cs_reg_csr); + ZS_DELAY(); + if ((rr0 & ZSRR0_DCD) == 0) + cs->cs_preg[3] &= ~ZSWR3_HFC; + zs_loadchannelregs(cs); + splx(s); + cs->cs_heldchange = 0; + + if (zst->zst_heldtbc && + (tp->t_state & TS_TTSTOP) == 0) + { + zst->zst_tbc = zst->zst_heldtbc - 1; + *(cs->cs_reg_data) = *zst->zst_tba++; + ZS_DELAY(); + goto tx_resumed; + } + } + tp->t_state &= ~TS_BUSY; + if (tp->t_state & TS_FLUSH) + tp->t_state &= ~TS_FLUSH; + else + ndflush(&tp->t_outq, zst->zst_tba - + (caddr_t) tp->t_outq.c_cf); + line->l_start(tp); + tx_resumed: + } + + if (intr_flags & INTR_ST_CHECK) { + /* + * Status line change. + * + * The chip's hardware flow control is, as noted in zsreg.h, + * busted---if the DCD line goes low the chip shuts off the + * receiver (!). If we want hardware CTS flow control but do + * not have it, and carrier is now on, turn HFC on; if we have + * HFC now but carrier has gone low, turn it off. + */ + s = splzs(); + rr0 = *(cs->cs_reg_csr); + if (rr0 & ZSRR0_DCD) { + if (tp->t_cflag & CCTS_OFLOW && + (cs->cs_creg[3] & ZSWR3_HFC) == 0) { + cs->cs_creg[3] |= ZSWR3_HFC; + ZS_WRITE(cs, 3, cs->cs_creg[3]); + } + } else { + if (cs->cs_creg[3] & ZSWR3_HFC) { + cs->cs_creg[3] &= ~ZSWR3_HFC; + ZS_WRITE(cs, 3, cs->cs_creg[3]); + } + } + splx(s); + + /* Was there a change on DCD? */ + if ((rr0 ^ cs->cs_rr0) & ZSRR0_DCD) { + c = ((rr0 & ZSRR0_DCD) != 0); + if (line->l_modem(tp, c) == 0) + zs_modem(zst, c); + } + cs->cs_rr0 = rr0; + } + + return (1); +} + +struct zsops zsops_tty = { + zstty_rxint, /* receive char available */ + zstty_stint, /* external/status */ + zstty_txint, /* xmit buffer empty */ + zstty_softint, /* process software interrupt */ +}; + |