diff options
Diffstat (limited to 'sys/dev/ic')
| -rw-r--r-- | sys/dev/ic/aic7xxx.c | 9089 | ||||
| -rw-r--r-- | sys/dev/ic/aic7xxx.h | 1218 | ||||
| -rw-r--r-- | sys/dev/ic/aic7xxx_inline.h | 561 | ||||
| -rw-r--r-- | sys/dev/ic/aic7xxx_openbsd.c | 1732 | ||||
| -rw-r--r-- | sys/dev/ic/aic7xxx_openbsd.h | 837 | ||||
| -rw-r--r-- | sys/dev/ic/aic7xxxreg.h | 276 | ||||
| -rw-r--r-- | sys/dev/ic/smc93cx6.c | 30 | ||||
| -rw-r--r-- | sys/dev/ic/smc93cx6var.h | 21 |
8 files changed, 9643 insertions, 4121 deletions
diff --git a/sys/dev/ic/aic7xxx.c b/sys/dev/ic/aic7xxx.c index 428be419620..ff610c24f37 100644 --- a/sys/dev/ic/aic7xxx.c +++ b/sys/dev/ic/aic7xxx.c @@ -1,11 +1,7 @@ /* - * Generic driver for the aic7xxx based adaptec SCSI controllers - * Product specific probe and attach routines can be found in: - * i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers - * pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890, - * aic7880, aic7870, aic7860, and aic7850 controllers + * Core routines and tables shareable across OS platforms. * - * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. + * Copyright (c) 1994-2001 Justin T. Gibbs. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -18,7 +14,7 @@ * derived from this software without specific prior written permission. * * Alternatively, this software may be distributed under the terms of the - * the GNU Public License ("GPL"). + * GNU Public License ("GPL"). * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE @@ -32,766 +28,54 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.40 2000/01/07 23:08:17 gibbs Exp $ - * $OpenBSD: aic7xxx.c,v 1.39 2002/06/14 21:34:59 todd Exp $ - */ -/* - * A few notes on features of the driver. - * - * SCB paging takes advantage of the fact that devices stay disconnected - * from the bus a relatively long time and that while they're disconnected, - * having the SCBs for these transactions down on the host adapter is of - * little use. Instead of leaving this idle SCB down on the card we copy - * it back up into kernel memory and reuse the SCB slot on the card to - * schedule another transaction. This can be a real payoff when doing random - * I/O to tagged queueing devices since there are more transactions active at - * once for the device to sort for optimal seek reduction. The algorithm goes - * like this... - * - * The sequencer maintains two lists of its hardware SCBs. The first is the - * singly linked free list which tracks all SCBs that are not currently in - * use. The second is the doubly linked disconnected list which holds the - * SCBs of transactions that are in the disconnected state sorted most - * recently disconnected first. When the kernel queues a transaction to - * the card, a hardware SCB to "house" this transaction is retrieved from - * either of these two lists. If the SCB came from the disconnected list, - * a check is made to see if any data transfer or SCB linking (more on linking - * in a bit) information has been changed since it was copied from the host - * and if so, DMAs the SCB back up before it can be used. Once a hardware - * SCB has been obtained, the SCB is DMAed from the host. Before any work - * can begin on this SCB, the sequencer must ensure that either the SCB is - * for a tagged transaction or the target is not already working on another - * non-tagged transaction. If a conflict arises in the non-tagged case, the - * sequencer finds the SCB for the active transactions and sets the SCB_LINKED - * field in that SCB to this next SCB to execute. To facilitate finding - * active non-tagged SCBs, the last four bytes of up to the first four hardware - * SCBs serve as a storage area for the currently active SCB ID for each - * target. - * - * When a device reconnects, a search is made of the hardware SCBs to find - * the SCB for this transaction. If the search fails, a hardware SCB is - * pulled from either the free or disconnected SCB list and the proper - * SCB is DMAed from the host. If the MK_MESSAGE control bit is set - * in the control byte of the SCB while it was disconnected, the sequencer - * will assert ATN and attempt to issue a message to the host. - * - * When a command completes, a check for non-zero status and residuals is - * made. If either of these conditions exists, the SCB is DMAed back up to - * the host so that it can interpret this information. Additionally, in the - * case of bad status, the sequencer generates a special interrupt and pauses - * itself. This allows the host to setup a request sense command if it - * chooses for this target synchronously with the error so that sense - * information isn't lost. + * $Id: aic7xxx.c,v 1.40 2002/06/28 00:34:54 smurph Exp $ * + * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.80 2001/12/16 17:38:30 gibbs Exp $ + * $OpenBSD: aic7xxx.c,v 1.40 2002/06/28 00:34:54 smurph Exp $ */ -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/device.h> -#include <machine/bus.h> -#include <machine/intr.h> - -#include <sys/malloc.h> -#include <sys/buf.h> -#include <sys/proc.h> - -#include <scsi/scsi_all.h> -#include <scsi/scsi_message.h> -#include <scsi/scsi_debug.h> -#include <scsi/scsiconf.h> - -#include <uvm/uvm_extern.h> - -#include <dev/ic/aic7xxxreg.h> -#include <dev/ic/aic7xxxvar.h> -#include <dev/microcode/aic7xxx/aic7xxx_seq.h> +#ifdef __OpenBSD__ +#include <dev/ic/aic7xxx_openbsd.h> +#include <dev/ic/aic7xxx_inline.h> #include <dev/microcode/aic7xxx/sequencer.h> -#include "pci.h" - -/* - * Some ISA devices (e.g. on a VLB) can perform 32-bit DMA. This - * flag is passed to bus_dmamap_create() to indicate that fact. - */ -#ifndef ISABUS_DMA_32BIT -#define ISABUS_DMA_32BIT BUS_DMA_BUS1 -#endif - -#ifndef AHC_TMODE_ENABLE -#define AHC_TMODE_ENABLE 0 -#endif -#include <sys/kernel.h> - -#ifndef le32toh -#define le32toh letoh32 /* to match Free/Net macros */ #endif - -#define IS_SCSIBUS_B(ahc, sc_link) \ - ((sc_link)->scsibus == (ahc)->sc_link_b.scsibus) -#define ALL_CHANNELS '\0' -#define ALL_TARGETS_MASK 0xFFFF -#define INITIATOR_WILDCARD (~0) - -#define SIM_IS_SCSIBUS_B(ahc, sc_link) \ - ((sc_link)->scsibus == (ahc)->sc_link_b.scsibus) -#define SIM_CHANNEL(ahc, sc_link) \ - (SIM_IS_SCSIBUS_B(ahc, sc_link) ? 'B' : 'A') -#define SIM_SCSI_ID(ahc, sc_link) \ - (SIM_IS_SCSIBUS_B(ahc, sc_link) ? ahc->our_id_b : ahc->our_id) -#define SCB_IS_SCSIBUS_B(scb) \ - (((scb)->hscb->tcl & SELBUSB) != 0) -#define SCB_TARGET(scb) \ - (((scb)->hscb->tcl & TID) >> 4) -#define SCB_CHANNEL(scb) \ - (SCB_IS_SCSIBUS_B(scb) ? 'B' : 'A') -#define SCB_LUN(scb) \ - ((scb)->hscb->tcl & LID) -#define SCB_TARGET_OFFSET(scb) \ - (SCB_TARGET(scb) + (SCB_IS_SCSIBUS_B(scb) ? 8 : 0)) -#define SCB_TARGET_MASK(scb) \ - (0x01 << (SCB_TARGET_OFFSET(scb))) -#define TCL_CHANNEL(ahc, tcl) \ - ((((ahc)->features & AHC_TWIN) && ((tcl) & SELBUSB)) ? 'B' : 'A') -#define TCL_SCSI_ID(ahc, tcl) \ - (TCL_CHANNEL((ahc), (tcl)) == 'B' ? (ahc)->our_id_b : (ahc)->our_id) -#define TCL_TARGET(tcl) (((tcl) & TID) >> TCL_TARGET_SHIFT) -#define TCL_LUN(tcl) ((tcl) & LID) - -#define XS_TCL(ahc, xs) \ - ((((xs)->sc_link->target << 4) & 0xF0) \ - | (SIM_IS_SCSIBUS_B((ahc), (xs)->sc_link) ? SELBUSB : 0) \ - | ((xs)->sc_link->lun & 0x07)) - -/* - * Under normal circumstances, these messages are unnecessary - * and not terribly cosmetic. - */ -#ifdef DEBUG -#define bootverbose 1 -#define STATIC -#define INLINE -#else -#define bootverbose 0 -#define STATIC static -#define INLINE __inline +#ifdef __FreeBSD__ +#include <dev/aic7xxx/aic7xxx_freebsd.h> +#include <dev/aic7xxx/aic7xxx_inline.h> +#include <dev/aic7xxx/aicasm/aicasm_insformat.h> #endif +/****************************** Softc Data ************************************/ +struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq); -typedef enum { - ROLE_UNKNOWN, - ROLE_INITIATOR, - ROLE_TARGET -} role_t; - -struct ahc_devinfo { - int our_scsiid; - int target_offset; - u_int16_t target_mask; - u_int8_t target; - u_int8_t lun; - char channel; - role_t role; /* - * Only guaranteed to be correct if not - * in the busfree state. - */ -}; - -typedef enum { - SEARCH_COMPLETE, - SEARCH_COUNT, - SEARCH_REMOVE -} ahc_search_action; - -#ifdef AHC_DEBUG -static int ahc_debug = AHC_DEBUG; -#endif - -#if NPCI > 0 -void ahc_pci_intr(struct ahc_softc *ahc); -#endif - -STATIC int ahcinitscbdata(struct ahc_softc *ahc); -STATIC void ahcfiniscbdata(struct ahc_softc *ahc); - -STATIC int ahc_poll(struct ahc_softc *ahc, int wait); -STATIC void ahc_shutdown(void *arg); -STATIC int ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, - int nsegments); -STATIC int ahc_setup_data(struct ahc_softc *ahc, struct scsi_xfer *xs, - struct scb *scb); -STATIC void ahc_freeze_devq(struct ahc_softc *ahc, - struct scsi_link *sc_link); -STATIC void ahcallocscbs(struct ahc_softc *ahc); -STATIC void ahc_fetch_devinfo(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo); -STATIC void ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, - u_int target, u_int lun, char channel, role_t role); -STATIC u_int ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev); -STATIC void ahc_done(struct ahc_softc *ahc, struct scb *scbp); -STATIC struct tmode_tstate * - ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, - char channel); -STATIC void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); -STATIC void ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat); -STATIC void ahc_build_transfer_msg(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo); -STATIC void ahc_setup_initiator_msgout(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo, struct scb *scb); -STATIC void ahc_setup_target_msgin(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo); -STATIC int ahc_handle_msg_reject(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo); -STATIC void ahc_clear_msg_state(struct ahc_softc *ahc); -STATIC void ahc_handle_message_phase(struct ahc_softc *ahc, - struct scsi_link *sc_link); -STATIC int ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full); - -typedef enum { - MSGLOOP_IN_PROG, - MSGLOOP_MSGCOMPLETE, - MSGLOOP_TERMINATED -} msg_loop_stat; - -STATIC int ahc_parse_msg(struct ahc_softc *ahc, struct scsi_link *sc_link, - struct ahc_devinfo *devinfo); -STATIC void ahc_handle_ign_wide_residue(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo); -STATIC void ahc_handle_devreset(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo, int status, char *message, - int verbose_level); -#ifdef AHC_DUMP_SEQ -STATIC void ahc_dumpseq(struct ahc_softc *ahc); -#endif -STATIC void ahc_loadseq(struct ahc_softc *ahc); -STATIC int ahc_check_patch(struct ahc_softc *ahc, - struct patch **start_patch, int start_instr, - int *skip_addr); -STATIC void ahc_download_instr(struct ahc_softc *ahc, int instrptr, - u_int8_t *dconsts); -STATIC int ahc_match_scb(struct scb *scb, int target, char channel, - int lun, u_int tag, role_t role); -#ifdef AHC_DEBUG -STATIC void ahc_print_scb(struct scb *scb); -#endif -STATIC int ahc_search_qinfifo(struct ahc_softc *ahc, int target, - char channel, int lun, u_int tag, role_t role, - u_int32_t status, ahc_search_action action); -STATIC int ahc_reset_channel(struct ahc_softc *ahc, char channel, - int initiate_reset); -STATIC int ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, - int lun, u_int tag, role_t role, u_int32_t status); -STATIC int ahc_search_disc_list(struct ahc_softc *ahc, int target, - char channel, int lun, u_int tag, int stop_on_first, - int remove, int save_state); -STATIC u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, - u_int scbptr); -STATIC void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); -STATIC void ahc_clear_intstat(struct ahc_softc *ahc); -STATIC void ahc_reset_current_bus(struct ahc_softc *ahc); -STATIC struct ahc_syncrate * - ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period); -STATIC struct ahc_syncrate * - ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, - u_int maxsync); -STATIC u_int ahc_find_period(struct ahc_softc *ahc, u_int scsirate, - u_int maxsync); -STATIC void ahc_validate_offset(struct ahc_softc *ahc, - struct ahc_syncrate *syncrate, - u_int *offset, int wide); -STATIC void ahc_update_target_msg_request(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo, - struct ahc_initiator_tinfo *tinfo, int force, int paused); -STATIC void ahc_set_syncrate(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo, struct ahc_syncrate *syncrate, - u_int period, u_int offset, u_int type, int paused, - int done); -STATIC void ahc_set_width(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo, u_int width, u_int type, - int paused, int done); -STATIC void ahc_set_tags(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo,int enable); -STATIC int ahc_istagged_device(struct ahc_softc *ahc, - struct scsi_xfer *xs, int nocmdcheck); -STATIC void ahc_check_tags(struct ahc_softc *ahc, struct scsi_xfer *xs); -STATIC void ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, - u_int offset); -STATIC void ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width); - -STATIC void ahc_calc_residual(struct scb *scb); - -STATIC void ahc_update_pending_syncrates(struct ahc_softc *ahc); - -STATIC void ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb); -STATIC void ahc_timeout(void *); - -static __inline int sequencer_paused(struct ahc_softc *ahc); -static __inline void pause_sequencer(struct ahc_softc *ahc); -static __inline void unpause_sequencer(struct ahc_softc *ahc); -STATIC void restart_sequencer(struct ahc_softc *ahc); -static __inline u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl, - int unbusy); - -static __inline void ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb); -static __inline int ahc_isbusy_tcl(struct ahc_softc *ahc, struct scb *scb); -static __inline void ahc_freeze_ccb(struct scb* scb); -static __inline void ahcsetccbstatus(struct scsi_xfer *xs, int status); -STATIC void ahc_run_qoutfifo(struct ahc_softc *ahc); - -static __inline struct ahc_initiator_tinfo * - ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, - u_int target, struct tmode_tstate **tstate); -STATIC void ahcfreescb(struct ahc_softc *ahc, struct scb *scb); -static __inline struct scb *ahcgetscb(struct ahc_softc *ahc); -int ahc_createdmamem(struct ahc_softc *ahc, int size, bus_dmamap_t *mapp, - caddr_t *vaddr, bus_addr_t *baddr, bus_dma_segment_t *segs, - int *nseg, const char *what); -STATIC void ahc_freedmamem(bus_dma_tag_t tag, int size, bus_dmamap_t map, - caddr_t vaddr, bus_dma_segment_t *seg, int nseg); -STATIC void ahcminphys(struct buf *bp); - -STATIC INLINE struct scsi_xfer *ahc_first_xs(struct ahc_softc *); -STATIC INLINE void ahc_list_insert_before(struct ahc_softc *ahc, - struct scsi_xfer *xs, struct scsi_xfer *next_xs); -STATIC INLINE void ahc_list_insert_head(struct ahc_softc *ahc, - struct scsi_xfer *xs); -STATIC INLINE void ahc_list_insert_tail(struct ahc_softc *ahc, - struct scsi_xfer *xs); -STATIC INLINE void ahc_list_remove(struct ahc_softc *ahc, - struct scsi_xfer *xs); -STATIC INLINE struct scsi_xfer *ahc_list_next(struct ahc_softc *ahc, - struct scsi_xfer *xs); -STATIC int32_t ahc_scsi_cmd(struct scsi_xfer *xs); -static __inline void ahc_swap_hscb(struct hardware_scb *); -static __inline void ahc_swap_sg(struct ahc_dma_seg *); - -struct cfdriver ahc_cd = { - NULL, "ahc", DV_DULL -}; - -static struct scsi_adapter ahc_switch = +/***************************** Lookup Tables **********************************/ +char *ahc_chip_names[] = { - ahc_scsi_cmd, - ahcminphys, - 0, - 0, + "NONE", + "aic7770", + "aic7850", + "aic7855", + "aic7859", + "aic7860", + "aic7870", + "aic7880", + "aic7895", + "aic7895C", + "aic7890/91", + "aic7896/97", + "aic7892", + "aic7899" }; - -/* the below structure is so we have a default dev struct for our link struct */ -static struct scsi_device ahc_dev = -{ - NULL, /* Use default error handler */ - NULL, /* have a queue, served by this */ - NULL, /* have no async handler */ - NULL, /* Use default 'done' routine */ -}; - -static __inline void -ahc_swap_hscb(struct hardware_scb *hscb) -{ - hscb->SG_pointer = htole32(hscb->SG_pointer); - hscb->data = htole32(hscb->data); - hscb->datalen = htole32(hscb->datalen); - /* - * No need to swap cmdpointer; it's either 0 or set to - * cmdstore_busaddr, which is already swapped. - */ -} - -static __inline void -ahc_swap_sg(struct ahc_dma_seg *sg) -{ - sg->addr = htole32(sg->addr); - sg->len = htole32(sg->len); -} - -STATIC void -ahcminphys(bp) - struct buf *bp; -{ -/* - * Even though the card can transfer up to 16megs per command - * we are limited by the number of segments in the dma segment - * list that we can hold. The worst case is that all pages are - * discontinuous physically, hense the "page per segment" limit - * enforced here. - */ - if (bp->b_bcount > ((AHC_NSEG - 1) * PAGE_SIZE)) { - bp->b_bcount = ((AHC_NSEG - 1) * PAGE_SIZE); - } - minphys(bp); -} - - -static __inline u_int32_t -ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) -{ - return (ahc->scb_data->hscb_busaddr - + (sizeof(struct hardware_scb) * index)); -} - -#define AHC_BUSRESET_DELAY 25 /* Reset delay in us */ - -static __inline int -sequencer_paused(ahc) - struct ahc_softc *ahc; -{ - return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); -} - -static __inline void -pause_sequencer(ahc) - struct ahc_softc *ahc; -{ - ahc_outb(ahc, HCNTRL, ahc->pause); - - /* - * Since the sequencer can disable pausing in a critical section, we - * must loop until it actually stops. - */ - while (sequencer_paused(ahc) == 0) - ; -} - -static __inline void -unpause_sequencer(ahc) - struct ahc_softc *ahc; -{ - if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) - ahc_outb(ahc, HCNTRL, ahc->unpause); -} - -/* - * Restart the sequencer program from address zero - */ -STATIC void -restart_sequencer(ahc) - struct ahc_softc *ahc; -{ - u_int i; - - pause_sequencer(ahc); - - /* - * Everytime we restart the sequencer, there - * is the possiblitity that we have restarted - * within a three instruction window where an - * SCB has been marked free but has not made it - * onto the free list. Since SCSI events(bus reset, - * unexpected bus free) will always freeze the - * sequencer, we cannot close this window. To - * avoid losing an SCB, we reconsitute the free - * list every time we restart the sequencer. - */ - ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); - for (i = 0; i < ahc->scb_data->maxhscbs; i++) { - - ahc_outb(ahc, SCBPTR, i); - if (ahc_inb(ahc, SCB_TAG) == SCB_LIST_NULL) - ahc_add_curscb_to_free_list(ahc); - } - ahc_outb(ahc, SEQCTL, FASTMODE|SEQRESET); - unpause_sequencer(ahc); -} - -static __inline u_int -ahc_index_busy_tcl(ahc, tcl, unbusy) - struct ahc_softc *ahc; - u_int tcl; - int unbusy; -{ - u_int scbid; - - scbid = ahc->untagged_scbs[tcl]; - if (unbusy) { - ahc->untagged_scbs[tcl] = SCB_LIST_NULL; - bus_dmamap_sync(ahc->sc_dmat, ahc->shared_data_dmamap, - UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); - } - - return (scbid); -} - -static __inline void -ahc_busy_tcl(ahc, scb) - struct ahc_softc *ahc; - struct scb *scb; -{ - ahc->untagged_scbs[scb->hscb->tcl] = scb->hscb->tag; - bus_dmamap_sync(ahc->sc_dmat, ahc->shared_data_dmamap, - UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); -} - -static __inline int -ahc_isbusy_tcl(ahc, scb) - struct ahc_softc *ahc; - struct scb *scb; -{ - return ahc->untagged_scbs[scb->hscb->tcl] != SCB_LIST_NULL; -} - -static __inline void -ahc_freeze_ccb(scb) - struct scb *scb; -{ - struct scsi_xfer *xs = scb->xs; - struct ahc_softc *ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; - int target; - - target = xs->sc_link->target; - if (!(scb->flags & SCB_FREEZE_QUEUE)) { - ahc->devqueue_blocked[target]++; - scb->flags |= SCB_FREEZE_QUEUE; - } -} - -static __inline void -ahcsetccbstatus(xs, status) - struct scsi_xfer *xs; - int status; -{ - xs->error = status; -} - -static __inline struct ahc_initiator_tinfo * -ahc_fetch_transinfo(ahc, channel, our_id, remote_id, tstate) - struct ahc_softc *ahc; - char channel; - u_int our_id; - u_int remote_id; - struct tmode_tstate **tstate; -{ - /* - * Transfer data structures are stored from the perspective - * of the target role. Since the parameters for a connection - * in the initiator role to a given target are the same as - * when the roles are reversed, we pretend we are the target. - */ - if (channel == 'B') - our_id += 8; - *tstate = ahc->enabled_targets[our_id]; - return (&(*tstate)->transinfo[remote_id]); -} - -STATIC void -ahc_run_qoutfifo(ahc) - struct ahc_softc *ahc; -{ - struct scb *scb; - u_int scb_index; - - bus_dmamap_sync(ahc->sc_dmat, ahc->shared_data_dmamap, - 0, 256, BUS_DMASYNC_POSTREAD); - - while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { - scb_index = ahc->qoutfifo[ahc->qoutfifonext]; - ahc->qoutfifo[ahc->qoutfifonext++] = SCB_LIST_NULL; - - scb = &ahc->scb_data->scbarray[scb_index]; - if (scb_index >= ahc->scb_data->numscbs - || (scb->flags & SCB_ACTIVE) == 0) { - printf("%s: WARNING no command for scb %d " - "(cmdcmplt)\nQOUTPOS = %d\n", - ahc_name(ahc), scb_index, - ahc->qoutfifonext - 1); - continue; - } - - /* - * Save off the residual - * if there is one. - */ - if (scb->hscb->residual_SG_count != 0) - ahc_calc_residual(scb); - else - scb->xs->resid = 0; - ahc_done(ahc, scb); - } -} - - -/* - * An scb (and hence an scb entry on the board) is put onto the - * free list. - */ -STATIC void -ahcfreescb(ahc, scb) - struct ahc_softc *ahc; - struct scb *scb; -{ - struct hardware_scb *hscb; - int opri; - - hscb = scb->hscb; - -#ifdef AHC_DEBUG - if (ahc_debug & AHC_SHOWSCBS) - printf("%s: free SCB tag %x\n", ahc_name(ahc), hscb->tag); -#endif - - opri = splbio(); - - if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0 || - (scb->flags & SCB_RECOVERY_SCB) != 0) { - ahc->flags &= ~AHC_RESOURCE_SHORTAGE; - ahc->queue_blocked = 0; - } - - /* Clean up for the next user */ - scb->flags = SCB_FREE; - hscb->control = 0; - hscb->status = 0; - timeout_del(&scb->xs->stimeout); - - SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links); - - splx(opri); -} +static const u_int num_chip_names = NUM_ELEMENTS(ahc_chip_names); /* - * Get a free scb, either one already assigned to a hardware slot - * on the adapter or one that will require an SCB to be paged out before - * use. If there are none, see if we can allocate a new SCB. Otherwise - * either return an error or sleep. + * Hardware error codes. */ -static __inline struct scb * -ahcgetscb(ahc) - struct ahc_softc *ahc; -{ - struct scb *scbp; - int opri; - - opri = splbio(); - if ((scbp = SLIST_FIRST(&ahc->scb_data->free_scbs))) { - SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); - } else { - ahcallocscbs(ahc); - scbp = SLIST_FIRST(&ahc->scb_data->free_scbs); - if (scbp != NULL) - SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); - } - - splx(opri); - - return (scbp); -} - -int -ahc_createdmamem(ahc, size, mapp, vaddr, baddr, seg, nseg, what) - struct ahc_softc *ahc; - int size; - bus_dmamap_t *mapp; - caddr_t *vaddr; - bus_addr_t *baddr; - bus_dma_segment_t *seg; - int *nseg; - const char *what; -{ - int error, level = 0; - int dma_flags = BUS_DMA_NOWAIT; - bus_dma_tag_t tag = ahc->sc_dmat; - const char *myname = ahc_name(ahc); - if ((ahc->chip & AHC_VL) !=0) - dma_flags |= ISABUS_DMA_32BIT; - - if ((error = bus_dmamem_alloc(tag, size, NBPG, 0, - seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { - printf("%s: failed to allocate DMA mem for %s, error = %d\n", - myname, what, error); - goto out; - } - level++; - - if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, - BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { - printf("%s: failed to map DMA mem for %s, error = %d\n", - myname, what, error); - goto out; - } - level++; - - if ((error = bus_dmamap_create(tag, size, 1, size, 0, - dma_flags, mapp)) != 0) { - printf("%s: failed to create DMA map for %s, error = %d\n", - myname, what, error); - goto out; - } - level++; - - if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, - BUS_DMA_NOWAIT)) != 0) { - printf("%s: failed to load DMA map for %s, error = %d\n", - myname, what, error); - goto out; - } - - *baddr = (*mapp)->dm_segs[0].ds_addr; - return 0; -out: - switch (level) { - case 3: - bus_dmamap_destroy(tag, *mapp); - /* FALLTHROUGH */ - case 2: - bus_dmamem_unmap(tag, *vaddr, size); - /* FALLTHROUGH */ - case 1: - bus_dmamem_free(tag, seg, *nseg); - break; - default: - break; - } - - return error; -} - -STATIC void -ahc_freedmamem(tag, size, map, vaddr, seg, nseg) - bus_dma_tag_t tag; - int size; - bus_dmamap_t map; - caddr_t vaddr; - bus_dma_segment_t *seg; - int nseg; -{ - - bus_dmamap_unload(tag, map); - bus_dmamap_destroy(tag, map); - bus_dmamem_unmap(tag, vaddr, size); - bus_dmamem_free(tag, seg, nseg); -} - -#ifdef AHC_DEBUG -STATIC void -ahc_print_scb(scb) - struct scb *scb; -{ - struct hardware_scb *hscb = scb->hscb; - - printf("scb:%p tag %x control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%lx\n", - scb, - hscb->tag, - hscb->control, - hscb->tcl, - hscb->cmdlen, - (unsigned long)le32toh(hscb->cmdpointer)); - printf(" datlen:%u data:0x%lx segs:0x%x segp:0x%lx\n", - le32toh(hscb->datalen), - (unsigned long)(le32toh(hscb->data)), - hscb->SG_count, - (unsigned long)(le32toh(hscb->SG_pointer))); - printf(" sg_addr:%lx sg_len:%lu\n", - (unsigned long)(le32toh(scb->sg_list[0].addr)), - (unsigned long)(le32toh(scb->sg_list[0].len))); - printf(" cdb:%x %x %x %x %x %x %x %x %x %x %x %x\n", - hscb->cmdstore[0], hscb->cmdstore[1], hscb->cmdstore[2], - hscb->cmdstore[3], hscb->cmdstore[4], hscb->cmdstore[5], - hscb->cmdstore[6], hscb->cmdstore[7], hscb->cmdstore[8], - hscb->cmdstore[9], hscb->cmdstore[10], hscb->cmdstore[11]); -} -#endif - -static struct { - u_int8_t errno; +struct ahc_hard_error_entry { + uint8_t errno; char *errmesg; -} hard_error[] = { +}; + +static struct ahc_hard_error_entry ahc_hard_errors[] = { { ILLHADDR, "Illegal Host Access" }, { ILLSADDR, "Illegal Sequencer Address referrenced" }, { ILLOPCODE, "Illegal Opcode in sequencer program" }, @@ -801,15 +85,14 @@ static struct { { PCIERRSTAT, "PCI Error detected" }, { CIOPARERR, "CIOBUS Parity Error" }, }; -static const int num_errors = sizeof(hard_error)/sizeof(hard_error[0]); +static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors); -static struct { - u_int8_t phase; - u_int8_t mesg_out; /* Message response to parity errors */ - char *phasemsg; -} phase_table[] = { +static struct ahc_phase_table_entry ahc_phase_table[] = +{ { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, + { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, + { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, { P_COMMAND, MSG_NOOP, "in Command phase" }, { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, @@ -817,18 +100,20 @@ static struct { { P_BUSFREE, MSG_NOOP, "while idle" }, { 0, MSG_NOOP, "in unknown phase" } }; -static const int num_phases = (sizeof(phase_table)/sizeof(phase_table[0])) - 1; + +/* + * In most cases we only wish to itterate over real phases, so + * exclude the last element from the count. + */ +static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1; /* * Valid SCSIRATE values. (p. 3-17) * Provides a mapping of tranfer periods in ns to the proper value to - * stick in the scsiscfr reg to use that transfer rate. + * stick in the scsixfer reg. */ -#define AHC_SYNCRATE_DT 0 -#define AHC_SYNCRATE_ULTRA2 1 -#define AHC_SYNCRATE_ULTRA 3 -#define AHC_SYNCRATE_FAST 6 -static struct ahc_syncrate ahc_syncrates[] = { +static struct ahc_syncrate ahc_syncrates[] = +{ /* ultra2 fast/ultra period rate */ { 0x42, 0x000, 9, "80.0" }, { 0x03, 0x000, 10, "40.0" }, @@ -847,863 +132,272 @@ static struct ahc_syncrate ahc_syncrates[] = { { 0x00, 0x000, 0, NULL } }; -/* - * Allocate a controller structure for a new device and initialize it. - * ahc_reset should be called before now since we assume that the card - * is paused. - */ -void -ahc_construct(ahc, iot, ioh, chip, flags, features, channel) - struct ahc_softc *ahc; - bus_space_tag_t iot; - bus_space_handle_t ioh; - ahc_chip chip; - ahc_flag flags; - ahc_feature features; - u_char channel; -{ - /* - * find unit and check we have that many defined - */ - LIST_INIT(&ahc->pending_scbs); - ahc->sc_iot = iot; - ahc->sc_ioh = ioh; - ahc->chip = chip; - ahc->flags = flags; - ahc->features = features; - ahc->channel = channel; - ahc->scb_data = NULL; - ahc->pci_intr_func = NULL; - - ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS) | INTEN; - /* The IRQMS bit is only valid on VL and EISA chips */ - if ((ahc->chip & AHC_PCI) != 0) - ahc->unpause &= ~IRQMS; - ahc->pause = ahc->unpause | PAUSE; -} - -void -ahc_free(ahc) - struct ahc_softc *ahc; -{ - ahcfiniscbdata(ahc); - if (ahc->init_level != 0) - ahc_freedmamem(ahc->sc_dmat, ahc->shared_data_size, - ahc->shared_data_dmamap, ahc->qoutfifo, - &ahc->shared_data_seg, ahc->shared_data_nseg); - - if (ahc->scb_data != NULL) - free(ahc->scb_data, M_DEVBUF); - if (ahc->pci_data != NULL) - free(ahc->pci_data, M_DEVBUF); - return; -} - -STATIC int -ahcinitscbdata(ahc) - struct ahc_softc *ahc; -{ - struct scb_data *scb_data; - int i; - - scb_data = ahc->scb_data; - SLIST_INIT(&scb_data->free_scbs); - SLIST_INIT(&scb_data->sg_maps); - - /* Allocate SCB resources */ - scb_data->scbarray = - (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX, - M_DEVBUF, M_NOWAIT); - if (scb_data->scbarray == NULL) - return (ENOMEM); - bzero(scb_data->scbarray, sizeof(struct scb) * AHC_SCB_MAX); - - /* Determine the number of hardware SCBs and initialize them */ - - scb_data->maxhscbs = ahc_probe_scbs(ahc); - /* SCB 0 heads the free list */ - ahc_outb(ahc, FREE_SCBH, 0); - for (i = 0; i < ahc->scb_data->maxhscbs; i++) { - ahc_outb(ahc, SCBPTR, i); - - /* Clear the control byte. */ - ahc_outb(ahc, SCB_CONTROL, 0); - - /* Set the next pointer */ - ahc_outb(ahc, SCB_NEXT, i+1); - - /* Make the tag number invalid */ - ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); - } - - /* Make sure that the last SCB terminates the free list */ - ahc_outb(ahc, SCBPTR, i-1); - ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); - - /* Ensure we clear the 0 SCB's control byte. */ - ahc_outb(ahc, SCBPTR, 0); - ahc_outb(ahc, SCB_CONTROL, 0); - - scb_data->maxhscbs = i; - - if (ahc->scb_data->maxhscbs == 0) - panic("%s: No SCB space found", ahc_name(ahc)); - - /* - * Create our DMA tags. These tags define the kinds of device - * accessable memory allocations and memory mappings we will - * need to perform during normal operation. - * - * Unless we need to further restrict the allocation, we rely - * on the restrictions of the parent dmat, hence the common - * use of MAXADDR and MAXSIZE. - */ - - if (ahc_createdmamem(ahc, - AHC_SCB_MAX * sizeof(struct hardware_scb), - &scb_data->hscb_dmamap, (caddr_t *)&scb_data->hscbs, - &scb_data->hscb_busaddr, &scb_data->hscb_seg, - &scb_data->hscb_nseg, "hardware SCB structures") < 0) - goto error_exit; - - scb_data->init_level++; - - if (ahc_createdmamem(ahc, - AHC_SCB_MAX * sizeof(struct scsi_sense_data), - &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, - &scb_data->sense_busaddr, &scb_data->sense_seg, - &scb_data->sense_nseg, "sense buffers") < 0) - goto error_exit; - - scb_data->init_level++; - - /* Perform initial CCB allocation */ - bzero(scb_data->hscbs, AHC_SCB_MAX * sizeof(struct hardware_scb)); - ahcallocscbs(ahc); - - if (scb_data->numscbs == 0) { - printf("%s: ahc_init_scb_data - " - "Unable to allocate initial scbs\n", - ahc_name(ahc)); - goto error_exit; - } - - scb_data->init_level++; - - /* - * Note that we were successfull - */ - return 0; - -error_exit: - - return ENOMEM; -} - -STATIC void -ahcfiniscbdata(ahc) - struct ahc_softc *ahc; -{ - struct scb_data *scb_data; - - scb_data = ahc->scb_data; - - switch (scb_data->init_level) { - default: - case 3: - { - struct sg_map_node *sg_map; - - while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { - SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); - ahc_freedmamem(ahc->sc_dmat, PAGE_SIZE, - sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, - &sg_map->sg_dmasegs, sg_map->sg_nseg); - free(sg_map, M_DEVBUF); - } - } - /*FALLTHROUGH*/ - case 2: - ahc_freedmamem(ahc->sc_dmat, - AHC_SCB_MAX * sizeof(struct scsi_sense_data), - scb_data->sense_dmamap, (caddr_t)scb_data->sense, - &scb_data->sense_seg, scb_data->sense_nseg); - /*FALLTHROUGH*/ - case 1: - ahc_freedmamem(ahc->sc_dmat, - AHC_SCB_MAX * sizeof(struct hardware_scb), - scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, - &scb_data->hscb_seg, scb_data->hscb_nseg); - /*FALLTHROUGH*/ - } - if (scb_data->scbarray != NULL) - free(scb_data->scbarray, M_DEVBUF); -} - -void -ahc_xxx_reset(devname, iot, ioh) - char *devname; - bus_space_tag_t iot; - bus_space_handle_t ioh; -{ - u_char hcntrl; - int wait; +/* Our Sequencer Program */ +#ifdef __OpenBSD__ +#include <dev/microcode/aic7xxx/aic7xxx_seq.h> +#else +#include "aic7xxx_seq.h" +#endif -#ifdef AHC_DUMP_SEQ - ahc_dumpseq(ahc); +/**************************** Function Declarations ***************************/ +static struct ahc_tmode_tstate* + ahc_alloc_tstate(struct ahc_softc *ahc, + u_int scsi_id, char channel); +#ifdef AHC_TARGET_MODE +static void ahc_free_tstate(struct ahc_softc *ahc, + u_int scsi_id, char channel, int force); +#endif +static struct ahc_syncrate* + ahc_devlimited_syncrate(struct ahc_softc *ahc, + struct ahc_initiator_tinfo *, + u_int *period, + u_int *ppr_options, + role_t role); +static void ahc_update_pending_scbs(struct ahc_softc *ahc); +static void ahc_fetch_devinfo(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo); +static void ahc_scb_devinfo(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo, + struct scb *scb); +static void ahc_assert_atn(struct ahc_softc *ahc); +static void ahc_setup_initiator_msgout(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo, + struct scb *scb); +static void ahc_build_transfer_msg(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo); +static void ahc_construct_sdtr(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo, + u_int period, u_int offset); +static void ahc_construct_wdtr(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo, + u_int bus_width); +static void ahc_construct_ppr(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo, + u_int period, u_int offset, + u_int bus_width, u_int ppr_options); +static void ahc_clear_msg_state(struct ahc_softc *ahc); +static void ahc_handle_message_phase(struct ahc_softc *ahc); +typedef enum { + AHCMSG_1B, + AHCMSG_2B, + AHCMSG_EXT +} ahc_msgtype; +static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, + u_int msgval, int full); +static int ahc_parse_msg(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo); +static int ahc_handle_msg_reject(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo); +static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo); +static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc); +static void ahc_handle_devreset(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo, + cam_status status, char *message, + int verbose_level); +#if AHC_TARGET_MODE +static void ahc_setup_target_msgin(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo, + struct scb *scb); #endif - /* Retain the IRQ type across the chip reset */ - hcntrl = (bus_space_read_1(iot, ioh, HCNTRL) & IRQMS) | INTEN; - bus_space_write_1(iot, ioh, HCNTRL, CHIPRST | PAUSE); - /* - * Ensure that the reset has finished - */ - wait = 1000; - while (--wait && !(bus_space_read_1(iot, ioh, HCNTRL) & CHIPRSTACK)) - DELAY(1000); - if (wait == 0) { - printf("%s: WARNING - Failed chip reset! " - "Trying to initialize anyway.\n", devname); - } - bus_space_write_1(iot, ioh, HCNTRL, hcntrl | PAUSE); -} +#ifdef __OpenBSD__ +int ahc_init_scbdata(struct ahc_softc *ahc); +void ahc_fini_scbdata(struct ahc_softc *ahc); +void ahc_build_free_scb_list(struct ahc_softc *ahc); +#else +static bus_dmamap_callback_t ahc_dmamap_cb; +static int ahc_init_scbdata(struct ahc_softc *ahc); +static void ahc_fini_scbdata(struct ahc_softc *ahc); +static void ahc_build_free_scb_list(struct ahc_softc *ahc); +#endif -int -ahc_reset(ahc) - struct ahc_softc *ahc; -{ - u_int sblkctl; - int wait; - +static void ahc_qinfifo_requeue(struct ahc_softc *ahc, + struct scb *prev_scb, + struct scb *scb); +static int ahc_qinfifo_count(struct ahc_softc *ahc); +static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, + u_int prev, u_int scbptr); +static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); +static u_int ahc_rem_wscb(struct ahc_softc *ahc, + u_int scbpos, u_int prev); +static int ahc_abort_scbs(struct ahc_softc *ahc, int target, + char channel, int lun, u_int tag, + role_t role, uint32_t status); +static void ahc_reset_current_bus(struct ahc_softc *ahc); #ifdef AHC_DUMP_SEQ - if (ahc->init_level == 0) - ahc_dumpseq(ahc); +static void ahc_dumpseq(struct ahc_softc *ahc); #endif - ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); - /* - * Ensure that the reset has finished - */ - wait = 1000; - do { - DELAY(1000); - } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); - - if (wait == 0) { - printf("%s: WARNING - Failed chip reset! " - "Trying to initialize anyway.\n", ahc_name(ahc)); - } - ahc_outb(ahc, HCNTRL, ahc->pause); - - /* Determine channel configuration */ - sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); - /* No Twin Channel PCI cards */ - if ((ahc->chip & AHC_PCI) != 0) - sblkctl &= ~SELBUSB; - switch (sblkctl) { - case 0: - /* Single Narrow Channel */ - break; - case 2: - /* Wide Channel */ - ahc->features |= AHC_WIDE; - break; - case 8: - /* Twin Channel */ - ahc->features |= AHC_TWIN; - break; - default: - printf(" Unsupported adapter type. Ignoring\n"); - return(-1); - } - return (0); -} - -/* - * Called when we have an active connection to a target on the bus, - * this function finds the nearest syncrate to the input period limited - * by the capabilities of the bus connectivity of the target. - */ -STATIC struct ahc_syncrate * -ahc_devlimited_syncrate(ahc, period) - struct ahc_softc *ahc; - u_int *period; -{ - u_int maxsync; - - if ((ahc->features & AHC_ULTRA2) != 0) { - if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 - && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { - maxsync = AHC_SYNCRATE_ULTRA2; - } else { - maxsync = AHC_SYNCRATE_ULTRA; - } - } else if ((ahc->features & AHC_ULTRA) != 0) { - maxsync = AHC_SYNCRATE_ULTRA; - } else { - maxsync = AHC_SYNCRATE_FAST; - } - return (ahc_find_syncrate(ahc, period, maxsync)); -} - +static void ahc_loadseq(struct ahc_softc *ahc); +static int ahc_check_patch(struct ahc_softc *ahc, + struct patch **start_patch, + u_int start_instr, u_int *skip_addr); +static void ahc_download_instr(struct ahc_softc *ahc, + u_int instrptr, uint8_t *dconsts); +#ifdef AHC_TARGET_MODE +static void ahc_queue_lstate_event(struct ahc_softc *ahc, + struct ahc_tmode_lstate *lstate, + u_int initiator_id, + u_int event_type, + u_int event_arg); +static void ahc_update_scsiid(struct ahc_softc *ahc, + u_int targid_mask); +static int ahc_handle_target_cmd(struct ahc_softc *ahc, + struct target_cmd *cmd); +#endif +/************************* Sequencer Execution Control ************************/ /* - * Look up the valid period to SCSIRATE conversion in our table. - * Return the period and offset that should be sent to the target - * if this was the beginning of an SDTR. + * Restart the sequencer program from address zero */ -STATIC struct ahc_syncrate * -ahc_find_syncrate(ahc, period, maxsync) - struct ahc_softc *ahc; - u_int *period; - u_int maxsync; -{ - struct ahc_syncrate *syncrate; - - syncrate = &ahc_syncrates[maxsync]; - while ((syncrate->rate != NULL) - && ((ahc->features & AHC_ULTRA2) == 0 - || (syncrate->sxfr_u2 != 0))) { - - if (*period <= syncrate->period) { - /* - * When responding to a target that requests - * sync, the requested rate may fall between - * two rates that we can output, but still be - * a rate that we can receive. Because of this, - * we want to respond to the target with - * the same rate that it sent to us even - * if the period we use to send data to it - * is lower. Only lower the response period - * if we must. - */ - if (syncrate == &ahc_syncrates[maxsync]) - *period = syncrate->period; - break; - } - syncrate++; - } - - if ((*period == 0) - || (syncrate->rate == NULL) - || ((ahc->features & AHC_ULTRA2) != 0 - && (syncrate->sxfr_u2 == 0))) { - /* Use asynchronous transfers. */ - *period = 0; - syncrate = NULL; - } - return (syncrate); -} - -STATIC u_int -ahc_find_period(ahc, scsirate, maxsync) - struct ahc_softc *ahc; - u_int scsirate; - u_int maxsync; +void +ahc_restart(struct ahc_softc *ahc) { - struct ahc_syncrate *syncrate; - if ((ahc->features & AHC_ULTRA2) != 0) - scsirate &= SXFR_ULTRA2; - else - scsirate &= SXFR; + ahc_pause(ahc); - syncrate = &ahc_syncrates[maxsync]; - while (syncrate->rate != NULL) { + ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */ + ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */ + ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); - if ((ahc->features & AHC_ULTRA2) != 0) { - if (syncrate->sxfr_u2 == 0) - break; - else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) - return (syncrate->period); - } else if (scsirate == (syncrate->sxfr & SXFR)) { - return (syncrate->period); - } - syncrate++; - } - return (0); /* async */ -} - -STATIC void -ahc_validate_offset(ahc, syncrate, offset, wide) - struct ahc_softc *ahc; - struct ahc_syncrate *syncrate; - u_int *offset; - int wide; -{ - u_int maxoffset; + /* + * Ensure that the sequencer's idea of TQINPOS + * matches our own. The sequencer increments TQINPOS + * only after it sees a DMA complete and a reset could + * occur before the increment leaving the kernel to believe + * the command arrived but the sequencer to not. + */ + ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); - /* Limit offset to what we can do */ - if (syncrate == NULL) { - maxoffset = 0; - } else if ((ahc->features & AHC_ULTRA2) != 0) { - maxoffset = MAX_OFFSET_ULTRA2; - } else { - if (wide) - maxoffset = MAX_OFFSET_16BIT; - else - maxoffset = MAX_OFFSET_8BIT; + /* Always allow reselection */ + ahc_outb(ahc, SCSISEQ, + ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); + if ((ahc->features & AHC_CMD_CHAN) != 0) { + /* Ensure that no DMA operations are in progress */ + ahc_outb(ahc, CCSCBCNT, 0); + ahc_outb(ahc, CCSGCTL, 0); + ahc_outb(ahc, CCSCBCTL, 0); } - *offset = MIN(*offset, maxoffset); -} - -STATIC void -ahc_update_target_msg_request(ahc, devinfo, tinfo, force, paused) - struct ahc_softc *ahc; - struct ahc_devinfo *devinfo; - struct ahc_initiator_tinfo *tinfo; - int force; - int paused; -{ - u_int targ_msg_req_orig; - - targ_msg_req_orig = ahc->targ_msg_req; - if (tinfo->current.period != tinfo->goal.period - || tinfo->current.width != tinfo->goal.width - || tinfo->current.offset != tinfo->goal.offset - || (force && (tinfo->goal.period != 0 - || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT))) - ahc->targ_msg_req |= devinfo->target_mask; - else - ahc->targ_msg_req &= ~devinfo->target_mask; - - if (ahc->targ_msg_req != targ_msg_req_orig) { - /* Update the message request bit for this target */ - if ((ahc->features & AHC_HS_MAILBOX) != 0) { - if (paused) { - ahc_outb(ahc, TARGET_MSG_REQUEST, - ahc->targ_msg_req & 0xFF); - ahc_outb(ahc, TARGET_MSG_REQUEST + 1, - (ahc->targ_msg_req >> 8) & 0xFF); - } else { - ahc_outb(ahc, HS_MAILBOX, - 0x01 << HOST_MAILBOX_SHIFT); - } - } else { - if (!paused) - pause_sequencer(ahc); - - ahc_outb(ahc, TARGET_MSG_REQUEST, - ahc->targ_msg_req & 0xFF); - ahc_outb(ahc, TARGET_MSG_REQUEST + 1, - (ahc->targ_msg_req >> 8) & 0xFF); - - if (!paused) - unpause_sequencer(ahc); - } + /* + * If we were in the process of DMA'ing SCB data into + * an SCB, replace that SCB on the free list. This prevents + * an SCB leak. + */ + if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) { + ahc_add_curscb_to_free_list(ahc); + ahc_outb(ahc, SEQ_FLAGS2, + ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA); } + ahc_outb(ahc, MWI_RESIDUAL, 0); + ahc_outb(ahc, SEQCTL, FASTMODE); + ahc_outb(ahc, SEQADDR0, 0); + ahc_outb(ahc, SEQADDR1, 0); + ahc_unpause(ahc); } -STATIC void -ahc_set_syncrate(ahc, devinfo, syncrate, period, offset, type, paused, done) - struct ahc_softc *ahc; - struct ahc_devinfo *devinfo; - struct ahc_syncrate *syncrate; - u_int period; - u_int offset; - u_int type; - int paused; - int done; +/************************* Input/Output Queues ********************************/ +void +ahc_run_qoutfifo(struct ahc_softc *ahc) { - struct ahc_initiator_tinfo *tinfo; - struct tmode_tstate *tstate; - u_int old_period; - u_int old_offset; - int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; - - if (syncrate == NULL) { - period = 0; - offset = 0; - } - - tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, - devinfo->our_scsiid, - devinfo->target, &tstate); - old_period = tinfo->current.period; - old_offset = tinfo->current.offset; - - if ((type & AHC_TRANS_CUR) != 0 - && (old_period != period || old_offset != offset)) { - u_int scsirate; - - scsirate = tinfo->scsirate; - if ((ahc->features & AHC_ULTRA2) != 0) { + struct scb *scb; + u_int scb_index; - /* XXX */ - /* Force single edge until DT is fully implemented */ - scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); - if (syncrate != NULL) - scsirate |= syncrate->sxfr_u2|SINGLE_EDGE; + ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); + while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { - if (active) - ahc_outb(ahc, SCSIOFFSET, offset); - } else { + scb_index = ahc->qoutfifo[ahc->qoutfifonext]; + if ((ahc->qoutfifonext & 0x03) == 0x03) { + u_int modnext; - scsirate &= ~(SXFR|SOFS); /* - * Ensure Ultra mode is set properly for - * this target. + * Clear 32bits of QOUTFIFO at a time + * so that we don't clobber an incoming + * byte DMA to the array on architectures + * that only support 32bit load and store + * operations. */ - tstate->ultraenb &= ~devinfo->target_mask; - if (syncrate != NULL) { - if (syncrate->sxfr & ULTRA_SXFR) { - tstate->ultraenb |= - devinfo->target_mask; - } - scsirate |= syncrate->sxfr & SXFR; - scsirate |= offset & SOFS; - } - if (active) { - u_int sxfrctl0; - - sxfrctl0 = ahc_inb(ahc, SXFRCTL0); - sxfrctl0 &= ~FAST20; - if (tstate->ultraenb & devinfo->target_mask) - sxfrctl0 |= FAST20; - ahc_outb(ahc, SXFRCTL0, sxfrctl0); - } + modnext = ahc->qoutfifonext & ~0x3; + *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL; + ahc_dmamap_sync(ahc, ahc->shared_data_dmat, + ahc->shared_data_dmamap, + /*offset*/modnext, /*len*/4, + BUS_DMASYNC_PREREAD); } - if (active) - ahc_outb(ahc, SCSIRATE, scsirate); - - tinfo->scsirate = scsirate; - tinfo->current.period = period; - tinfo->current.offset = offset; + ahc->qoutfifonext++; - /* Update the syncrates in any pending scbs */ - ahc_update_pending_syncrates(ahc); - } - - /* - * Print messages if we're verbose and at the end of a negotiation - * cycle. - */ - if (done) { - if (offset != 0) { - printf("%s: target %d synchronous at %sMHz, " - "offset = 0x%x\n", ahc_name(ahc), - devinfo->target, syncrate->rate, offset); - } else { - printf("%s: target %d using " - "asynchronous transfers\n", - ahc_name(ahc), devinfo->target); + scb = ahc_lookup_scb(ahc, scb_index); + if (scb == NULL) { + printf("%s: WARNING no command for scb %d " + "(cmdcmplt)\nQOUTPOS = %d\n", + ahc_name(ahc), scb_index, + ahc->qoutfifonext - 1); + continue; } - } - - if ((type & AHC_TRANS_GOAL) != 0) { - tinfo->goal.period = period; - tinfo->goal.offset = offset; - } - - if ((type & AHC_TRANS_USER) != 0) { - tinfo->user.period = period; - tinfo->user.offset = offset; - } - - ahc_update_target_msg_request(ahc, devinfo, tinfo, - /*force*/FALSE, - paused); -} -STATIC void -ahc_set_width(ahc, devinfo, width, type, paused, done) - struct ahc_softc *ahc; - struct ahc_devinfo *devinfo; - u_int width; - u_int type; - int paused; - int done; -{ - struct ahc_initiator_tinfo *tinfo; - struct tmode_tstate *tstate; - u_int oldwidth; - int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; - - tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, - devinfo->our_scsiid, - devinfo->target, - &tstate); - oldwidth = tinfo->current.width; - - if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { - u_int scsirate; - - scsirate = tinfo->scsirate; - scsirate &= ~WIDEXFER; - if (width == MSG_EXT_WDTR_BUS_16_BIT) - scsirate |= WIDEXFER; - - tinfo->scsirate = scsirate; - - if (active) - ahc_outb(ahc, SCSIRATE, scsirate); - - tinfo->current.width = width; - } - - if (done) { - printf("%s: target %d using %dbit transfers\n", - ahc_name(ahc), devinfo->target, - 8 * (0x01 << width)); + /* + * Save off the residual + * if there is one. + */ + ahc_update_residual(scb); + ahc_done(ahc, scb); } - - if ((type & AHC_TRANS_GOAL) != 0) - tinfo->goal.width = width; - if ((type & AHC_TRANS_USER) != 0) - tinfo->user.width = width; - - ahc_update_target_msg_request(ahc, devinfo, tinfo, - /*force*/FALSE, paused); } -STATIC void -ahc_set_tags(ahc, devinfo, enable) - struct ahc_softc *ahc; - struct ahc_devinfo *devinfo; - int enable; +void +ahc_run_untagged_queues(struct ahc_softc *ahc) { - struct ahc_initiator_tinfo *tinfo; - struct tmode_tstate *tstate; + int i; - tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, - devinfo->our_scsiid, - devinfo->target, - &tstate); - if (enable) - tstate->tagenable |= devinfo->target_mask; - else { - tstate->tagenable &= ~devinfo->target_mask; - } + for (i = 0; i < 16; i++) + ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]); } -/* - * Attach all the sub-devices we can find - */ -int -ahc_attach(ahc) - struct ahc_softc *ahc; +void +ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue) { - /* - * Initialize the software queue. - */ - LIST_INIT(&ahc->sc_xxxq); - -#ifdef AHC_BROKEN_CACHE - if (cpu_class == CPUCLASS_386) /* doesn't have "wbinvd" instruction */ - ahc_broken_cache = 0; -#endif - /* - * fill in the prototype scsi_links. - */ - ahc->sc_link.adapter_target = ahc->our_id; - if (ahc->features & AHC_WIDE) - ahc->sc_link.adapter_buswidth = 16; - ahc->sc_link.adapter_softc = ahc; - ahc->sc_link.adapter = &ahc_switch; - ahc->sc_link.openings = 2; - ahc->sc_link.device = &ahc_dev; - ahc->sc_link.flags = SCSIDEBUG_LEVEL; - - if (ahc->features & AHC_TWIN) { - /* Configure the second scsi bus */ - ahc->sc_link_b = ahc->sc_link; - ahc->sc_link_b.adapter_target = ahc->our_id_b; - if (ahc->features & AHC_WIDE) - ahc->sc_link.adapter_buswidth = 16; - } - - /* - * ask the adapter what subunits are present - */ - if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) == 0) { - /* make IS_SCSIBUS_B() == false, while probing channel A */ - ahc->sc_link_b.scsibus = 0xff; + struct scb *scb; - config_found((void *)ahc, &ahc->sc_link, scsiprint); - if (ahc->features & AHC_TWIN) - config_found((void *)ahc, &ahc->sc_link_b, scsiprint); - } else { - /* - * if implementation of IS_SCSIBUS_B() is changed to use - * ahc->sc_link.scsibus, then "ahc->sc_link.scsibus = 0xff;" - * is needed, here. - */ + if (ahc->untagged_queue_lock != 0) + return; - /* assert(ahc->features & AHC_TWIN); */ - config_found((void *)ahc, &ahc->sc_link_b, scsiprint); - config_found((void *)ahc, &ahc->sc_link, scsiprint); + if ((scb = TAILQ_FIRST(queue)) != NULL + && (scb->flags & SCB_ACTIVE) == 0) { + scb->flags |= SCB_ACTIVE; + ahc_queue_scb(ahc, scb); } - return 1; -} - -STATIC void -ahc_fetch_devinfo(ahc, devinfo) - struct ahc_softc *ahc; - struct ahc_devinfo *devinfo; -{ - u_int saved_tcl; - role_t role; - int our_id; - - if (ahc_inb(ahc, SSTAT0) & TARGET) - role = ROLE_TARGET; - else - role = ROLE_INITIATOR; - - if (role == ROLE_TARGET - && (ahc->features & AHC_MULTI_TID) != 0 - && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { - /* We were selected, so pull our id from TARGIDIN */ - our_id = ahc_inb(ahc, TARGIDIN) & OID; - } else if ((ahc->features & AHC_ULTRA2) != 0) - our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; - else - our_id = ahc_inb(ahc, SCSIID) & OID; - - saved_tcl = ahc_inb(ahc, SAVED_TCL); - ahc_compile_devinfo(devinfo, our_id, TCL_TARGET(saved_tcl), - TCL_LUN(saved_tcl), TCL_CHANNEL(ahc, saved_tcl), - role); } -STATIC void -ahc_compile_devinfo(devinfo, our_id, target, lun, channel, role) - struct ahc_devinfo *devinfo; - u_int our_id; - u_int target; - u_int lun; - char channel; - role_t role; -{ - devinfo->our_scsiid = our_id; - devinfo->target = target; - devinfo->lun = lun; - devinfo->target_offset = target; - devinfo->channel = channel; - devinfo->role = role; - if (channel == 'B') - devinfo->target_offset += 8; - devinfo->target_mask = (0x01 << devinfo->target_offset); -} - -/* - * Catch an interrupt from the adapter - */ -int -ahc_intr(void *arg) +/************************* Interrupt Handling *********************************/ +void +ahc_handle_brkadrint(struct ahc_softc *ahc) { - struct ahc_softc *ahc; - u_int intstat; - - ahc = (struct ahc_softc *)arg; - - intstat = ahc_inb(ahc, INTSTAT); - /* - * Any interrupts to process? + * We upset the sequencer :-( + * Lookup the error message */ - if ((intstat & INT_PEND) == 0) { - if (ahc->pci_intr_func && ahc->pci_intr_func(ahc)) { -#ifdef AHC_DEBUG - printf("%s: bus intr: CCHADDR %x HADDR %x SEQADDR %x\n", - ahc_name(ahc), - ahc_inb(ahc, CCHADDR) | - (ahc_inb(ahc, CCHADDR+1) << 8) - | (ahc_inb(ahc, CCHADDR+2) << 16) - | (ahc_inb(ahc, CCHADDR+3) << 24), - ahc_inb(ahc, HADDR) | (ahc_inb(ahc, HADDR+1) << 8) - | (ahc_inb(ahc, HADDR+2) << 16) - | (ahc_inb(ahc, HADDR+3) << 24), - ahc_inb(ahc, SEQADDR0) | - (ahc_inb(ahc, SEQADDR1) << 8)); -#endif - return 1; - } - return 0; - } + int i; + int error; - if (intstat & CMDCMPLT) { - ahc_outb(ahc, CLRINT, CLRCMDINT); - ahc_run_qoutfifo(ahc); - } - if (intstat & BRKADRINT) { - /* - * We upset the sequencer :-( - * Lookup the error message - */ - int i, error, num_errors; - - error = ahc_inb(ahc, ERROR); - num_errors = sizeof(hard_error)/sizeof(hard_error[0]); - for (i = 0; error != 1 && i < num_errors; i++) - error >>= 1; - panic("%s: brkadrint, %s at seqaddr = 0x%x\n", - ahc_name(ahc), hard_error[i].errmesg, - ahc_inb(ahc, SEQADDR0) | - (ahc_inb(ahc, SEQADDR1) << 8)); - - /* Tell everyone that this HBA is no longer availible */ - ahc_abort_scbs(ahc, ALL_TARGETS, ALL_CHANNELS, - ALL_LUNS, SCB_LIST_NULL, ROLE_UNKNOWN, - XS_DRIVER_STUFFUP); - } - if (intstat & SEQINT) - ahc_handle_seqint(ahc, intstat); - - if (intstat & SCSIINT) - ahc_handle_scsiint(ahc, intstat); - return(1); -} + error = ahc_inb(ahc, ERROR); + for (i = 0; error != 1 && i < num_errors; i++) + error >>= 1; + printf("%s: brkadrint, %s at seqaddr = 0x%x\n", + ahc_name(ahc), ahc_hard_errors[i].errmesg, + ahc_inb(ahc, SEQADDR0) | + (ahc_inb(ahc, SEQADDR1) << 8)); -STATIC struct tmode_tstate * -ahc_alloc_tstate(ahc, scsi_id, channel) - struct ahc_softc *ahc; - u_int scsi_id; - char channel; -{ - struct tmode_tstate *master_tstate; - struct tmode_tstate *tstate; - int i, s; + ahc_dump_card_state(ahc); - master_tstate = ahc->enabled_targets[ahc->our_id]; - if (channel == 'B') { - scsi_id += 8; - master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; - } - if (ahc->enabled_targets[scsi_id] != NULL - && ahc->enabled_targets[scsi_id] != master_tstate) - panic("%s: ahc_alloc_tstate - Target already allocated", - ahc_name(ahc)); - tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); - if (tstate == NULL) - return (NULL); + /* Tell everyone that this HBA is no longer availible */ + ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS, + CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, + CAM_NO_HBA); - /* - * If we have allocated a master tstate, copy user settings from - * the master tstate (taken from SRAM or the EEPROM) for this - * channel, but reset our current and goal settings to async/narrow - * until an initiator talks to us. - */ - if (master_tstate != NULL) { - bcopy(master_tstate, tstate, sizeof(*tstate)); - tstate->ultraenb = 0; - for (i = 0; i < 16; i++) { - bzero(&tstate->transinfo[i].current, - sizeof(tstate->transinfo[i].current)); - bzero(&tstate->transinfo[i].goal, - sizeof(tstate->transinfo[i].goal)); - } - } else - bzero(tstate, sizeof(*tstate)); - s = splbio(); - ahc->enabled_targets[scsi_id] = tstate; - splx(s); - return (tstate); + /* Disable all interrupt sources by resetting the controller */ + ahc_shutdown(ahc); } -STATIC void -ahc_handle_seqint(ahc, intstat) - struct ahc_softc *ahc; - u_int intstat; +void +ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) { struct scb *scb; struct ahc_devinfo devinfo; @@ -1718,86 +412,18 @@ ahc_handle_seqint(ahc, intstat) */ ahc_outb(ahc, CLRINT, CLRSEQINT); switch (intstat & SEQINT_MASK) { - case NO_MATCH: + case BAD_STATUS: { - /* Ensure we don't leave the selection hardware on */ - ahc_outb(ahc, SCSISEQ, - ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); + u_int scb_index; + struct hardware_scb *hscb; - printf("%s:%c:%d: no active SCB for reconnecting " - "target - issuing BUS DEVICE RESET\n", - ahc_name(ahc), devinfo.channel, devinfo.target); - printf("SAVED_TCL == 0x%x, ARG_1 == 0x%x, SEQ_FLAGS == 0x%x\n", - ahc_inb(ahc, SAVED_TCL), ahc_inb(ahc, ARG_1), - ahc_inb(ahc, SEQ_FLAGS)); - ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; - ahc->msgout_len = 1; - ahc->msgout_index = 0; - ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; - ahc_outb(ahc, MSG_OUT, HOST_MSG); - ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, LASTPHASE) | ATNO); - break; - } - case UPDATE_TMSG_REQ: - ahc_outb(ahc, TARGET_MSG_REQUEST, ahc->targ_msg_req & 0xFF); - ahc_outb(ahc, TARGET_MSG_REQUEST + 1, - (ahc->targ_msg_req >> 8) & 0xFF); - ahc_outb(ahc, HS_MAILBOX, 0); - break; - case SEND_REJECT: - { - u_int rejbyte = ahc_inb(ahc, ACCUM); - printf("%s:%c:%d: Warning - unknown message received from " - "target (0x%x). Rejecting\n", - ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); - break; - } - case NO_IDENT: - { /* - * The reconnecting target either did not send an identify - * message, or did, but we didn't find and SCB to match and - * before it could respond to our ATN/abort, it hit a dataphase. - * The only safe thing to do is to blow it away with a bus - * reset. + * Set the default return value to 0 (don't + * send sense). The sense code will change + * this if needed. */ - int found; - - printf("%s:%c:%d: Target did not send an IDENTIFY message. " - "LASTPHASE = 0x%x, SAVED_TCL == 0x%x\n", - ahc_name(ahc), devinfo.channel, devinfo.target, - ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_TCL)); - found = ahc_reset_channel(ahc, devinfo.channel, - /*initiate reset*/TRUE); - printf("%s: Issued Channel %c Bus Reset. " - "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel, - found); - return; - } - case BAD_PHASE: - { - u_int lastphase; + ahc_outb(ahc, RETURN_1, 0); - lastphase = ahc_inb(ahc, LASTPHASE); - if (lastphase == P_BUSFREE) { - printf("%s:%c:%d: Missed busfree. Curphase = 0x%x\n", - ahc_name(ahc), devinfo.channel, devinfo.target, - ahc_inb(ahc, SCSISIGI)); - restart_sequencer(ahc); - return; - } else { - printf("%s:%c:%d: unknown scsi bus phase %x. " - "Attempting to continue\n", - ahc_name(ahc), devinfo.channel, devinfo.target, - ahc_inb(ahc, SCSISIGI)); - } - break; - } - case BAD_STATUS: - { - u_int scb_index; - struct hardware_scb *hscb; - struct scsi_xfer *xs; /* * The sequencer will notify us when a command * has an error that would be of interest to @@ -1808,25 +434,18 @@ ahc_handle_seqint(ahc, intstat) * the in kernel copy directly. */ scb_index = ahc_inb(ahc, SCB_TAG); - scb = &ahc->scb_data->scbarray[scb_index]; - - /* - * Set the default return value to 0 (don't - * send sense). The sense code will change - * this if needed. - */ - ahc_outb(ahc, RETURN_1, 0); - if (!(scb_index < ahc->scb_data->numscbs - && (scb->flags & SCB_ACTIVE) != 0)) { + scb = ahc_lookup_scb(ahc, scb_index); + if (scb == NULL) { printf("%s:%c:%d: ahc_intr - referenced scb " "not valid during seqint 0x%x scb(%d)\n", ahc_name(ahc), devinfo.channel, devinfo.target, intstat, scb_index); + ahc_dump_card_state(ahc); + panic("for safety"); goto unpause; } hscb = scb->hscb; - xs = scb->xs; /* Don't want to clobber the original sense code */ if ((scb->flags & SCB_SENSE) != 0) { @@ -1836,146 +455,234 @@ ahc_handle_seqint(ahc, intstat) * complete. */ scb->flags &= ~SCB_SENSE; - ahcsetccbstatus(xs, XS_DRIVER_STUFFUP); + ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); break; } - /* Freeze the queue unit the client sees the error. */ - ahc_freeze_devq(ahc, xs->sc_link); - ahc_freeze_ccb(scb); - xs->status = hscb->status; - switch (hscb->status) { - case SCSI_OK: + ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR); + /* Freeze the queue until the client sees the error. */ + ahc_freeze_devq(ahc, scb); + ahc_freeze_scb(scb); + ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status); + switch (hscb->shared_data.status.scsi_status) { + case SCSI_STATUS_OK: printf("%s: Interrupted for staus of 0???\n", ahc_name(ahc)); break; - case SCSI_CHECK: + case SCSI_STATUS_CMD_TERMINATED: + case SCSI_STATUS_CHECK_COND: + { + struct ahc_dma_seg *sg; + struct scsi_sense *sc; + struct ahc_initiator_tinfo *targ_info; + struct ahc_tmode_tstate *tstate; + struct ahc_transinfo *tinfo; #ifdef AHC_DEBUG if (ahc_debug & AHC_SHOWSENSE) { - sc_print_addr(scb->xs->sc_link); + ahc_print_path(ahc, scb); printf("SCB %d: requests Check Status\n", scb->hscb->tag); } #endif - if (xs->error == XS_NOERROR && - !(scb->flags & SCB_SENSE)) { - struct ahc_dma_seg *sg; - struct scsi_sense *sc; - struct ahc_initiator_tinfo *tinfo; - struct tmode_tstate *tstate; - - sg = scb->sg_list; - sc = (struct scsi_sense *)(&hscb->cmdstore); - /* - * Save off the residual if there is one. - */ - if (hscb->residual_SG_count != 0) - ahc_calc_residual(scb); - else - xs->resid = 0; + if (ahc_perform_autosense(scb) == 0) + break; + targ_info = ahc_fetch_transinfo(ahc, + devinfo.channel, + devinfo.our_scsiid, + devinfo.target, + &tstate); + tinfo = &targ_info->curr; + sg = scb->sg_list; + sc = (struct scsi_sense *)(&hscb->shared_data.cdb); + /* + * Save off the residual if there is one. + */ + ahc_update_residual(scb); #ifdef AHC_DEBUG - if (ahc_debug & AHC_SHOWSENSE) { - sc_print_addr(scb->xs->sc_link); - printf("Sending Sense\n"); - } + if (ahc_debug & AHC_SHOWSENSE) { + ahc_print_path(ahc, scb); + printf("Sending Sense\n"); + } #endif - sg->addr = ahc->scb_data->sense_busaddr + - (hscb->tag*sizeof(struct scsi_sense_data)); - - sg->len = sizeof(struct scsi_sense_data); - - sc->opcode = REQUEST_SENSE; - sc->byte2 = SCB_LUN(scb) << 5; - sc->unused[0] = 0; - sc->unused[1] = 0; - sc->length = sg->len; - sc->control = 0; + sg->addr = ahc_get_sense_bufaddr(ahc, scb); + sg->len = ahc_get_sense_bufsize(ahc, scb); + sg->len |= AHC_DMA_LAST_SEG; + + /* Fixup byte order */ + sg->addr = ahc_htole32(sg->addr); + sg->len = ahc_htole32(sg->len); + + sc->opcode = REQUEST_SENSE; + sc->byte2 = 0; + if (tinfo->protocol_version <= SCSI_REV_2 + && SCB_GET_LUN(scb) < 8) + sc->byte2 = SCB_GET_LUN(scb) << 5; + sc->unused[0] = 0; + sc->unused[1] = 0; + sc->length = sg->len; + sc->control = 0; - /* - * Would be nice to preserve DISCENB here, - * but due to the way we page SCBs, we can't. - */ - hscb->control = 0; + /* + * We can't allow the target to disconnect. + * This will be an untagged transaction and + * having the target disconnect will make this + * transaction indestinguishable from outstanding + * tagged transactions. + */ + hscb->control = 0; - /* - * This request sense could be because the - * the device lost power or in some other - * way has lost our transfer negotiations. - * Renegotiate if appropriate. - */ - ahc_calc_residual(scb); -#ifdef AHC_DEBUG - if (ahc_debug & AHC_SHOWSENSE) { - sc_print_addr(xs->sc_link); - printf("Sense: datalen %d resid %d" - "chan %d id %d targ %d\n", - xs->datalen, xs->resid, - devinfo.channel, - devinfo.our_scsiid, - devinfo.target); - } + /* + * This request sense could be because the + * the device lost power or in some other + * way has lost our transfer negotiations. + * Renegotiate if appropriate. Unit attention + * errors will be reported before any data + * phases occur. + */ +#ifdef __OpenBSD__ + if (ahc_get_transfer_length(scb) > 0 && + ahc_get_residual(scb) == + ahc_get_transfer_length(scb)) { +#else + if (ahc_get_residual(scb) + == ahc_get_transfer_length(scb)) { #endif - if (xs->datalen > 0 && - xs->resid == xs->datalen) { - tinfo = ahc_fetch_transinfo(ahc, - devinfo.channel, - devinfo.our_scsiid, - devinfo.target, - &tstate); - ahc_update_target_msg_request(ahc, - &devinfo, - tinfo, - /*force*/TRUE, - /*paused*/TRUE); - } - hscb->status = 0; - hscb->SG_count = 1; - hscb->SG_pointer = scb->sg_list_phys; - hscb->data = sg->addr; - hscb->datalen = sg->len; - hscb->cmdpointer = hscb->cmdstore_busaddr; - hscb->cmdlen = sizeof(*sc); - scb->sg_count = hscb->SG_count; - ahc_swap_hscb(hscb); - ahc_swap_sg(scb->sg_list); - scb->flags |= SCB_SENSE; - /* - * Ensure the target is busy since this - * will be an untagged request. - */ - ahc_busy_tcl(ahc, scb); - ahc_outb(ahc, RETURN_1, SEND_SENSE); - - /* - * Ensure we have enough time to actually - * retrieve the sense. - */ - if (!(scb->xs->flags & SCSI_POLL)) - timeout_add(&scb->xs->stimeout, 5 * hz); + ahc_update_neg_request(ahc, &devinfo, + tstate, targ_info, + /*force*/TRUE); } - break; - case SCSI_BUSY: + if (tstate->auto_negotiate & devinfo.target_mask) { + hscb->control |= MK_MESSAGE; + scb->flags &= ~SCB_NEGOTIATE; + scb->flags |= SCB_AUTO_NEGOTIATE; + } + hscb->cdb_len = sizeof(*sc); + hscb->dataptr = ahc_htole32(sg->addr); + hscb->datacnt = ahc_htole32(sg->len); + hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID; + hscb->sgptr = ahc_htole32(hscb->sgptr); + scb->sg_count = 1; + scb->flags |= SCB_SENSE; + ahc_qinfifo_requeue_tail(ahc, scb); + ahc_outb(ahc, RETURN_1, SEND_SENSE); +#ifdef __OpenBSD__ + if (!(scb->io_ctx->flags & SCSI_POLL)) + timeout_add(&scb->io_ctx->stimeout, 5 * hz); +#endif +#ifdef __FreeBSD__ /* - * Requeue any transactions that haven't been - * sent yet. + * Ensure we have enough time to actually + * retrieve the sense. */ - ahc_freeze_devq(ahc, xs->sc_link); - ahc_freeze_ccb(scb); + untimeout(ahc_timeout, (caddr_t)scb, + scb->io_ctx->ccb_h.timeout_ch); + scb->io_ctx->ccb_h.timeout_ch = + timeout(ahc_timeout, (caddr_t)scb, 5 * hz); +#endif + break; + } + default: break; } break; } - case TRACE_POINT: + case NO_MATCH: + { + /* Ensure we don't leave the selection hardware on */ + ahc_outb(ahc, SCSISEQ, + ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); + + printf("%s:%c:%d: no active SCB for reconnecting " + "target - issuing BUS DEVICE RESET\n", + ahc_name(ahc), devinfo.channel, devinfo.target); + printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " + "ARG_1 == 0x%x ACCUM = 0x%x\n", + ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), + ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); + printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " + "SINDEX == 0x%x\n", + ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), + ahc_index_busy_tcl(ahc, + BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), + ahc_inb(ahc, SAVED_LUN))), + ahc_inb(ahc, SINDEX)); + printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " + "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", + ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), + ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), + ahc_inb(ahc, SCB_CONTROL)); + printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", + ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); + printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0)); + printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL)); + ahc_dump_card_state(ahc); + ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; + ahc->msgout_len = 1; + ahc->msgout_index = 0; + ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; + ahc_outb(ahc, MSG_OUT, HOST_MSG); + ahc_assert_atn(ahc); + break; + } + case SEND_REJECT: + { + u_int rejbyte = ahc_inb(ahc, ACCUM); + printf("%s:%c:%d: Warning - unknown message received from " + "target (0x%x). Rejecting\n", + ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); + break; + } + case NO_IDENT: { - printf("SSTAT2 = 0x%x DFCNTRL = 0x%x\n", ahc_inb(ahc, SSTAT2), - ahc_inb(ahc, DFCNTRL)); - printf("SSTAT3 = 0x%x DSTATUS = 0x%x\n", ahc_inb(ahc, SSTAT3), - ahc_inb(ahc, DFSTATUS)); - printf("SSTAT0 = 0x%x, SCB_DATACNT = 0x%x\n", - ahc_inb(ahc, SSTAT0), - ahc_inb(ahc, SCB_DATACNT)); + /* + * The reconnecting target either did not send an identify + * message, or did, but we didn't find an SCB to match and + * before it could respond to our ATN/abort, it hit a dataphase. + * The only safe thing to do is to blow it away with a bus + * reset. + */ + int found; + + printf("%s:%c:%d: Target did not send an IDENTIFY message. " + "LASTPHASE = 0x%x, SAVED_SCSIID == 0x%x\n", + ahc_name(ahc), devinfo.channel, devinfo.target, + ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_SCSIID)); + found = ahc_reset_channel(ahc, devinfo.channel, + /*initiate reset*/TRUE); + printf("%s: Issued Channel %c Bus Reset. " + "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel, + found); + return; + } + case IGN_WIDE_RES: + ahc_handle_ign_wide_residue(ahc, &devinfo); break; + case PDATA_REINIT: + ahc_reinitialize_dataptrs(ahc); + break; + case BAD_PHASE: + { + u_int lastphase; + + lastphase = ahc_inb(ahc, LASTPHASE); + printf("%s:%c:%d: unknown scsi bus phase %x, " + "lastphase = 0x%x. Attempting to continue\n", + ahc_name(ahc), devinfo.channel, devinfo.target, + lastphase, ahc_inb(ahc, SCSISIGI)); + break; + } + case MISSED_BUSFREE: + { + u_int lastphase; + + lastphase = ahc_inb(ahc, LASTPHASE); + printf("%s:%c:%d: Missed busfree. " + "Lastphase = 0x%x, Curphase = 0x%x\n", + ahc_name(ahc), devinfo.channel, devinfo.target, + lastphase, ahc_inb(ahc, SCSISIGI)); + ahc_restart(ahc); + return; } case HOST_MSG_LOOP: { @@ -1984,12 +691,15 @@ ahc_handle_seqint(ahc, intstat) * that requires host assistance for completion. * While handling the message phase(s), we will be * notified by the sequencer after each byte is - * transfered so we can track bus phases. + * transfered so we can track bus phase changes. * - * If this is the first time we've seen a HOST_MSG_LOOP, - * initialize the state of the host message loop. + * If this is the first time we've seen a HOST_MSG_LOOP + * interrupt, initialize the state of the host message + * loop. */ if (ahc->msg_type == MSG_TYPE_NONE) { + struct scb *scb; + u_int scb_index; u_int bus_phase; bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; @@ -2003,15 +713,16 @@ ahc_handle_seqint(ahc, intstat) * we got here. Just punt the message. */ ahc_clear_intstat(ahc); - restart_sequencer(ahc); + ahc_restart(ahc); + return; } + scb_index = ahc_inb(ahc, SCB_TAG); + scb = ahc_lookup_scb(ahc, scb_index); if (devinfo.role == ROLE_INITIATOR) { - struct scb *scb; - u_int scb_index; - - scb_index = ahc_inb(ahc, SCB_TAG); - scb = &ahc->scb_data->scbarray[scb_index]; + if (scb == NULL) + panic("HOST_MSG_LOOP with " + "invalid SCB %x\n", scb_index); if (bus_phase == P_MESGOUT) ahc_setup_initiator_msgout(ahc, @@ -2027,14 +738,17 @@ ahc_handle_seqint(ahc, intstat) ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; ahc->msgin_index = 0; - } else - /* XXX Ever executed??? */ - ahc_setup_target_msgin(ahc, &devinfo); + } +#if AHC_TARGET_MODE + else + ahc_setup_target_msgin(ahc, + &devinfo, + scb); +#endif } } - /* Pass a NULL path so that handlers generate their own */ - ahc_handle_message_phase(ahc, /*path*/NULL); + ahc_handle_message_phase(ahc); break; } case PERR_DETECTED: @@ -2052,17 +766,20 @@ ahc_handle_seqint(ahc, intstat) */ if ((intstat & SCSIINT) == 0 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { - u_int curphase; - /* - * The hardware will only let you ack bytes - * if the expected phase in SCSISIGO matches - * the current phase. Make sure this is - * currently the case. - */ - curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; - ahc_outb(ahc, LASTPHASE, curphase); - ahc_outb(ahc, SCSISIGO, curphase); + if ((ahc->features & AHC_DT) == 0) { + u_int curphase; + + /* + * The hardware will only let you ack bytes + * if the expected phase in SCSISIGO matches + * the current phase. Make sure this is + * currently the case. + */ + curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; + ahc_outb(ahc, LASTPHASE, curphase); + ahc_outb(ahc, SCSISIGO, curphase); + } ahc_inb(ahc, SCSIDATL); } break; @@ -2079,98 +796,158 @@ ahc_handle_seqint(ahc, intstat) */ u_int scbindex = ahc_inb(ahc, SCB_TAG); u_int lastphase = ahc_inb(ahc, LASTPHASE); - int i; + u_int i; - scb = &ahc->scb_data->scbarray[scbindex]; + scb = ahc_lookup_scb(ahc, scbindex); for (i = 0; i < num_phases; i++) { - if (lastphase == phase_table[i].phase) + if (lastphase == ahc_phase_table[i].phase) break; } - sc_print_addr(scb->xs->sc_link); + ahc_print_path(ahc, scb); printf("data overrun detected %s." " Tag == 0x%x.\n", - phase_table[i].phasemsg, + ahc_phase_table[i].phasemsg, scb->hscb->tag); - sc_print_addr(scb->xs->sc_link); - printf("%s seen Data Phase. Length = %d. NumSGs = %d.\n", + ahc_print_path(ahc, scb); + printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n", ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", - scb->xs->datalen, scb->sg_count); + ahc_get_transfer_length(scb), scb->sg_count); if (scb->sg_count > 0) { for (i = 0; i < scb->sg_count; i++) { - printf("sg[%d] - Addr 0x%x : Length %d\n", + + printf("sg[%d] - Addr 0x%x%x : Length %d\n", i, - (unsigned int)le32toh(scb->sg_list[i].addr), - (unsigned int)le32toh(scb->sg_list[i].len)); + (ahc_le32toh(scb->sg_list[i].len) >> 24 + & SG_HIGH_ADDR_BITS), + ahc_le32toh(scb->sg_list[i].addr), + ahc_le32toh(scb->sg_list[i].len) + & AHC_SG_LEN_MASK); } } /* - * Set this and it will take affect when the + * Set this and it will take effect when the * target does a command complete. */ - ahc_freeze_devq(ahc, scb->xs->sc_link); - ahcsetccbstatus(scb->xs, XS_DRIVER_STUFFUP); - ahc_freeze_ccb(scb); + ahc_freeze_devq(ahc, scb); + ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR); + ahc_freeze_scb(scb); + + if ((ahc->features & AHC_ULTRA2) != 0) { + /* + * Clear the channel in case we return + * to data phase later. + */ + ahc_outb(ahc, SXFRCTL0, + ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); + ahc_outb(ahc, SXFRCTL0, + ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); + } + if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { + u_int dscommand1; + + /* Ensure HHADDR is 0 for future DMA operations. */ + dscommand1 = ahc_inb(ahc, DSCOMMAND1); + ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); + ahc_outb(ahc, HADDR, 0); + ahc_outb(ahc, DSCOMMAND1, dscommand1); + } break; } - case TRACEPOINT: + case MKMSG_FAILED: { - printf("TRACEPOINT: RETURN_2 = %d\n", ahc_inb(ahc, RETURN_2)); -#if 0 - printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); - printf("SSTAT0 == 0x%x\n", ahc_inb(ahc, SSTAT0)); - printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); - printf("TRACEPOINT: CCHCNT = %d, SG_COUNT = %d\n", - ahc_inb(ahc, CCHCNT), ahc_inb(ahc, SG_COUNT)); - printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); - printf("TRACEPOINT1: CCHADDR = %d, CCHCNT = %d, SCBPTR = %d\n", - ahc_inb(ahc, CCHADDR) - | (ahc_inb(ahc, CCHADDR+1) << 8) - | (ahc_inb(ahc, CCHADDR+2) << 16) - | (ahc_inb(ahc, CCHADDR+3) << 24), - ahc_inb(ahc, CCHCNT) - | (ahc_inb(ahc, CCHCNT+1) << 8) - | (ahc_inb(ahc, CCHCNT+2) << 16), - ahc_inb(ahc, SCBPTR)); - printf("TRACEPOINT: WAITING_SCBH = %d\n", - ahc_inb(ahc, WAITING_SCBH)); - printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); -#endif + u_int scbindex; + + printf("%s:%c:%d:%d: Attempt to issue message failed\n", + ahc_name(ahc), devinfo.channel, devinfo.target, + devinfo.lun); + scbindex = ahc_inb(ahc, SCB_TAG); + scb = ahc_lookup_scb(ahc, scbindex); + if (scb != NULL + && (scb->flags & SCB_RECOVERY_SCB) != 0) + /* + * Ensure that we didn't put a second instance of this + * SCB into the QINFIFO. + */ + ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), + SCB_GET_CHANNEL(ahc, scb), + SCB_GET_LUN(scb), scb->hscb->tag, + ROLE_INITIATOR, /*status*/0, + SEARCH_REMOVE); + break; + } + case NO_FREE_SCB: + { + printf("%s: No free or disconnected SCBs\n", ahc_name(ahc)); + ahc_dump_card_state(ahc); + panic("for safety"); break; } -#if NOT_YET - /* XXX Fill these in later */ - case MESG_BUFFER_BUSY: + case SCB_MISMATCH: + { + u_int scbptr; + + scbptr = ahc_inb(ahc, SCBPTR); + printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n", + scbptr, ahc_inb(ahc, ARG_1), + ahc->scb_data->hscbs[scbptr].tag); + ahc_dump_card_state(ahc); + panic("for saftey"); break; - case MSGIN_PHASEMIS: + } + case OUT_OF_RANGE: + { + printf("%s: BTT calculation out of range\n", ahc_name(ahc)); + printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " + "ARG_1 == 0x%x ACCUM = 0x%x\n", + ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), + ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); + printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " + "SINDEX == 0x%x\n, A == 0x%x\n", + ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), + ahc_index_busy_tcl(ahc, + BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), + ahc_inb(ahc, SAVED_LUN))), + ahc_inb(ahc, SINDEX), + ahc_inb(ahc, ACCUM)); + printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " + "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", + ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), + ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), + ahc_inb(ahc, SCB_CONTROL)); + printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", + ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); + ahc_dump_card_state(ahc); + panic("for safety"); break; -#endif + } default: printf("ahc_intr: seqint, " "intstat == 0x%x, scsisigi = 0x%x\n", intstat, ahc_inb(ahc, SCSISIGI)); break; } - unpause: /* * The sequencer is paused immediately on * a SEQINT, so we should restart it when * we're done. */ - unpause_sequencer(ahc); + ahc_unpause(ahc); } -STATIC void -ahc_handle_scsiint(ahc, intstat) - struct ahc_softc *ahc; - u_int intstat; +void +ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) { u_int scb_index; + u_int status0; u_int status; struct scb *scb; char cur_channel; char intr_channel; + /* Make sure the sequencer is in a safe location. */ + ahc_clear_critical_section(ahc); + if ((ahc->features & AHC_TWIN) != 0 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) cur_channel = 'B'; @@ -2178,34 +955,59 @@ ahc_handle_scsiint(ahc, intstat) cur_channel = 'A'; intr_channel = cur_channel; - status = ahc_inb(ahc, SSTAT1); - if (status == 0) { + if ((ahc->features & AHC_ULTRA2) != 0) + status0 = ahc_inb(ahc, SSTAT0) & IOERR; + else + status0 = 0; + status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); + if (status == 0 && status0 == 0) { if ((ahc->features & AHC_TWIN) != 0) { /* Try the other channel */ ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); - status = ahc_inb(ahc, SSTAT1); - ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); + status = ahc_inb(ahc, SSTAT1) + & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); intr_channel = (cur_channel == 'A') ? 'B' : 'A'; } if (status == 0) { printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); + ahc_outb(ahc, CLRINT, CLRSCSIINT); + ahc_unpause(ahc); return; } } scb_index = ahc_inb(ahc, SCB_TAG); - if (scb_index < ahc->scb_data->numscbs) { - scb = &ahc->scb_data->scbarray[scb_index]; - if ((scb->flags & SCB_ACTIVE) == 0 - || (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0) - scb = NULL; - } else + scb = ahc_lookup_scb(ahc, scb_index); + if (scb != NULL + && (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0) scb = NULL; - if ((status & SCSIRSTI) != 0) { + if ((ahc->features & AHC_ULTRA2) != 0 + && (status0 & IOERR) != 0) { + int now_lvd; + + now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40; + printf("%s: Transceiver State Has Changed to %s mode\n", + ahc_name(ahc), now_lvd ? "LVD" : "SE"); + ahc_outb(ahc, CLRSINT0, CLRIOERR); + /* + * When transitioning to SE mode, the reset line + * glitches, triggering an arbitration bug in some + * Ultra2 controllers. This bug is cleared when we + * assert the reset line. Since a reset glitch has + * already occurred with this transition and a + * transceiver state change is handled just like + * a bus reset anyway, asserting the reset line + * ourselves is safe. + */ + ahc_reset_channel(ahc, intr_channel, + /*Initiate Reset*/now_lvd == 0); + } else if ((status & SCSIRSTI) != 0) { printf("%s: Someone reset channel %c\n", ahc_name(ahc), intr_channel); - ahc_reset_channel(ahc, intr_channel, /* Initiate Reset */FALSE); + if (intr_channel != cur_channel) + ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); + ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE); } else if ((status & SCSIPERR) != 0) { /* * Determine the bus phase and queue an appropriate message. @@ -2221,10 +1023,13 @@ ahc_handle_scsiint(ahc, intstat) u_int curphase; u_int errorphase; u_int lastphase; - int i; + u_int scsirate; + u_int i; + u_int sstat2; lastphase = ahc_inb(ahc, LASTPHASE); curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; + sstat2 = ahc_inb(ahc, SSTAT2); ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); /* * For all phases save DATA, the sequencer won't @@ -2238,28 +1043,40 @@ ahc_handle_scsiint(ahc, intstat) * curphase and lastphase. */ if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 - || curphase == P_DATAIN) + || curphase == P_DATAIN || curphase == P_DATAIN_DT) errorphase = curphase; else errorphase = lastphase; for (i = 0; i < num_phases; i++) { - if (errorphase == phase_table[i].phase) + if (errorphase == ahc_phase_table[i].phase) break; } - mesg_out = phase_table[i].mesg_out; + mesg_out = ahc_phase_table[i].mesg_out; if (scb != NULL) - sc_print_addr(scb->xs->sc_link); + ahc_print_path(ahc, scb); else - printf("%s:%c:%d: ", ahc_name(ahc), - intr_channel, - TCL_TARGET(ahc_inb(ahc, SAVED_TCL))); - + printf("%s:%c:%d: ", ahc_name(ahc), intr_channel, + SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID))); + scsirate = ahc_inb(ahc, SCSIRATE); printf("parity error detected %s. " "SEQADDR(0x%x) SCSIRATE(0x%x)\n", - phase_table[i].phasemsg, + ahc_phase_table[i].phasemsg, ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8), - ahc_inb(ahc, SCSIRATE)); + scsirate); + + if ((ahc->features & AHC_DT) != 0) { + + if ((sstat2 & CRCVALERR) != 0) + printf("\tCRC Value Mismatch\n"); + if ((sstat2 & CRCENDERR) != 0) + printf("\tNo terminal CRC packet recevied\n"); + if ((sstat2 & CRCREQERR) != 0) + printf("\tIllegal CRC packet request\n"); + if ((sstat2 & DUAL_EDGE_ERR) != 0) + printf("\tUnexpected %sDT Data Phase\n", + (scsirate & SINGLE_EDGE) ? "" : "non-"); + } /* * We've set the hardware to assert ATN if we @@ -2275,76 +1092,179 @@ ahc_handle_scsiint(ahc, intstat) ahc_outb(ahc, MSG_OUT, mesg_out); } ahc_outb(ahc, CLRINT, CLRSCSIINT); - unpause_sequencer(ahc); + ahc_unpause(ahc); + } else if ((status & SELTO) != 0) { + u_int scbptr; + + /* Stop the selection */ + ahc_outb(ahc, SCSISEQ, 0); + + /* No more pending messages */ + ahc_clear_msg_state(ahc); + + /* Clear interrupt state */ + ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); + ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); + + /* + * Although the driver does not care about the + * 'Selection in Progress' status bit, the busy + * LED does. SELINGO is only cleared by a sucessfull + * selection, so we must manually clear it to insure + * the LED turns off just incase no future successful + * selections occur (e.g. no devices on the bus). + */ + ahc_outb(ahc, CLRSINT0, CLRSELINGO); + + scbptr = ahc_inb(ahc, WAITING_SCBH); + ahc_outb(ahc, SCBPTR, scbptr); + scb_index = ahc_inb(ahc, SCB_TAG); + + scb = ahc_lookup_scb(ahc, scb_index); + if (scb == NULL) { + printf("%s: ahc_intr - referenced scb not " + "valid during SELTO scb(%d, %d)\n", + ahc_name(ahc), scbptr, scb_index); + } else { + ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT); + ahc_freeze_devq(ahc, scb); + } + ahc_outb(ahc, CLRINT, CLRSCSIINT); + ahc_restart(ahc); } else if ((status & BUSFREE) != 0 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { + u_int lastphase; + u_int saved_scsiid; + u_int saved_lun; + u_int target; + u_int initiator_role_id; + char channel; + int printerror; + /* - * First look at what phase we were last in. + * Clear our selection hardware as soon as possible. + * We may have an entry in the waiting Q for this target, + * that is affected by this busfree and we don't want to + * go about selecting the target while we handle the event. + */ + ahc_outb(ahc, SCSISEQ, + ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); + + /* + * Disable busfree interrupts and clear the busfree + * interrupt status. We do this here so that several + * bus transactions occur prior to clearing the SCSIINT + * latch. It can take a bit for the clearing to take effect. + */ + ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); + ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); + + /* + * Look at what phase we were last in. * If its message out, chances are pretty good * that the busfree was in response to one of * our abort requests. */ - u_int lastphase = ahc_inb(ahc, LASTPHASE); - u_int saved_tcl = ahc_inb(ahc, SAVED_TCL); - u_int target = TCL_TARGET(saved_tcl); - u_int initiator_role_id = TCL_SCSI_ID(ahc, saved_tcl); - char channel = TCL_CHANNEL(ahc, saved_tcl); - int printerror = 1; + lastphase = ahc_inb(ahc, LASTPHASE); + saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); + saved_lun = ahc_inb(ahc, SAVED_LUN); + target = SCSIID_TARGET(ahc, saved_scsiid); + initiator_role_id = SCSIID_OUR_ID(saved_scsiid); + channel = SCSIID_CHANNEL(ahc, saved_scsiid); + printerror = 1; - ahc_outb(ahc, SCSISEQ, - ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); if (lastphase == P_MESGOUT) { - u_int message; + struct ahc_devinfo devinfo; u_int tag; - message = ahc->msgout_buf[ahc->msgout_index - 1]; + ahc_fetch_devinfo(ahc, &devinfo); tag = SCB_LIST_NULL; - switch (message) { - case MSG_ABORT_TAG: - tag = scb->hscb->tag; - /* FALLTRHOUGH */ - case MSG_ABORT: - sc_print_addr(scb->xs->sc_link); - printf("SCB %d - Abort %s Completed.\n", + if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE) + || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) { + if (ahc->msgout_buf[ahc->msgout_index - 1] + == MSG_ABORT_TAG) + tag = scb->hscb->tag; + ahc_print_path(ahc, scb); + printf("SCB %d - Abort%s Completed.\n", scb->hscb->tag, tag == SCB_LIST_NULL ? - "" : "Tag"); + "" : " Tag"); ahc_abort_scbs(ahc, target, channel, - TCL_LUN(saved_tcl), tag, + saved_lun, tag, ROLE_INITIATOR, - XS_DRIVER_STUFFUP); + CAM_REQ_ABORTED); printerror = 0; - break; - case MSG_BUS_DEV_RESET: - { + } else if (ahc_sent_msg(ahc, AHCMSG_1B, + MSG_BUS_DEV_RESET, TRUE)) { struct ahc_devinfo devinfo; - - if (scb != NULL && - (scb->xs->flags & SCSI_RESET) - && ahc_match_scb(scb, target, channel, - TCL_LUN(saved_tcl), +#ifdef __FreeBSD__ + /* + * Don't mark the user's request for this BDR + * as completing with CAM_BDR_SENT. CAM3 + * specifies CAM_REQ_CMP. + */ + if (scb != NULL + && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV + && ahc_match_scb(ahc, scb, target, channel, + CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_INITIATOR)) { - ahcsetccbstatus(scb->xs, XS_NOERROR); + ahc_set_transaction_status(scb, CAM_REQ_CMP); } +#endif ahc_compile_devinfo(&devinfo, initiator_role_id, target, - TCL_LUN(saved_tcl), + CAM_LUN_WILDCARD, channel, ROLE_INITIATOR); ahc_handle_devreset(ahc, &devinfo, - XS_RESET, + CAM_BDR_SENT, "Bus Device Reset", /*verbose_level*/0); printerror = 0; - break; - } - default: - break; + } else if (ahc_sent_msg(ahc, AHCMSG_EXT, + MSG_EXT_PPR, FALSE)) { + struct ahc_initiator_tinfo *tinfo; + struct ahc_tmode_tstate *tstate; + + /* + * PPR Rejected. Try non-ppr negotiation + * and retry command. + */ + tinfo = ahc_fetch_transinfo(ahc, + devinfo.channel, + devinfo.our_scsiid, + devinfo.target, + &tstate); + tinfo->curr.transport_version = 2; + tinfo->goal.transport_version = 2; + tinfo->goal.ppr_options = 0; + ahc_qinfifo_requeue_tail(ahc, scb); + printerror = 0; + } else if (ahc_sent_msg(ahc, AHCMSG_EXT, + MSG_EXT_WDTR, FALSE) + || ahc_sent_msg(ahc, AHCMSG_EXT, + MSG_EXT_SDTR, FALSE)) { + /* + * Negotiation Rejected. Go-async and + * retry command. + */ + ahc_set_width(ahc, &devinfo, + MSG_EXT_WDTR_BUS_8_BIT, + AHC_TRANS_CUR|AHC_TRANS_GOAL, + /*paused*/TRUE); + ahc_set_syncrate(ahc, &devinfo, + /*syncrate*/NULL, + /*period*/0, /*offset*/0, + /*ppr_options*/0, + AHC_TRANS_CUR|AHC_TRANS_GOAL, + /*paused*/TRUE); + ahc_qinfifo_requeue_tail(ahc, scb); + printerror = 0; } } if (printerror != 0) { - int i; + u_int i; if (scb != NULL) { u_int tag; @@ -2353,11 +1273,11 @@ ahc_handle_scsiint(ahc, intstat) tag = scb->hscb->tag; else tag = SCB_LIST_NULL; + ahc_print_path(ahc, scb); ahc_abort_scbs(ahc, target, channel, - SCB_LUN(scb), tag, + SCB_GET_LUN(scb), tag, ROLE_INITIATOR, - XS_DRIVER_STUFFUP); - sc_print_addr(scb->xs->sc_link); + CAM_UNEXP_BUSFREE); } else { /* * We had not fully identified this connection, @@ -2366,127 +1286,847 @@ ahc_handle_scsiint(ahc, intstat) printf("%s: ", ahc_name(ahc)); } for (i = 0; i < num_phases; i++) { - if (lastphase == phase_table[i].phase) + if (lastphase == ahc_phase_table[i].phase) break; } printf("Unexpected busfree %s\n" "SEQADDR == 0x%x\n", - phase_table[i].phasemsg, ahc_inb(ahc, SEQADDR0) + ahc_phase_table[i].phasemsg, + ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); } ahc_clear_msg_state(ahc); - ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); - ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); ahc_outb(ahc, CLRINT, CLRSCSIINT); - restart_sequencer(ahc); - } else if ((status & SELTO) != 0) { - u_int scbptr; + ahc_restart(ahc); + } else { + printf("%s: Missing case in ahc_handle_scsiint. status = %x\n", + ahc_name(ahc), status); + ahc_outb(ahc, CLRINT, CLRSCSIINT); + } +} - scbptr = ahc_inb(ahc, WAITING_SCBH); - ahc_outb(ahc, SCBPTR, scbptr); - scb_index = ahc_inb(ahc, SCB_TAG); +#define AHC_MAX_STEPS 2000 +void +ahc_clear_critical_section(struct ahc_softc *ahc) +{ + int stepping; + int steps; + u_int simode0; + u_int simode1; - if (scb_index < ahc->scb_data->numscbs) { - scb = &ahc->scb_data->scbarray[scb_index]; - if ((scb->flags & SCB_ACTIVE) == 0) - scb = NULL; - } else - scb = NULL; + if (ahc->num_critical_sections == 0) + return; - if (scb == NULL) { - printf("%s: ahc_intr - referenced scb not " - "valid during SELTO scb(%d, %d)\n", - ahc_name(ahc), scbptr, scb_index); - } else { - u_int tag; + stepping = FALSE; + steps = 0; + simode0 = 0; + simode1 = 0; + for (;;) { + struct cs *cs; + u_int seqaddr; + u_int i; - tag = SCB_LIST_NULL; - if ((scb->hscb->control & TAG_ENB) != 0) - tag = scb->hscb->tag; + seqaddr = ahc_inb(ahc, SEQADDR0) + | (ahc_inb(ahc, SEQADDR1) << 8); - ahc_abort_scbs(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), - SCB_LUN(scb), tag, - ROLE_INITIATOR, XS_SELTIMEOUT); + /* + * Seqaddr represents the next instruction to execute, + * so we are really executing the instruction just + * before it. + */ + if (seqaddr != 0) + seqaddr -= 1; + cs = ahc->critical_sections; + for (i = 0; i < ahc->num_critical_sections; i++, cs++) { + + if (cs->begin < seqaddr && cs->end >= seqaddr) + break; } - /* Stop the selection */ - ahc_outb(ahc, SCSISEQ, 0); - /* No more pending messages */ - ahc_clear_msg_state(ahc); + if (i == ahc->num_critical_sections) + break; + + if (steps > AHC_MAX_STEPS) { + printf("%s: Infinite loop in critical section\n", + ahc_name(ahc)); + ahc_dump_card_state(ahc); + panic("critical section loop"); + } + + steps++; + if (stepping == FALSE) { + + /* + * Disable all interrupt sources so that the + * sequencer will not be stuck by a pausing + * interrupt condition while we attempt to + * leave a critical section. + */ + simode0 = ahc_inb(ahc, SIMODE0); + ahc_outb(ahc, SIMODE0, 0); + simode1 = ahc_inb(ahc, SIMODE1); + ahc_outb(ahc, SIMODE1, 0); + ahc_outb(ahc, CLRINT, CLRSCSIINT); + ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) | STEP); + stepping = TRUE; + } + ahc_outb(ahc, HCNTRL, ahc->unpause); + do { + ahc_delay(200); + } while (!ahc_is_paused(ahc)); + } + if (stepping) { + ahc_outb(ahc, SIMODE0, simode0); + ahc_outb(ahc, SIMODE1, simode1); + ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) & ~STEP); + } +} + +/* + * Clear any pending interrupt status. + */ +void +ahc_clear_intstat(struct ahc_softc *ahc) +{ + /* Clear any interrupt conditions this may have caused */ + ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI + |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| + CLRREQINIT); + ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); + ahc_outb(ahc, CLRINT, CLRSCSIINT); +} + +/**************************** Debugging Routines ******************************/ +void +ahc_print_scb(struct scb *scb) +{ + int i; + + struct hardware_scb *hscb = scb->hscb; + + printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", + (void *)scb, + hscb->control, + hscb->scsiid, + hscb->lun, + hscb->cdb_len); + printf("Shared Data: "); + for (i = 0; i < sizeof(hscb->shared_data.cdb); i++) + printf("%#02x", hscb->shared_data.cdb[i]); + printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n", + ahc_le32toh(hscb->dataptr), + ahc_le32toh(hscb->datacnt), + ahc_le32toh(hscb->sgptr), + hscb->tag); + if (scb->sg_count > 0) { + for (i = 0; i < scb->sg_count; i++) { + printf("sg[%d] - Addr 0x%x%x : Length %d\n", + i, + (ahc_le32toh(scb->sg_list[i].len) >> 24 + & SG_HIGH_ADDR_BITS), + ahc_le32toh(scb->sg_list[i].addr), + ahc_le32toh(scb->sg_list[i].len)); + } + } +} + +/************************* Transfer Negotiation *******************************/ +/* + * Allocate per target mode instance (ID we respond to as a target) + * transfer negotiation data structures. + */ +static struct ahc_tmode_tstate * +ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) +{ + struct ahc_tmode_tstate *master_tstate; + struct ahc_tmode_tstate *tstate; + int i; + + master_tstate = ahc->enabled_targets[ahc->our_id]; + if (channel == 'B') { + scsi_id += 8; + master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; + } + if (ahc->enabled_targets[scsi_id] != NULL + && ahc->enabled_targets[scsi_id] != master_tstate) + panic("%s: ahc_alloc_tstate - Target already allocated", + ahc_name(ahc)); + tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); + if (tstate == NULL) + return (NULL); + + /* + * If we have allocated a master tstate, copy user settings from + * the master tstate (taken from SRAM or the EEPROM) for this + * channel, but reset our current and goal settings to async/narrow + * until an initiator talks to us. + */ + if (master_tstate != NULL) { + memcpy(tstate, master_tstate, sizeof(*tstate)); + memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); + tstate->ultraenb = 0; + for (i = 0; i < 16; i++) { + memset(&tstate->transinfo[i].curr, 0, + sizeof(tstate->transinfo[i].curr)); + memset(&tstate->transinfo[i].goal, 0, + sizeof(tstate->transinfo[i].goal)); + } + } else + memset(tstate, 0, sizeof(*tstate)); + ahc->enabled_targets[scsi_id] = tstate; + return (tstate); +} + +#ifdef AHC_TARGET_MODE +/* + * Free per target mode instance (ID we respond to as a target) + * transfer negotiation data structures. + */ +static void +ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) +{ + struct ahc_tmode_tstate *tstate; + + /* + * Don't clean up our "master" tstate. + * It has our default user settings. + */ + if (((channel == 'B' && scsi_id == ahc->our_id_b) + || (channel == 'A' && scsi_id == ahc->our_id)) + && force == FALSE) + return; + + if (channel == 'B') + scsi_id += 8; + tstate = ahc->enabled_targets[scsi_id]; + if (tstate != NULL) + free(tstate, M_DEVBUF); + ahc->enabled_targets[scsi_id] = NULL; +} +#endif + +/* + * Called when we have an active connection to a target on the bus, + * this function finds the nearest syncrate to the input period limited + * by the capabilities of the bus connectivity of and sync settings for + * the target. + */ +struct ahc_syncrate * +ahc_devlimited_syncrate(struct ahc_softc *ahc, + struct ahc_initiator_tinfo *tinfo, + u_int *period, u_int *ppr_options, role_t role) { + struct ahc_transinfo *transinfo; + u_int maxsync; + + if ((ahc->features & AHC_ULTRA2) != 0) { + if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 + && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { + maxsync = AHC_SYNCRATE_DT; + } else { + maxsync = AHC_SYNCRATE_ULTRA; + /* Can't do DT on an SE bus */ + *ppr_options &= ~MSG_EXT_PPR_DT_REQ; + } + } else if ((ahc->features & AHC_ULTRA) != 0) { + maxsync = AHC_SYNCRATE_ULTRA; + } else { + maxsync = AHC_SYNCRATE_FAST; + } + /* + * Never allow a value higher than our current goal + * period otherwise we may allow a target initiated + * negotiation to go above the limit as set by the + * user. In the case of an initiator initiated + * sync negotiation, we limit based on the user + * setting. This allows the system to still accept + * incoming negotiations even if target initiated + * negotiation is not performed. + */ + if (role == ROLE_TARGET) + transinfo = &tinfo->user; + else + transinfo = &tinfo->goal; + *ppr_options &= transinfo->ppr_options; + if (transinfo->period == 0) { + *period = 0; + *ppr_options = 0; + return (NULL); + } + *period = MAX(*period, transinfo->period); + return (ahc_find_syncrate(ahc, period, ppr_options, maxsync)); +} + +/* + * Look up the valid period to SCSIRATE conversion in our table. + * Return the period and offset that should be sent to the target + * if this was the beginning of an SDTR. + */ +struct ahc_syncrate * +ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, + u_int *ppr_options, u_int maxsync) +{ + struct ahc_syncrate *syncrate; + + if ((ahc->features & AHC_DT) == 0) + *ppr_options &= ~MSG_EXT_PPR_DT_REQ; + + /* Skip all DT only entries if DT is not available */ + if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 + && maxsync < AHC_SYNCRATE_ULTRA2) + maxsync = AHC_SYNCRATE_ULTRA2; + + for (syncrate = &ahc_syncrates[maxsync]; + syncrate->rate != NULL; + syncrate++) { /* - * Although the driver does not care about the - * 'Selection in Progress' status bit, the busy - * LED does. SELINGO is only cleared by a sucessful - * selection, so we must manually clear it to ensure - * the LED turns off just incase no future successful - * selections occur (e.g. no devices on the bus). + * The Ultra2 table doesn't go as low + * as for the Fast/Ultra cards. */ - ahc_outb(ahc, CLRSINT0, CLRSELINGO); + if ((ahc->features & AHC_ULTRA2) != 0 + && (syncrate->sxfr_u2 == 0)) + break; - /* Clear interrupt state */ - ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); - ahc_outb(ahc, CLRINT, CLRSCSIINT); - restart_sequencer(ahc); + if (*period <= syncrate->period) { + /* + * When responding to a target that requests + * sync, the requested rate may fall between + * two rates that we can output, but still be + * a rate that we can receive. Because of this, + * we want to respond to the target with + * the same rate that it sent to us even + * if the period we use to send data to it + * is lower. Only lower the response period + * if we must. + */ + if (syncrate == &ahc_syncrates[maxsync]) + *period = syncrate->period; + + /* + * At some speeds, we only support + * ST transfers. + */ + if ((syncrate->sxfr_u2 & ST_SXFR) != 0) + *ppr_options &= ~MSG_EXT_PPR_DT_REQ; + break; + } + } + + if ((*period == 0) + || (syncrate->rate == NULL) + || ((ahc->features & AHC_ULTRA2) != 0 + && (syncrate->sxfr_u2 == 0))) { + /* Use asynchronous transfers. */ + *period = 0; + syncrate = NULL; + *ppr_options &= ~MSG_EXT_PPR_DT_REQ; + } + return (syncrate); +} + +/* + * Convert from an entry in our syncrate table to the SCSI equivalent + * sync "period" factor. + */ +u_int +ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) +{ + struct ahc_syncrate *syncrate; + + if ((ahc->features & AHC_ULTRA2) != 0) + scsirate &= SXFR_ULTRA2; + else + scsirate &= SXFR; + + syncrate = &ahc_syncrates[maxsync]; + while (syncrate->rate != NULL) { + + if ((ahc->features & AHC_ULTRA2) != 0) { + if (syncrate->sxfr_u2 == 0) + break; + else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) + return (syncrate->period); + } else if (scsirate == (syncrate->sxfr & SXFR)) { + return (syncrate->period); + } + syncrate++; + } + return (0); /* async */ +} + +/* + * Truncate the given synchronous offset to a value the + * current adapter type and syncrate are capable of. + */ +void +ahc_validate_offset(struct ahc_softc *ahc, + struct ahc_initiator_tinfo *tinfo, + struct ahc_syncrate *syncrate, + u_int *offset, int wide, role_t role) +{ + u_int maxoffset; + + /* Limit offset to what we can do */ + if (syncrate == NULL) { + maxoffset = 0; + } else if ((ahc->features & AHC_ULTRA2) != 0) { + maxoffset = MAX_OFFSET_ULTRA2; } else { - sc_print_addr(scb->xs->sc_link); - printf("Unknown SCSIINT. Status = 0x%x\n", status); - ahc_outb(ahc, CLRSINT1, status); - ahc_outb(ahc, CLRINT, CLRSCSIINT); - unpause_sequencer(ahc); + if (wide) + maxoffset = MAX_OFFSET_16BIT; + else + maxoffset = MAX_OFFSET_8BIT; + } + *offset = MIN(*offset, maxoffset); + if (tinfo != NULL) { + if (role == ROLE_TARGET) + *offset = MIN(*offset, tinfo->user.offset); + else + *offset = MIN(*offset, tinfo->goal.offset); } } -STATIC void -ahc_build_transfer_msg(ahc, devinfo) - struct ahc_softc *ahc; - struct ahc_devinfo *devinfo; +/* + * Truncate the given transfer width parameter to a value the + * current adapter type is capable of. + */ +void +ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo, + u_int *bus_width, role_t role) +{ + switch (*bus_width) { + default: + if (ahc->features & AHC_WIDE) { + /* Respond Wide */ + *bus_width = MSG_EXT_WDTR_BUS_16_BIT; + break; + } + /* FALLTHROUGH */ + case MSG_EXT_WDTR_BUS_8_BIT: + *bus_width = MSG_EXT_WDTR_BUS_8_BIT; + break; + } + if (tinfo != NULL) { + if (role == ROLE_TARGET) + *bus_width = MIN(tinfo->user.width, *bus_width); + else + *bus_width = MIN(tinfo->goal.width, *bus_width); + } +} + +/* + * Update the bitmask of targets for which the controller should + * negotiate with at the next convenient oportunity. This currently + * means the next time we send the initial identify messages for + * a new transaction. + */ +int +ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, + struct ahc_tmode_tstate *tstate, + struct ahc_initiator_tinfo *tinfo, int force) +{ + u_int auto_negotiate_orig; + + auto_negotiate_orig = tstate->auto_negotiate; + if (tinfo->curr.period != tinfo->goal.period + || tinfo->curr.width != tinfo->goal.width + || tinfo->curr.offset != tinfo->goal.offset + || tinfo->curr.ppr_options != tinfo->goal.ppr_options + || (force + && (tinfo->goal.period != 0 + || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT + || tinfo->goal.ppr_options != 0))) + tstate->auto_negotiate |= devinfo->target_mask; + else + tstate->auto_negotiate &= ~devinfo->target_mask; + + return (auto_negotiate_orig != tstate->auto_negotiate); +} + +/* + * Update the user/goal/curr tables of synchronous negotiation + * parameters as well as, in the case of a current or active update, + * any data structures on the host controller. In the case of an + * active update, the specified target is currently talking to us on + * the bus, so the transfer parameter update must take effect + * immediately. + */ +void +ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, + struct ahc_syncrate *syncrate, u_int period, + u_int offset, u_int ppr_options, u_int type, int paused) { - /* - * We need to initiate transfer negotiations. - * If our current and goal settings are identical, - * we want to renegotiate due to a check condition. - */ struct ahc_initiator_tinfo *tinfo; - struct tmode_tstate *tstate; - int dowide; - int dosync; + struct ahc_tmode_tstate *tstate; + u_int old_period; + u_int old_offset; + u_int old_ppr; + int active; + int update_needed; - tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, - devinfo->our_scsiid, + active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; + update_needed = 0; + + if (syncrate == NULL) { + period = 0; + offset = 0; + } + + tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, devinfo->target, &tstate); - dowide = tinfo->current.width != tinfo->goal.width; - dosync = tinfo->current.period != tinfo->goal.period; - if (!dowide && !dosync) { - dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; - dosync = tinfo->goal.period != 0; + if ((type & AHC_TRANS_USER) != 0) { + tinfo->user.period = period; + tinfo->user.offset = offset; + tinfo->user.ppr_options = ppr_options; } - if (dowide) { - ahc_construct_wdtr(ahc, tinfo->goal.width); - } else if (dosync) { - struct ahc_syncrate *rate; - u_int period; - u_int offset; + if ((type & AHC_TRANS_GOAL) != 0) { + tinfo->goal.period = period; + tinfo->goal.offset = offset; + tinfo->goal.ppr_options = ppr_options; + } - period = tinfo->goal.period; - rate = ahc_devlimited_syncrate(ahc, &period); - offset = tinfo->goal.offset; - ahc_validate_offset(ahc, rate, &offset, - tinfo->current.width); - ahc_construct_sdtr(ahc, period, offset); + old_period = tinfo->curr.period; + old_offset = tinfo->curr.offset; + old_ppr = tinfo->curr.ppr_options; + + if ((type & AHC_TRANS_CUR) != 0 + && (old_period != period + || old_offset != offset + || old_ppr != ppr_options)) { + u_int scsirate; + + update_needed++; + scsirate = tinfo->scsirate; + if ((ahc->features & AHC_ULTRA2) != 0) { + + scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); + if (syncrate != NULL) { + scsirate |= syncrate->sxfr_u2; + if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) + scsirate |= ENABLE_CRC; + else + scsirate |= SINGLE_EDGE; + } + } else { + + scsirate &= ~(SXFR|SOFS); + /* + * Ensure Ultra mode is set properly for + * this target. + */ + tstate->ultraenb &= ~devinfo->target_mask; + if (syncrate != NULL) { + if (syncrate->sxfr & ULTRA_SXFR) { + tstate->ultraenb |= + devinfo->target_mask; + } + scsirate |= syncrate->sxfr & SXFR; + scsirate |= offset & SOFS; + } + if (active) { + u_int sxfrctl0; + + sxfrctl0 = ahc_inb(ahc, SXFRCTL0); + sxfrctl0 &= ~FAST20; + if (tstate->ultraenb & devinfo->target_mask) + sxfrctl0 |= FAST20; + ahc_outb(ahc, SXFRCTL0, sxfrctl0); + } + } + if (active) { + ahc_outb(ahc, SCSIRATE, scsirate); + if ((ahc->features & AHC_ULTRA2) != 0) + ahc_outb(ahc, SCSIOFFSET, offset); + } + + tinfo->scsirate = scsirate; + tinfo->curr.period = period; + tinfo->curr.offset = offset; + tinfo->curr.ppr_options = ppr_options; + + ahc_send_async(ahc, devinfo->channel, devinfo->target, + CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); + if (1 /*bootverbose*/) { + if (offset != 0) { + printf("%s: target %d synchronous at %sMHz%s, " + "offset = 0x%x\n", ahc_name(ahc), + devinfo->target, syncrate->rate, + (ppr_options & MSG_EXT_PPR_DT_REQ) + ? " DT" : "", offset); + } else { + printf("%s: target %d using " + "asynchronous transfers\n", + ahc_name(ahc), devinfo->target); + } + } + } + + update_needed += ahc_update_neg_request(ahc, devinfo, tstate, + tinfo, /*force*/FALSE); + + if (update_needed) + ahc_update_pending_scbs(ahc); +} + +/* + * Update the user/goal/curr tables of wide negotiation + * parameters as well as, in the case of a current or active update, + * any data structures on the host controller. In the case of an + * active update, the specified target is currently talking to us on + * the bus, so the transfer parameter update must take effect + * immediately. + */ +void +ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, + u_int width, u_int type, int paused) +{ + struct ahc_initiator_tinfo *tinfo; + struct ahc_tmode_tstate *tstate; + u_int oldwidth; + int active; + int update_needed; + + active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; + update_needed = 0; + tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, + devinfo->target, &tstate); + + if ((type & AHC_TRANS_USER) != 0) + tinfo->user.width = width; + + if ((type & AHC_TRANS_GOAL) != 0) + tinfo->goal.width = width; + + oldwidth = tinfo->curr.width; + if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { + u_int scsirate; + + update_needed++; + scsirate = tinfo->scsirate; + scsirate &= ~WIDEXFER; + if (width == MSG_EXT_WDTR_BUS_16_BIT) + scsirate |= WIDEXFER; + + tinfo->scsirate = scsirate; + + if (active) + ahc_outb(ahc, SCSIRATE, scsirate); + + tinfo->curr.width = width; + + ahc_send_async(ahc, devinfo->channel, devinfo->target, + CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); + if (bootverbose) { + printf("%s: target %d using %dbit transfers\n", + ahc_name(ahc), devinfo->target, + 8 * (0x01 << width)); + } + } + + update_needed += ahc_update_neg_request(ahc, devinfo, tstate, + tinfo, /*force*/FALSE); + if (update_needed) + ahc_update_pending_scbs(ahc); +} + +/* + * Update the current state of tagged queuing for a given target. + */ +void +ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, + ahc_queue_alg alg) +{ + ahc_platform_set_tags(ahc, devinfo, alg); + ahc_send_async(ahc, devinfo->channel, devinfo->target, + devinfo->lun, AC_TRANSFER_NEG, &alg); +} + +/* + * When the transfer settings for a connection change, update any + * in-transit SCBs to contain the new data so the hardware will + * be set correctly during future (re)selections. + */ +static void +ahc_update_pending_scbs(struct ahc_softc *ahc) +{ + struct scb *pending_scb; + int pending_scb_count; + int i; + int paused; + u_int saved_scbptr; + + /* + * Traverse the pending SCB list and ensure that all of the + * SCBs there have the proper settings. + */ + pending_scb_count = 0; + LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) { + struct ahc_devinfo devinfo; + struct hardware_scb *pending_hscb; + struct ahc_initiator_tinfo *tinfo; + struct ahc_tmode_tstate *tstate; + + ahc_scb_devinfo(ahc, &devinfo, pending_scb); + tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, + devinfo.our_scsiid, + devinfo.target, &tstate); + pending_hscb = pending_scb->hscb; + pending_hscb->control &= ~ULTRAENB; + if ((tstate->ultraenb & devinfo.target_mask) != 0) + pending_hscb->control |= ULTRAENB; + pending_hscb->scsirate = tinfo->scsirate; + pending_hscb->scsioffset = tinfo->curr.offset; + if ((tstate->auto_negotiate & devinfo.target_mask) == 0 + && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { + pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; + pending_hscb->control &= ~MK_MESSAGE; + } + ahc_sync_scb(ahc, pending_scb, + BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); + pending_scb_count++; + } + + if (pending_scb_count == 0) + return; + + if (ahc_is_paused(ahc)) { + paused = 1; } else { - panic("ahc_intr: AWAITING_MSG for negotiation, " - "but no negotiation needed\n"); + paused = 0; + ahc_pause(ahc); + } + + saved_scbptr = ahc_inb(ahc, SCBPTR); + /* Ensure that the hscbs down on the card match the new information */ + for (i = 0; i < ahc->scb_data->maxhscbs; i++) { + struct hardware_scb *pending_hscb; + u_int control; + u_int scb_tag; + + ahc_outb(ahc, SCBPTR, i); + scb_tag = ahc_inb(ahc, SCB_TAG); + pending_scb = ahc_lookup_scb(ahc, scb_tag); + if (pending_scb == NULL) + continue; + + pending_hscb = pending_scb->hscb; + control = ahc_inb(ahc, SCB_CONTROL); + control &= ~(ULTRAENB|MK_MESSAGE); + control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE); + ahc_outb(ahc, SCB_CONTROL, control); + ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate); + ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset); } + ahc_outb(ahc, SCBPTR, saved_scbptr); + + if (paused == 0) + ahc_unpause(ahc); } -STATIC void -ahc_setup_initiator_msgout(ahc, devinfo, scb) - struct ahc_softc *ahc; - struct ahc_devinfo *devinfo; - struct scb *scb; +/**************************** Pathing Information *****************************/ +static void +ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) +{ + u_int saved_scsiid; + role_t role; + int our_id; + + if (ahc_inb(ahc, SSTAT0) & TARGET) + role = ROLE_TARGET; + else + role = ROLE_INITIATOR; + + if (role == ROLE_TARGET + && (ahc->features & AHC_MULTI_TID) != 0 + && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { + /* We were selected, so pull our id from TARGIDIN */ + our_id = ahc_inb(ahc, TARGIDIN) & OID; + } else if ((ahc->features & AHC_ULTRA2) != 0) + our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; + else + our_id = ahc_inb(ahc, SCSIID) & OID; + + saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); + ahc_compile_devinfo(devinfo, + our_id, + SCSIID_TARGET(ahc, saved_scsiid), + ahc_inb(ahc, SAVED_LUN), + SCSIID_CHANNEL(ahc, saved_scsiid), + role); +} + +struct ahc_phase_table_entry* +ahc_lookup_phase_entry(int phase) +{ + struct ahc_phase_table_entry *entry; + struct ahc_phase_table_entry *last_entry; + + /* + * num_phases doesn't include the default entry which + * will be returned if the phase doesn't match. + */ + last_entry = &ahc_phase_table[num_phases]; + for (entry = ahc_phase_table; entry < last_entry; entry++) { + if (phase == entry->phase) + break; + } + return (entry); +} + +void +ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, + u_int lun, char channel, role_t role) +{ + devinfo->our_scsiid = our_id; + devinfo->target = target; + devinfo->lun = lun; + devinfo->target_offset = target; + devinfo->channel = channel; + devinfo->role = role; + if (channel == 'B') + devinfo->target_offset += 8; + devinfo->target_mask = (0x01 << devinfo->target_offset); +} + +static void +ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, + struct scb *scb) +{ + role_t role; + int our_id; + + our_id = SCSIID_OUR_ID(scb->hscb->scsiid); + role = ROLE_INITIATOR; + if ((scb->hscb->control & TARGET_SCB) != 0) + role = ROLE_TARGET; + ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb), + SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role); +} + + +/************************ Message Phase Processing ****************************/ +static void +ahc_assert_atn(struct ahc_softc *ahc) +{ + u_int scsisigo; + + scsisigo = ATNO; + if ((ahc->features & AHC_DT) == 0) + scsisigo |= ahc_inb(ahc, SCSISIGI); + ahc_outb(ahc, SCSISIGO, scsisigo); +} + +/* + * When an initiator transaction with the MK_MESSAGE flag either reconnects + * or enters the initial message out phase, we are interrupted. Fill our + * outgoing message buffer with the appropriate message and beging handing + * the message phase(s) manually. + */ +static void +ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, + struct scb *scb) { /* * To facilitate adding multiple messages together, @@ -2500,15 +2140,15 @@ ahc_setup_initiator_msgout(ahc, devinfo, scb) && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { u_int identify_msg; - identify_msg = MSG_IDENTIFYFLAG | SCB_LUN(scb); + identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); if ((scb->hscb->control & DISCENB) != 0) identify_msg |= MSG_IDENTIFY_DISCFLAG; ahc->msgout_buf[ahc->msgout_index++] = identify_msg; ahc->msgout_len++; if ((scb->hscb->control & TAG_ENB) != 0) { - /* XXX fvdl FreeBSD has tag action passed down */ - ahc->msgout_buf[ahc->msgout_index++] = MSG_SIMPLE_Q_TAG; + ahc->msgout_buf[ahc->msgout_index++] = + scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; ahc->msgout_len += 2; } @@ -2517,22 +2157,40 @@ ahc_setup_initiator_msgout(ahc, devinfo, scb) if (scb->flags & SCB_DEVICE_RESET) { ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; ahc->msgout_len++; - - sc_print_addr(scb->xs->sc_link); + ahc_print_path(ahc, scb); printf("Bus Device Reset Message Sent\n"); - } else if (scb->flags & SCB_ABORT) { + /* + * Clear our selection hardware in advance of + * the busfree. We may have an entry in the waiting + * Q for this target, and we don't want to go about + * selecting while we handle the busfree and blow it + * away. + */ + ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); + } else if ((scb->flags & SCB_ABORT) != 0) { if ((scb->hscb->control & TAG_ENB) != 0) ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; else ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; ahc->msgout_len++; - sc_print_addr(scb->xs->sc_link); - printf("Abort Message Sent\n"); - } else if ((ahc->targ_msg_req & devinfo->target_mask) != 0) { + ahc_print_path(ahc, scb); + printf("Abort%s Message Sent\n", + (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); + /* + * Clear our selection hardware in advance of + * the busfree. We may have an entry in the waiting + * Q for this target, and we don't want to go about + * selecting while we handle the busfree and blow it + * away. + */ + ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); + } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { ahc_build_transfer_msg(ahc, devinfo); } else { printf("ahc_intr: AWAITING_MSG for an SCB that " - "does not have a waiting message"); + "does not have a waiting message\n"); + printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, + devinfo->target_mask); panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " "SCB flags = %x", scb->hscb->tag, scb->hscb->control, ahc_inb(ahc, MSG_OUT), scb->flags); @@ -2543,153 +2201,186 @@ ahc_setup_initiator_msgout(ahc, devinfo, scb) * asked to send this message again. */ ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); + scb->hscb->control &= ~MK_MESSAGE; ahc->msgout_index = 0; ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; } -STATIC void -ahc_setup_target_msgin(ahc, devinfo) - struct ahc_softc *ahc; - struct ahc_devinfo *devinfo; +/* + * Build an appropriate transfer negotiation message for the + * currently active target. + */ +static void +ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) { /* - * To facilitate adding multiple messages together, - * each routine should increment the index and len - * variables instead of setting them explicitly. + * We need to initiate transfer negotiations. + * If our current and goal settings are identical, + * we want to renegotiate due to a check condition. */ - ahc->msgout_index = 0; - ahc->msgout_len = 0; - - if ((ahc->targ_msg_req & devinfo->target_mask) != 0) - ahc_build_transfer_msg(ahc, devinfo); - else - panic("ahc_intr: AWAITING target message with no message"); - - ahc->msgout_index = 0; - ahc->msg_type = MSG_TYPE_TARGET_MSGIN; -} + struct ahc_initiator_tinfo *tinfo; + struct ahc_tmode_tstate *tstate; + struct ahc_syncrate *rate; + int dowide; + int dosync; + int doppr; + int use_ppr; + u_int period; + u_int ppr_options; + u_int offset; -STATIC int -ahc_handle_msg_reject(ahc, devinfo) - struct ahc_softc *ahc; - struct ahc_devinfo *devinfo; -{ + tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, + devinfo->target, &tstate); /* - * What we care about here is if we had an - * outstanding SDTR or WDTR message for this - * target. If we did, this is a signal that - * the target is refusing negotiation. + * Filter our period based on the current connection. + * If we can't perform DT transfers on this segment (not in LVD + * mode for instance), then our decision to issue a PPR message + * may change. */ - struct scb *scb; - u_int scb_index; - u_int last_msg; - int response = 0; - - scb_index = ahc_inb(ahc, SCB_TAG); - scb = &ahc->scb_data->scbarray[scb_index]; + period = tinfo->goal.period; + ppr_options = tinfo->goal.ppr_options; + /* Target initiated PPR is not allowed in the SCSI spec */ + if (devinfo->role == ROLE_TARGET) + ppr_options = 0; + rate = ahc_devlimited_syncrate(ahc, tinfo, &period, + &ppr_options, devinfo->role); + dowide = tinfo->curr.width != tinfo->goal.width; + dosync = tinfo->curr.period != period; + doppr = tinfo->curr.ppr_options != ppr_options; + + if (!dowide && !dosync && !doppr) { + dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; + dosync = tinfo->goal.period != 0; + doppr = tinfo->goal.ppr_options != 0; + } - /* Might be necessary */ - last_msg = ahc_inb(ahc, LAST_MSG); + if (!dowide && !dosync && !doppr) { + panic("ahc_intr: AWAITING_MSG for negotiation, " + "but no negotiation needed\n"); + } - if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/FALSE)) { - struct ahc_initiator_tinfo *tinfo; - struct tmode_tstate *tstate; + use_ppr = (tinfo->curr.transport_version >= 3) || doppr; + /* Target initiated PPR is not allowed in the SCSI spec */ + if (devinfo->role == ROLE_TARGET) + use_ppr = 0; - /* note 8bit xfers */ - if (bootverbose) - printf("%s:%c:%d: refuses WIDE negotiation. Using " - "8bit transfers\n", ahc_name(ahc), - devinfo->channel, devinfo->target); - ahc_set_width(ahc, devinfo, - MSG_EXT_WDTR_BUS_8_BIT, - AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, - /*paused*/TRUE, /*done*/TRUE); - /* - * No need to clear the sync rate. If the target - * did not accept the command, our syncrate is - * unaffected. If the target started the negotiation, - * but rejected our response, we already cleared the - * sync rate before sending our WDTR. - */ - tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, - devinfo->our_scsiid, - devinfo->target, &tstate); - if (tinfo->goal.period) { - u_int period; + /* + * Both the PPR message and SDTR message require the + * goal syncrate to be limited to what the target device + * is capable of handling (based on whether an LVD->SE + * expander is on the bus), so combine these two cases. + * Regardless, guarantee that if we are using WDTR and SDTR + * messages that WDTR comes first. + */ + if (use_ppr || (dosync && !dowide)) { - /* Start the sync negotiation */ - period = tinfo->goal.period; - ahc_devlimited_syncrate(ahc, &period); - ahc->msgout_index = 0; - ahc->msgout_len = 0; - ahc_construct_sdtr(ahc, period, tinfo->goal.offset); - ahc->msgout_index = 0; - response = 1; + offset = tinfo->goal.offset; + ahc_validate_offset(ahc, tinfo, rate, &offset, + use_ppr ? tinfo->goal.width + : tinfo->curr.width, + devinfo->role); + if (use_ppr) { + ahc_construct_ppr(ahc, devinfo, period, offset, + tinfo->goal.width, ppr_options); + } else { + ahc_construct_sdtr(ahc, devinfo, period, offset); } - } else if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/FALSE)) { - /* note asynch xfers and clear flag */ - ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, - /*offset*/0, - AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, - /*paused*/TRUE, - /*done*/TRUE); - if (bootverbose) - printf("%s:%c:%d: refuses synchronous negotiation. " - "Using asynchronous transfers\n", - ahc_name(ahc), - devinfo->channel, devinfo->target); - } else if ((scb->hscb->control & TAG_ENB) != 0) { - if (bootverbose) - printf("%s:%c:%d: refuses tagged commands. Performing " - "non-tagged I/O\n", ahc_name(ahc), - devinfo->channel, devinfo->target); - - ahc_set_tags(ahc, devinfo, FALSE); + } else { + ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width); + } +} - /* - * Resend the identify for this CCB as the target - * may believe that the selection is invalid otherwise. - */ - ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) - & ~MSG_SIMPLE_Q_TAG); - scb->hscb->control &= ~TAG_ENB; - ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); - ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); +/* + * Build a synchronous negotiation message in our message + * buffer based on the input parameters. + */ +static void +ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, + u_int period, u_int offset) +{ + ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; + ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; + ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; + ahc->msgout_buf[ahc->msgout_index++] = period; + ahc->msgout_buf[ahc->msgout_index++] = offset; + ahc->msgout_len += 5; + if (bootverbose) { + printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", + ahc_name(ahc), devinfo->channel, devinfo->target, + devinfo->lun, period, offset); + } +} - /* - * Requeue all tagged commands for this target - * currently in our posession so they can be - * converted to untagged commands. - */ - ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), - SCB_LUN(scb), /*tag*/SCB_LIST_NULL, - ROLE_INITIATOR, SCB_REQUEUE, - SEARCH_COMPLETE); - } else { - /* - * Otherwise, we ignore it. - */ - printf("%s:%c:%d: Message reject for %x -- ignored\n", +/* + * Build a wide negotiateion message in our message + * buffer based on the input parameters. + */ +static void +ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, + u_int bus_width) +{ + ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; + ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; + ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; + ahc->msgout_buf[ahc->msgout_index++] = bus_width; + ahc->msgout_len += 4; + if (bootverbose) { + printf("(%s:%c:%d:%d): Sending WDTR %x\n", ahc_name(ahc), devinfo->channel, devinfo->target, - last_msg); + devinfo->lun, bus_width); + } +} + +/* + * Build a parallel protocol request message in our message + * buffer based on the input parameters. + */ +static void +ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, + u_int period, u_int offset, u_int bus_width, + u_int ppr_options) +{ + ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; + ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN; + ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR; + ahc->msgout_buf[ahc->msgout_index++] = period; + ahc->msgout_buf[ahc->msgout_index++] = 0; + ahc->msgout_buf[ahc->msgout_index++] = offset; + ahc->msgout_buf[ahc->msgout_index++] = bus_width; + ahc->msgout_buf[ahc->msgout_index++] = ppr_options; + ahc->msgout_len += 8; + if (bootverbose) { + printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, " + "offset %x, ppr_options %x\n", ahc_name(ahc), + devinfo->channel, devinfo->target, devinfo->lun, + bus_width, period, offset, ppr_options); } - return (response); } -STATIC void -ahc_clear_msg_state(ahc) - struct ahc_softc *ahc; +/* + * Clear any active message state. + */ +static void +ahc_clear_msg_state(struct ahc_softc *ahc) { ahc->msgout_len = 0; ahc->msgin_index = 0; ahc->msg_type = MSG_TYPE_NONE; + if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) { + /* + * The target didn't care to respond to our + * message request, so clear ATN. + */ + ahc_outb(ahc, CLRSINT1, CLRATNO); + } ahc_outb(ahc, MSG_OUT, MSG_NOOP); } -STATIC void -ahc_handle_message_phase(ahc, sc_link) - struct ahc_softc *ahc; - struct scsi_link *sc_link; +/* + * Manual message loop handler. + */ +static void +ahc_handle_message_phase(struct ahc_softc *ahc) { struct ahc_devinfo devinfo; u_int bus_phase; @@ -2708,7 +2399,7 @@ reswitch: int msgdone; if (ahc->msgout_len == 0) - panic("REQINIT interrupt with no active message"); + panic("HOST_MSG_LOOP interrupt with no active message"); phasemis = bus_phase != P_MESGOUT; if (phasemis) { @@ -2744,7 +2435,7 @@ reswitch: * 0, and try again. */ ahc->msgout_index = 0; - ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); + ahc_assert_atn(ahc); } lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); @@ -2784,7 +2475,7 @@ reswitch: /* Pull the byte in without acking it */ ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); - message_done = ahc_parse_msg(ahc, sc_link, &devinfo); + message_done = ahc_parse_msg(ahc, &devinfo); if (message_done) { /* @@ -2799,8 +2490,7 @@ reswitch: * message out phase. */ if (ahc->msgout_len != 0) - ahc_outb(ahc, SCSISIGO, - ahc_inb(ahc, SCSISIGO) | ATNO); + ahc_assert_atn(ahc); } else ahc->msgin_index++; @@ -2880,7 +2570,7 @@ reswitch: */ ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); - msgdone = ahc_parse_msg(ahc, sc_link, &devinfo); + msgdone = ahc_parse_msg(ahc, &devinfo); if (msgdone == MSGLOOP_TERMINATED) { /* * The message is *really* done in that it caused @@ -2937,59 +2627,62 @@ reswitch: /* * See if we sent a particular extended message to the target. - * If "full" is true, the target saw the full message. - * If "full" is false, the target saw at least the first - * byte of the message. + * If "full" is true, return true only if the target saw the full + * message. If "full" is false, return true if the target saw at + * least the first byte of the message. */ -STATIC int -ahc_sent_msg(ahc, msgtype, full) - struct ahc_softc *ahc; - u_int msgtype; - int full; +static int +ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full) { int found; - int index; + u_int index; found = FALSE; index = 0; while (index < ahc->msgout_len) { if (ahc->msgout_buf[index] == MSG_EXTENDED) { + u_int end_index; - /* Found a candidate */ - if (ahc->msgout_buf[index+2] == msgtype) { - u_int end_index; + end_index = index + 1 + ahc->msgout_buf[index + 1]; + if (ahc->msgout_buf[index+2] == msgval + && type == AHCMSG_EXT) { - end_index = index + 1 - + ahc->msgout_buf[index + 1]; if (full) { if (ahc->msgout_index > end_index) found = TRUE; } else if (ahc->msgout_index > index) found = TRUE; } - break; - } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_Q_TAG + index = end_index; + } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { /* Skip tag type and tag id or residue param*/ index += 2; } else { /* Single byte message */ + if (type == AHCMSG_1B + && ahc->msgout_buf[index] == msgval + && ahc->msgout_index > index) + found = TRUE; index++; } + + if (found) + break; } return (found); } -STATIC int -ahc_parse_msg(ahc, sc_link, devinfo) - struct ahc_softc *ahc; - struct scsi_link *sc_link; - struct ahc_devinfo *devinfo; +/* + * Wait for a complete incoming message, parse it, and respond accordingly. + */ +static int +ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) { struct ahc_initiator_tinfo *tinfo; - struct tmode_tstate *tstate; + struct ahc_tmode_tstate *tstate; int reject; int done; int response; @@ -3020,19 +2713,6 @@ ahc_parse_msg(ahc, sc_link, devinfo) case MSG_NOOP: done = MSGLOOP_MSGCOMPLETE; break; - case MSG_IGN_WIDE_RESIDUE: - { - /* Wait for the whole message */ - if (ahc->msgin_index >= 1) { - if (ahc->msgin_buf[1] != 1 - || tinfo->current.width == MSG_EXT_WDTR_BUS_8_BIT) { - reject = TRUE; - done = MSGLOOP_MSGCOMPLETE; - } else - ahc_handle_ign_wide_residue(ahc, devinfo); - } - break; - } case MSG_EXTENDED: { /* Wait for enough of the message to begin validation */ @@ -3043,6 +2723,7 @@ ahc_parse_msg(ahc, sc_link, devinfo) { struct ahc_syncrate *syncrate; u_int period; + u_int ppr_options; u_int offset; u_int saved_offset; @@ -3062,21 +2743,35 @@ ahc_parse_msg(ahc, sc_link, devinfo) break; period = ahc->msgin_buf[3]; + ppr_options = 0; saved_offset = offset = ahc->msgin_buf[4]; - syncrate = ahc_devlimited_syncrate(ahc, &period); - ahc_validate_offset(ahc, syncrate, &offset, - targ_scsirate & WIDEXFER); + syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, + &ppr_options, + devinfo->role); + ahc_validate_offset(ahc, tinfo, syncrate, &offset, + targ_scsirate & WIDEXFER, + devinfo->role); + if (bootverbose) { + printf("(%s:%c:%d:%d): Received " + "SDTR period %x, offset %x\n\t" + "Filtered to period %x, offset %x\n", + ahc_name(ahc), devinfo->channel, + devinfo->target, devinfo->lun, + ahc->msgin_buf[3], saved_offset, + period, offset); + } ahc_set_syncrate(ahc, devinfo, - syncrate, period, offset, + syncrate, period, + offset, ppr_options, AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, - /*paused*/TRUE, /*done*/TRUE); + /*paused*/TRUE); /* * See if we initiated Sync Negotiation * and didn't have to fall down to async * transfers. */ - if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/TRUE)) { + if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) { /* We started it */ if (saved_offset != offset) { /* Went too low - force async */ @@ -3086,11 +2781,17 @@ ahc_parse_msg(ahc, sc_link, devinfo) /* * Send our own SDTR in reply */ - if (bootverbose) - printf("Sending SDTR!\n"); + if (bootverbose + && devinfo->role == ROLE_INITIATOR) { + printf("(%s:%c:%d:%d): Target " + "Initiated SDTR\n", + ahc_name(ahc), devinfo->channel, + devinfo->target, devinfo->lun); + } ahc->msgout_index = 0; ahc->msgout_len = 0; - ahc_construct_sdtr(ahc, period, offset); + ahc_construct_sdtr(ahc, devinfo, + period, offset); ahc->msgout_index = 0; response = TRUE; } @@ -3099,8 +2800,9 @@ ahc_parse_msg(ahc, sc_link, devinfo) } case MSG_EXT_WDTR: { - u_int bus_width; - u_int sending_reply; + u_int bus_width; + u_int saved_width; + u_int sending_reply; sending_reply = FALSE; if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { @@ -3119,82 +2821,65 @@ ahc_parse_msg(ahc, sc_link, devinfo) break; bus_width = ahc->msgin_buf[3]; - if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/TRUE)) { + saved_width = bus_width; + ahc_validate_width(ahc, tinfo, &bus_width, + devinfo->role); + if (bootverbose) { + printf("(%s:%c:%d:%d): Received WDTR " + "%x filtered to %x\n", + ahc_name(ahc), devinfo->channel, + devinfo->target, devinfo->lun, + saved_width, bus_width); + } + + if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) { /* * Don't send a WDTR back to the * target, since we asked first. + * If the width went higher than our + * request, reject it. */ - switch (bus_width){ - default: - /* - * How can we do anything greater - * than 16bit transfers on a 16bit - * bus? - */ + if (saved_width > bus_width) { reject = TRUE; - printf("%s: target %d requested %dBit " + printf("(%s:%c:%d:%d): requested %dBit " "transfers. Rejecting...\n", - ahc_name(ahc), devinfo->target, + ahc_name(ahc), devinfo->channel, + devinfo->target, devinfo->lun, 8 * (0x01 << bus_width)); - /* FALLTHROUGH */ - case MSG_EXT_WDTR_BUS_8_BIT: - bus_width = MSG_EXT_WDTR_BUS_8_BIT; - break; - case MSG_EXT_WDTR_BUS_16_BIT: - break; + bus_width = 0; } } else { /* * Send our own WDTR in reply */ - if (bootverbose) - printf("Sending WDTR!\n"); - switch (bus_width) { - default: - if (ahc->features & AHC_WIDE) { - /* Respond Wide */ - bus_width = - MSG_EXT_WDTR_BUS_16_BIT; - break; - } - /* FALLTHROUGH */ - case MSG_EXT_WDTR_BUS_8_BIT: - bus_width = MSG_EXT_WDTR_BUS_8_BIT; - break; + if (bootverbose + && devinfo->role == ROLE_INITIATOR) { + printf("(%s:%c:%d:%d): Target " + "Initiated WDTR\n", + ahc_name(ahc), devinfo->channel, + devinfo->target, devinfo->lun); } ahc->msgout_index = 0; ahc->msgout_len = 0; - ahc_construct_wdtr(ahc, bus_width); + ahc_construct_wdtr(ahc, devinfo, bus_width); ahc->msgout_index = 0; response = TRUE; sending_reply = TRUE; } ahc_set_width(ahc, devinfo, bus_width, AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, - /*paused*/TRUE, /*done*/TRUE); - + /*paused*/TRUE); /* After a wide message, we are async */ ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, - /*offset*/0, AHC_TRANS_ACTIVE, - /*paused*/TRUE, /*done*/FALSE); + /*offset*/0, /*ppr_options*/0, + AHC_TRANS_ACTIVE, /*paused*/TRUE); if (sending_reply == FALSE && reject == FALSE) { if (tinfo->goal.period) { - struct ahc_syncrate *rate; - u_int period; - u_int offset; - - /* Start the sync negotiation */ - period = tinfo->goal.period; - rate = ahc_devlimited_syncrate(ahc, - &period); - offset = tinfo->goal.offset; - ahc_validate_offset(ahc, rate, &offset, - tinfo->current.width); ahc->msgout_index = 0; ahc->msgout_len = 0; - ahc_construct_sdtr(ahc, period, offset); + ahc_build_transfer_msg(ahc, devinfo); ahc->msgout_index = 0; response = TRUE; } @@ -3202,6 +2887,122 @@ ahc_parse_msg(ahc, sc_link, devinfo) done = MSGLOOP_MSGCOMPLETE; break; } + case MSG_EXT_PPR: + { + struct ahc_syncrate *syncrate; + u_int period; + u_int offset; + u_int bus_width; + u_int ppr_options; + u_int saved_width; + u_int saved_offset; + u_int saved_ppr_options; + + if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) { + reject = TRUE; + break; + } + + /* + * Wait until we have all args before validating + * and acting on this message. + * + * Add one to MSG_EXT_PPR_LEN to account for + * the extended message preamble. + */ + if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1)) + break; + + period = ahc->msgin_buf[3]; + offset = ahc->msgin_buf[5]; + bus_width = ahc->msgin_buf[6]; + saved_width = bus_width; + ppr_options = ahc->msgin_buf[7]; + /* + * According to the spec, a DT only + * period factor with no DT option + * set implies async. + */ + if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 + && period == 9) + offset = 0; + saved_ppr_options = ppr_options; + saved_offset = offset; + + /* + * Mask out any options we don't support + * on any controller. Transfer options are + * only available if we are negotiating wide. + */ + ppr_options &= MSG_EXT_PPR_DT_REQ; + if (bus_width == 0) + ppr_options = 0; + + ahc_validate_width(ahc, tinfo, &bus_width, + devinfo->role); + syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, + &ppr_options, + devinfo->role); + ahc_validate_offset(ahc, tinfo, syncrate, + &offset, bus_width, + devinfo->role); + + if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) { + /* + * If we are unable to do any of the + * requested options (we went too low), + * then we'll have to reject the message. + */ + if (saved_width > bus_width + || saved_offset != offset + || saved_ppr_options != ppr_options) { + reject = TRUE; + period = 0; + offset = 0; + bus_width = 0; + ppr_options = 0; + syncrate = NULL; + } + } else { + if (devinfo->role != ROLE_TARGET) + printf("(%s:%c:%d:%d): Target " + "Initiated PPR\n", + ahc_name(ahc), devinfo->channel, + devinfo->target, devinfo->lun); + else + printf("(%s:%c:%d:%d): Initiator " + "Initiated PPR\n", + ahc_name(ahc), devinfo->channel, + devinfo->target, devinfo->lun); + ahc->msgout_index = 0; + ahc->msgout_len = 0; + ahc_construct_ppr(ahc, devinfo, period, offset, + bus_width, ppr_options); + ahc->msgout_index = 0; + response = TRUE; + } + if (bootverbose) { + printf("(%s:%c:%d:%d): Received PPR width %x, " + "period %x, offset %x,options %x\n" + "\tFiltered to width %x, period %x, " + "offset %x, options %x\n", + ahc_name(ahc), devinfo->channel, + devinfo->target, devinfo->lun, + saved_width, ahc->msgin_buf[3], + saved_offset, saved_ppr_options, + bus_width, period, offset, ppr_options); + } + ahc_set_width(ahc, devinfo, bus_width, + AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, + /*paused*/TRUE); + ahc_set_syncrate(ahc, devinfo, + syncrate, period, + offset, ppr_options, + AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, + /*paused*/TRUE); + done = MSGLOOP_MSGCOMPLETE; + break; + } default: /* Unknown extended message. Reject it. */ reject = TRUE; @@ -3211,29 +3012,31 @@ ahc_parse_msg(ahc, sc_link, devinfo) } case MSG_BUS_DEV_RESET: ahc_handle_devreset(ahc, devinfo, - XS_RESET, "Bus Device Reset Received", + CAM_BDR_SENT, + "Bus Device Reset Received", /*verbose_level*/0); - restart_sequencer(ahc); + ahc_restart(ahc); done = MSGLOOP_TERMINATED; break; case MSG_ABORT_TAG: case MSG_ABORT: case MSG_CLEAR_QUEUE: +#ifdef AHC_TARGET_MODE /* Target mode messages */ if (devinfo->role != ROLE_TARGET) { reject = TRUE; break; } -#if AHC_TARGET_MODE ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, devinfo->lun, - ahc->msgin_buf[0] == MSG_ABORT_TAG ? SCB_LIST_NULL - : ahc_inb(ahc, INITIATOR_TAG), - ROLE_TARGET, XS_DRIVER_STUFFUP); + ahc->msgin_buf[0] == MSG_ABORT_TAG + ? SCB_LIST_NULL + : ahc_inb(ahc, INITIATOR_TAG), + ROLE_TARGET, CAM_REQ_ABORTED); tstate = ahc->enabled_targets[devinfo->our_scsiid]; if (tstate != NULL) { - struct tmode_lstate* lstate; + struct ahc_tmode_lstate* lstate; lstate = tstate->enabled_luns[devinfo->lun]; if (lstate != NULL) { @@ -3245,10 +3048,8 @@ ahc_parse_msg(ahc, sc_link, devinfo) } } done = MSGLOOP_MSGCOMPLETE; -#else - panic("ahc: got target mode message"); -#endif break; +#endif case MSG_TERM_IO_PROC: default: reject = TRUE; @@ -3273,18 +3074,174 @@ ahc_parse_msg(ahc, sc_link, devinfo) return (done); } -STATIC void -ahc_handle_ign_wide_residue(ahc, devinfo) - struct ahc_softc *ahc; - struct ahc_devinfo *devinfo; +/* + * Process a message reject message. + */ +static int +ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) +{ + /* + * What we care about here is if we had an + * outstanding SDTR or WDTR message for this + * target. If we did, this is a signal that + * the target is refusing negotiation. + */ + struct scb *scb; + struct ahc_initiator_tinfo *tinfo; + struct ahc_tmode_tstate *tstate; + u_int scb_index; + u_int last_msg; + int response = 0; + + scb_index = ahc_inb(ahc, SCB_TAG); + scb = ahc_lookup_scb(ahc, scb_index); + tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, + devinfo->our_scsiid, + devinfo->target, &tstate); + /* Might be necessary */ + last_msg = ahc_inb(ahc, LAST_MSG); + + if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { + /* + * Target does not support the PPR message. + * Attempt to negotiate SPI-2 style. + */ + if (bootverbose) { + printf("(%s:%c:%d:%d): PPR Rejected. " + "Trying WDTR/SDTR\n", + ahc_name(ahc), devinfo->channel, + devinfo->target, devinfo->lun); + } + tinfo->goal.ppr_options = 0; + tinfo->curr.transport_version = 2; + tinfo->goal.transport_version = 2; + ahc->msgout_index = 0; + ahc->msgout_len = 0; + ahc_build_transfer_msg(ahc, devinfo); + ahc->msgout_index = 0; + response = 1; + } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { + + /* note 8bit xfers */ + printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " + "8bit transfers\n", ahc_name(ahc), + devinfo->channel, devinfo->target, devinfo->lun); + ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, + AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, + /*paused*/TRUE); + /* + * No need to clear the sync rate. If the target + * did not accept the command, our syncrate is + * unaffected. If the target started the negotiation, + * but rejected our response, we already cleared the + * sync rate before sending our WDTR. + */ + if (tinfo->goal.period) { + + /* Start the sync negotiation */ + ahc->msgout_index = 0; + ahc->msgout_len = 0; + ahc_build_transfer_msg(ahc, devinfo); + ahc->msgout_index = 0; + response = 1; + } + } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { + /* note asynch xfers and clear flag */ + ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, + /*offset*/0, /*ppr_options*/0, + AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, + /*paused*/TRUE); + printf("(%s:%c:%d:%d): refuses synchronous negotiation. " + "Using asynchronous transfers\n", + ahc_name(ahc), devinfo->channel, + devinfo->target, devinfo->lun); + } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { + int tag_type; + int mask; + + tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); + + if (tag_type == MSG_SIMPLE_TASK) { + printf("(%s:%c:%d:%d): refuses tagged commands. " + "Performing non-tagged I/O\n", ahc_name(ahc), + devinfo->channel, devinfo->target, devinfo->lun); + ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE); + mask = ~0x23; + } else { + printf("(%s:%c:%d:%d): refuses %s tagged commands. " + "Performing simple queue tagged I/O only\n", + ahc_name(ahc), devinfo->channel, devinfo->target, + devinfo->lun, tag_type == MSG_ORDERED_TASK + ? "ordered" : "head of queue"); + ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC); + mask = ~0x03; + } + + /* + * Resend the identify for this CCB as the target + * may believe that the selection is invalid otherwise. + */ + ahc_outb(ahc, SCB_CONTROL, + ahc_inb(ahc, SCB_CONTROL) & mask); + scb->hscb->control &= mask; + ahc_set_transaction_tag(scb, /*enabled*/FALSE, + /*type*/MSG_SIMPLE_TASK); + ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); + ahc_assert_atn(ahc); + + /* + * This transaction is now at the head of + * the untagged queue for this target. + */ + if ((ahc->flags & AHC_SCB_BTT) == 0) { + struct scb_tailq *untagged_q; + + untagged_q = + &(ahc->untagged_queues[devinfo->target_offset]); + TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe); + scb->flags |= SCB_UNTAGGEDQ; + } + ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), + scb->hscb->tag); + + /* + * Requeue all tagged commands for this target + * currently in our posession so they can be + * converted to untagged commands. + */ + ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), + SCB_GET_CHANNEL(ahc, scb), + SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, + ROLE_INITIATOR, CAM_REQUEUE_REQ, + SEARCH_COMPLETE); + } else { + /* + * Otherwise, we ignore it. + */ + printf("%s:%c:%d: Message reject for %x -- ignored\n", + ahc_name(ahc), devinfo->channel, devinfo->target, + last_msg); + } + return (response); +} + +/* + * Process an ingnore wide residue message. + */ +static void +ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) { u_int scb_index; struct scb *scb; scb_index = ahc_inb(ahc, SCB_TAG); - scb = &ahc->scb_data->scbarray[scb_index]; + scb = ahc_lookup_scb(ahc, scb_index); + /* + * XXX Actually check data direction in the sequencer? + * Perhaps add datadir to some spare bits in the hscb? + */ if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 - || !(scb->xs->flags & SCSI_DATA_IN)) { + || ahc_get_transfer_dir(scb) != CAM_DIR_IN) { /* * Ignore the message if we haven't * seen an appropriate data phase yet. @@ -3297,10 +3254,10 @@ ahc_handle_ign_wide_residue(ahc, devinfo) * nothing. Otherwise, subtract a byte * and update the residual count accordingly. */ - u_int resid_sgcnt; + uint32_t sgptr; - resid_sgcnt = ahc_inb(ahc, SCB_RESID_SGCNT); - if (resid_sgcnt == 0 + sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR); + if ((sgptr & SG_LIST_NULL) != 0 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { /* * If the residual occurred on the last @@ -3309,13 +3266,20 @@ ahc_handle_ign_wide_residue(ahc, devinfo) * nothing. */ } else { - u_int data_cnt; - u_int data_addr; - u_int sg_index; - - data_cnt = (ahc_inb(ahc, SCB_RESID_DCNT + 2) << 16) - | (ahc_inb(ahc, SCB_RESID_DCNT + 1) << 8) - | (ahc_inb(ahc, SCB_RESID_DCNT)); + struct ahc_dma_seg *sg; + uint32_t data_cnt; + uint32_t data_addr; + uint32_t sglen; + + /* Pull in the rest of the sgptr */ + sgptr |= (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24) + | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) + | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8); + sgptr &= SG_PTR_MASK; + data_cnt = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+3) << 24) + | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+2) << 16) + | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+1) << 8) + | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT)); data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) | (ahc_inb(ahc, SHADDR + 2) << 16) @@ -3325,260 +3289,922 @@ ahc_handle_ign_wide_residue(ahc, devinfo) data_cnt += 1; data_addr -= 1; - sg_index = scb->sg_count - resid_sgcnt; + sg = ahc_sg_bus_to_virt(scb, sgptr); + /* + * The residual sg ptr points to the next S/G + * to load so we must go back one. + */ + sg--; + sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK; + if (sg != scb->sg_list + && sglen < (data_cnt & AHC_SG_LEN_MASK)) { - if (sg_index != 0 - && (le32toh(scb->sg_list[sg_index].len) < data_cnt)) { - u_int32_t sg_addr; + sg--; + sglen = ahc_le32toh(sg->len); + /* + * Preserve High Address and SG_LIST bits + * while setting the count to 1. + */ + data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK)); + data_addr = ahc_le32toh(sg->addr) + + (sglen & AHC_SG_LEN_MASK) - 1; - sg_index--; - data_cnt = 1; - data_addr = le32toh(scb->sg_list[sg_index].addr) - + le32toh(scb->sg_list[sg_index].len) - - 1; - /* - * The physical address base points to the - * second entry as it is always used for - * calculating the "next S/G pointer". + * Increment sg so it points to the + * "next" sg. */ - sg_addr = scb->sg_list_phys - + (sg_index* sizeof(*scb->sg_list)); - ahc_outb(ahc, SG_NEXT + 3, sg_addr >> 24); - ahc_outb(ahc, SG_NEXT + 2, sg_addr >> 16); - ahc_outb(ahc, SG_NEXT + 1, sg_addr >> 8); - ahc_outb(ahc, SG_NEXT, sg_addr); + sg++; + sgptr = ahc_sg_virt_to_bus(scb, sg); + ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 3, + sgptr >> 24); + ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 2, + sgptr >> 16); + ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 1, + sgptr >> 8); + ahc_outb(ahc, SCB_RESIDUAL_SGPTR, sgptr); } - ahc_outb(ahc, SCB_RESID_DCNT + 2, data_cnt >> 16); - ahc_outb(ahc, SCB_RESID_DCNT + 1, data_cnt >> 8); - ahc_outb(ahc, SCB_RESID_DCNT, data_cnt); - - ahc_outb(ahc, SHADDR + 3, data_addr >> 24); - ahc_outb(ahc, SHADDR + 2, data_addr >> 16); - ahc_outb(ahc, SHADDR + 1, data_addr >> 8); - ahc_outb(ahc, SHADDR, data_addr); + ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 3, data_cnt >> 24); + ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 2, data_cnt >> 16); + ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 1, data_cnt >> 8); + ahc_outb(ahc, SCB_RESIDUAL_DATACNT, data_cnt); } } } -STATIC void -ahc_handle_devreset(ahc, devinfo, status, message, verbose_level) - struct ahc_softc *ahc; - struct ahc_devinfo *devinfo; - int status; - char *message; - int verbose_level; + +/* + * Reinitialize the data pointers for the active transfer + * based on its current residual. + */ +static void +ahc_reinitialize_dataptrs(struct ahc_softc *ahc) { + struct scb *scb; + struct ahc_dma_seg *sg; + u_int scb_index; + uint32_t sgptr; + uint32_t resid; + uint32_t dataptr; + + scb_index = ahc_inb(ahc, SCB_TAG); + scb = ahc_lookup_scb(ahc, scb_index); + sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24) + | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) + | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8) + | ahc_inb(ahc, SCB_RESIDUAL_SGPTR); + + sgptr &= SG_PTR_MASK; + sg = ahc_sg_bus_to_virt(scb, sgptr); + + /* The residual sg_ptr always points to the next sg */ + sg--; + + resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16) + | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8) + | ahc_inb(ahc, SCB_RESIDUAL_DATACNT); + + dataptr = ahc_le32toh(sg->addr) + + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK) + - resid; + if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { + u_int dscommand1; + + dscommand1 = ahc_inb(ahc, DSCOMMAND1); + ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); + ahc_outb(ahc, HADDR, + (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS); + ahc_outb(ahc, DSCOMMAND1, dscommand1); + } + ahc_outb(ahc, HADDR + 3, dataptr >> 24); + ahc_outb(ahc, HADDR + 2, dataptr >> 16); + ahc_outb(ahc, HADDR + 1, dataptr >> 8); + ahc_outb(ahc, HADDR, dataptr); + ahc_outb(ahc, HCNT + 2, resid >> 16); + ahc_outb(ahc, HCNT + 1, resid >> 8); + ahc_outb(ahc, HCNT, resid); + if ((ahc->features & AHC_ULTRA2) == 0) { + ahc_outb(ahc, STCNT + 2, resid >> 16); + ahc_outb(ahc, STCNT + 1, resid >> 8); + ahc_outb(ahc, STCNT, resid); + } +} + +/* + * Handle the effects of issuing a bus device reset message. + */ +static void +ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, + cam_status status, char *message, int verbose_level) +{ +#ifdef AHC_TARGET_MODE + struct ahc_tmode_tstate* tstate; + u_int lun; +#endif int found; found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, - ALL_LUNS, SCB_LIST_NULL, devinfo->role, + CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, status); +#ifdef AHC_TARGET_MODE + /* + * Send an immediate notify ccb to all target mord peripheral + * drivers affected by this action. + */ + tstate = ahc->enabled_targets[devinfo->our_scsiid]; + if (tstate != NULL) { + for (lun = 0; lun < AHC_NUM_LUNS; lun++) { + struct ahc_tmode_lstate* lstate; + + lstate = tstate->enabled_luns[lun]; + if (lstate == NULL) + continue; + + ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid, + MSG_BUS_DEV_RESET, /*arg*/0); + ahc_send_lstate_events(ahc, lstate); + } + } +#endif + /* * Go back to async/narrow transfers and renegotiate. - * ahc_set_width and ahc_set_syncrate can cope with NULL - * paths. */ ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, - AHC_TRANS_CUR, /*paused*/TRUE, /*done*/FALSE); + AHC_TRANS_CUR, /*paused*/TRUE); ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, - /*period*/0, /*offset*/0, AHC_TRANS_CUR, - /*paused*/TRUE, /*done*/FALSE); + /*period*/0, /*offset*/0, /*ppr_options*/0, + AHC_TRANS_CUR, /*paused*/TRUE); + ahc_send_async(ahc, devinfo->channel, devinfo->target, + CAM_LUN_WILDCARD, AC_SENT_BDR, NULL); + if (message != NULL && (verbose_level <= bootverbose)) printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), message, devinfo->channel, devinfo->target, found); } -/* - * We have an scb which has been processed by the - * adaptor, now we look to see how the operation - * went. - */ -STATIC void -ahc_done(ahc, scb) - struct ahc_softc *ahc; - struct scb *scb; +#ifdef AHC_TARGET_MODE +static void +ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, + struct scb *scb) { - struct scsi_xfer *xs = scb->xs; - struct scsi_link *sc_link = xs->sc_link; - int requeue = 0; - int target; - SC_DEBUG(xs->sc_link, SDEV_DB2, ("ahc_done\n")); - - LIST_REMOVE(scb, pend_links); + /* + * To facilitate adding multiple messages together, + * each routine should increment the index and len + * variables instead of setting them explicitly. + */ + ahc->msgout_index = 0; + ahc->msgout_len = 0; + + if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) + ahc_build_transfer_msg(ahc, devinfo); + else + panic("ahc_intr: AWAITING target message with no message"); - timeout_del(&scb->xs->stimeout); + ahc->msgout_index = 0; + ahc->msg_type = MSG_TYPE_TARGET_MSGIN; +} +#endif +/**************************** Initialization **********************************/ +/* + * Allocate a controller structure for a new device + * and perform initial initializion. + */ +struct ahc_softc * +ahc_alloc(void *platform_arg, char *name) +{ + struct ahc_softc *ahc; + int i; -#ifdef AHC_DEBUG - if (ahc_debug & AHC_SHOWCMDS) { - sc_print_addr(sc_link); - printf("ahc_done opcode %d tag %x\n", xs->cmdstore.opcode, - scb->hscb->tag); +#ifdef __OpenBSD__ /* OpenBSD provides softc! */ + ahc = (struct ahc_softc *)platform_arg; +#else +#ifndef __FreeBSD__ + ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT); + if (!ahc) { + printf("aic7xxx: cannot malloc softc!\n"); + free(name, M_DEVBUF); + return NULL; } +#else + ahc = device_get_softc((device_t)platform_arg); #endif - - target = sc_link->target; - - if (xs->datalen) { - int op; - - if ((xs->flags & SCSI_DATA_IN) != 0) - op = BUS_DMASYNC_POSTREAD; - else - op = BUS_DMASYNC_POSTWRITE; - bus_dmamap_sync(ahc->sc_dmat, scb->dmamap, - 0, scb->dmamap->dm_mapsize, op); - bus_dmamap_unload(ahc->sc_dmat, scb->dmamap); + memset(ahc, 0, sizeof(*ahc)); +#endif + LIST_INIT(&ahc->pending_scbs); + /* We don't know our unit number until the OSM sets it */ + ahc->name = name; + ahc->unit = -1; + ahc->description = NULL; + ahc->channel = 'A'; + ahc->channel_b = 'B'; + ahc->chip = AHC_NONE; + ahc->features = AHC_FENONE; + ahc->bugs = AHC_BUGNONE; + ahc->flags = AHC_FNONE; + + for (i = 0; i < 16; i++) + TAILQ_INIT(&ahc->untagged_queues[i]); + if (ahc_platform_alloc(ahc, platform_arg) != 0) { + ahc_free(ahc); + ahc = NULL; + } + return (ahc); +} + +int +ahc_softc_init(struct ahc_softc *ahc) +{ + + /* The IRQMS bit is only valid on VL and EISA chips */ + if ((ahc->chip & AHC_PCI) == 0) + ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS; + else + ahc->unpause = 0; + ahc->pause = ahc->unpause | PAUSE; + /* XXX The shared scb data stuff should be deprecated */ + if (ahc->scb_data == NULL) { + ahc->scb_data = malloc(sizeof(*ahc->scb_data), + M_DEVBUF, M_NOWAIT); + if (ahc->scb_data == NULL) + return (ENOMEM); + memset(ahc->scb_data, 0, sizeof(*ahc->scb_data)); } + return (0); +} + +void +ahc_softc_insert(struct ahc_softc *ahc) +{ + struct ahc_softc *list_ahc; + +#if AHC_PCI_CONFIG > 0 /* - * Unbusy this target/channel/lun. - * XXX if we are holding two commands per lun, - * send the next command. + * Second Function PCI devices need to inherit some + * settings from function 0. */ - if (!(scb->hscb->control & TAG_ENB)) - ahc_index_busy_tcl(ahc, scb->hscb->tcl, /*unbusy*/TRUE); + if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI + && (ahc->features & AHC_MULTI_FUNC) != 0) { + TAILQ_FOREACH(list_ahc, &ahc_tailq, links) { + ahc_dev_softc_t list_pci; + ahc_dev_softc_t pci; + + list_pci = list_ahc->dev_softc; + pci = ahc->dev_softc; + if (ahc_get_pci_slot(list_pci) == ahc_get_pci_slot(pci) + && ahc_get_pci_bus(list_pci) == ahc_get_pci_bus(pci)) { + struct ahc_softc *master; + struct ahc_softc *slave; + + if (ahc_get_pci_function(list_pci) == 0) { + master = list_ahc; + slave = ahc; + } else { + master = ahc; + slave = list_ahc; + } + slave->flags &= ~AHC_BIOS_ENABLED; + slave->flags |= + master->flags & AHC_BIOS_ENABLED; + slave->flags &= ~AHC_PRIMARY_CHANNEL; + slave->flags |= + master->flags & AHC_PRIMARY_CHANNEL; + break; + } + } + } +#endif /* - * If the recovery SCB completes, we have to be - * out of our timeout. + * Insertion sort into our list of softcs. */ - if ((scb->flags & SCB_RECOVERY_SCB) != 0) { + list_ahc = TAILQ_FIRST(&ahc_tailq); + while (list_ahc != NULL + && ahc_softc_comp(list_ahc, ahc) <= 0) + list_ahc = TAILQ_NEXT(list_ahc, links); + if (list_ahc != NULL) + TAILQ_INSERT_BEFORE(list_ahc, ahc, links); + else + TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links); + ahc->init_level++; +} - struct scb *scbp; +void +ahc_set_unit(struct ahc_softc *ahc, int unit) +{ + ahc->unit = unit; +} - /* - * We were able to complete the command successfully, - * so reinstate the timeouts for all other pending - * commands. - */ - scbp = ahc->pending_scbs.lh_first; - while (scbp != NULL) { - struct scsi_xfer *txs = scbp->xs; - - if (!(txs->flags & SCSI_POLL)) - timeout_add(&scbp->xs->stimeout, - (scbp->xs->timeout * hz)/1000); - scbp = LIST_NEXT(scbp, pend_links); - } +void +ahc_set_name(struct ahc_softc *ahc, char *name) +{ + if (ahc->name != NULL) + free(ahc->name, M_DEVBUF); + ahc->name = name; +} - /* - * Ensure that we didn't put a second instance of this - * SCB into the QINFIFO. - */ - ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), - SCB_LUN(scb), scb->hscb->tag, - ROLE_INITIATOR, /*status*/0, - SEARCH_REMOVE); - if (xs->error != XS_NOERROR) - ahcsetccbstatus(xs, XS_TIMEOUT); - sc_print_addr(xs->sc_link); - printf("no longer in timeout, status = %x\n", xs->status); - } - - if (xs->error != XS_NOERROR) { - /* Don't clobber any existing error state */ - } else if ((scb->flags & SCB_SENSE) != 0) { - /* - * We performed autosense retrieval. - * - * bzero the sense data before having - * the drive fill it. The SCSI spec mandates - * that any untransfered data should be - * assumed to be zero. Complete the 'bounce' - * of sense information through buffers accessible - * via bus-space by copying it into the clients - * csio. - */ - bzero(&xs->sense, sizeof(struct scsi_sense)); - bcopy(&ahc->scb_data->sense[scb->hscb->tag], - &xs->sense, le32toh(scb->sg_list->len)); - xs->error = XS_SENSE; +#ifndef __OpenBSD__ +void +ahc_free(struct ahc_softc *ahc) +{ + int i; + + ahc_fini_scbdata(ahc); + switch (ahc->init_level) { + default: + case 5: + ahc_shutdown(ahc); + TAILQ_REMOVE(&ahc_tailq, ahc, links); + /* FALLTHROUGH */ + case 4: + ahc_dmamap_unload(ahc, ahc->shared_data_dmat, + ahc->shared_data_dmamap); + /* FALLTHROUGH */ + case 3: + ahc_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo, + ahc->shared_data_dmamap); + ahc_dmamap_destroy(ahc, ahc->shared_data_dmat, + ahc->shared_data_dmamap); + /* FALLTHROUGH */ + case 2: + ahc_dma_tag_destroy(ahc, ahc->shared_data_dmat); + case 1: +#ifndef __linux__ + ahc_dma_tag_destroy(ahc, ahc->buffer_dmat); +#endif + break; + case 0: + break; } - if (scb->flags & SCB_FREEZE_QUEUE) { - ahc->devqueue_blocked[target]--; - scb->flags &= ~SCB_FREEZE_QUEUE; + +#ifndef __linux__ + ahc_dma_tag_destroy(ahc, ahc->parent_dmat); +#endif + ahc_platform_free(ahc); + for (i = 0; i < AHC_NUM_TARGETS; i++) { + struct ahc_tmode_tstate *tstate; + + tstate = ahc->enabled_targets[i]; + if (tstate != NULL) { +#if AHC_TARGET_MODE + int j; + + for (j = 0; j < AHC_NUM_LUNS; j++) { + struct ahc_tmode_lstate *lstate; + + lstate = tstate->enabled_luns[j]; + if (lstate != NULL) { + xpt_free_path(lstate->path); + free(lstate, M_DEVBUF); + } + } +#endif + free(tstate, M_DEVBUF); + } + } +#if AHC_TARGET_MODE + if (ahc->black_hole != NULL) { + xpt_free_path(ahc->black_hole->path); + free(ahc->black_hole, M_DEVBUF); } +#endif + if (ahc->name != NULL) + free(ahc->name, M_DEVBUF); +#ifndef __FreeBSD__ + free(ahc, M_DEVBUF); +#endif + return; +} +#endif /* __OpenBSD__ */ + +void +ahc_shutdown(void *arg) +{ + struct ahc_softc *ahc; + int i; + + ahc = (struct ahc_softc *)arg; + + /* This will reset most registers to 0, but not all */ + ahc_reset(ahc); + ahc_outb(ahc, SCSISEQ, 0); + ahc_outb(ahc, SXFRCTL0, 0); + ahc_outb(ahc, DSPCISTATUS, 0); + + for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) + ahc_outb(ahc, i, 0); +} + +/* + * Reset the controller and record some information about it + * that is only availabel just after a reset. + */ +int +ahc_reset(struct ahc_softc *ahc) +{ + u_int sblkctl; + u_int sxfrctl1_a, sxfrctl1_b; + int wait; - requeue = scb->flags & SCB_REQUEUE; - ahcfreescb(ahc, scb); + /* + * Preserve the value of the SXFRCTL1 register for all channels. + * It contains settings that affect termination and we don't want + * to disturb the integrity of the bus. + */ + ahc_pause(ahc); + sxfrctl1_b = 0; + if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) { + u_int sblkctl; - if (requeue) { /* - * Re-insert at the front of the private queue to - * preserve order. + * Save channel B's settings in case this chip + * is setup for TWIN channel operation. */ - int s; + sblkctl = ahc_inb(ahc, SBLKCTL); + ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); + sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); + ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); + } + sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); - s = splbio(); - /* TAILQ_INSERT_HEAD(&ahc->sc_q, xs, adapter_q); */ - ahc_list_insert_head(ahc, xs); - splx(s); - } else { - if (((xs->flags & SCSI_POLL) != 0) && - (xs->error == XS_NOERROR)) - ahc_check_tags(ahc, xs); - xs->flags |= ITSDONE; - scsi_done(xs); + ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); + + /* + * Ensure that the reset has finished + */ + wait = 1000; + do { + ahc_delay(1000); + } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); + + if (wait == 0) { + printf("%s: WARNING - Failed chip reset! " + "Trying to initialize anyway.\n", ahc_name(ahc)); + } + ahc_outb(ahc, HCNTRL, ahc->pause); + + /* Determine channel configuration */ + sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); + /* No Twin Channel PCI cards */ + if ((ahc->chip & AHC_PCI) != 0) + sblkctl &= ~SELBUSB; + switch (sblkctl) { + case 0: + /* Single Narrow Channel */ + break; + case 2: + /* Wide Channel */ + ahc->features |= AHC_WIDE; + break; + case 8: + /* Twin Channel */ + ahc->features |= AHC_TWIN; + break; + default: + printf(" Unsupported adapter type. Ignoring\n"); + return(-1); } /* - * If there are entries in the software queue, try to - * run the first one. We should be more or less guaranteed - * to succeed, since we just freed an SCB. + * Reload sxfrctl1. * - * NOTE: ahc_scsi_cmd() relies on our calling it with - * the first entry in the queue. + * We must always initialize STPWEN to 1 before we + * restore the saved values. STPWEN is initialized + * to a tri-state condition which can only be cleared + * by turning it on. */ - if ((xs = ahc->sc_xxxq.lh_first) != NULL) - (void) ahc_scsi_cmd(xs); + if ((ahc->features & AHC_TWIN) != 0) { + u_int sblkctl; + + sblkctl = ahc_inb(ahc, SBLKCTL); + ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); + ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); + ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); + } + ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); + +#ifdef AHC_DUMP_SEQ + if (ahc->init_level == 0) + ahc_dumpseq(ahc); +#endif + + return (0); } /* * Determine the number of SCBs available on the controller */ int -ahc_probe_scbs(ahc) - struct ahc_softc *ahc; -{ +ahc_probe_scbs(struct ahc_softc *ahc) { int i; for (i = 0; i < AHC_SCB_MAX; i++) { + ahc_outb(ahc, SCBPTR, i); - ahc_outb(ahc, SCB_CONTROL, i); - if (ahc_inb(ahc, SCB_CONTROL) != i) + ahc_outb(ahc, SCB_BASE, i); + if (ahc_inb(ahc, SCB_BASE) != i) break; ahc_outb(ahc, SCBPTR, 0); - if (ahc_inb(ahc, SCB_CONTROL) != 0) + if (ahc_inb(ahc, SCB_BASE) != 0) break; } - return (i); } +#ifndef __OpenBSD__ +static void +ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) +{ + bus_addr_t *baddr; + + baddr = (bus_addr_t *)arg; + *baddr = segs->ds_addr; +} +#endif + +#ifndef __OpenBSD__ +static void +#else +void +#endif +ahc_build_free_scb_list(struct ahc_softc *ahc) +{ + int i; + + for (i = 0; i < ahc->scb_data->maxhscbs; i++) { + ahc_outb(ahc, SCBPTR, i); + + /* Clear the control byte. */ + ahc_outb(ahc, SCB_CONTROL, 0); + + /* Set the next pointer */ + if ((ahc->flags & AHC_PAGESCBS) != 0) + ahc_outb(ahc, SCB_NEXT, i+1); + else + ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); + + /* Make the tag number invalid */ + ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); + } + + /* Make sure that the last SCB terminates the free list */ + ahc_outb(ahc, SCBPTR, i-1); + ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); + + /* Ensure we clear the 0 SCB's control byte. */ + ahc_outb(ahc, SCBPTR, 0); + ahc_outb(ahc, SCB_CONTROL, 0); +} + +#ifndef __OpenBSD__ +static int +ahc_init_scbdata(struct ahc_softc *ahc) +{ + struct scb_data *scb_data; + + scb_data = ahc->scb_data; + SLIST_INIT(&scb_data->free_scbs); + SLIST_INIT(&scb_data->sg_maps); + + /* Allocate SCB resources */ + scb_data->scbarray = + (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX, + M_DEVBUF, M_NOWAIT); + if (scb_data->scbarray == NULL) + return (ENOMEM); + memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX); + + /* Determine the number of hardware SCBs and initialize them */ + + scb_data->maxhscbs = ahc_probe_scbs(ahc); + if ((ahc->flags & AHC_PAGESCBS) != 0) { + /* SCB 0 heads the free list */ + ahc_outb(ahc, FREE_SCBH, 0); + } else { + ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); + } + + if (ahc->scb_data->maxhscbs == 0) { + printf("%s: No SCB space found\n", ahc_name(ahc)); + return (ENXIO); + } + + ahc_build_free_scb_list(ahc); + + /* + * Create our DMA tags. These tags define the kinds of device + * accessible memory allocations and memory mappings we will + * need to perform during normal operation. + * + * Unless we need to further restrict the allocation, we rely + * on the restrictions of the parent dmat, hence the common + * use of MAXADDR and MAXSIZE. + */ + + /* DMA tag for our hardware scb structures */ + if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, + /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, + /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, + /*highaddr*/BUS_SPACE_MAXADDR, + /*filter*/NULL, /*filterarg*/NULL, + AHC_SCB_MAX * sizeof(struct hardware_scb), + /*nsegments*/1, + /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, + /*flags*/0, &scb_data->hscb_dmat) != 0) { + goto error_exit; + } + + scb_data->init_level++; + + /* Allocation for our hscbs */ + if (ahc_dmamem_alloc(ahc, scb_data->hscb_dmat, + (void **)&scb_data->hscbs, + BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) { + goto error_exit; + } + + scb_data->init_level++; + + /* And permanently map them */ + ahc_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap, + scb_data->hscbs, + AHC_SCB_MAX * sizeof(struct hardware_scb), + ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0); + + scb_data->init_level++; + + /* DMA tag for our sense buffers */ + if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, + /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, + /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, + /*highaddr*/BUS_SPACE_MAXADDR, + /*filter*/NULL, /*filterarg*/NULL, + AHC_SCB_MAX * sizeof(struct scsi_sense_data), + /*nsegments*/1, + /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, + /*flags*/0, &scb_data->sense_dmat) != 0) { + goto error_exit; + } + + scb_data->init_level++; + + /* Allocate them */ + if (ahc_dmamem_alloc(ahc, scb_data->sense_dmat, + (void **)&scb_data->sense, + BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) { + goto error_exit; + } + + scb_data->init_level++; + + /* And permanently map them */ + ahc_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap, + scb_data->sense, + AHC_SCB_MAX * sizeof(struct scsi_sense_data), + ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0); + + scb_data->init_level++; + + /* DMA tag for our S/G structures. We allocate in page sized chunks */ + if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, + /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, + /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, + /*highaddr*/BUS_SPACE_MAXADDR, + /*filter*/NULL, /*filterarg*/NULL, + PAGE_SIZE, /*nsegments*/1, + /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, + /*flags*/0, &scb_data->sg_dmat) != 0) { + goto error_exit; + } + + scb_data->init_level++; + + /* Perform initial CCB allocation */ + memset(scb_data->hscbs, 0, AHC_SCB_MAX * sizeof(struct hardware_scb)); + ahc_alloc_scbs(ahc); + + if (scb_data->numscbs == 0) { + printf("%s: ahc_init_scbdata - " + "Unable to allocate initial scbs\n", + ahc_name(ahc)); + goto error_exit; + } + + /* + * Tell the sequencer which SCB will be the next one it receives. + */ + ahc->next_queued_scb = ahc_get_scb(ahc); + ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); + + /* + * Note that we were successfull + */ + return (0); + +error_exit: + + return (ENOMEM); +} + +static void +ahc_fini_scbdata(struct ahc_softc *ahc) +{ + struct scb_data *scb_data; + + scb_data = ahc->scb_data; + if (scb_data == NULL) + return; + + switch (scb_data->init_level) { + default: + case 7: + { + struct sg_map_node *sg_map; + + while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { + SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); + ahc_dmamap_unload(ahc, scb_data->sg_dmat, + sg_map->sg_dmamap); + ahc_dmamem_free(ahc, scb_data->sg_dmat, + sg_map->sg_vaddr, + sg_map->sg_dmamap); + free(sg_map, M_DEVBUF); + } + ahc_dma_tag_destroy(ahc, scb_data->sg_dmat); + } + case 6: + ahc_dmamap_unload(ahc, scb_data->sense_dmat, + scb_data->sense_dmamap); + case 5: + ahc_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense, + scb_data->sense_dmamap); + ahc_dmamap_destroy(ahc, scb_data->sense_dmat, + scb_data->sense_dmamap); + case 4: + ahc_dma_tag_destroy(ahc, scb_data->sense_dmat); + case 3: + ahc_dmamap_unload(ahc, scb_data->hscb_dmat, + scb_data->hscb_dmamap); + case 2: + ahc_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs, + scb_data->hscb_dmamap); + ahc_dmamap_destroy(ahc, scb_data->hscb_dmat, + scb_data->hscb_dmamap); + case 1: + ahc_dma_tag_destroy(ahc, scb_data->hscb_dmat); + break; + case 0: + break; + } + if (scb_data->scbarray != NULL) + free(scb_data->scbarray, M_DEVBUF); +} + +void +ahc_alloc_scbs(struct ahc_softc *ahc) +{ + struct scb_data *scb_data; + struct scb *next_scb; + struct sg_map_node *sg_map; + bus_addr_t physaddr; + struct ahc_dma_seg *segs; + int newcount; + int i; + + scb_data = ahc->scb_data; + if (scb_data->numscbs >= AHC_SCB_MAX) + /* Can't allocate any more */ + return; + + next_scb = &scb_data->scbarray[scb_data->numscbs]; + + sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); + + if (sg_map == NULL) + return; + + /* Allocate S/G space for the next batch of SCBS */ + if (ahc_dmamem_alloc(ahc, scb_data->sg_dmat, + (void **)&sg_map->sg_vaddr, + BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) { + free(sg_map, M_DEVBUF); + return; + } + + SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); + + ahc_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap, + sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb, + &sg_map->sg_physaddr, /*flags*/0); + + segs = sg_map->sg_vaddr; + physaddr = sg_map->sg_physaddr; + + newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); + for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) { + struct scb_platform_data *pdata; +#ifndef __linux__ + int error; +#endif + pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), + M_DEVBUF, M_NOWAIT); + if (pdata == NULL) + break; + next_scb->platform_data = pdata; + next_scb->sg_map = sg_map; + next_scb->sg_list = segs; + /* + * The sequencer always starts with the second entry. + * The first entry is embedded in the scb. + */ + next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); + next_scb->ahc_softc = ahc; + next_scb->flags = SCB_FREE; +#ifndef __linux__ + error = ahc_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0, + &next_scb->dmamap); + if (error != 0) + break; +#endif + next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; + next_scb->hscb->tag = ahc->scb_data->numscbs; + SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, + next_scb, links.sle); + segs += AHC_NSEG; + physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); + next_scb++; + ahc->scb_data->numscbs++; + } +} +#endif /* __OpenBSD__ */ + +void +ahc_controller_info(struct ahc_softc *ahc, char *buf) +{ + int len; + + len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); + buf += len; + if ((ahc->features & AHC_TWIN) != 0) + len = sprintf(buf, "Twin Channel, A SCSI Id=%d, " + "B SCSI Id=%d, primary %c, ", + ahc->our_id, ahc->our_id_b, + (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A'); + else { + const char *speed; + const char *type; + + speed = ""; + if ((ahc->features & AHC_ULTRA) != 0) { + speed = "Ultra "; + } else if ((ahc->features & AHC_DT) != 0) { + speed = "Ultra160 "; + } else if ((ahc->features & AHC_ULTRA2) != 0) { + speed = "Ultra2 "; + } + if ((ahc->features & AHC_WIDE) != 0) { + type = "Wide"; + } else { + type = "Single"; + } + len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ", + speed, type, ahc->channel, ahc->our_id); + } + buf += len; + + if ((ahc->flags & AHC_PAGESCBS) != 0) + sprintf(buf, "%d/%d SCBs", + ahc->scb_data->maxhscbs, AHC_SCB_MAX); + else + sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs); +} + /* * Start the board, ready for normal operation */ int -ahc_init(ahc) - struct ahc_softc *ahc; +ahc_init(struct ahc_softc *ahc) { - int max_targ = 15; - int i; - int term; - u_int scsi_conf; - u_int scsiseq_template; - u_int ultraenb; - u_int discenable; - u_int tagenable; - size_t driver_data_size; - u_int32_t physaddr; - struct scb_data *scb_data = NULL; + int max_targ; + int i; + int term; + u_int scsi_conf; + u_int scsiseq_template; + u_int ultraenb; + u_int discenable; + u_int tagenable; + size_t driver_data_size; + uint32_t physaddr; + +#define AHC_DEBUG_SEQUENCER +#ifdef AHC_DEBUG_SEQUENCER + ahc->flags |= AHC_SEQUENCER_DEBUG; +#endif #ifdef AHC_PRINT_SRAM printf("Scratch Ram:"); @@ -3598,16 +4224,7 @@ ahc_init(ahc) } printf ("\n"); #endif - - if (ahc->scb_data == NULL) { - scb_data = malloc(sizeof (struct scb_data), M_DEVBUF, M_NOWAIT); - if (scb_data == NULL) { - printf("%s: cannot malloc scb_data!\n", ahc_name(ahc)); - return (ENOMEM); - } - bzero(scb_data, sizeof(struct scb_data)); - ahc->scb_data = scb_data; - } + max_targ = 15; /* * Assume we have a board at this stage and it has been reset. */ @@ -3617,82 +4234,131 @@ ahc_init(ahc) /* * Default to allowing initiator operations. */ - ahc->flags |= AHC_INITIATORMODE; - + ahc->flags |= AHC_INITIATORROLE; + + /* + * Only allow target mode features if this unit has them enabled. + */ + if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0) + ahc->features &= ~AHC_TARGETMODE; + +#if !defined(__linux__) && !defined(__OpenBSD__) + /* DMA tag for mapping buffers into device visible space. */ + if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, + /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, + /*lowaddr*/BUS_SPACE_MAXADDR, + /*highaddr*/BUS_SPACE_MAXADDR, + /*filter*/NULL, /*filterarg*/NULL, + /*maxsize*/MAXBSIZE, /*nsegments*/AHC_NSEG, + /*maxsegsz*/AHC_MAXTRANSFER_SIZE, + /*flags*/BUS_DMA_ALLOCNOW, + &ahc->buffer_dmat) != 0) { + return (ENOMEM); + } +#endif + + ahc->init_level++; + /* * DMA tag for our command fifos and other data in system memory * the card's sequencer must be able to access. For initiator - * roles, we need to allocate space for the qinfifo, qoutfifo, - * and untagged_scb arrays each of which are composed of 256 - * 1 byte elements. When providing for the target mode role, - * we additionally must provide space for the incoming target - * command fifo. + * roles, we need to allocate space for the the qinfifo and qoutfifo. + * The qinfifo and qoutfifo are composed of 256 1 byte elements. + * When providing for the target mode role, we must additionally + * provide space for the incoming target command fifo and an extra + * byte to deal with a dma bug in some chip versions. */ - driver_data_size = 3 * 256 * sizeof(u_int8_t); - - if (ahc_createdmamem(ahc, driver_data_size, + driver_data_size = 2 * 256 * sizeof(uint8_t); +#ifdef __OpenBSD__ + if (ahc_createdmamem(ahc, ahc->shared_data_dmat, driver_data_size, &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, &ahc->shared_data_busaddr, &ahc->shared_data_seg, &ahc->shared_data_nseg, "shared data") < 0) return (ENOMEM); ahc->init_level++; +#else - /* Allocate SCB data now that sc_dmat is initialized */ - if (ahc->scb_data->maxhscbs == 0) - if (ahcinitscbdata(ahc) != 0) - return (ENOMEM); + if ((ahc->features & AHC_TARGETMODE) != 0) + driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd) + + /*DMA WideOdd Bug Buffer*/1; + if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, + /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, + /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, + /*highaddr*/BUS_SPACE_MAXADDR, + /*filter*/NULL, /*filterarg*/NULL, + driver_data_size, + /*nsegments*/1, + /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, + /*flags*/0, &ahc->shared_data_dmat) != 0) { + return (ENOMEM); + } + + ahc->init_level++; + + /* Allocation of driver data */ + if (ahc_dmamem_alloc(ahc, ahc->shared_data_dmat, + (void **)&ahc->qoutfifo, + BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) { + return (ENOMEM); + } + + ahc->init_level++; + /* And permanently map it in */ + ahc_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap, + ahc->qoutfifo, driver_data_size, ahc_dmamap_cb, + &ahc->shared_data_busaddr, /*flags*/0); + if ((ahc->features & AHC_TARGETMODE) != 0) { + ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo; + ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS]; + ahc->dma_bug_buf = ahc->shared_data_busaddr + + driver_data_size - 1; + /* All target command blocks start out invalid. */ + for (i = 0; i < AHC_TMODE_CMDS; i++) + ahc->targetcmds[i].cmd_valid = 0; + ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD); + ahc->tqinfifonext = 1; + ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1); + ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); + ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256]; + } +#endif ahc->qinfifo = &ahc->qoutfifo[256]; - ahc->untagged_scbs = &ahc->qinfifo[256]; - /* There are no untagged SCBs active yet. */ - for (i = 0; i < 256; i++) - ahc->untagged_scbs[i] = SCB_LIST_NULL; - /* All of our queues are empty */ - for (i = 0; i < 256; i++) - ahc->qoutfifo[i] = SCB_LIST_NULL; + ahc->init_level++; + + /* Allocate SCB data now that buffer_dmat is initialized */ + if (ahc->scb_data->maxhscbs == 0) + if (ahc_init_scbdata(ahc) != 0) + return (ENOMEM); - bus_dmamap_sync(ahc->sc_dmat, ahc->shared_data_dmamap, - 0, driver_data_size, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); - /* * Allocate a tstate to house information for our * initiator presence on the bus as well as the user * data for any target mode initiator. */ if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { - printf("%s: unable to allocate tmode_tstate. " + printf("%s: unable to allocate ahc_tmode_tstate. " "Failing attach\n", ahc_name(ahc)); - return (-1); + return (ENOMEM); } if ((ahc->features & AHC_TWIN) != 0) { if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { - printf("%s: unable to allocate tmode_tstate. " + printf("%s: unable to allocate ahc_tmode_tstate. " "Failing attach\n", ahc_name(ahc)); - return (-1); - } - printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ", - ahc->our_id, ahc->our_id_b, - ahc->flags & AHC_CHANNEL_B_PRIMARY? 'B': 'A'); - } else { - if ((ahc->features & AHC_WIDE) != 0) { - printf("Wide "); - } else { - printf("Single "); + return (ENOMEM); } - printf("Channel %c, SCSI Id=%d, ", ahc->channel, ahc->our_id); } ahc_outb(ahc, SEQ_FLAGS, 0); + ahc_outb(ahc, SEQ_FLAGS2, 0); if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) { ahc->flags |= AHC_PAGESCBS; - printf("%d/%d SCBs\n", ahc->scb_data->maxhscbs, AHC_SCB_MAX); } else { ahc->flags &= ~AHC_PAGESCBS; - printf("%d SCBs\n", ahc->scb_data->maxhscbs); } #ifdef AHC_DEBUG @@ -3706,31 +4372,32 @@ ahc_init(ahc) } #endif /* AHC_DEBUG */ - /* Set the SCSI Id,SXFRCTL0,SXFRCTL1, and SIMODE1, for both channels*/ + /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ if (ahc->features & AHC_TWIN) { /* * The device is gated to channel B after a chip reset, * so set those values first */ + ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; - if ((ahc->features & AHC_ULTRA2) != 0) - ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id_b); - else - ahc_outb(ahc, SCSIID, ahc->our_id_b); + ahc_outb(ahc, SCSIID, ahc->our_id_b); scsi_conf = ahc_inb(ahc, SCSICONF + 1); ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) - |term|ENSTIMER|ACTNEGEN); + |term|ahc->seltime_b|ENSTIMER|ACTNEGEN); + if ((ahc->features & AHC_ULTRA2) != 0) + ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); if ((scsi_conf & RESET_SCSI) != 0 - && (ahc->flags & AHC_INITIATORMODE) != 0) + && (ahc->flags & AHC_INITIATORROLE) != 0) ahc->flags |= AHC_RESET_BUS_B; /* Select Channel A */ ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); } + term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; if ((ahc->features & AHC_ULTRA2) != 0) ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); @@ -3738,13 +4405,15 @@ ahc_init(ahc) ahc_outb(ahc, SCSIID, ahc->our_id); scsi_conf = ahc_inb(ahc, SCSICONF); ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) - |term + |term|ahc->seltime |ENSTIMER|ACTNEGEN); + if ((ahc->features & AHC_ULTRA2) != 0) + ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); if ((scsi_conf & RESET_SCSI) != 0 - && (ahc->flags & AHC_INITIATORMODE) != 0) + && (ahc->flags & AHC_INITIATORROLE) != 0) ahc->flags |= AHC_RESET_BUS_A; /* @@ -3776,7 +4445,7 @@ ahc_init(ahc) for (i = 0; i <= max_targ; i++) { struct ahc_initiator_tinfo *tinfo; - struct tmode_tstate *tstate; + struct ahc_tmode_tstate *tstate; u_int our_id; u_int target_id; char channel; @@ -3792,7 +4461,7 @@ ahc_init(ahc) tinfo = ahc_fetch_transinfo(ahc, channel, our_id, target_id, &tstate); /* Default to async narrow across the board */ - bzero(tinfo, sizeof(*tinfo)); + memset(tinfo, 0, sizeof(*tinfo)); if (ahc->flags & AHC_USEDEFAULTS) { if ((ahc->features & AHC_WIDE) != 0) tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; @@ -3805,7 +4474,7 @@ ahc_init(ahc) tinfo->user.offset = ~0; } else { u_int scsirate; - u_int16_t mask; + uint16_t mask; /* Take the settings leftover in scratch RAM. */ scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); @@ -3826,6 +4495,9 @@ ahc_init(ahc) offset = MAX_OFFSET_ULTRA2; } else offset = ahc_inb(ahc, TARG_OFFSET + i); + if ((scsirate & ~WIDEXFER) == 0 && offset != 0) + /* Set to the lowest sync rate, 5MHz */ + scsirate |= 0x1c; maxsync = AHC_SYNCRATE_ULTRA2; if ((ahc->features & AHC_DT) != 0) maxsync = AHC_SYNCRATE_DT; @@ -3835,7 +4507,17 @@ ahc_init(ahc) tinfo->user.period = 0; else tinfo->user.offset = ~0; + if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/ + && (ahc->features & AHC_DT) != 0) + tinfo->user.ppr_options = + MSG_EXT_PPR_DT_REQ; } else if ((scsirate & SOFS) != 0) { + if ((scsirate & SXFR) == 0x40 + && (ultraenb & mask) != 0) { + /* Treat 10MHz as a non-ultra speed */ + scsirate &= ~SXFR; + ultraenb &= ~mask; + } tinfo->user.period = ahc_find_period(ahc, scsirate, (ultraenb & mask) @@ -3844,18 +4526,55 @@ ahc_init(ahc) if (tinfo->user.period != 0) tinfo->user.offset = ~0; } + if (tinfo->user.period == 0) + tinfo->user.offset = 0; if ((scsirate & WIDEXFER) != 0 && (ahc->features & AHC_WIDE) != 0) tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; + tinfo->user.protocol_version = 4; + if ((ahc->features & AHC_DT) != 0) + tinfo->user.transport_version = 3; + else + tinfo->user.transport_version = 2; + tinfo->goal.protocol_version = 2; + tinfo->goal.transport_version = 2; + tinfo->curr.protocol_version = 2; + tinfo->curr.transport_version = 2; } - tinfo->goal = tinfo->user; /* force negotiation */ tstate->ultraenb = ultraenb; - tstate->discenable = discenable; - tstate->tagenable = 0; /* Wait until the XPT says its okay */ } ahc->user_discenable = discenable; ahc->user_tagenable = tagenable; + /* There are no untagged SCBs active yet. */ + for (i = 0; i < 16; i++) { + ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0)); + if ((ahc->flags & AHC_SCB_BTT) != 0) { + int lun; + + /* + * The SCB based BTT allows an entry per + * target and lun pair. + */ + for (lun = 1; lun < AHC_NUM_LUNS; lun++) + ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun)); + } + } + + /* All of our queues are empty */ + for (i = 0; i < 256; i++) + ahc->qoutfifo[i] = SCB_LIST_NULL; + + ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD); + + for (i = 0; i < 256; i++) + ahc->qinfifo[i] = SCB_LIST_NULL; + + if ((ahc->features & AHC_MULTI_TID) != 0) { + ahc_outb(ahc, TARGID, 0); + ahc_outb(ahc, TARGID + 1, 0); + } + /* * Tell the sequencer where it can find our arrays in memory. */ @@ -3866,17 +4585,10 @@ ahc_init(ahc) ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); physaddr = ahc->shared_data_busaddr; - ahc_outb(ahc, SCBID_ADDR, physaddr & 0xFF); - ahc_outb(ahc, SCBID_ADDR + 1, (physaddr >> 8) & 0xFF); - ahc_outb(ahc, SCBID_ADDR + 2, (physaddr >> 16) & 0xFF); - ahc_outb(ahc, SCBID_ADDR + 3, (physaddr >> 24) & 0xFF); - - /* Target mode incomding command fifo */ - physaddr += 3 * 256 * sizeof(u_int8_t); - ahc_outb(ahc, TMODE_CMDADDR, physaddr & 0xFF); - ahc_outb(ahc, TMODE_CMDADDR + 1, (physaddr >> 8) & 0xFF); - ahc_outb(ahc, TMODE_CMDADDR + 2, (physaddr >> 16) & 0xFF); - ahc_outb(ahc, TMODE_CMDADDR + 3, (physaddr >> 24) & 0xFF); + ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF); + ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF); + ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF); + ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF); /* * Initialize the group code to command length table. @@ -3897,16 +4609,6 @@ ahc_init(ahc) ahc_outb(ahc, QINPOS, 0); ahc_outb(ahc, QOUTPOS, 0); -#ifdef AHC_DEBUG - if (ahc_debug & AHC_SHOWMISC) - printf("DISCENABLE == 0x%x\nULTRAENB == 0x%x\n", - discenable, ultraenb); -#endif - - /* Don't have any special messages to send to targets */ - ahc_outb(ahc, TARGET_MSG_REQUEST, 0); - ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 0); - /* * Use the built in queue management registers * if they are available. @@ -3918,7 +4620,6 @@ ahc_init(ahc) ahc_outb(ahc, HNSCB_QOFF, 0); } - /* We don't have any waiting selections */ ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); @@ -3930,11 +4631,11 @@ ahc_init(ahc) /* * Setup the allowed SCSI Sequences based on operational mode. - * If we are a target, we'll enable select in operations once + * If we are a target, we'll enalbe select in operations once * we've had a lun enabled. */ scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; - if ((ahc->flags & AHC_INITIATORMODE) != 0) + if ((ahc->flags & AHC_INITIATORROLE) != 0) scsiseq_template |= ENRSELI; ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); @@ -3948,1325 +4649,702 @@ ahc_init(ahc) ahc_loadseq(ahc); - /* We have to wait until after any system dumps... */ - shutdownhook_establish(ahc_shutdown, ahc); - return (0); -} - -/* - * Routines to manage a scsi_xfer into the software queue. - * We overload xs->free_list to to ensure we don't run into a queue - * resource shortage, and keep a pointer to the last entry around - * to make insertion O(C). - */ -STATIC INLINE void -ahc_list_insert_before(ahc, xs, next_xs) - struct ahc_softc *ahc; - struct scsi_xfer *xs; - struct scsi_xfer *next_xs; -{ - LIST_INSERT_BEFORE(xs, next_xs, free_list); - -} - -STATIC INLINE void -ahc_list_insert_head(ahc, xs) - struct ahc_softc *ahc; - struct scsi_xfer *xs; -{ - if (ahc->sc_xxxq.lh_first == NULL) - ahc->sc_xxxqlast = xs; - LIST_INSERT_HEAD(&ahc->sc_xxxq, xs, free_list); - return; -} - -STATIC INLINE void -ahc_list_insert_tail(ahc, xs) - struct ahc_softc *ahc; - struct scsi_xfer *xs; -{ - if (ahc->sc_xxxq.lh_first == NULL){ - ahc->sc_xxxqlast = xs; - LIST_INSERT_HEAD(&ahc->sc_xxxq, xs, free_list); - return; - } - LIST_INSERT_AFTER(ahc->sc_xxxqlast, xs, free_list); - ahc->sc_xxxqlast = xs; -} + if ((ahc->features & AHC_ULTRA2) != 0) { + int wait; -STATIC INLINE void -ahc_list_remove(ahc, xs) - struct ahc_softc *ahc; - struct scsi_xfer *xs; -{ - struct scsi_xfer *lxs; - if (xs == ahc->sc_xxxqlast) { - lxs = ahc->sc_xxxq.lh_first; - while (lxs != NULL) { - if (LIST_NEXT(lxs, free_list) == ahc->sc_xxxqlast) { - ahc->sc_xxxqlast = lxs; - break; - } - lxs = LIST_NEXT(xs, free_list); - } + /* + * Wait for up to 500ms for our transceivers + * to settle. If the adapter does not have + * a cable attached, the tranceivers may + * never settle, so don't complain if we + * fail here. + */ + ahc_pause(ahc); + for (wait = 5000; + (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; + wait--) + ahc_delay(100); + ahc_unpause(ahc); } - - LIST_REMOVE(xs, free_list); - if (ahc->sc_xxxq.lh_first == NULL) - ahc->sc_xxxqlast = NULL; + return (0); } -STATIC INLINE struct scsi_xfer * -ahc_list_next(ahc, xs) - struct ahc_softc *ahc; - struct scsi_xfer *xs; +void +ahc_intr_enable(struct ahc_softc *ahc, int enable) { - return(LIST_NEXT(xs, free_list)); + u_int hcntrl; + + hcntrl = ahc_inb(ahc, HCNTRL); + hcntrl &= ~INTEN; + ahc->pause &= ~INTEN; + ahc->unpause &= ~INTEN; + if (enable) { + hcntrl |= INTEN; + ahc->pause |= INTEN; + ahc->unpause |= INTEN; + } + ahc_outb(ahc, HCNTRL, hcntrl); } /* - * Pick the first xs for a non-blocked target. + * Ensure that the card is paused in a location + * outside of all critical sections and that all + * pending work is completed prior to returning. + * This routine should only be called from outside + * an interrupt context. */ -STATIC INLINE struct scsi_xfer * -ahc_first_xs(struct ahc_softc *ahc) +void +ahc_pause_and_flushwork(struct ahc_softc *ahc) { - int target; - struct scsi_xfer *xs = ahc->sc_xxxq.lh_first; - - if (ahc->queue_blocked) - return NULL; + int intstat; + int maxloops; - while (xs != NULL) { - target = xs->sc_link->target; - if (ahc->devqueue_blocked[target] == 0 && - ahc_index_busy_tcl(ahc, XS_TCL(ahc, xs), FALSE) == - SCB_LIST_NULL) + maxloops = 1000; + ahc->flags |= AHC_ALL_INTERRUPTS; + intstat = 0; + do { + ahc_intr(ahc); + ahc_pause(ahc); + ahc_clear_critical_section(ahc); + if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0) break; - xs = LIST_NEXT(xs, free_list); - } - - return xs; + maxloops--; + } while (((intstat = ahc_inb(ahc, INTSTAT)) & INT_PEND) && --maxloops); + if (maxloops == 0) { + printf("Infinite interrupt loop, INTSTAT = %x", + ahc_inb(ahc, INTSTAT)); + } + ahc_platform_flushwork(ahc); + ahc->flags &= ~AHC_ALL_INTERRUPTS; } -STATIC int32_t -ahc_scsi_cmd(xs) - struct scsi_xfer *xs; +int +ahc_suspend(struct ahc_softc *ahc) { - struct scsi_xfer *first_xs, *next_xs = NULL; - struct ahc_softc *ahc; - struct scb *scb; - struct hardware_scb *hscb; - struct ahc_initiator_tinfo *tinfo; - struct tmode_tstate *tstate; - u_int target_id; - u_int our_id; - char channel; - int s, tcl; - u_int16_t mask; - int dontqueue = 0, fromqueue = 0; - - SC_DEBUG(xs->sc_link, SDEV_DB3, ("ahc_scsi_cmd\n")); - ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; - - /* must protect the queue */ - s = splbio(); - - if (xs == ahc->sc_xxxq.lh_first) { - /* - * Called from ahc_done. Calling with the first entry in - * the queue is really just a way of seeing where we're - * called from. Now, find the first eligible SCB to send, - * e.g. one which will be accepted immediately. - */ + uint8_t *ptr; + int i; - if (ahc->queue_blocked) { - splx(s); - return (TRY_AGAIN_LATER); - } - - xs = ahc_first_xs(ahc); - if (xs == NULL) { - splx(s); - return (TRY_AGAIN_LATER); - } + ahc_pause_and_flushwork(ahc); - next_xs = ahc_list_next(ahc, xs); - ahc_list_remove(ahc, xs); - fromqueue = 1; - goto get_scb; - } + if (LIST_FIRST(&ahc->pending_scbs) != NULL) + return (EBUSY); - /* determine safety of software queueing */ - dontqueue = xs->flags & SCSI_POLL; - +#if AHC_TARGET_MODE /* - * If no new requests are accepted, just insert into the - * private queue to wait for our turn. + * XXX What about ATIOs that have not yet been serviced? + * Perhaps we should just refuse to be suspended if we + * are acting in a target role. */ - tcl = XS_TCL(ahc, xs); - - if (ahc->queue_blocked || - ahc->devqueue_blocked[xs->sc_link->target] || - (!ahc_istagged_device(ahc, xs, 0) && - ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL)) { - if (dontqueue) { - splx(s); - xs->error = XS_DRIVER_STUFFUP; - return TRY_AGAIN_LATER; - } - ahc_list_insert_tail(ahc, xs); - splx(s); - return SUCCESSFULLY_QUEUED; + if (ahc->pending_device != NULL) + return (EBUSY); +#endif + + /* Save volatile registers */ + if ((ahc->features & AHC_TWIN) != 0) { + ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); + ahc->suspend_state.channel[1].scsiseq = ahc_inb(ahc, SCSISEQ); + ahc->suspend_state.channel[1].sxfrctl0 = ahc_inb(ahc, SXFRCTL0); + ahc->suspend_state.channel[1].sxfrctl1 = ahc_inb(ahc, SXFRCTL1); + ahc->suspend_state.channel[1].simode0 = ahc_inb(ahc, SIMODE0); + ahc->suspend_state.channel[1].simode1 = ahc_inb(ahc, SIMODE1); + ahc->suspend_state.channel[1].seltimer = ahc_inb(ahc, SELTIMER); + ahc->suspend_state.channel[1].seqctl = ahc_inb(ahc, SEQCTL); + ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); } + ahc->suspend_state.channel[0].scsiseq = ahc_inb(ahc, SCSISEQ); + ahc->suspend_state.channel[0].sxfrctl0 = ahc_inb(ahc, SXFRCTL0); + ahc->suspend_state.channel[0].sxfrctl1 = ahc_inb(ahc, SXFRCTL1); + ahc->suspend_state.channel[0].simode0 = ahc_inb(ahc, SIMODE0); + ahc->suspend_state.channel[0].simode1 = ahc_inb(ahc, SIMODE1); + ahc->suspend_state.channel[0].seltimer = ahc_inb(ahc, SELTIMER); + ahc->suspend_state.channel[0].seqctl = ahc_inb(ahc, SEQCTL); - first_xs = ahc_first_xs(ahc); - - /* determine safety of software queueing */ - dontqueue = xs->flags & SCSI_POLL; - - /* - * Handle situations where there's already entries in the - * queue. - */ - if (first_xs != NULL) { - /* - * If we can't queue, we have to abort, since - * we have to preserve order. - */ - if (dontqueue) { - splx(s); - xs->error = XS_DRIVER_STUFFUP; - return (TRY_AGAIN_LATER); - } + if ((ahc->chip & AHC_PCI) != 0) { + ahc->suspend_state.dscommand0 = ahc_inb(ahc, DSCOMMAND0); + ahc->suspend_state.dspcistatus = ahc_inb(ahc, DSPCISTATUS); + } - /* - * Swap with the first queue entry. - */ - ahc_list_insert_tail(ahc, xs); - xs = first_xs; - next_xs = ahc_list_next(ahc, xs); - ahc_list_remove(ahc, xs); - fromqueue = 1; + if ((ahc->features & AHC_DT) != 0) { + u_int sfunct; + sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; + ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); + ahc->suspend_state.optionmode = ahc_inb(ahc, OPTIONMODE); + ahc_outb(ahc, SFUNCT, sfunct); + ahc->suspend_state.crccontrol1 = ahc_inb(ahc, CRCCONTROL1); } -get_scb: + if ((ahc->features & AHC_MULTI_FUNC) != 0) + ahc->suspend_state.scbbaddr = ahc_inb(ahc, SCBBADDR); - target_id = xs->sc_link->target; - our_id = SIM_SCSI_ID(ahc, xs->sc_link); + if ((ahc->features & AHC_ULTRA2) != 0) + ahc->suspend_state.dff_thrsh = ahc_inb(ahc, DFF_THRSH); - /* - * get an scb to use. - */ - if ((scb = ahcgetscb(ahc)) == NULL) { + ptr = ahc->suspend_state.scratch_ram; + for (i = 0; i < 64; i++) + *ptr++ = ahc_inb(ahc, SRAM_BASE + i); - if (dontqueue) { - splx(s); - xs->error = XS_DRIVER_STUFFUP; - return (TRY_AGAIN_LATER); - } - - /* - * If we were pulled off the queue, put ourselves - * back to where we came from, otherwise tack ourselves - * onto the end. - */ - if (fromqueue && next_xs != NULL) - ahc_list_insert_before(ahc, xs, next_xs); - else - ahc_list_insert_tail(ahc, xs); - - splx(s); - return (SUCCESSFULLY_QUEUED); + if ((ahc->features & AHC_MORE_SRAM) != 0) { + for (i = 0; i < 16; i++) + *ptr++ = ahc_inb(ahc, TARG_OFFSET + i); } - tcl = XS_TCL(ahc, xs); + ptr = ahc->suspend_state.btt; + if ((ahc->flags & AHC_SCB_BTT) != 0) { + for (i = 0;i < AHC_NUM_TARGETS; i++) { + int j; -#ifdef DIAGNOSTIC - if (!ahc_istagged_device(ahc, xs, 0) && - ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) - panic("ahc: queuing for busy target"); -#endif - - scb->xs = xs; - hscb = scb->hscb; - hscb->tcl = tcl; - timeout_set(&xs->stimeout, ahc_timeout, scb); + for (j = 0;j < AHC_NUM_LUNS; j++) { + u_int tcl; - if (ahc_istagged_device(ahc, xs, 0)) - scb->hscb->control |= TAG_ENB; - else - ahc_busy_tcl(ahc, scb); - - splx(s); - - channel = SIM_CHANNEL(ahc, xs->sc_link); - if (ahc->inited_channels[channel - 'A'] == 0) { - if ((channel == 'A' && (ahc->flags & AHC_RESET_BUS_A)) || - (channel == 'B' && (ahc->flags & AHC_RESET_BUS_B))) { - s = splbio(); - ahc_reset_channel(ahc, channel, TRUE); - splx(s); + tcl = BUILD_TCL(i << 4, j); + *ptr = ahc_index_busy_tcl(ahc, tcl); + } } - ahc->inited_channels[channel - 'A'] = 1; - } - - /* - * Put all the arguments for the xfer in the scb - */ - - mask = SCB_TARGET_MASK(scb); - tinfo = ahc_fetch_transinfo(ahc, SIM_CHANNEL(ahc, xs->sc_link), our_id, - target_id, &tstate); - if (ahc->inited_targets[target_id] == 0) { - struct ahc_devinfo devinfo; - - s = splbio(); - ahc_compile_devinfo(&devinfo, our_id, target_id, - xs->sc_link->lun, SIM_CHANNEL(ahc, xs->sc_link), - ROLE_INITIATOR); - ahc_update_target_msg_request(ahc, &devinfo, tinfo, TRUE, - FALSE); - ahc->inited_targets[target_id] = 1; - splx(s); } - - hscb->scsirate = tinfo->scsirate; - hscb->scsioffset = tinfo->current.offset; - if ((tstate->ultraenb & mask) != 0) - hscb->control |= ULTRAENB; - - if ((tstate->discenable & mask) != 0) - hscb->control |= DISCENB; - - if (xs->flags & SCSI_RESET) { - hscb->cmdpointer = NULL; - scb->flags |= SCB_DEVICE_RESET; - hscb->control |= MK_MESSAGE; - return ahc_execute_scb(scb, NULL, 0); - } - - return ahc_setup_data(ahc, xs, scb); + ahc_shutdown(ahc); + return (0); } -STATIC int -ahc_execute_scb(arg, dm_segs, nsegments) - void *arg; - bus_dma_segment_t *dm_segs; - int nsegments; +int +ahc_resume(struct ahc_softc *ahc) { - struct scb *scb; - struct scsi_xfer *xs; - struct ahc_softc *ahc; - int s; - - scb = (struct scb *)arg; - xs = scb->xs; - ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; - - - if (nsegments != 0) { - struct ahc_dma_seg *sg; - bus_dma_segment_t *end_seg; - int op; + uint8_t *ptr; + int i; - end_seg = dm_segs + nsegments; - - /* Copy the first SG into the data pointer area */ - scb->hscb->data = dm_segs->ds_addr; - scb->hscb->datalen = dm_segs->ds_len; + ahc_reset(ahc); - /* Copy the segments into our SG list */ - sg = scb->sg_list; - while (dm_segs < end_seg) { - sg->addr = dm_segs->ds_addr; - sg->len = dm_segs->ds_len; - ahc_swap_sg(sg); - sg++; - dm_segs++; - } + ahc_build_free_scb_list(ahc); - /* Note where to find the SG entries in bus space */ - scb->hscb->SG_pointer = scb->sg_list_phys; - if ((scb->xs->flags & SCSI_DATA_IN) != 0) - op = BUS_DMASYNC_PREREAD; - else - op = BUS_DMASYNC_PREWRITE; - bus_dmamap_sync(ahc->sc_dmat, scb->dmamap, - 0, scb->dmamap->dm_mapsize, op); - } else { - scb->hscb->SG_pointer = 0; - scb->hscb->data = 0; - scb->hscb->datalen = 0; + /* Restore volatile registers */ + if ((ahc->features & AHC_TWIN) != 0) { + ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); + ahc_outb(ahc, SCSIID, ahc->our_id); + ahc_outb(ahc, SCSISEQ, ahc->suspend_state.channel[1].scsiseq); + ahc_outb(ahc, SXFRCTL0, ahc->suspend_state.channel[1].sxfrctl0); + ahc_outb(ahc, SXFRCTL1, ahc->suspend_state.channel[1].sxfrctl1); + ahc_outb(ahc, SIMODE0, ahc->suspend_state.channel[1].simode0); + ahc_outb(ahc, SIMODE1, ahc->suspend_state.channel[1].simode1); + ahc_outb(ahc, SELTIMER, ahc->suspend_state.channel[1].seltimer); + ahc_outb(ahc, SEQCTL, ahc->suspend_state.channel[1].seqctl); + ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); } - - scb->sg_count = scb->hscb->SG_count = nsegments; - - s = splbio(); + ahc_outb(ahc, SCSISEQ, ahc->suspend_state.channel[0].scsiseq); + ahc_outb(ahc, SXFRCTL0, ahc->suspend_state.channel[0].sxfrctl0); + ahc_outb(ahc, SXFRCTL1, ahc->suspend_state.channel[0].sxfrctl1); + ahc_outb(ahc, SIMODE0, ahc->suspend_state.channel[0].simode0); + ahc_outb(ahc, SIMODE1, ahc->suspend_state.channel[0].simode1); + ahc_outb(ahc, SELTIMER, ahc->suspend_state.channel[0].seltimer); + ahc_outb(ahc, SEQCTL, ahc->suspend_state.channel[0].seqctl); + if ((ahc->features & AHC_ULTRA2) != 0) + ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); + else + ahc_outb(ahc, SCSIID, ahc->our_id); - /* - * Last time we need to check if this SCB needs to - * be aborted. - */ - if (xs->flags & ITSDONE) { - if (!ahc_istagged_device(ahc, xs, 0)) - ahc_index_busy_tcl(ahc, scb->hscb->tcl, TRUE); - if (nsegments != 0) - bus_dmamap_unload(ahc->sc_dmat, scb->dmamap); - ahcfreescb(ahc, scb); - splx(s); - return (COMPLETE); - } - -#ifdef DIAGNOSTIC - if (scb->sg_count > 255) - panic("ahc bad sg_count"); -#endif + if ((ahc->chip & AHC_PCI) != 0) { + ahc_outb(ahc, DSCOMMAND0, ahc->suspend_state.dscommand0); + ahc_outb(ahc, DSPCISTATUS, ahc->suspend_state.dspcistatus); + } - ahc_swap_hscb(scb->hscb); - - LIST_INSERT_HEAD(&ahc->pending_scbs, scb, pend_links); + if ((ahc->features & AHC_DT) != 0) { + u_int sfunct; - scb->flags |= SCB_ACTIVE; + sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; + ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); + ahc_outb(ahc, OPTIONMODE, ahc->suspend_state.optionmode); + ahc_outb(ahc, SFUNCT, sfunct); + ahc_outb(ahc, CRCCONTROL1, ahc->suspend_state.crccontrol1); + } - if (!(xs->flags & SCSI_POLL)) - timeout_add(&xs->stimeout, (xs->timeout * hz) / 1000); + if ((ahc->features & AHC_MULTI_FUNC) != 0) + ahc_outb(ahc, SCBBADDR, ahc->suspend_state.scbbaddr); - if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { -#if 0 - printf("Continueing Immediate Command %d:%d\n", - xs->sc_link->target, - xs->sc_link->lun); -#endif - pause_sequencer(ahc); - if ((ahc->flags & AHC_PAGESCBS) == 0) - ahc_outb(ahc, SCBPTR, scb->hscb->tag); - ahc_outb(ahc, SCB_TAG, scb->hscb->tag); - ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); - unpause_sequencer(ahc); - } else { + if ((ahc->features & AHC_ULTRA2) != 0) + ahc_outb(ahc, DFF_THRSH, ahc->suspend_state.dff_thrsh); - ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; + ptr = ahc->suspend_state.scratch_ram; + for (i = 0; i < 64; i++) + ahc_outb(ahc, SRAM_BASE + i, *ptr++); - bus_dmamap_sync(ahc->sc_dmat, ahc->shared_data_dmamap, - QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); - - if ((ahc->features & AHC_QUEUE_REGS) != 0) { - ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); - } else { - pause_sequencer(ahc); - ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); - unpause_sequencer(ahc); - } + if ((ahc->features & AHC_MORE_SRAM) != 0) { + for (i = 0; i < 16; i++) + ahc_outb(ahc, TARG_OFFSET + i, *ptr++); } -#ifdef AHC_DEBUG - if (ahc_debug & AHC_SHOWCMDS) { - sc_print_addr(xs->sc_link); - printf("opcode %d tag %x len %d flags %x control %x fpos %u" - " rate %x\n", - xs->cmdstore.opcode, scb->hscb->tag, scb->hscb->datalen, - scb->flags, scb->hscb->control, ahc->qinfifonext, - scb->hscb->scsirate); - } -#endif + ptr = ahc->suspend_state.btt; + if ((ahc->flags & AHC_SCB_BTT) != 0) { + for (i = 0;i < AHC_NUM_TARGETS; i++) { + int j; - if (!(xs->flags & SCSI_POLL)) { - splx(s); - return (SUCCESSFULLY_QUEUED); - } - /* - * If we can't use interrupts, poll for completion - */ - SC_DEBUG(xs->sc_link, SDEV_DB3, ("cmd_poll\n")); - do { - if (ahc_poll(ahc, xs->timeout)) { - if (!(xs->flags & SCSI_SILENT)) - printf("cmd fail\n"); - ahc_timeout(scb); - break; - } - } while (!(xs->flags & ITSDONE)); - splx(s); - return (COMPLETE); -} + for (j = 0;j < AHC_NUM_LUNS; j++) { + u_int tcl; -STATIC int -ahc_poll(ahc, wait) - struct ahc_softc *ahc; - int wait; /* in msec */ -{ - while (--wait) { - DELAY(1000); - if (ahc_inb(ahc, INTSTAT) & INT_PEND) - break; - } - - if (wait == 0) { - printf("%s: board is not responding\n", ahc_name(ahc)); - return (EIO); + tcl = BUILD_TCL(i << 4, j); + ahc_busy_tcl(ahc, tcl, *ptr); + } + } } - - ahc_intr((void *)ahc); return (0); } -STATIC int -ahc_setup_data(ahc, xs, scb) - struct ahc_softc *ahc; - struct scsi_xfer *xs; - struct scb *scb; +/************************** Busy Target Table *********************************/ +/* + * Return the untagged transaction id for a given target/channel lun. + * Optionally, clear the entry. + */ +u_int +ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl) { - struct hardware_scb *hscb; - - hscb = scb->hscb; - xs->resid = xs->status = 0; - - hscb->cmdlen = xs->cmdlen; - bcopy(xs->cmd, hscb->cmdstore, xs->cmdlen); - hscb->cmdpointer = hscb->cmdstore_busaddr; - - /* Only use S/G if there is a transfer */ - if (xs->datalen) { - int error; + u_int scbid; + u_int target_offset; - error = bus_dmamap_load(ahc->sc_dmat, - scb->dmamap, xs->data, - xs->datalen, NULL, - (xs->flags & SCSI_NOSLEEP) ? - BUS_DMA_NOWAIT : BUS_DMA_WAITOK); - if (error) { - if (!ahc_istagged_device(ahc, xs, 0)) - ahc_index_busy_tcl(ahc, hscb->tcl, TRUE); - return (TRY_AGAIN_LATER); /* XXX fvdl */ - } - error = ahc_execute_scb(scb, - scb->dmamap->dm_segs, - scb->dmamap->dm_nsegs); - return error; + if ((ahc->flags & AHC_SCB_BTT) != 0) { + u_int saved_scbptr; + + saved_scbptr = ahc_inb(ahc, SCBPTR); + ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); + scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl)); + ahc_outb(ahc, SCBPTR, saved_scbptr); } else { - return ahc_execute_scb(scb, NULL, 0); + target_offset = TCL_TARGET_OFFSET(tcl); + scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset); } -} -STATIC void -ahc_freeze_devq(ahc, sc_link) - struct ahc_softc *ahc; - struct scsi_link *sc_link; -{ - int target; - char channel; - int lun; - - target = sc_link->target; - lun = sc_link->lun; - channel = SIM_CHANNEL(ahc, sc_link); - - ahc_search_qinfifo(ahc, target, channel, lun, - /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, - SCB_REQUEUE, SEARCH_COMPLETE); + return (scbid); } -STATIC void -ahcallocscbs(ahc) - struct ahc_softc *ahc; +void +ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl) { - struct scb_data *scb_data; - struct scb *next_scb; - struct sg_map_node *sg_map; - bus_addr_t physaddr; - struct ahc_dma_seg *segs; - int newcount; - int i; - int dma_flags = 0; - - scb_data = ahc->scb_data; - if (scb_data->numscbs >= AHC_SCB_MAX) - /* Can't allocate any more */ - return; - - next_scb = &scb_data->scbarray[scb_data->numscbs]; - - sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); - - if (sg_map == NULL) - return; - bzero(sg_map, sizeof(struct sg_map_node)); - - if (ahc_createdmamem(ahc, PAGE_SIZE, &sg_map->sg_dmamap, - (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, - &sg_map->sg_dmasegs, &sg_map->sg_nseg, "SG space") < 0) { - free(sg_map, M_DEVBUF); - return; - } - - SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); - - segs = sg_map->sg_vaddr; - physaddr = sg_map->sg_physaddr; - - newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); - - for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) { - int error; + u_int target_offset; - next_scb->sg_list = segs; - /* - * The sequencer always starts with the second entry. - * The first entry is embedded in the scb. - */ - next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); - next_scb->flags = SCB_FREE; + if ((ahc->flags & AHC_SCB_BTT) != 0) { + u_int saved_scbptr; - /* set up AHA-284x right. */ - dma_flags = ((ahc->chip & AHC_VL) !=0) ? - BUS_DMA_NOWAIT|ISABUS_DMA_32BIT : - BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW; - - error = bus_dmamap_create(ahc->sc_dmat, - AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXBSIZE, 0, - dma_flags, &next_scb->dmamap); - if (error !=0) - break; - - next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; - next_scb->hscb->tag = ahc->scb_data->numscbs; - next_scb->hscb->cmdstore_busaddr = - ahc_hscb_busaddr(ahc, next_scb->hscb->tag) - + offsetof(struct hardware_scb, cmdstore); - next_scb->hscb->cmdstore_busaddr = - htole32(next_scb->hscb->cmdstore_busaddr); - SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, next_scb, links); - segs += AHC_NSEG; - physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); - next_scb++; - ahc->scb_data->numscbs++; + saved_scbptr = ahc_inb(ahc, SCBPTR); + ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); + ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL); + ahc_outb(ahc, SCBPTR, saved_scbptr); + } else { + target_offset = TCL_TARGET_OFFSET(tcl); + ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL); } } -#ifdef AHC_DUMP_SEQ -STATIC void -ahc_dumpseq(ahc) - struct ahc_softc* ahc; +void +ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid) { - int i; - int max_prog; - - if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) - max_prog = 448; - else if ((ahc->features & AHC_ULTRA2) != 0) - max_prog = 768; - else - max_prog = 512; - - ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); - ahc_outb(ahc, SEQADDR0, 0); - ahc_outb(ahc, SEQADDR1, 0); - for (i = 0; i < max_prog; i++) { - u_int8_t ins_bytes[4]; + u_int target_offset; - ahc_insb(ahc, SEQRAM, ins_bytes, 4); - printf("0x%08x\n", ins_bytes[0] << 24 - | ins_bytes[1] << 16 - | ins_bytes[2] << 8 - | ins_bytes[3]); + if ((ahc->flags & AHC_SCB_BTT) != 0) { + u_int saved_scbptr; + + saved_scbptr = ahc_inb(ahc, SCBPTR); + ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); + ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid); + ahc_outb(ahc, SCBPTR, saved_scbptr); + } else { + target_offset = TCL_TARGET_OFFSET(tcl); + ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid); } } -#endif -STATIC void -ahc_loadseq(ahc) - struct ahc_softc* ahc; +/************************** SCB and SCB queue management **********************/ +int +ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target, + char channel, int lun, u_int tag, role_t role) { - struct patch *cur_patch; - int i; - int downloaded; - int skip_addr; - u_int8_t download_consts[4]; - - /* Setup downloadable constant table */ -#if 0 - /* No downloaded constants are currently defined. */ - download_consts[TMODE_NUMCMDS] = ahc->num_targetcmds; -#endif - - cur_patch = patches; - downloaded = 0; - skip_addr = 0; - ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); - ahc_outb(ahc, SEQADDR0, 0); - ahc_outb(ahc, SEQADDR1, 0); + int targ = SCB_GET_TARGET(ahc, scb); + char chan = SCB_GET_CHANNEL(ahc, scb); + int slun = SCB_GET_LUN(scb); + int match; - for (i = 0; i < sizeof(seqprog)/4; i++) { - if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { - /* - * Don't download this instruction as it - * is in a patch that was removed. - */ - continue; + match = ((chan == channel) || (channel == ALL_CHANNELS)); + if (match != 0) + match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); + if (match != 0) + match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); + if (match != 0) { +#if AHC_TARGET_MODE + int group; + + group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); + if (role == ROLE_INITIATOR) { + match = (group != XPT_FC_GROUP_TMODE) + && ((tag == scb->hscb->tag) + || (tag == SCB_LIST_NULL)); + } else if (role == ROLE_TARGET) { + match = (group == XPT_FC_GROUP_TMODE) + && ((tag == scb->io_ctx->csio.tag_id) + || (tag == SCB_LIST_NULL)); } - ahc_download_instr(ahc, i, download_consts); - downloaded++; +#else /* !AHC_TARGET_MODE */ + match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL)); +#endif /* AHC_TARGET_MODE */ } - ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); - restart_sequencer(ahc); - if (bootverbose) - printf(" %d instructions downloaded\n", downloaded); + return match; } -STATIC int -ahc_check_patch(ahc, start_patch, start_instr,skip_addr) - struct ahc_softc *ahc; - struct patch **start_patch; - int start_instr; - int *skip_addr; +void +ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb) { - struct patch *cur_patch; - struct patch *last_patch; - int num_patches; - - num_patches = sizeof(patches)/sizeof(struct patch); - last_patch = &patches[num_patches]; - cur_patch = *start_patch; - - while (cur_patch < last_patch && start_instr == cur_patch->begin) { - - if (cur_patch->patch_func(ahc) == 0) { - - /* Start rejecting code */ - *skip_addr = start_instr + cur_patch->skip_instr; - cur_patch += cur_patch->skip_patch; - } else { - /* Accepted this patch. Advance to the next - * one and wait for our intruction pointer to - * hit this point. - */ - cur_patch++; - } - } + int target; + char channel; + int lun; - *start_patch = cur_patch; - if (start_instr < *skip_addr) - /* Still skipping */ - return (0); + target = SCB_GET_TARGET(ahc, scb); + lun = SCB_GET_LUN(scb); + channel = SCB_GET_CHANNEL(ahc, scb); + + ahc_search_qinfifo(ahc, target, channel, lun, + /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, + CAM_REQUEUE_REQ, SEARCH_COMPLETE); - return (1); + ahc_platform_freeze_devq(ahc, scb); } -STATIC void -ahc_download_instr(ahc, instrptr, dconsts) - struct ahc_softc *ahc; - int instrptr; - u_int8_t *dconsts; +void +ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb) { - union ins_formats instr; - struct ins_format1 *fmt1_ins; - struct ins_format3 *fmt3_ins; - u_int opcode; - - /* Structure copy */ - instr = *(union ins_formats*)&seqprog[instrptr * 4]; - - instr.integer = le32toh(instr.integer); - - fmt1_ins = &instr.format1; - fmt3_ins = NULL; - - /* Pull the opcode */ - opcode = instr.format1.opcode; - switch (opcode) { - case AIC_OP_JMP: - case AIC_OP_JC: - case AIC_OP_JNC: - case AIC_OP_CALL: - case AIC_OP_JNE: - case AIC_OP_JNZ: - case AIC_OP_JE: - case AIC_OP_JZ: - { - struct patch *cur_patch; - int address_offset; - u_int address; - int skip_addr; - int i; - - fmt3_ins = &instr.format3; - address_offset = 0; - address = fmt3_ins->address; - cur_patch = patches; - skip_addr = 0; + struct scb *prev_scb; - for (i = 0; i < address;) { + prev_scb = NULL; + if (ahc_qinfifo_count(ahc) != 0) { + u_int prev_tag; + uint8_t prev_pos; - ahc_check_patch(ahc, &cur_patch, i, &skip_addr); - - if (skip_addr > i) { - int end_addr; - - end_addr = MIN(address, skip_addr); - address_offset += end_addr - i; - i = skip_addr; - } else { - i++; - } - } - address -= address_offset; - fmt3_ins->address = address; - /* FALLTHROUGH */ + prev_pos = ahc->qinfifonext - 1; + prev_tag = ahc->qinfifo[prev_pos]; + prev_scb = ahc_lookup_scb(ahc, prev_tag); } - case AIC_OP_OR: - case AIC_OP_AND: - case AIC_OP_XOR: - case AIC_OP_ADD: - case AIC_OP_ADC: - case AIC_OP_BMOV: - if (fmt1_ins->parity != 0) { - fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; - } - fmt1_ins->parity = 0; - /* FALLTHROUGH */ - case AIC_OP_ROL: - if ((ahc->features & AHC_ULTRA2) != 0) { - int i, count; - - /* Calculate odd parity for the instruction */ - for (i = 0, count = 0; i < 31; i++) { - u_int32_t mask; - - mask = 0x01 << i; - if ((instr.integer & mask) != 0) - count++; - } - if ((count & 0x01) == 0) - instr.format1.parity = 1; - } else { - /* Compress the instruction for older sequencers */ - if (fmt3_ins != NULL) { - instr.integer = - fmt3_ins->immediate - | (fmt3_ins->source << 8) - | (fmt3_ins->address << 16) - | (fmt3_ins->opcode << 25); - } else { - instr.integer = - fmt1_ins->immediate - | (fmt1_ins->source << 8) - | (fmt1_ins->destination << 16) - | (fmt1_ins->ret << 24) - | (fmt1_ins->opcode << 25); - } - } - instr.integer = htole32(instr.integer); - ahc_outsb(ahc, SEQRAM, instr.bytes, 4); - break; - default: - panic("Unknown opcode encountered in seq program"); - break; + ahc_qinfifo_requeue(ahc, prev_scb, scb); + if ((ahc->features & AHC_QUEUE_REGS) != 0) { + ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); + } else { + ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); } } -STATIC void -ahc_set_recoveryscb(ahc, scb) - struct ahc_softc *ahc; - struct scb *scb; +static void +ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb, + struct scb *scb) { - - if ((scb->flags & SCB_RECOVERY_SCB) == 0) { - struct scb *scbp; - - scb->flags |= SCB_RECOVERY_SCB; - - /* - * Take all queued, but not sent SCBs out of the equation. - * Also ensure that no new CCBs are queued to us while we - * try to fix this problem. - */ - ahc->queue_blocked = 1; - - /* - * Go through all of our pending SCBs and remove - * any scheduled timeouts for them. We will reschedule - * them after we've successfully fixed this problem. - */ - scbp = ahc->pending_scbs.lh_first; - while (scbp != NULL) { - timeout_del(&scbp->xs->stimeout); - scbp = scbp->pend_links.le_next; - } + if (prev_scb == NULL) { + ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); + } else { + prev_scb->hscb->next = scb->hscb->tag; + ahc_sync_scb(ahc, prev_scb, + BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); } + ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; + scb->hscb->next = ahc->next_queued_scb->hscb->tag; + ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); } -STATIC void -ahc_timeout(void *arg) +static int +ahc_qinfifo_count(struct ahc_softc *ahc) { - struct scb *scb; - struct ahc_softc *ahc; - int s, found; - u_int last_phase; - int target; - int lun; - int i; - char channel; - - scb = (struct scb *)arg; - ahc = (struct ahc_softc *)scb->xs->sc_link->adapter_softc; - - s = splbio(); - - /* - * Ensure that the card doesn't do anything - * behind our back. Also make sure that we - * didn't "just" miss an interrupt that would - * affect this timeout. - */ - do { - ahc_intr(ahc); - pause_sequencer(ahc); - } while (ahc_inb(ahc, INTSTAT) & INT_PEND); - - if ((scb->flags & SCB_ACTIVE) == 0) { - /* Previous timeout took care of me already */ - printf("Timedout SCB handled by another timeout\n"); - unpause_sequencer(ahc); - splx(s); - return; - } - - target = SCB_TARGET(scb); - channel = SCB_CHANNEL(scb); - lun = SCB_LUN(scb); - - sc_print_addr(scb->xs->sc_link); - printf("SCB 0x%x - timed out ", scb->hscb->tag); - /* - * Take a snapshot of the bus state and print out - * some information so we can track down driver bugs. - */ - last_phase = ahc_inb(ahc, LASTPHASE); - - for (i = 0; i < num_phases; i++) { - if (last_phase == phase_table[i].phase) - break; - } - printf("%s", phase_table[i].phasemsg); - - printf(", SEQADDR == 0x%x\n", - ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); -#if 0 - printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); - printf("SSTAT3 == 0x%x\n", ahc_inb(ahc, SSTAT3)); - printf("SCSIPHASE == 0x%x\n", ahc_inb(ahc, SCSIPHASE)); - printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); - printf("SCSIOFFSET == 0x%x\n", ahc_inb(ahc, SCSIOFFSET)); - printf("SEQ_FLAGS == 0x%x\n", ahc_inb(ahc, SEQ_FLAGS)); - printf("SCB_DATAPTR == 0x%x\n", ahc_inb(ahc, SCB_DATAPTR) - | ahc_inb(ahc, SCB_DATAPTR + 1) << 8 - | ahc_inb(ahc, SCB_DATAPTR + 2) << 16 - | ahc_inb(ahc, SCB_DATAPTR + 3) << 24); - printf("SCB_DATACNT == 0x%x\n", ahc_inb(ahc, SCB_DATACNT) - | ahc_inb(ahc, SCB_DATACNT + 1) << 8 - | ahc_inb(ahc, SCB_DATACNT + 2) << 16); - printf("SCB_SGCOUNT == 0x%x\n", ahc_inb(ahc, SCB_SGCOUNT)); - printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL)); - printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT)); - printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL)); - printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS)); - printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT)); - if (scb->sg_count > 0) { - for (i = 0; i < scb->sg_count; i++) { - printf("sg[%d] - Addr 0x%x : Length %d\n", - i, - le32toh(scb->sg_list[i].addr), - le32toh(scb->sg_list[i].len)); - } - } -#endif - if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { - /* - * Been down this road before. - * Do a full bus reset. - */ -bus_reset: - ahcsetccbstatus(scb->xs, XS_TIMEOUT); - found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); - printf("%s: Issued Channel %c Bus Reset. " - "%d SCBs aborted\n", ahc_name(ahc), channel, found); - } else { - /* - * If we are a target, transition to bus free and report - * the timeout. - * - * The target/initiator that is holding up the bus may not - * be the same as the one that triggered this timeout - * (different commands have different timeout lengths). - * If the bus is idle and we are actiing as the initiator - * for this request, queue a BDR message to the timed out - * target. Otherwise, if the timed out transaction is - * active: - * Initiator transaction: - * Stuff the message buffer with a BDR message and assert - * ATN in the hopes that the target will let go of the bus - * and go to the mesgout phase. If this fails, we'll - * get another timeout 2 seconds later which will attempt - * a bus reset. - * - * Target transaction: - * Transition to BUS FREE and report the error. - * It's good to be the target! - */ - u_int active_scb_index; - - active_scb_index = ahc_inb(ahc, SCB_TAG); - - if (last_phase != P_BUSFREE - && (active_scb_index < ahc->scb_data->numscbs)) { - struct scb *active_scb; - - /* - * If the active SCB is not from our device, - * assume that another device is hogging the bus - * and wait for it's timeout to expire before - * taking additional action. - */ - active_scb = &ahc->scb_data->scbarray[active_scb_index]; - if (active_scb->hscb->tcl != scb->hscb->tcl) { - u_int newtimeout; - - sc_print_addr(scb->xs->sc_link); - printf("Other SCB Timeout%s", - (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 - ? " again\n" : "\n"); - scb->flags |= SCB_OTHERTCL_TIMEOUT; - newtimeout = MAX(active_scb->xs->timeout, - scb->xs->timeout); - timeout_add(&scb->xs->stimeout, - (newtimeout * hz) / 1000); - splx(s); - return; - } - - /* It's us */ - if ((scb->hscb->control & TARGET_SCB) != 0) { - - /* - * Send back any queued up transactions - * and properly record the error condition. - */ - ahc_freeze_devq(ahc, scb->xs->sc_link); - ahcsetccbstatus(scb->xs, XS_TIMEOUT); - ahc_freeze_ccb(scb); - ahc_done(ahc, scb); - - /* Will clear us from the bus */ - restart_sequencer(ahc); - splx(s); - return; - } - - ahc_set_recoveryscb(ahc, active_scb); - ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); - ahc_outb(ahc, SCSISIGO, last_phase|ATNO); - sc_print_addr(active_scb->xs->sc_link); - printf("BDR message in message buffer\n"); - active_scb->flags |= SCB_DEVICE_RESET; - timeout_add(&active_scb->xs->stimeout, 2 * hz); - unpause_sequencer(ahc); - } else { - int disconnected; - - /* XXX Shouldn't panic. Just punt instead */ - if ((scb->hscb->control & TARGET_SCB) != 0) - panic("Timed-out target SCB but bus idle"); - - if (last_phase != P_BUSFREE - && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { - /* XXX What happened to the SCB? */ - /* Hung target selection. Goto busfree */ - printf("%s: Hung target selection\n", - ahc_name(ahc)); - restart_sequencer(ahc); - splx(s); - return; - } - - if (ahc_search_qinfifo(ahc, target, channel, lun, - scb->hscb->tag, ROLE_INITIATOR, - /*status*/0, SEARCH_COUNT) > 0) { - disconnected = FALSE; - } else { - disconnected = TRUE; - } - - if (disconnected) { - u_int active_scb; - - ahc_set_recoveryscb(ahc, scb); - /* - * Simply set the MK_MESSAGE control bit. - */ - scb->hscb->control |= MK_MESSAGE; - scb->flags |= SCB_QUEUED_MSG - | SCB_DEVICE_RESET; - - /* - * Mark the cached copy of this SCB in the - * disconnected list too, so that a reconnect - * at this point causes a BDR or abort. - */ - active_scb = ahc_inb(ahc, SCBPTR); - if (ahc_search_disc_list(ahc, target, - channel, lun, - scb->hscb->tag, - /*stop_on_first*/TRUE, - /*remove*/FALSE, - /*save_state*/FALSE)) { - u_int scb_control; - - scb_control = ahc_inb(ahc, SCB_CONTROL); - scb_control |= MK_MESSAGE; - ahc_outb(ahc, SCB_CONTROL, scb_control); - } - ahc_outb(ahc, SCBPTR, active_scb); - ahc_index_busy_tcl(ahc, scb->hscb->tcl, - /*unbusy*/TRUE); + u_int8_t qinpos; + u_int8_t diff; - /* - * Actually re-queue this SCB in case we can - * select the device before it reconnects. - * Clear out any entries in the QINFIFO first - * so we are the next SCB for this target - * to run. - */ - ahc_search_qinfifo(ahc, SCB_TARGET(scb), - channel, SCB_LUN(scb), - SCB_LIST_NULL, - ROLE_INITIATOR, - SCB_REQUEUE, - SEARCH_COMPLETE); - sc_print_addr(scb->xs->sc_link); - printf("Queuing a BDR SCB\n"); - ahc->qinfifo[ahc->qinfifonext++] = - scb->hscb->tag; - - bus_dmamap_sync(ahc->sc_dmat, - ahc->shared_data_dmamap, - QINFIFO_OFFSET * 256, 256, - BUS_DMASYNC_PREWRITE); - - if ((ahc->features & AHC_QUEUE_REGS) != 0) { - ahc_outb(ahc, HNSCB_QOFF, - ahc->qinfifonext); - } else { - ahc_outb(ahc, KERNEL_QINPOS, - ahc->qinfifonext); - } - timeout_add(&scb->xs->stimeout, 2 * hz); - unpause_sequencer(ahc); - } else { - /* Go "immediatly" to the bus reset */ - /* This shouldn't happen */ - ahc_set_recoveryscb(ahc, scb); - sc_print_addr(scb->xs->sc_link); - printf("SCB %d: Immediate reset. " - "Flags = 0x%x\n", scb->hscb->tag, - scb->flags); - goto bus_reset; - } - } - } - splx(s); + if ((ahc->features & AHC_QUEUE_REGS) != 0) { + qinpos = ahc_inb(ahc, SNSCB_QOFF); + ahc_outb(ahc, SNSCB_QOFF, qinpos); + } else + qinpos = ahc_inb(ahc, QINPOS); + diff = ahc->qinfifonext - qinpos; + return (diff); } -STATIC int -ahc_search_qinfifo(ahc, target, channel, lun, tag, role, status, action) - struct ahc_softc *ahc; - int target; - char channel; - int lun; - u_int tag; - role_t role; - u_int32_t status; - ahc_search_action action; +int +ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, + int lun, u_int tag, role_t role, uint32_t status, + ahc_search_action action) { - struct scb *scbp; - u_int8_t qinpos; - u_int8_t qintail; - int found; + struct scb *scb; + struct scb *prev_scb; + uint8_t qinstart; + uint8_t qinpos; + uint8_t qintail; + uint8_t next, prev; + uint8_t curscbptr; + int found; + int maxtarget; + int i; + int have_qregs; - qinpos = ahc_inb(ahc, QINPOS); qintail = ahc->qinfifonext; + have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0; + if (have_qregs) { + qinstart = ahc_inb(ahc, SNSCB_QOFF); + ahc_outb(ahc, SNSCB_QOFF, qinstart); + } else + qinstart = ahc_inb(ahc, QINPOS); + qinpos = qinstart; + next = ahc_inb(ahc, NEXT_QUEUED_SCB); found = 0; + prev_scb = NULL; + + if (action == SEARCH_COMPLETE) { + /* + * Don't attempt to run any queued untagged transactions + * until we are done with the abort process. + */ + ahc_freeze_untagged_queues(ahc); + } /* * Start with an empty queue. Entries that are not chosen * for removal will be re-added to the queue as we go. */ ahc->qinfifonext = qinpos; - bus_dmamap_sync(ahc->sc_dmat, ahc->shared_data_dmamap, - QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_POSTREAD); + ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); while (qinpos != qintail) { - scbp = &ahc->scb_data->scbarray[ahc->qinfifo[qinpos]]; - if (ahc_match_scb(scbp, target, channel, lun, tag, role)) { + scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]); + if (scb == NULL) { + printf("qinpos = %d, SCB index = %d\n", + qinpos, ahc->qinfifo[qinpos]); + panic("Loop 1\n"); + } + + if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) { /* - * We found an scb that needs to be removed. + * We found an scb that needs to be acted on. */ + found++; switch (action) { case SEARCH_COMPLETE: - if (!(scbp->xs->flags & ITSDONE)) { - scbp->flags |= status; - scbp->xs->error = XS_NOERROR; - } - ahc_freeze_ccb(scbp); - ahc_done(ahc, scbp); + { + cam_status ostat; + cam_status cstat; + + ostat = ahc_get_transaction_status(scb); + if (ostat == CAM_REQ_INPROG) + ahc_set_transaction_status(scb, + status); + cstat = ahc_get_transaction_status(scb); + if (cstat != CAM_REQ_CMP) + ahc_freeze_scb(scb); + if ((scb->flags & SCB_ACTIVE) == 0) + printf("Inactive SCB in qinfifo\n"); + ahc_done(ahc, scb); + /* FALLTHROUGH */ + } + case SEARCH_REMOVE: break; case SEARCH_COUNT: - ahc->qinfifo[ahc->qinfifonext++] = - scbp->hscb->tag; - break; - case SEARCH_REMOVE: + ahc_qinfifo_requeue(ahc, prev_scb, scb); + prev_scb = scb; break; } - found++; } else { - ahc->qinfifo[ahc->qinfifonext++] = scbp->hscb->tag; + ahc_qinfifo_requeue(ahc, prev_scb, scb); + prev_scb = scb; } qinpos++; } - bus_dmamap_sync(ahc->sc_dmat, ahc->shared_data_dmamap, - QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); - + if ((ahc->features & AHC_QUEUE_REGS) != 0) { ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); } else { ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); } - return (found); -} + if (action != SEARCH_COUNT + && (found != 0) + && (qinstart != ahc->qinfifonext)) { + /* + * The sequencer may be in the process of dmaing + * down the SCB at the beginning of the queue. + * This could be problematic if either the first, + * or the second SCB is removed from the queue + * (the first SCB includes a pointer to the "next" + * SCB to dma). If we have removed any entries, swap + * the first element in the queue with the next HSCB + * so the sequencer will notice that NEXT_QUEUED_SCB + * has changed during its dma attempt and will retry + * the DMA. + */ + scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]); -/* - * Abort all SCBs that match the given description (target/channel/lun/tag), - * setting their status to the passed in status if the status has not already - * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer - * is paused before it is called. - */ -STATIC int -ahc_abort_scbs(ahc, target, channel, lun, tag, role, status) - struct ahc_softc *ahc; - int target; - char channel; - int lun; - u_int tag; - role_t role; - u_int32_t status; -{ - struct scb *scbp; - u_int active_scb; - int i; - int found; + if (scb == NULL) { + printf("found = %d, qinstart = %d, qinfifionext = %d\n", + found, qinstart, ahc->qinfifonext); + panic("First/Second Qinfifo fixup\n"); + } + /* + * ahc_swap_with_next_hscb forces our next pointer to + * point to the reserved SCB for future commands. Save + * and restore our original next pointer to maintain + * queue integrity. + */ + next = scb->hscb->next; + ahc->scb_data->scbindex[scb->hscb->tag] = NULL; + ahc_swap_with_next_hscb(ahc, scb); + scb->hscb->next = next; + ahc->qinfifo[qinstart] = scb->hscb->tag; - /* restore this when we're done */ - active_scb = ahc_inb(ahc, SCBPTR); + /* Tell the card about the new head of the qinfifo. */ + ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); - found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, - role, SCB_REQUEUE, SEARCH_COMPLETE); + /* Fixup the tail "next" pointer. */ + qintail = ahc->qinfifonext - 1; + scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]); + scb->hscb->next = ahc->next_queued_scb->hscb->tag; + } /* * Search waiting for selection list. */ - { - u_int8_t next, prev; - /* Start at head of list. */ - next = ahc_inb(ahc, WAITING_SCBH); - prev = SCB_LIST_NULL; + curscbptr = ahc_inb(ahc, SCBPTR); + next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ + prev = SCB_LIST_NULL; - while (next != SCB_LIST_NULL) { - u_int8_t scb_index; + while (next != SCB_LIST_NULL) { + uint8_t scb_index; - ahc_outb(ahc, SCBPTR, next); - scb_index = ahc_inb(ahc, SCB_TAG); - if (scb_index >= ahc->scb_data->numscbs) { - panic("Waiting List inconsistency. " - "SCB index == %d, yet numscbs == %d.", - scb_index, ahc->scb_data->numscbs); + ahc_outb(ahc, SCBPTR, next); + scb_index = ahc_inb(ahc, SCB_TAG); + if (scb_index >= ahc->scb_data->numscbs) { + printf("Waiting List inconsistency. " + "SCB index == %d, yet numscbs == %d.", + scb_index, ahc->scb_data->numscbs); + ahc_dump_card_state(ahc); + panic("for safety"); + } + scb = ahc_lookup_scb(ahc, scb_index); + if (scb == NULL) { + printf("scb_index = %d, next = %d\n", + scb_index, next); + panic("Waiting List traversal\n"); + } + if (ahc_match_scb(ahc, scb, target, channel, + lun, SCB_LIST_NULL, role)) { + /* + * We found an scb that needs to be acted on. + */ + found++; + switch (action) { + case SEARCH_COMPLETE: + { + cam_status ostat; + cam_status cstat; + + ostat = ahc_get_transaction_status(scb); + if (ostat == CAM_REQ_INPROG) + ahc_set_transaction_status(scb, + status); + cstat = ahc_get_transaction_status(scb); + if (cstat != CAM_REQ_CMP) + ahc_freeze_scb(scb); + if ((scb->flags & SCB_ACTIVE) == 0) + printf("Inactive SCB in Waiting List\n"); + ahc_done(ahc, scb); + /* FALLTHROUGH */ } - scbp = &ahc->scb_data->scbarray[scb_index]; - if (ahc_match_scb(scbp, target, channel, - lun, SCB_LIST_NULL, role)) { - - next = ahc_abort_wscb(ahc, next, prev); - } else { - + case SEARCH_REMOVE: + next = ahc_rem_wscb(ahc, next, prev); + break; + case SEARCH_COUNT: prev = next; next = ahc_inb(ahc, SCB_NEXT); + break; } + } else { + + prev = next; + next = ahc_inb(ahc, SCB_NEXT); } } - /* - * Go through the disconnected list and remove any entries we - * have queued for completion, 0'ing their control byte too. - * We save the active SCB and restore it ourselves, so there - * is no reason for this search to restore it too. - */ - ahc_search_disc_list(ahc, target, channel, lun, tag, - /*stop_on_first*/FALSE, /*remove*/TRUE, - /*save_state*/FALSE); + ahc_outb(ahc, SCBPTR, curscbptr); /* - * Go through the hardware SCB array looking for commands that - * were active but not on any list. + * And lastly, the untagged holding queues. */ - for(i = 0; i < ahc->scb_data->maxhscbs; i++) { - u_int scbid; + i = 0; + if ((ahc->flags & AHC_SCB_BTT) == 0) { - ahc_outb(ahc, SCBPTR, i); - scbid = ahc_inb(ahc, SCB_TAG); - scbp = &ahc->scb_data->scbarray[scbid]; - if (scbid < ahc->scb_data->numscbs && - ahc_match_scb(scbp, target, channel, lun, tag, role)) - ahc_add_curscb_to_free_list(ahc); + maxtarget = 16; + if (target != CAM_TARGET_WILDCARD) { + + i = target; + if (channel == 'B') + i += 8; + maxtarget = i + 1; + } + } else { + maxtarget = 0; } - /* - * Go through the pending CCB list and look for - * commands for this target that are still active. - * These are other tagged commands that were - * disconnected when the reset occurred. - */ - { - struct scb *scb; + for (; i < maxtarget; i++) { + struct scb_tailq *untagged_q; + struct scb *next_scb; + + untagged_q = &(ahc->untagged_queues[i]); + next_scb = TAILQ_FIRST(untagged_q); + while (next_scb != NULL) { + + scb = next_scb; + next_scb = TAILQ_NEXT(scb, links.tqe); + + /* + * The head of the list may be the currently + * active untagged command for a device. + * We're only searching for commands that + * have not been started. A transaction + * marked active but still in the qinfifo + * is removed by the qinfifo scanning code + * above. + */ + if ((scb->flags & SCB_ACTIVE) != 0) + continue; - scb = ahc->pending_scbs.lh_first; - while (scb != NULL) { - scbp = scb; - scb = scb->pend_links.le_next; - if (ahc_match_scb(scbp, target, channel, - lun, tag, role)) { - if (!(scbp->xs->flags & ITSDONE)) - ahcsetccbstatus(scbp->xs, status); - ahc_freeze_ccb(scbp); - ahc_done(ahc, scbp); + if (ahc_match_scb(ahc, scb, target, channel, + lun, SCB_LIST_NULL, role)) { + /* + * We found an scb that needs to be acted on. + */ found++; + switch (action) { + case SEARCH_COMPLETE: + { + cam_status ostat; + cam_status cstat; + + ostat = ahc_get_transaction_status(scb); + if (ostat == CAM_REQ_INPROG) + ahc_set_transaction_status(scb, + status); + cstat = ahc_get_transaction_status(scb); + if (cstat != CAM_REQ_CMP) + ahc_freeze_scb(scb); + if ((scb->flags & SCB_ACTIVE) == 0) + printf("Inactive SCB in untaggedQ\n"); + ahc_done(ahc, scb); + break; + } + case SEARCH_REMOVE: + TAILQ_REMOVE(untagged_q, scb, + links.tqe); + break; + case SEARCH_COUNT: + break; + } } } } - ahc_outb(ahc, SCBPTR, active_scb); - return found; + + if (action == SEARCH_COMPLETE) + ahc_release_untagged_queues(ahc); + return (found); } -STATIC int -ahc_search_disc_list(ahc, target, channel, lun, tag, stop_on_first, - remove, save_state) - struct ahc_softc *ahc; - int target; - char channel; - int lun; - u_int tag; - int stop_on_first; - int remove; - int save_state; +int +ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, + int lun, u_int tag, int stop_on_first, int remove, + int save_state) { struct scb *scbp; u_int next; @@ -5279,8 +5357,8 @@ ahc_search_disc_list(ahc, target, channel, lun, tag, stop_on_first, prev = SCB_LIST_NULL; if (save_state) { - /* restore this when we're done */ - active_scb = ahc_inb(ahc, SCBPTR); + /* restore this when we're done */ + active_scb = ahc_inb(ahc, SCBPTR); } else /* Silence compiler */ active_scb = SCB_LIST_NULL; @@ -5291,12 +5369,20 @@ ahc_search_disc_list(ahc, target, channel, lun, tag, stop_on_first, ahc_outb(ahc, SCBPTR, next); scb_index = ahc_inb(ahc, SCB_TAG); if (scb_index >= ahc->scb_data->numscbs) { - panic("Disconnected List inconsistency. " - "SCB index == %d, yet numscbs == %d.", - scb_index, ahc->scb_data->numscbs); + printf("Disconnected List inconsistency. " + "SCB index == %d, yet numscbs == %d.", + scb_index, ahc->scb_data->numscbs); + ahc_dump_card_state(ahc); + panic("for safety"); } - scbp = &ahc->scb_data->scbarray[scb_index]; - if (ahc_match_scb(scbp, target, channel, lun, + + if (next == prev) { + panic("Disconnected List Loop. " + "cur SCBPTR == %x, prev SCBPTR == %x.", + next, prev); + } + scbp = ahc_lookup_scb(ahc, scb_index); + if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, ROLE_INITIATOR)) { count++; if (remove) { @@ -5314,15 +5400,16 @@ ahc_search_disc_list(ahc, target, channel, lun, tag, stop_on_first, } } if (save_state) - ahc_outb(ahc, SCBPTR, active_scb); + ahc_outb(ahc, SCBPTR, active_scb); return (count); } -STATIC u_int -ahc_rem_scb_from_disc_list(ahc, prev, scbptr) - struct ahc_softc *ahc; - u_int prev; - u_int scbptr; +/* + * Remove an SCB from the on chip list of disconnected transactions. + * This is empty/unused if we are not performing SCB paging. + */ +static u_int +ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) { u_int next; @@ -5342,26 +5429,32 @@ ahc_rem_scb_from_disc_list(ahc, prev, scbptr) return (next); } -STATIC void -ahc_add_curscb_to_free_list(ahc) - struct ahc_softc *ahc; +/* + * Add the SCB as selected by SCBPTR onto the on chip list of + * free hardware SCBs. This list is empty/unused if we are not + * performing SCB paging. + */ +static void +ahc_add_curscb_to_free_list(struct ahc_softc *ahc) { - /* Invalidate the tag so that ahc_find_scb doesn't think it's active */ + /* + * Invalidate the tag so that our abort + * routines don't think it's active. + */ ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); - ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); - ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); + if ((ahc->flags & AHC_PAGESCBS) != 0) { + ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); + ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); + } } /* * Manipulate the waiting for selection list and return the * scb that follows the one that we remove. */ -STATIC u_int -ahc_abort_wscb(ahc, scbpos, prev) - struct ahc_softc *ahc; - u_int scbpos; - u_int prev; +static u_int +ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) { u_int curscb, next; @@ -5404,28 +5497,137 @@ ahc_abort_wscb(ahc, scbpos, prev) return next; } -STATIC void -ahc_clear_intstat(ahc) - struct ahc_softc *ahc; +/******************************** Error Handling ******************************/ +/* + * Abort all SCBs that match the given description (target/channel/lun/tag), + * setting their status to the passed in status if the status has not already + * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer + * is paused before it is called. + */ +int +ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, + int lun, u_int tag, role_t role, uint32_t status) { - /* Clear any interrupt conditions this may have caused */ - ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); - ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI - |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| - CLRREQINIT); - ahc_outb(ahc, CLRINT, CLRSCSIINT); + struct scb *scbp; + struct scb *scbp_next; + u_int active_scb; + int i, j; + int maxtarget; + int minlun; + int maxlun; + + int found; + + /* + * Don't attempt to run any queued untagged transactions + * until we are done with the abort process. + */ + ahc_freeze_untagged_queues(ahc); + + /* restore this when we're done */ + active_scb = ahc_inb(ahc, SCBPTR); + + found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, + role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); + + /* + * Clean out the busy target table for any untagged commands. + */ + i = 0; + maxtarget = 16; + if (target != CAM_TARGET_WILDCARD) { + i = target; + if (channel == 'B') + i += 8; + maxtarget = i + 1; + } + + if (lun == CAM_LUN_WILDCARD) { + + /* + * Unless we are using an SCB based + * busy targets table, there is only + * one table entry for all luns of + * a target. + */ + minlun = 0; + maxlun = 1; + if ((ahc->flags & AHC_SCB_BTT) != 0) + maxlun = AHC_NUM_LUNS; + } else { + minlun = lun; + maxlun = lun + 1; + } + + for (;i < maxtarget; i++) { + for (j = minlun;j < maxlun; j++) + ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j)); + } + + /* + * Go through the disconnected list and remove any entries we + * have queued for completion, 0'ing their control byte too. + * We save the active SCB and restore it ourselves, so there + * is no reason for this search to restore it too. + */ + ahc_search_disc_list(ahc, target, channel, lun, tag, + /*stop_on_first*/FALSE, /*remove*/TRUE, + /*save_state*/FALSE); + + /* + * Go through the hardware SCB array looking for commands that + * were active but not on any list. + */ + for (i = 0; i < ahc->scb_data->maxhscbs; i++) { + u_int scbid; + + ahc_outb(ahc, SCBPTR, i); + scbid = ahc_inb(ahc, SCB_TAG); + scbp = ahc_lookup_scb(ahc, scbid); + if (scbp != NULL + && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) + ahc_add_curscb_to_free_list(ahc); + } + + /* + * Go through the pending CCB list and look for + * commands for this target that are still active. + * These are other tagged commands that were + * disconnected when the reset occurred. + */ + scbp_next = LIST_FIRST(&ahc->pending_scbs); + while (scbp_next != NULL) { + scbp = scbp_next; + scbp_next = LIST_NEXT(scbp, pending_links); + if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) { + cam_status ostat; + + ostat = ahc_get_transaction_status(scbp); + if (ostat == CAM_REQ_INPROG) + ahc_set_transaction_status(scbp, status); + if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP) + ahc_freeze_scb(scbp); + if ((scbp->flags & SCB_ACTIVE) == 0) + printf("Inactive SCB on pending list\n"); + ahc_done(ahc, scbp); + found++; + } + } + ahc_outb(ahc, SCBPTR, active_scb); + ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status); + ahc_release_untagged_queues(ahc); + return found; } -STATIC void -ahc_reset_current_bus(ahc) - struct ahc_softc *ahc; +static void +ahc_reset_current_bus(struct ahc_softc *ahc) { - u_int8_t scsiseq; + uint8_t scsiseq; ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); scsiseq = ahc_inb(ahc, SCSISEQ); ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); - DELAY(AHC_BUSRESET_DELAY); + ahc_delay(AHC_BUSRESET_DELAY); /* Turn off the bus reset */ ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); @@ -5435,22 +5637,29 @@ ahc_reset_current_bus(ahc) ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); } -STATIC int -ahc_reset_channel(ahc, channel, initiate_reset) - struct ahc_softc *ahc; - char channel; - int initiate_reset; +int +ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) { + struct ahc_devinfo devinfo; u_int initiator, target, max_scsiid; u_int sblkctl; - u_int our_id; + u_int scsiseq; + u_int simode1; int found; int restart_needed; char cur_channel; ahc->pending_device = NULL; - pause_sequencer(ahc); + ahc_compile_devinfo(&devinfo, + CAM_TARGET_WILDCARD, + CAM_TARGET_WILDCARD, + CAM_LUN_WILDCARD, + channel, ROLE_UNKNOWN); + ahc_pause(ahc); + + /* Make sure the sequencer is in a safe location. */ + ahc_clear_critical_section(ahc); /* * Run our command complete fifos to ensure that we perform @@ -5458,6 +5667,11 @@ ahc_reset_channel(ahc, channel, initiate_reset) * before the reset occurred. */ ahc_run_qoutfifo(ahc); +#if AHC_TARGET_MODE + if ((ahc->flags & AHC_TARGETROLE) != 0) { + ahc_run_tqinfifo(ahc, /*paused*/TRUE); + } +#endif /* * Reset the bus if we are initiating this reset @@ -5467,40 +5681,48 @@ ahc_reset_channel(ahc, channel, initiate_reset) if ((ahc->features & AHC_TWIN) != 0 && ((sblkctl & SELBUSB) != 0)) cur_channel = 'B'; + scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); if (cur_channel != channel) { /* Case 1: Command for another bus is active * Stealthily reset the other bus without * upsetting the current bus. */ ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); - ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); - ahc_outb(ahc, SCSISEQ, - ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); + simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); + ahc_outb(ahc, SIMODE1, simode1); if (initiate_reset) ahc_reset_current_bus(ahc); ahc_clear_intstat(ahc); +#if AHC_TARGET_MODE + /* + * Bus resets clear ENSELI, so we cannot + * defer re-enabling bus reset interrupts + * if we are in target mode. + */ + if ((ahc->flags & AHC_TARGETROLE) != 0) + ahc_outb(ahc, SIMODE1, simode1 | ENSCSIRST); +#endif + ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); ahc_outb(ahc, SBLKCTL, sblkctl); restart_needed = FALSE; } else { /* Case 2: A command from this bus is active or we're idle */ ahc_clear_msg_state(ahc); - ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); - ahc_outb(ahc, SCSISEQ, - ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); + simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); + ahc_outb(ahc, SIMODE1, simode1); if (initiate_reset) ahc_reset_current_bus(ahc); ahc_clear_intstat(ahc); - +#if AHC_TARGET_MODE /* - * Since we are going to restart the sequencer, avoid - * a race in the sequencer that could cause corruption - * of our Q pointers by starting over from index 0. + * Bus resets clear ENSELI, so we cannot + * defer re-enabling bus reset interrupts + * if we are in target mode. */ - ahc->qoutfifonext = 0; - if ((ahc->features & AHC_QUEUE_REGS) != 0) - ahc_outb(ahc, SDSCB_QOFF, 0); - else - ahc_outb(ahc, QOUTPOS, 0); + if ((ahc->flags & AHC_TARGETROLE) != 0) + ahc_outb(ahc, SIMODE1, simode1 | ENSCSIRST); +#endif + ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); restart_needed = TRUE; } @@ -5508,17 +5730,41 @@ ahc_reset_channel(ahc, channel, initiate_reset) * Clean up all the state information for the * pending transactions on this bus. */ - found = ahc_abort_scbs(ahc, ALL_TARGETS, channel, - ALL_LUNS, SCB_LIST_NULL, - ROLE_UNKNOWN, XS_RESET); - if (channel == 'B') { - our_id = ahc->our_id_b; - } else { - our_id = ahc->our_id; - } + found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel, + CAM_LUN_WILDCARD, SCB_LIST_NULL, + ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; +#ifdef AHC_TARGET_MODE + /* + * Send an immediate notify ccb to all target more peripheral + * drivers affected by this action. + */ + for (target = 0; target <= max_scsiid; target++) { + struct ahc_tmode_tstate* tstate; + u_int lun; + + tstate = ahc->enabled_targets[target]; + if (tstate == NULL) + continue; + for (lun = 0; lun < AHC_NUM_LUNS; lun++) { + struct ahc_tmode_lstate* lstate; + + lstate = tstate->enabled_luns[lun]; + if (lstate == NULL) + continue; + + ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD, + EVENT_TYPE_BUS_RESET, /*arg*/0); + ahc_send_lstate_events(ahc, lstate); + } + } +#endif + /* Notify the XPT that a bus reset occurred */ + ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD, + CAM_LUN_WILDCARD, AC_BUS_RESET, NULL); + /* * Revert to async/narrow transfers until we renegotiate. */ @@ -5530,345 +5776,1194 @@ ahc_reset_channel(ahc, channel, initiate_reset) struct ahc_devinfo devinfo; ahc_compile_devinfo(&devinfo, target, initiator, - ALL_LUNS, + CAM_LUN_WILDCARD, channel, ROLE_UNKNOWN); - ahc_set_width(ahc, &devinfo, - MSG_EXT_WDTR_BUS_8_BIT, - AHC_TRANS_CUR, - /*paused*/TRUE, - /*done*/FALSE); - ahc_set_syncrate(ahc, &devinfo, - /*syncrate*/NULL, /*period*/0, - /*offset*/0, AHC_TRANS_CUR, - /*paused*/TRUE, - /*done*/FALSE); + ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, + AHC_TRANS_CUR, /*paused*/TRUE); + ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL, + /*period*/0, /*offset*/0, + /*ppr_options*/0, AHC_TRANS_CUR, + /*paused*/TRUE); } } if (restart_needed) - restart_sequencer(ahc); + ahc_restart(ahc); else - unpause_sequencer(ahc); + ahc_unpause(ahc); return found; } -STATIC int -ahc_match_scb(scb, target, channel, lun, role, tag) - struct scb *scb; - int target; - char channel; - int lun; - role_t role; - u_int tag; -{ - int targ = SCB_TARGET(scb); - char chan = SCB_CHANNEL(scb); - int slun = SCB_LUN(scb); - int match; - - match = ((chan == channel) || (channel == ALL_CHANNELS)); - if (match != 0) - match = ((targ == target) || (target == ALL_TARGETS)); - if (match != 0) - match = ((lun == slun) || (lun == ALL_LUNS)); - return match; -} - -STATIC void -ahc_construct_sdtr(ahc, period, offset) - struct ahc_softc *ahc; - u_int period; - u_int offset; -{ - ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; - ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; - ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; - ahc->msgout_buf[ahc->msgout_index++] = period; - ahc->msgout_buf[ahc->msgout_index++] = offset; - ahc->msgout_len += 5; -} -STATIC void -ahc_construct_wdtr(ahc, bus_width) - struct ahc_softc *ahc; - u_int bus_width; +/***************************** Residual Processing ****************************/ +/* + * Calculate the residual for a just completed SCB. + */ +void +ahc_calc_residual(struct scb *scb) { - ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; - ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; - ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; - ahc->msgout_buf[ahc->msgout_index++] = bus_width; - ahc->msgout_len += 4; -} + struct hardware_scb *hscb; + struct status_pkt *spkt; + uint32_t sgptr; + uint32_t resid_sgptr; + uint32_t resid; -STATIC void -ahc_calc_residual(scb) - struct scb *scb; -{ - struct hardware_scb *hscb; + /* + * 5 cases. + * 1) No residual. + * SG_RESID_VALID clear in sgptr. + * 2) Transferless command + * 3) Never performed any transfers. + * sgptr has SG_FULL_RESID set. + * 4) No residual but target did not + * save data pointers after the + * last transfer, so sgptr was + * never updated. + * 5) We have a partial residual. + * Use residual_sgptr to determine + * where we are. + */ hscb = scb->hscb; + sgptr = ahc_le32toh(hscb->sgptr); + if ((sgptr & SG_RESID_VALID) == 0) + /* Case 1 */ + return; + sgptr &= ~SG_RESID_VALID; + + if ((sgptr & SG_LIST_NULL) != 0) + /* Case 2 */ + return; + + spkt = &hscb->shared_data.status; + resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr); + if ((sgptr & SG_FULL_RESID) != 0) { + /* Case 3 */ + resid = ahc_get_transfer_length(scb); + } else if ((resid_sgptr & SG_LIST_NULL) != 0) { + /* Case 4 */ + return; + } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { + panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); + } else { + struct ahc_dma_seg *sg; - /* - * If the disconnected flag is still set, this is bogus - * residual information left over from a sequencer - * pagin/pageout, so ignore this case. - */ - if ((scb->hscb->control & DISCONNECTED) == 0) { - u_int32_t resid; - int resid_sgs; - int sg; - /* * Remainder of the SG where the transfer * stopped. */ - resid = (hscb->residual_data_count[2] << 16) - | (hscb->residual_data_count[1] <<8) - | (hscb->residual_data_count[0]); + resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK; + sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK); + + /* The residual sg_ptr always points to the next sg */ + sg--; /* * Add up the contents of all residual * SG segments that are after the SG where * the transfer stopped. */ - resid_sgs = scb->hscb->residual_SG_count - 1/*current*/; - sg = scb->sg_count - resid_sgs; - while (resid_sgs > 0) { - - resid += le32toh(scb->sg_list[sg].len); + while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) { sg++; - resid_sgs--; + resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK; } - scb->xs->resid = resid; } - - /* - * Clean out the residual information in this SCB for its - * next consumer. - */ - hscb->residual_SG_count = 0; + if ((scb->flags & SCB_SENSE) == 0) + ahc_set_residual(scb, resid); + else + ahc_set_sense_residual(scb, resid); #ifdef AHC_DEBUG if (ahc_debug & AHC_SHOWMISC) { - sc_print_addr(scb->xs->sc_link); - printf("Handled Residual of %ld bytes\n" ,scb->xs->resid); + ahc_print_path(scb->ahc_softc, scb); + printf("Handled Residual of %d bytes\n", resid); } #endif } -STATIC void -ahc_update_pending_syncrates(ahc) - struct ahc_softc *ahc; +/******************************* Target Mode **********************************/ +#ifdef AHC_TARGET_MODE +/* + * Add a target mode event to this lun's queue + */ +static void +ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate, + u_int initiator_id, u_int event_type, u_int event_arg) { - struct scb *scb; - int pending_scb_count; - int i; - u_int saved_scbptr; + struct ahc_tmode_event *event; + int pending; + + xpt_freeze_devq(lstate->path, /*count*/1); + if (lstate->event_w_idx >= lstate->event_r_idx) + pending = lstate->event_w_idx - lstate->event_r_idx; + else + pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1 + - (lstate->event_r_idx - lstate->event_w_idx); + + if (event_type == EVENT_TYPE_BUS_RESET + || event_type == MSG_BUS_DEV_RESET) { + /* + * Any earlier events are irrelevant, so reset our buffer. + * This has the effect of allowing us to deal with reset + * floods (an external device holding down the reset line) + * without losing the event that is really interesting. + */ + lstate->event_r_idx = 0; + lstate->event_w_idx = 0; + xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); + } + + if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) { + xpt_print_path(lstate->path); + printf("immediate event %x:%x lost\n", + lstate->event_buffer[lstate->event_r_idx].event_type, + lstate->event_buffer[lstate->event_r_idx].event_arg); + lstate->event_r_idx++; + if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) + lstate->event_r_idx = 0; + xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); + } + + event = &lstate->event_buffer[lstate->event_w_idx]; + event->initiator_id = initiator_id; + event->event_type = event_type; + event->event_arg = event_arg; + lstate->event_w_idx++; + if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE) + lstate->event_w_idx = 0; +} + +/* + * Send any target mode events queued up waiting + * for immediate notify resources. + */ +void +ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate) +{ + struct ccb_hdr *ccbh; + struct ccb_immed_notify *inot; + + while (lstate->event_r_idx != lstate->event_w_idx + && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { + struct ahc_tmode_event *event; + + event = &lstate->event_buffer[lstate->event_r_idx]; + SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); + inot = (struct ccb_immed_notify *)ccbh; + switch (event->event_type) { + case EVENT_TYPE_BUS_RESET: + ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; + break; + default: + ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; + inot->message_args[0] = event->event_type; + inot->message_args[1] = event->event_arg; + break; + } + inot->initiator_id = event->initiator_id; + inot->sense_len = 0; + xpt_done((union ccb *)inot); + lstate->event_r_idx++; + if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) + lstate->event_r_idx = 0; + } +} +#endif + +/******************** Sequencer Program Patching/Download *********************/ + +#ifdef AHC_DUMP_SEQ +void +ahc_dumpseq(struct ahc_softc* ahc) +{ + int i; + int max_prog; + + if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) + max_prog = 448; + else if ((ahc->features & AHC_ULTRA2) != 0) + max_prog = 768; + else + max_prog = 512; + + ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); + ahc_outb(ahc, SEQADDR0, 0); + ahc_outb(ahc, SEQADDR1, 0); + for (i = 0; i < max_prog; i++) { + uint8_t ins_bytes[4]; + + ahc_insb(ahc, SEQRAM, ins_bytes, 4); + printf("0x%08x\n", ins_bytes[0] << 24 + | ins_bytes[1] << 16 + | ins_bytes[2] << 8 + | ins_bytes[3]); + } +} +#endif + +static void +ahc_loadseq(struct ahc_softc *ahc) +{ + struct cs cs_table[num_critical_sections]; + u_int begin_set[num_critical_sections]; + u_int end_set[num_critical_sections]; + struct patch *cur_patch; + u_int cs_count; + u_int cur_cs; + u_int i; + int downloaded; + u_int skip_addr; + u_int sg_prefetch_cnt; + uint8_t download_consts[7]; /* - * Traverse the pending SCB list and ensure that all of the - * SCBs there have the proper settings. + * Start out with 0 critical sections + * that apply to this firmware load. */ - scb = LIST_FIRST(&ahc->pending_scbs); - pending_scb_count = 0; - while (scb != NULL) { - struct ahc_devinfo devinfo; - struct scsi_xfer *xs; - struct scb *pending_scb; - struct hardware_scb *pending_hscb; - struct ahc_initiator_tinfo *tinfo; - struct tmode_tstate *tstate; - u_int our_id, remote_id; - - xs = scb->xs; - pending_scb = scb; - pending_hscb = pending_scb->hscb; - our_id = SCB_IS_SCSIBUS_B(pending_scb) - ? ahc->our_id_b : ahc->our_id; - remote_id = xs->sc_link->target; - ahc_compile_devinfo(&devinfo, our_id, remote_id, - SCB_LUN(pending_scb), - SCB_CHANNEL(pending_scb), - ROLE_UNKNOWN); - tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, - our_id, remote_id, &tstate); - pending_hscb->control &= ~ULTRAENB; - if ((tstate->ultraenb & devinfo.target_mask) != 0) - pending_hscb->control |= ULTRAENB; - pending_hscb->scsirate = tinfo->scsirate; - pending_hscb->scsioffset = tinfo->current.offset; - pending_scb_count++; - scb = LIST_NEXT(scb, pend_links); - } + cs_count = 0; + cur_cs = 0; + memset(begin_set, 0, sizeof(begin_set)); + memset(end_set, 0, sizeof(end_set)); - if (pending_scb_count == 0) - return; + /* Setup downloadable constant table */ + download_consts[QOUTFIFO_OFFSET] = 0; + if (ahc->targetcmds != NULL) + download_consts[QOUTFIFO_OFFSET] += 32; + download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1; + download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1; + download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1); + sg_prefetch_cnt = ahc->pci_cachesize; + if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg))) + sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg); + download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; + download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1); + download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1); - saved_scbptr = ahc_inb(ahc, SCBPTR); - /* Ensure that the hscbs down on the card match the new information */ - for (i = 0; i < ahc->scb_data->maxhscbs; i++) { - u_int scb_tag; + cur_patch = patches; + downloaded = 0; + skip_addr = 0; + ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); + ahc_outb(ahc, SEQADDR0, 0); + ahc_outb(ahc, SEQADDR1, 0); - ahc_outb(ahc, SCBPTR, i); - scb_tag = ahc_inb(ahc, SCB_TAG); - if (scb_tag != SCB_LIST_NULL) { - struct ahc_devinfo devinfo; - struct scb *pending_scb; - struct scsi_xfer *xs; - struct hardware_scb *pending_hscb; - struct ahc_initiator_tinfo *tinfo; - struct tmode_tstate *tstate; - u_int our_id, remote_id; - u_int control; - - pending_scb = &ahc->scb_data->scbarray[scb_tag]; - if (pending_scb->flags == SCB_FREE) + for (i = 0; i < sizeof(seqprog)/4; i++) { + if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { + /* + * Don't download this instruction as it + * is in a patch that was removed. + */ + continue; + } + /* + * Move through the CS table until we find a CS + * that might apply to this instruction. + */ + for (; cur_cs < num_critical_sections; cur_cs++) { + if (critical_sections[cur_cs].end <= i) { + if (begin_set[cs_count] == TRUE + && end_set[cs_count] == FALSE) { + cs_table[cs_count].end = downloaded; + end_set[cs_count] = TRUE; + cs_count++; + } continue; - pending_hscb = pending_scb->hscb; - xs = pending_scb->xs; - our_id = SCB_IS_SCSIBUS_B(pending_scb) - ? ahc->our_id_b : ahc->our_id; - remote_id = xs->sc_link->target; - ahc_compile_devinfo(&devinfo, our_id, remote_id, - SCB_LUN(pending_scb), - SCB_CHANNEL(pending_scb), - ROLE_UNKNOWN); - tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, - our_id, remote_id, &tstate); - control = ahc_inb(ahc, SCB_CONTROL); - control &= ~ULTRAENB; - if ((tstate->ultraenb & devinfo.target_mask) != 0) - control |= ULTRAENB; - ahc_outb(ahc, SCB_CONTROL, control); - ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); - ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); + } + if (critical_sections[cur_cs].begin <= i + && begin_set[cs_count] == FALSE) { + cs_table[cs_count].begin = downloaded; + begin_set[cs_count] = TRUE; + } + break; } + ahc_download_instr(ahc, i, download_consts); + downloaded++; } - ahc_outb(ahc, SCBPTR, saved_scbptr); + + ahc->num_critical_sections = cs_count; + if (cs_count != 0) { + + cs_count *= sizeof(struct cs); + ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); + if (ahc->critical_sections == NULL) + panic("ahc_loadseq: Could not malloc"); + memcpy(ahc->critical_sections, cs_table, cs_count); + } + ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); + ahc_restart(ahc); + + if (bootverbose) + printf(" %d instructions downloaded\n", downloaded); } -STATIC void -ahc_shutdown(void *arg) +static int +ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, + u_int start_instr, u_int *skip_addr) { - struct ahc_softc *ahc; - int i; - u_int sxfrctl1_a, sxfrctl1_b; + struct patch *cur_patch; + struct patch *last_patch; + u_int num_patches; - ahc = (struct ahc_softc *)arg; + num_patches = sizeof(patches)/sizeof(struct patch); + last_patch = &patches[num_patches]; + cur_patch = *start_patch; + + while (cur_patch < last_patch && start_instr == cur_patch->begin) { + + if (cur_patch->patch_func(ahc) == 0) { + + /* Start rejecting code */ + *skip_addr = start_instr + cur_patch->skip_instr; + cur_patch += cur_patch->skip_patch; + } else { + /* Accepted this patch. Advance to the next + * one and wait for our intruction pointer to + * hit this point. + */ + cur_patch++; + } + } + + *start_patch = cur_patch; + if (start_instr < *skip_addr) + /* Still skipping */ + return (0); - pause_sequencer(ahc); + return (1); +} + +static void +ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts) +{ + union ins_formats instr; + struct ins_format1 *fmt1_ins; + struct ins_format3 *fmt3_ins; + u_int opcode; /* - * Preserve the value of the SXFRCTL1 register for all channels. - * It contains settings that affect termination and we don't want - * to disturb the integrity of the bus during shutdown in case - * we are in a multi-initiator setup. + * The firmware is always compiled into a little endian format. */ - sxfrctl1_b = 0; - if ((ahc->features & AHC_TWIN) != 0) { - u_int sblkctl; + instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); - sblkctl = ahc_inb(ahc, SBLKCTL); - ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); - sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); - ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); + fmt1_ins = &instr.format1; + fmt3_ins = NULL; + + /* Pull the opcode */ + opcode = instr.format1.opcode; + switch (opcode) { + case AIC_OP_JMP: + case AIC_OP_JC: + case AIC_OP_JNC: + case AIC_OP_CALL: + case AIC_OP_JNE: + case AIC_OP_JNZ: + case AIC_OP_JE: + case AIC_OP_JZ: + { + struct patch *cur_patch; + int address_offset; + u_int address; + u_int skip_addr; + u_int i; + + fmt3_ins = &instr.format3; + address_offset = 0; + address = fmt3_ins->address; + cur_patch = patches; + skip_addr = 0; + + for (i = 0; i < address;) { + + ahc_check_patch(ahc, &cur_patch, i, &skip_addr); + + if (skip_addr > i) { + int end_addr; + + end_addr = MIN(address, skip_addr); + address_offset += end_addr - i; + i = skip_addr; + } else { + i++; + } + } + address -= address_offset; + fmt3_ins->address = address; + /* FALLTHROUGH */ } + case AIC_OP_OR: + case AIC_OP_AND: + case AIC_OP_XOR: + case AIC_OP_ADD: + case AIC_OP_ADC: + case AIC_OP_BMOV: + if (fmt1_ins->parity != 0) { + fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; + } + fmt1_ins->parity = 0; + if ((ahc->features & AHC_CMD_CHAN) == 0 + && opcode == AIC_OP_BMOV) { + /* + * Block move was added at the same time + * as the command channel. Verify that + * this is only a move of a single element + * and convert the BMOV to a MOV + * (AND with an immediate of FF). + */ + if (fmt1_ins->immediate != 1) + panic("%s: BMOV not supported\n", + ahc_name(ahc)); + fmt1_ins->opcode = AIC_OP_AND; + fmt1_ins->immediate = 0xff; + } + /* FALLTHROUGH */ + case AIC_OP_ROL: + if ((ahc->features & AHC_ULTRA2) != 0) { + int i, count; - sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); + /* Calculate odd parity for the instruction */ + for (i = 0, count = 0; i < 31; i++) { + uint32_t mask; - /* This will reset most registers to 0, but not all */ - ahc_reset(ahc); + mask = 0x01 << i; + if ((instr.integer & mask) != 0) + count++; + } + if ((count & 0x01) == 0) + instr.format1.parity = 1; + } else { + /* Compress the instruction for older sequencers */ + if (fmt3_ins != NULL) { + instr.integer = + fmt3_ins->immediate + | (fmt3_ins->source << 8) + | (fmt3_ins->address << 16) + | (fmt3_ins->opcode << 25); + } else { + instr.integer = + fmt1_ins->immediate + | (fmt1_ins->source << 8) + | (fmt1_ins->destination << 16) + | (fmt1_ins->ret << 24) + | (fmt1_ins->opcode << 25); + } + } + /* The sequencer is a little endian cpu */ + instr.integer = ahc_htole32(instr.integer); + ahc_outsb(ahc, SEQRAM, instr.bytes, 4); + break; + default: + panic("Unknown opcode encountered in seq program"); + break; + } +} - if ((ahc->features & AHC_TWIN) != 0) { - u_int sblkctl; +void +ahc_dump_card_state(struct ahc_softc *ahc) +{ + struct scb *scb; + struct scb_tailq *untagged_q; + int target; + int maxtarget; + int i; + uint8_t last_phase; + uint8_t qinpos; + uint8_t qintail; + uint8_t qoutpos; + uint8_t scb_index; + uint8_t saved_scbptr; - sblkctl = ahc_inb(ahc, SBLKCTL); - ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); - ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); - ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); + saved_scbptr = ahc_inb(ahc, SCBPTR); + + last_phase = ahc_inb(ahc, LASTPHASE); + printf("%s: Dumping Card State %s, at SEQADDR 0x%x\n", + ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg, + ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); + printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n", + ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX), + ahc_inb(ahc, ARG_2)); + printf("HCNT = 0x%x\n", ahc_inb(ahc, HCNT)); + printf("SCSISEQ = 0x%x, SBLKCTL = 0x%x\n", + ahc_inb(ahc, SCSISEQ), ahc_inb(ahc, SBLKCTL)); + printf(" DFCNTRL = 0x%x, DFSTATUS = 0x%x\n", + ahc_inb(ahc, DFCNTRL), ahc_inb(ahc, DFSTATUS)); + printf("LASTPHASE = 0x%x, SCSISIGI = 0x%x, SXFRCTL0 = 0x%x\n", + last_phase, ahc_inb(ahc, SCSISIGI), ahc_inb(ahc, SXFRCTL0)); + printf("SSTAT0 = 0x%x, SSTAT1 = 0x%x\n", + ahc_inb(ahc, SSTAT0), ahc_inb(ahc, SSTAT1)); + if ((ahc->features & AHC_DT) != 0) + printf("SCSIPHASE = 0x%x\n", ahc_inb(ahc, SCSIPHASE)); + printf("STACK == 0x%x, 0x%x, 0x%x, 0x%x\n", + ahc_inb(ahc, STACK) | (ahc_inb(ahc, STACK) << 8), + ahc_inb(ahc, STACK) | (ahc_inb(ahc, STACK) << 8), + ahc_inb(ahc, STACK) | (ahc_inb(ahc, STACK) << 8), + ahc_inb(ahc, STACK) | (ahc_inb(ahc, STACK) << 8)); + printf("SCB count = %d\n", ahc->scb_data->numscbs); + printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag); + printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB)); + /* QINFIFO */ + printf("QINFIFO entries: "); + if ((ahc->features & AHC_QUEUE_REGS) != 0) { + qinpos = ahc_inb(ahc, SNSCB_QOFF); + ahc_outb(ahc, SNSCB_QOFF, qinpos); + } else + qinpos = ahc_inb(ahc, QINPOS); + qintail = ahc->qinfifonext; + while (qinpos != qintail) { + printf("%d ", ahc->qinfifo[qinpos]); + qinpos++; } - ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); + printf("\n"); - ahc_outb(ahc, SCSISEQ, 0); - ahc_outb(ahc, SXFRCTL0, 0); - ahc_outb(ahc, DSPCISTATUS, 0); + printf("Waiting Queue entries: "); + scb_index = ahc_inb(ahc, WAITING_SCBH); + i = 0; + while (scb_index != SCB_LIST_NULL && i++ < 256) { + ahc_outb(ahc, SCBPTR, scb_index); + printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); + scb_index = ahc_inb(ahc, SCB_NEXT); + } + printf("\n"); - for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) - ahc_outb(ahc, i, 0); + printf("Disconnected Queue entries: "); + scb_index = ahc_inb(ahc, DISCONNECTED_SCBH); + i = 0; + while (scb_index != SCB_LIST_NULL && i++ < 256) { + ahc_outb(ahc, SCBPTR, scb_index); + printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); + scb_index = ahc_inb(ahc, SCB_NEXT); + } + printf("\n"); + + ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); + printf("QOUTFIFO entries: "); + qoutpos = ahc->qoutfifonext; + i = 0; + while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) { + printf("%d ", ahc->qoutfifo[qoutpos]); + qoutpos++; + } + printf("\n"); + + printf("Sequencer Free SCB List: "); + scb_index = ahc_inb(ahc, FREE_SCBH); + i = 0; + while (scb_index != SCB_LIST_NULL && i++ < 256) { + ahc_outb(ahc, SCBPTR, scb_index); + printf("%d ", scb_index); + scb_index = ahc_inb(ahc, SCB_NEXT); + } + printf("\n"); + + printf("Pending list: "); + i = 0; + LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { + if (i++ > 256) + break; + if (scb != LIST_FIRST(&ahc->pending_scbs)) + printf(", "); + printf("%d", scb->hscb->tag); + if ((ahc->flags & AHC_PAGESCBS) == 0) { + ahc_outb(ahc, SCBPTR, scb->hscb->tag); + printf("(0x%x, 0x%x)", ahc_inb(ahc, SCB_CONTROL), + ahc_inb(ahc, SCB_TAG)); + } + } + printf("\n"); + + printf("Kernel Free SCB list: "); + i = 0; + SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) { + if (i++ > 256) + break; + printf("%d ", scb->hscb->tag); + } + printf("\n"); + + maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7; + for (target = 0; target <= maxtarget; target++) { + untagged_q = &ahc->untagged_queues[target]; + if (TAILQ_FIRST(untagged_q) == NULL) + continue; + printf("Untagged Q(%d): ", target); + i = 0; + TAILQ_FOREACH(scb, untagged_q, links.tqe) { + if (i++ > 256) + break; + printf("%d ", scb->hscb->tag); + } + printf("\n"); + } + + ahc_platform_dump_card_state(ahc); + ahc_outb(ahc, SCBPTR, saved_scbptr); } -STATIC void -ahc_check_tags(ahc, xs) -struct ahc_softc *ahc; -struct scsi_xfer *xs; +/************************* Target Mode ****************************************/ +#ifdef AHC_TARGET_MODE +cam_status +ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb, + struct ahc_tmode_tstate **tstate, + struct ahc_tmode_lstate **lstate, + int notfound_failure) { - struct ahc_devinfo devinfo; - if (xs->sc_link->quirks & SDEV_NOTAGS) + if ((ahc->features & AHC_TARGETMODE) == 0) + return (CAM_REQ_INVALID); + + /* + * Handle the 'black hole' device that sucks up + * requests to unattached luns on enabled targets. + */ + if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD + && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { + *tstate = NULL; + *lstate = ahc->black_hole; + } else { + u_int max_id; + + max_id = (ahc->features & AHC_WIDE) ? 15 : 7; + if (ccb->ccb_h.target_id > max_id) + return (CAM_TID_INVALID); + + if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS) + return (CAM_LUN_INVALID); + + *tstate = ahc->enabled_targets[ccb->ccb_h.target_id]; + *lstate = NULL; + if (*tstate != NULL) + *lstate = + (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; + } + + if (notfound_failure != 0 && *lstate == NULL) + return (CAM_PATH_INVALID); + + return (CAM_REQ_CMP); +} + +void +ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb) +{ + struct ahc_tmode_tstate *tstate; + struct ahc_tmode_lstate *lstate; + struct ccb_en_lun *cel; + cam_status status; + u_int target; + u_int lun; + u_int target_mask; + u_long s; + char channel; + + status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate, + /*notfound_failure*/FALSE); + + if (status != CAM_REQ_CMP) { + ccb->ccb_h.status = status; return; + } - if (ahc_istagged_device(ahc, xs, 1)) + if ((ahc->features & AHC_MULTIROLE) != 0) { + u_int our_id; + + if (cam_sim_bus(sim) == 0) + our_id = ahc->our_id; + else + our_id = ahc->our_id_b; + + if (ccb->ccb_h.target_id != our_id) { + if ((ahc->features & AHC_MULTI_TID) != 0 + && (ahc->flags & AHC_INITIATORROLE) != 0) { + /* + * Only allow additional targets if + * the initiator role is disabled. + * The hardware cannot handle a re-select-in + * on the initiator id during a re-select-out + * on a different target id. + */ + status = CAM_TID_INVALID; + } else if ((ahc->flags & AHC_INITIATORROLE) != 0 + || ahc->enabled_luns > 0) { + /* + * Only allow our target id to change + * if the initiator role is not configured + * and there are no enabled luns which + * are attached to the currently registered + * scsi id. + */ + status = CAM_TID_INVALID; + } + } + } + + if (status != CAM_REQ_CMP) { + ccb->ccb_h.status = status; return; + } - ahc_compile_devinfo(&devinfo, - SIM_SCSI_ID(ahc, xs->sc_link), - xs->sc_link->target, - xs->sc_link->lun, - SIM_CHANNEL(ahc, xs->sc_link), - ROLE_INITIATOR); + /* + * We now have an id that is valid. + * If we aren't in target mode, switch modes. + */ + if ((ahc->flags & AHC_TARGETROLE) == 0 + && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { + u_long s; + + printf("Configuring Target Mode\n"); + ahc_lock(ahc, &s); + if (LIST_FIRST(&ahc->pending_scbs) != NULL) { + ccb->ccb_h.status = CAM_BUSY; + ahc_unlock(ahc, &s); + return; + } + ahc->flags |= AHC_TARGETROLE; + if ((ahc->features & AHC_MULTIROLE) == 0) + ahc->flags &= ~AHC_INITIATORROLE; + ahc_pause(ahc); + ahc_loadseq(ahc); + ahc_unlock(ahc, &s); + } + cel = &ccb->cel; + target = ccb->ccb_h.target_id; + lun = ccb->ccb_h.target_lun; + channel = SIM_CHANNEL(ahc, sim); + target_mask = 0x01 << target; + if (channel == 'B') + target_mask <<= 8; - ahc_set_tags(ahc, &devinfo, TRUE); + if (cel->enable != 0) { + u_int scsiseq; - printf("%s: target %d using tagged queuing\n", - ahc_name(ahc), xs->sc_link->target); + /* Are we already enabled?? */ + if (lstate != NULL) { + xpt_print_path(ccb->ccb_h.path); + printf("Lun already enabled\n"); + ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; + return; + } + + if (cel->grp6_len != 0 + || cel->grp7_len != 0) { + /* + * Don't (yet?) support vendor + * specific commands. + */ + ccb->ccb_h.status = CAM_REQ_INVALID; + printf("Non-zero Group Codes\n"); + return; + } - if (ahc->scb_data->maxhscbs >= 16 || - (ahc->flags & AHC_PAGESCBS)) { - /* Default to 16 tags */ - xs->sc_link->openings += 14; - } else { /* - * Default to 4 tags on whimpy - * cards that don't have much SCB - * space and can't page. This prevents - * a single device from hogging all - * slots. We should really have a better - * way of providing fairness. + * Seems to be okay. + * Setup our data structures. */ - xs->sc_link->openings += 2; + if (target != CAM_TARGET_WILDCARD && tstate == NULL) { + tstate = ahc_alloc_tstate(ahc, target, channel); + if (tstate == NULL) { + xpt_print_path(ccb->ccb_h.path); + printf("Couldn't allocate tstate\n"); + ccb->ccb_h.status = CAM_RESRC_UNAVAIL; + return; + } + } + lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); + if (lstate == NULL) { + xpt_print_path(ccb->ccb_h.path); + printf("Couldn't allocate lstate\n"); + ccb->ccb_h.status = CAM_RESRC_UNAVAIL; + return; + } + memset(lstate, 0, sizeof(*lstate)); + status = xpt_create_path(&lstate->path, /*periph*/NULL, + xpt_path_path_id(ccb->ccb_h.path), + xpt_path_target_id(ccb->ccb_h.path), + xpt_path_lun_id(ccb->ccb_h.path)); + if (status != CAM_REQ_CMP) { + free(lstate, M_DEVBUF); + xpt_print_path(ccb->ccb_h.path); + printf("Couldn't allocate path\n"); + ccb->ccb_h.status = CAM_RESRC_UNAVAIL; + return; + } + SLIST_INIT(&lstate->accept_tios); + SLIST_INIT(&lstate->immed_notifies); + ahc_lock(ahc, &s); + ahc_pause(ahc); + if (target != CAM_TARGET_WILDCARD) { + tstate->enabled_luns[lun] = lstate; + ahc->enabled_luns++; + + if ((ahc->features & AHC_MULTI_TID) != 0) { + u_int targid_mask; + + targid_mask = ahc_inb(ahc, TARGID) + | (ahc_inb(ahc, TARGID + 1) << 8); + + targid_mask |= target_mask; + ahc_outb(ahc, TARGID, targid_mask); + ahc_outb(ahc, TARGID+1, (targid_mask >> 8)); + + ahc_update_scsiid(ahc, targid_mask); + } else { + u_int our_id; + char channel; + + channel = SIM_CHANNEL(ahc, sim); + our_id = SIM_SCSI_ID(ahc, sim); + + /* + * This can only happen if selections + * are not enabled + */ + if (target != our_id) { + u_int sblkctl; + char cur_channel; + int swap; + + sblkctl = ahc_inb(ahc, SBLKCTL); + cur_channel = (sblkctl & SELBUSB) + ? 'B' : 'A'; + if ((ahc->features & AHC_TWIN) == 0) + cur_channel = 'A'; + swap = cur_channel != channel; + if (channel == 'A') + ahc->our_id = target; + else + ahc->our_id_b = target; + + if (swap) + ahc_outb(ahc, SBLKCTL, + sblkctl ^ SELBUSB); + + ahc_outb(ahc, SCSIID, target); + + if (swap) + ahc_outb(ahc, SBLKCTL, sblkctl); + } + } + } else + ahc->black_hole = lstate; + /* Allow select-in operations */ + if (ahc->black_hole != NULL && ahc->enabled_luns > 0) { + scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); + scsiseq |= ENSELI; + ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); + scsiseq = ahc_inb(ahc, SCSISEQ); + scsiseq |= ENSELI; + ahc_outb(ahc, SCSISEQ, scsiseq); + } + ahc_unpause(ahc); + ahc_unlock(ahc, &s); + ccb->ccb_h.status = CAM_REQ_CMP; + xpt_print_path(ccb->ccb_h.path); + printf("Lun now enabled for target mode\n"); + } else { + struct scb *scb; + int i, empty; + + if (lstate == NULL) { + ccb->ccb_h.status = CAM_LUN_INVALID; + return; + } + + ahc_lock(ahc, &s); + + ccb->ccb_h.status = CAM_REQ_CMP; + LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { + struct ccb_hdr *ccbh; + + ccbh = &scb->io_ctx->ccb_h; + if (ccbh->func_code == XPT_CONT_TARGET_IO + && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ + printf("CTIO pending\n"); + ccb->ccb_h.status = CAM_REQ_INVALID; + ahc_unlock(ahc, &s); + return; + } + } + + if (SLIST_FIRST(&lstate->accept_tios) != NULL) { + printf("ATIOs pending\n"); + ccb->ccb_h.status = CAM_REQ_INVALID; + } + + if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { + printf("INOTs pending\n"); + ccb->ccb_h.status = CAM_REQ_INVALID; + } + + if (ccb->ccb_h.status != CAM_REQ_CMP) { + ahc_unlock(ahc, &s); + return; + } + + xpt_print_path(ccb->ccb_h.path); + printf("Target mode disabled\n"); + xpt_free_path(lstate->path); + free(lstate, M_DEVBUF); + + ahc_pause(ahc); + /* Can we clean up the target too? */ + if (target != CAM_TARGET_WILDCARD) { + tstate->enabled_luns[lun] = NULL; + ahc->enabled_luns--; + for (empty = 1, i = 0; i < 8; i++) + if (tstate->enabled_luns[i] != NULL) { + empty = 0; + break; + } + + if (empty) { + ahc_free_tstate(ahc, target, channel, + /*force*/FALSE); + if (ahc->features & AHC_MULTI_TID) { + u_int targid_mask; + + targid_mask = ahc_inb(ahc, TARGID) + | (ahc_inb(ahc, TARGID + 1) + << 8); + + targid_mask &= ~target_mask; + ahc_outb(ahc, TARGID, targid_mask); + ahc_outb(ahc, TARGID+1, + (targid_mask >> 8)); + ahc_update_scsiid(ahc, targid_mask); + } + } + } else { + + ahc->black_hole = NULL; + + /* + * We can't allow selections without + * our black hole device. + */ + empty = TRUE; + } + if (ahc->enabled_luns == 0) { + /* Disallow select-in */ + u_int scsiseq; + + scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); + scsiseq &= ~ENSELI; + ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); + scsiseq = ahc_inb(ahc, SCSISEQ); + scsiseq &= ~ENSELI; + ahc_outb(ahc, SCSISEQ, scsiseq); + + if ((ahc->features & AHC_MULTIROLE) == 0) { + printf("Configuring Initiator Mode\n"); + ahc->flags &= ~AHC_TARGETROLE; + ahc->flags |= AHC_INITIATORROLE; + ahc_pause(ahc); + ahc_loadseq(ahc); + } + } + ahc_unpause(ahc); + ahc_unlock(ahc, &s); } } -STATIC int -ahc_istagged_device(ahc, xs, nocmdcheck) -struct ahc_softc *ahc; -struct scsi_xfer *xs; -int nocmdcheck; +static void +ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask) { - char channel; - u_int our_id, target; - struct tmode_tstate *tstate; - struct ahc_devinfo devinfo; + u_int scsiid_mask; + u_int scsiid; - if (xs->sc_link->quirks & SDEV_NOTAGS) - return 0; + if ((ahc->features & AHC_MULTI_TID) == 0) + panic("ahc_update_scsiid called on non-multitid unit\n"); /* - * XXX never do these commands with tags. Should really be - * in a higher layer. + * Since we will rely on the the TARGID mask + * for selection enables, ensure that OID + * in SCSIID is not set to some other ID + * that we don't want to allow selections on. */ - if (!nocmdcheck && (xs->cmd->opcode == INQUIRY || - xs->cmd->opcode == TEST_UNIT_READY || - xs->cmd->opcode == REQUEST_SENSE)) - return 0; + if ((ahc->features & AHC_ULTRA2) != 0) + scsiid = ahc_inb(ahc, SCSIID_ULTRA2); + else + scsiid = ahc_inb(ahc, SCSIID); + scsiid_mask = 0x1 << (scsiid & OID); + if ((targid_mask & scsiid_mask) == 0) { + u_int our_id; - channel = SIM_CHANNEL(ahc, xs->sc_link); - our_id = SIM_SCSI_ID(ahc, xs->sc_link); - target = xs->sc_link->target; - (void)ahc_fetch_transinfo(ahc, channel, our_id, target, &tstate); + /* ffs counts from 1 */ + our_id = ffs(targid_mask); + if (our_id == 0) + our_id = ahc->our_id; + else + our_id--; + scsiid &= TID; + scsiid |= our_id; + } + if ((ahc->features & AHC_ULTRA2) != 0) + ahc_outb(ahc, SCSIID_ULTRA2, scsiid); + else + ahc_outb(ahc, SCSIID, scsiid); +} + +void +ahc_run_tqinfifo(struct ahc_softc *ahc, int paused) +{ + struct target_cmd *cmd; - ahc_compile_devinfo(&devinfo, our_id, target, - xs->sc_link->lun, channel, ROLE_INITIATOR); + /* + * If the card supports auto-access pause, + * we can access the card directly regardless + * of whether it is paused or not. + */ + if ((ahc->features & AHC_AUTOPAUSE) != 0) + paused = TRUE; - return (tstate->tagenable & devinfo.target_mask); + ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD); + while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) { + + /* + * Only advance through the queue if we + * have the resources to process the command. + */ + if (ahc_handle_target_cmd(ahc, cmd) != 0) + break; + + cmd->cmd_valid = 0; + ahc_dmamap_sync(ahc, ahc->shared_data_dmat, + ahc->shared_data_dmamap, + ahc_targetcmd_offset(ahc, ahc->tqinfifonext), + sizeof(struct target_cmd), + BUS_DMASYNC_PREREAD); + ahc->tqinfifonext++; + + /* + * Lazily update our position in the target mode incoming + * command queue as seen by the sequencer. + */ + if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { + if ((ahc->features & AHC_HS_MAILBOX) != 0) { + u_int hs_mailbox; + + hs_mailbox = ahc_inb(ahc, HS_MAILBOX); + hs_mailbox &= ~HOST_TQINPOS; + hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS; + ahc_outb(ahc, HS_MAILBOX, hs_mailbox); + } else { + if (!paused) + ahc_pause(ahc); + ahc_outb(ahc, KERNEL_TQINPOS, + ahc->tqinfifonext & HOST_TQINPOS); + if (!paused) + ahc_unpause(ahc); + } + } + } +} + +static int +ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd) +{ + struct ahc_tmode_tstate *tstate; + struct ahc_tmode_lstate *lstate; + struct ccb_accept_tio *atio; + uint8_t *byte; + int initiator; + int target; + int lun; + + initiator = SCSIID_TARGET(ahc, cmd->scsiid); + target = SCSIID_OUR_ID(cmd->scsiid); + lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); + + byte = cmd->bytes; + tstate = ahc->enabled_targets[target]; + lstate = NULL; + if (tstate != NULL) + lstate = tstate->enabled_luns[lun]; + + /* + * Commands for disabled luns go to the black hole driver. + */ + if (lstate == NULL) + lstate = ahc->black_hole; + + atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); + if (atio == NULL) { + ahc->flags |= AHC_TQINFIFO_BLOCKED; + /* + * Wait for more ATIOs from the peripheral driver for this lun. + */ + return (1); + } else + ahc->flags &= ~AHC_TQINFIFO_BLOCKED; +#if 0 + printf("Incoming command from %d for %d:%d%s\n", + initiator, target, lun, + lstate == ahc->black_hole ? "(Black Holed)" : ""); +#endif + SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); + + if (lstate == ahc->black_hole) { + /* Fill in the wildcards */ + atio->ccb_h.target_id = target; + atio->ccb_h.target_lun = lun; + } + + /* + * Package it up and send it off to + * whomever has this lun enabled. + */ + atio->sense_len = 0; + atio->init_id = initiator; + if (byte[0] != 0xFF) { + /* Tag was included */ + atio->tag_action = *byte++; + atio->tag_id = *byte++; + atio->ccb_h.flags = CAM_TAG_ACTION_VALID; + } else { + atio->ccb_h.flags = 0; + } + byte++; + + /* Okay. Now determine the cdb size based on the command code */ + switch (*byte >> CMD_GROUP_CODE_SHIFT) { + case 0: + atio->cdb_len = 6; + break; + case 1: + case 2: + atio->cdb_len = 10; + break; + case 4: + atio->cdb_len = 16; + break; + case 5: + atio->cdb_len = 12; + break; + case 3: + default: + /* Only copy the opcode. */ + atio->cdb_len = 1; + printf("Reserved or VU command code type encountered\n"); + break; + } + + memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); + + atio->ccb_h.status |= CAM_CDB_RECVD; + + if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { + /* + * We weren't allowed to disconnect. + * We're hanging on the bus until a + * continue target I/O comes in response + * to this accept tio. + */ +#if 0 + printf("Received Immediate Command %d:%d:%d - %p\n", + initiator, target, lun, ahc->pending_device); +#endif + ahc->pending_device = lstate; + ahc_freeze_ccb((union ccb *)atio); + atio->ccb_h.flags |= CAM_DIS_DISCONNECT; + } + xpt_done((union ccb*)atio); + return (0); } + +#endif diff --git a/sys/dev/ic/aic7xxx.h b/sys/dev/ic/aic7xxx.h new file mode 100644 index 00000000000..29ac6feb435 --- /dev/null +++ b/sys/dev/ic/aic7xxx.h @@ -0,0 +1,1218 @@ +/* + * $OpenBSD: aic7xxx.h,v 1.4 2002/06/28 00:34:54 smurph Exp $ + * Core definitions and data structures shareable across OS platforms. + * + * Copyright (c) 1994-2001 Justin T. Gibbs. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU Public License ("GPL"). + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id: aic7xxx.h,v 1.4 2002/06/28 00:34:54 smurph Exp $ + * + * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.h,v 1.40 2001/07/18 21:39:47 gibbs Exp $ + */ + +#ifndef _AIC7XXX_H_ +#define _AIC7XXX_H_ + +/* Register Definitions */ +#include "aic7xxxreg.h" + +/************************* Forward Declarations *******************************/ +struct ahc_platform_data; +struct scb_platform_data; + +/****************************** Useful Macros *********************************/ +#ifndef MAX +#define MAX(a,b) (((a) > (b)) ? (a) : (b)) +#endif + +#ifndef MIN +#define MIN(a,b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) + +#define ALL_CHANNELS '\0' +#define ALL_TARGETS_MASK 0xFFFF +#define INITIATOR_WILDCARD (~0) + +#define SCSIID_TARGET(ahc, scsiid) \ + (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \ + >> TID_SHIFT) +#define SCSIID_OUR_ID(scsiid) \ + ((scsiid) & OID) +#define SCSIID_CHANNEL(ahc, scsiid) \ + ((((ahc)->features & AHC_TWIN) != 0) \ + ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \ + : 'A') +#define SCB_IS_SCSIBUS_B(ahc, scb) \ + (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B') +#define SCB_GET_OUR_ID(scb) \ + SCSIID_OUR_ID((scb)->hscb->scsiid) +#define SCB_GET_TARGET(ahc, scb) \ + SCSIID_TARGET((ahc), (scb)->hscb->scsiid) +#define SCB_GET_CHANNEL(ahc, scb) \ + SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) +#define SCB_GET_LUN(scb) \ + ((scb)->hscb->lun) +#define SCB_GET_TARGET_OFFSET(ahc, scb) \ + (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0)) +#define SCB_GET_TARGET_MASK(ahc, scb) \ + (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb))) +#define TCL_TARGET_OFFSET(tcl) \ + ((((tcl) >> 4) & TID) >> 4) +#define TCL_LUN(tcl) \ + (tcl & (AHC_NUM_LUNS - 1)) +#define BUILD_TCL(scsiid, lun) \ + ((lun) | (((scsiid) & TID) << 4)) + +#ifndef AHC_TARGET_MODE +#undef AHC_TMODE_ENABLE +#define AHC_TMODE_ENABLE 0 +#endif + +/**************************** Driver Constants ********************************/ +/* + * The maximum number of supported targets. + */ +#define AHC_NUM_TARGETS 16 + +/* + * The maximum number of supported luns. + * The identify message only supports 64 luns in SPI3. + * You can have 2^64 luns when information unit transfers are enabled, + * but it is doubtful this driver will ever support IUTs. + */ +#define AHC_NUM_LUNS 64 + +/* + * The maximum transfer per S/G segment. + */ +#define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ + +/* + * The maximum amount of SCB storage in hardware on a controller. + * This value represents an upper bound. Controllers vary in the number + * they actually support. + */ +#define AHC_SCB_MAX 255 + +/* + * The maximum number of concurrent transactions supported per driver instance. + * Sequencer Control Blocks (SCBs) store per-transaction information. Although + * the space for SCBs on the host adapter varies by model, the driver will + * page the SCBs between host and controller memory as needed. We are limited + * to 253 because: + * 1) The 8bit nature of the RISC engine holds us to an 8bit value. + * 2) We reserve one value, 255, to represent the invalid element. + * 3) Our input queue scheme requires one SCB to always be reserved + * in advance of queuing any SCBs. This takes us down to 254. + * 4) To handle our output queue correctly on machines that only + * support 32bit stores, we must clear the array 4 bytes at a + * time. To avoid colliding with a DMA write from the sequencer, + * we must be sure that 4 slots are empty when we write to clear + * the queue. This reduces us to 253 SCBs: 1 that just completed + * and the known three additional empty slots in the queue that + * precede it. + */ +#define AHC_MAX_QUEUE 253 + +/* + * Ring Buffer of incoming target commands. + * We allocate 256 to simplify the logic in the sequencer + * by using the natural wrap point of an 8bit counter. + */ +#define AHC_TMODE_CMDS 256 + +/* Reset line assertion time in us */ +#define AHC_BUSRESET_DELAY 250 + +/******************* Chip Characteristics/Operating Settings *****************/ +/* + * Chip Type + * The chip order is from least sophisticated to most sophisticated. + */ +typedef enum { + AHC_NONE = 0x0000, + AHC_CHIPID_MASK = 0x00FF, + AHC_AIC7770 = 0x0001, + AHC_AIC7850 = 0x0002, + AHC_AIC7855 = 0x0003, + AHC_AIC7859 = 0x0004, + AHC_AIC7860 = 0x0005, + AHC_AIC7870 = 0x0006, + AHC_AIC7880 = 0x0007, + AHC_AIC7895 = 0x0008, + AHC_AIC7895C = 0x0009, + AHC_AIC7890 = 0x000a, + AHC_AIC7896 = 0x000b, + AHC_AIC7892 = 0x000c, + AHC_AIC7899 = 0x000d, + AHC_VL = 0x0100, /* Bus type VL */ + AHC_EISA = 0x0200, /* Bus type EISA */ + AHC_PCI = 0x0400, /* Bus type PCI */ + AHC_BUS_MASK = 0x0F00 +} ahc_chip; + +/* + * Features available in each chip type. + */ +typedef enum { + AHC_FENONE = 0x00000, + AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */ + AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */ + AHC_WIDE = 0x00004, /* Wide Channel */ + AHC_TWIN = 0x00008, /* Twin Channel */ + AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */ + AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */ + AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */ + AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */ + AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */ + AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */ + AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */ + AHC_DT = 0x00800, /* Double Transition transfers */ + AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */ + AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */ + AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */ + AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/ + AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */ + AHC_TARGETMODE = 0x20000, /* Has tested target mode support */ + AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */ + AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */ + AHC_AIC7770_FE = AHC_FENONE, + /* + * The real 7850 does not support Ultra modes, but there are + * several cards that use the generic 7850 PCI ID even though + * they are using an Ultra capable chip (7859/7860). We start + * out with the AHC_ULTRA feature set and then check the DEVSTATUS + * register to determine if the capability is really present. + */ + AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA, + AHC_AIC7860_FE = AHC_AIC7850_FE, + AHC_AIC7870_FE = AHC_TARGETMODE, + AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA, + /* + * Although we have space for both the initiator and + * target roles on ULTRA2 chips, we currently disable + * the initiator role to allow multi-scsi-id target mode + * configurations. We can only respond on the same SCSI + * ID as our initiator role if we allow initiator operation. + * At some point, we should add a configuration knob to + * allow both roles to be loaded. + */ + AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2 + |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID + |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS + |AHC_TARGETMODE, + AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE, + AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE + |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS, + AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, + AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, + AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC +} ahc_feature; + +/* + * Bugs in the silicon that we work around in software. + */ +typedef enum { + AHC_BUGNONE = 0x00, + /* + * On all chips prior to the U2 product line, + * the WIDEODD S/G segment feature does not + * work during scsi->HostBus transfers. + */ + AHC_TMODE_WIDEODD_BUG = 0x01, + /* + * On the aic7890/91 Rev 0 chips, the autoflush + * feature does not work. A manual flush of + * the DMA FIFO is required. + */ + AHC_AUTOFLUSH_BUG = 0x02, + /* + * On many chips, cacheline streaming does not work. + */ + AHC_CACHETHEN_BUG = 0x04, + /* + * On the aic7896/97 chips, cacheline + * streaming must be enabled. + */ + AHC_CACHETHEN_DIS_BUG = 0x08, + /* + * PCI 2.1 Retry failure on non-empty data fifo. + */ + AHC_PCI_2_1_RETRY_BUG = 0x10, + /* + * Controller does not handle cacheline residuals + * properly on S/G segments if PCI MWI instructions + * are allowed. + */ + AHC_PCI_MWI_BUG = 0x20, + /* + * An SCB upload using the SCB channel's + * auto array entry copy feature may + * corrupt data. This appears to only + * occur on 66MHz systems. + */ + AHC_SCBCHAN_UPLOAD_BUG = 0x40 +} ahc_bug; + +/* + * Configuration specific settings. + * The driver determines these settings by probing the + * chip/controller's configuration. + */ +typedef enum { + AHC_FNONE = 0x000, + AHC_PRIMARY_CHANNEL = 0x003,/* + * The channel that should + * be probed first. + */ + AHC_USEDEFAULTS = 0x004,/* + * For cards without an seeprom + * or a BIOS to initialize the chip's + * SRAM, we use the default target + * settings. + */ + AHC_SEQUENCER_DEBUG = 0x008, + AHC_SHARED_SRAM = 0x010, + AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ + AHC_RESET_BUS_A = 0x040, + AHC_RESET_BUS_B = 0x080, + AHC_EXTENDED_TRANS_A = 0x100, + AHC_EXTENDED_TRANS_B = 0x200, + AHC_TERM_ENB_A = 0x400, + AHC_TERM_ENB_B = 0x800, + AHC_INITIATORROLE = 0x1000,/* + * Allow initiator operations on + * this controller. + */ + AHC_TARGETROLE = 0x2000,/* + * Allow target operations on this + * controller. + */ + AHC_NEWEEPROM_FMT = 0x4000, + AHC_RESOURCE_SHORTAGE = 0x8000, + AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */ + AHC_INT50_SPEEDFLEX = 0x20000,/* + * Internal 50pin connector + * sits behind an aic3860 + */ + AHC_SCB_BTT = 0x40000,/* + * The busy targets table is + * stored in SCB space rather + * than SRAM. + */ + AHC_BIOS_ENABLED = 0x80000, + AHC_ALL_INTERRUPTS = 0x100000, + AHC_PAGESCBS = 0x400000, /* Enable SCB paging */ + AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */ + AHC_39BIT_ADDRESSING = 0x1000000 /* Use 39 bit addressing scheme. */ +} ahc_flag; + +/************************* Hardware SCB Definition ***************************/ + +/* + * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB + * consists of a "hardware SCB" mirroring the fields availible on the card + * and additional information the kernel stores for each transaction. + * + * To minimize space utilization, a portion of the hardware scb stores + * different data during different portions of a SCSI transaction. + * As initialized by the host driver for the initiator role, this area + * contains the SCSI cdb (or a pointer to the cdb) to be executed. After + * the cdb has been presented to the target, this area serves to store + * residual transfer information and the SCSI status byte. + * For the target role, the contents of this area do not change, but + * still serve a different purpose than for the initiator role. See + * struct target_data for details. + */ + +/* + * Status information embedded in the shared poriton of + * an SCB after passing the cdb to the target. The kernel + * driver will only read this data for transactions that + * complete abnormally (non-zero status byte). + */ +struct status_pkt { + uint32_t residual_datacnt; /* Residual in the current S/G seg */ + uint32_t residual_sg_ptr; /* The next S/G for this transfer */ + uint8_t scsi_status; /* Standard SCSI status byte */ +}; + +/* + * Target mode version of the shared data SCB segment. + */ +struct target_data { + uint8_t target_phases; /* Bitmap of phases to execute */ + uint8_t data_phase; /* Data-In or Data-Out */ + uint8_t scsi_status; /* SCSI status to give to initiator */ + uint8_t initiator_tag; /* Initiator's transaction tag */ +}; + +struct hardware_scb { +/*0*/ union { + /* + * If the cdb is 12 bytes or less, we embed it directly + * in the SCB. For longer cdbs, we embed the address + * of the cdb payload as seen by the chip and a DMA + * is used to pull it in. + */ + uint8_t cdb[12]; + uint32_t cdb_ptr; + struct status_pkt status; + struct target_data tdata; + } shared_data; +/* + * A word about residuals. + * The scb is presented to the sequencer with the dataptr and datacnt + * fields initialized to the contents of the first S/G element to + * transfer. The sgptr field is initialized to the bus address for + * the S/G element that follows the first in the in core S/G array + * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid + * S/G entry for this transfer (single S/G element transfer with the + * first elements address and length preloaded in the dataptr/datacnt + * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. + * The SG_FULL_RESID flag ensures that the residual will be correctly + * noted even if no data transfers occur. Once the data phase is entered, + * the residual sgptr and datacnt are loaded from the sgptr and the + * datacnt fields. After each S/G element's dataptr and length are + * loaded into the hardware, the residual sgptr is advanced. After + * each S/G element is expired, its datacnt field is checked to see + * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the + * residual sg ptr and the transfer is considered complete. If the + * sequencer determines that there is a residual in the tranfer, it + * will set the SG_RESID_VALID flag in sgptr and dma the scb back into + * host memory. To sumarize: + * + * Sequencer: + * o A residual has occurred if SG_FULL_RESID is set in sgptr, + * or residual_sgptr does not have SG_LIST_NULL set. + * + * o We are transfering the last segment if residual_datacnt has + * the SG_LAST_SEG flag set. + * + * Host: + * o A residual has occurred if a completed scb has the + * SG_RESID_VALID flag set. + * + * o residual_sgptr and sgptr refer to the "next" sg entry + * and so may point beyond the last valid sg entry for the + * transfer. + */ +/*12*/ uint32_t dataptr; +/*16*/ uint32_t datacnt; /* + * Byte 3 (numbered from 0) of + * the datacnt is really the + * 4th byte in that data address. + */ +/*20*/ uint32_t sgptr; +#define SG_PTR_MASK 0xFFFFFFF8 +/*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */ +/*25*/ uint8_t scsiid; /* what to load in the SCSIID register */ +/*26*/ uint8_t lun; +/*27*/ uint8_t tag; /* + * Index into our kernel SCB array. + * Also used as the tag for tagged I/O + */ +/*28*/ uint8_t cdb_len; +/*29*/ uint8_t scsirate; /* Value for SCSIRATE register */ +/*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */ +/*31*/ uint8_t next; /* + * Used for threading SCBs in the + * "Waiting for Selection" and + * "Disconnected SCB" lists down + * in the sequencer. + */ +/*32*/ uint8_t cdb32[32]; /* + * CDB storage for cdbs of size + * 13->32. We store them here + * because hardware scbs are + * allocated from DMA safe + * memory so we are guaranteed + * the controller can access + * this data. + */ +}; + +/************************ Kernel SCB Definitions ******************************/ +/* + * Some fields of the SCB are OS dependent. Here we collect the + * definitions for elements that all OS platforms need to include + * in there SCB definition. + */ + +/* + * Definition of a scatter/gather element as transfered to the controller. + * The aic7xxx chips only support a 24bit length. We use the top byte of + * the length to store additional address bits and a flag to indicate + * that a given segment terminates the transfer. This gives us an + * addressable range of 512GB on machines with 64bit PCI or with chips + * that can support dual address cycles on 32bit PCI busses. + */ +struct ahc_dma_seg { + uint32_t addr; + uint32_t len; +#define AHC_DMA_LAST_SEG 0x80000000 +#define AHC_SG_HIGH_ADDR_MASK 0x7F000000 +#define AHC_SG_LEN_MASK 0x00FFFFFF +}; + +struct sg_map_node { + bus_dmamap_t sg_dmamap; + bus_addr_t sg_physaddr; + struct ahc_dma_seg* sg_vaddr; + SLIST_ENTRY(sg_map_node) links; +#ifdef __OpenBSD__ + bus_dma_segment_t sg_dmasegs; + int sg_nseg; +#endif +}; + +/* + * The current state of this SCB. + */ +typedef enum { + SCB_FREE = 0x0000, + SCB_OTHERTCL_TIMEOUT = 0x0002,/* + * Another device was active + * during the first timeout for + * this SCB so we gave ourselves + * an additional timeout period + * in case it was hogging the + * bus. + */ + SCB_DEVICE_RESET = 0x0004, + SCB_SENSE = 0x0008, + SCB_CDB32_PTR = 0x0010, + SCB_RECOVERY_SCB = 0x0020, + SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */ + SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */ + SCB_ABORT = 0x1000, + SCB_UNTAGGEDQ = 0x2000, + SCB_ACTIVE = 0x4000, + SCB_TARGET_IMMEDIATE = 0x8000 +} scb_flag; + +struct scb { + struct hardware_scb *hscb; + union { + SLIST_ENTRY(scb) sle; + TAILQ_ENTRY(scb) tqe; + } links; + LIST_ENTRY(scb) pending_links; + ahc_io_ctx_t io_ctx; + struct ahc_softc *ahc_softc; + scb_flag flags; +#ifndef __linux__ + bus_dmamap_t dmamap; +#endif + struct scb_platform_data *platform_data; + struct sg_map_node *sg_map; + struct ahc_dma_seg *sg_list; + bus_addr_t sg_list_phys; + u_int sg_count;/* How full ahc_dma_seg is */ +}; + +struct scb_data { + SLIST_HEAD(, scb) free_scbs; /* + * Pool of SCBs ready to be assigned + * commands to execute. + */ + struct scb *scbindex[AHC_SCB_MAX + 1];/* Mapping from tag to SCB */ + struct hardware_scb *hscbs; /* Array of hardware SCBs */ + struct scb *scbarray; /* Array of kernel SCBs */ + struct scsi_sense_data *sense; /* Per SCB sense data */ + + /* + * "Bus" addresses of our data structures. + */ + bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ + bus_dmamap_t hscb_dmamap; + bus_addr_t hscb_busaddr; +#ifdef __OpenBSD__ + bus_dma_segment_t hscb_seg; + int hscb_nseg; + int hscb_size; +#endif + bus_dma_tag_t sense_dmat; + bus_dmamap_t sense_dmamap; + bus_addr_t sense_busaddr; +#ifdef __OpenBSD__ + bus_dma_segment_t sense_seg; + int sense_nseg; + int sense_size; +#endif + bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ + SLIST_HEAD(, sg_map_node) sg_maps; + uint8_t numscbs; + uint8_t maxhscbs; /* Number of SCBs on the card */ + uint8_t init_level; /* + * How far we've initialized + * this structure. + */ +}; + +/************************ Target Mode Definitions *****************************/ + +/* + * Connection desciptor for select-in requests in target mode. + */ +struct target_cmd { + uint8_t scsiid; /* Our ID and the initiator's ID */ + uint8_t identify; /* Identify message */ + uint8_t bytes[22]; /* + * Bytes contains any additional message + * bytes terminated by 0xFF. The remainder + * is the cdb to execute. + */ + uint8_t cmd_valid; /* + * When a command is complete, the firmware + * will set cmd_valid to all bits set. + * After the host has seen the command, + * the bits are cleared. This allows us + * to just peek at host memory to determine + * if more work is complete. cmd_valid is on + * an 8 byte boundary to simplify setting + * it on aic7880 hardware which only has + * limited direct access to the DMA FIFO. + */ + uint8_t pad[7]; +}; + +/* + * Number of events we can buffer up if we run out + * of immediate notify ccbs. + */ +#define AHC_TMODE_EVENT_BUFFER_SIZE 8 +struct ahc_tmode_event { + uint8_t initiator_id; + uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ +#define EVENT_TYPE_BUS_RESET 0xFF + uint8_t event_arg; +}; + +/* + * Per enabled lun target mode state. + * As this state is directly influenced by the host OS'es target mode + * environment, we let the OS module define it. Forward declare the + * structure here so we can store arrays of them, etc. in OS neutral + * data structures. + */ +#ifdef AHC_TARGET_MODE +struct ahc_tmode_lstate { + struct cam_path *path; + struct ccb_hdr_slist accept_tios; + struct ccb_hdr_slist immed_notifies; + struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; + uint8_t event_r_idx; + uint8_t event_w_idx; +}; +#else +struct ahc_tmode_lstate; +#endif + +/******************** Transfer Negotiation Datastructures *********************/ +#define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ +#define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ +#define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ +#define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ + +/* + * Transfer Negotiation Information. + */ +struct ahc_transinfo { + uint8_t protocol_version; /* SCSI Revision level */ + uint8_t transport_version; /* SPI Revision level */ + uint8_t width; /* Bus width */ + uint8_t period; /* Sync rate factor */ + uint8_t offset; /* Sync offset */ + uint8_t ppr_options; /* Parallel Protocol Request options */ +}; + +/* + * Per-initiator current, goal and user transfer negotiation information. */ +struct ahc_initiator_tinfo { + uint8_t scsirate; /* Computed value for SCSIRATE reg */ + struct ahc_transinfo curr; + struct ahc_transinfo goal; + struct ahc_transinfo user; +}; + +/* + * Per enabled target ID state. + * Pointers to lun target state as well as sync/wide negotiation information + * for each initiator<->target mapping. For the initiator role we pretend + * that we are the target and the targets are the initiators since the + * negotiation is the same regardless of role. + */ +struct ahc_tmode_tstate { + struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS]; + struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS]; + + /* + * Per initiator state bitmasks. + */ + uint16_t auto_negotiate;/* Auto Negotiation Required */ + uint16_t ultraenb; /* Using ultra sync rate */ + uint16_t discenable; /* Disconnection allowed */ + uint16_t tagenable; /* Tagged Queuing allowed */ +}; + +/* + * Data structure for our table of allowed synchronous transfer rates. + */ +struct ahc_syncrate { + u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */ + u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */ +#define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */ +#define ST_SXFR 0x010 /* Rate Single Transition Only */ +#define DT_SXFR 0x040 /* Rate Double Transition Only */ + uint8_t period; /* Period to send to SCSI target */ + char *rate; +}; + +/* + * The synchronouse transfer rate table. + */ +extern struct ahc_syncrate ahc_syncrates[]; + +/* + * Indexes into our table of syncronous transfer rates. + */ +#define AHC_SYNCRATE_DT 0 +#define AHC_SYNCRATE_ULTRA2 1 +#define AHC_SYNCRATE_ULTRA 3 +#define AHC_SYNCRATE_FAST 6 + +/***************************** Lookup Tables **********************************/ +/* + * Phase -> name and message out response + * to parity errors in each phase table. + */ +struct ahc_phase_table_entry { + uint8_t phase; + uint8_t mesg_out; /* Message response to parity errors */ + char *phasemsg; +}; + +/************************** Serial EEPROM Format ******************************/ + +struct seeprom_config { +/* + * Per SCSI ID Configuration Flags + */ + uint16_t device_flags[16]; /* words 0-15 */ +#define CFXFER 0x0007 /* synchronous transfer rate */ +#define CFSYNCH 0x0008 /* enable synchronous transfer */ +#define CFDISC 0x0010 /* enable disconnection */ +#define CFWIDEB 0x0020 /* wide bus device */ +#define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ +#define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ +#define CFSTART 0x0100 /* send start unit SCSI command */ +#define CFINCBIOS 0x0200 /* include in BIOS scan */ +#define CFRNFOUND 0x0400 /* report even if not found */ +#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ +#define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ +#define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ + +/* + * BIOS Control Bits + */ + uint16_t bios_control; /* word 16 */ +#define CFSUPREM 0x0001 /* support all removeable drives */ +#define CFSUPREMB 0x0002 /* support removeable boot drives */ +#define CFBIOSEN 0x0004 /* BIOS enabled */ +#define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */ +#define CFSM2DRV 0x0010 /* support more than two drives */ +#define CFSTPWLEVEL 0x0010 /* Termination level control */ +#define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ +#define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ +#define CFTERM_MENU 0x0040 /* BIOS displays termination menu */ +#define CFEXTEND 0x0080 /* extended translation enabled */ +#define CFSCAMEN 0x0100 /* SCAM enable */ +#define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ +#define CFMSG_VERBOSE 0x0000 +#define CFMSG_SILENT 0x0200 +#define CFMSG_DIAG 0x0400 +#define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */ +/* UNUSED 0xff00 */ + +/* + * Host Adapter Control Bits + */ + uint16_t adapter_control; /* word 17 */ +#define CFAUTOTERM 0x0001 /* Perform Auto termination */ +#define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ +#define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ +#define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ +#define CFSTERM 0x0004 /* SCSI low byte termination */ +#define CFWSTERM 0x0008 /* SCSI high byte termination */ +#define CFSPARITY 0x0010 /* SCSI parity */ +#define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ +#define CFMULTILUN 0x0020 +#define CFRESETB 0x0040 /* reset SCSI bus at boot */ +#define CFCLUSTERENB 0x0080 /* Cluster Enable */ +#define CFBOOTCHAN 0x0300 /* probe this channel first */ +#define CFBOOTCHANSHIFT 8 +#define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/ +#define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */ +#define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */ +#define CFDOMAINVAL 0x4000 /* Perform Domain Validation*/ + +/* + * Bus Release Time, Host Adapter ID + */ + uint16_t brtime_id; /* word 18 */ +#define CFSCSIID 0x000f /* host adapter SCSI ID */ +/* UNUSED 0x00f0 */ +#define CFBRTIME 0xff00 /* bus release time */ + +/* + * Maximum targets + */ + uint16_t max_targets; /* word 19 */ +#define CFMAXTARG 0x00ff /* maximum targets */ +#define CFBOOTLUN 0x0f00 /* Lun to boot from */ +#define CFBOOTID 0xf000 /* Target to boot from */ + uint16_t res_1[10]; /* words 20-29 */ + uint16_t signature; /* Signature == 0x250 */ +#define CFSIGNATURE 0x250 +#define CFSIGNATURE2 0x300 + uint16_t checksum; /* word 31 */ +}; + +/**************************** Message Buffer *********************************/ +typedef enum { + MSG_TYPE_NONE = 0x00, + MSG_TYPE_INITIATOR_MSGOUT = 0x01, + MSG_TYPE_INITIATOR_MSGIN = 0x02, + MSG_TYPE_TARGET_MSGOUT = 0x03, + MSG_TYPE_TARGET_MSGIN = 0x04 +} ahc_msg_type; + +typedef enum { + MSGLOOP_IN_PROG, + MSGLOOP_MSGCOMPLETE, + MSGLOOP_TERMINATED +} msg_loop_stat; + +/*********************** Software Configuration Structure *********************/ +TAILQ_HEAD(scb_tailq, scb); + +struct ahc_suspend_channel_state { + uint8_t scsiseq; + uint8_t sxfrctl0; + uint8_t sxfrctl1; + uint8_t simode0; + uint8_t simode1; + uint8_t seltimer; + uint8_t seqctl; +}; + +struct ahc_suspend_state { + struct ahc_suspend_channel_state channel[2]; + uint8_t optionmode; + uint8_t dscommand0; + uint8_t dspcistatus; + /* hsmailbox */ + uint8_t crccontrol1; + uint8_t scbbaddr; + /* Host and sequencer SCB counts */ + uint8_t dff_thrsh; + uint8_t *scratch_ram; + uint8_t *btt; +}; + +typedef void (*ahc_bus_intr_t)(struct ahc_softc *); + +struct ahc_softc { +#ifdef __OpenBSD__ + struct device sc_dev; +#endif + bus_space_tag_t tag; + bus_space_handle_t bsh; +#ifndef __linux__ + bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ +#endif + struct scb_data *scb_data; + + struct scb *next_queued_scb; + + /* + * SCBs that have been sent to the controller + */ + LIST_HEAD(, scb) pending_scbs; + + /* + * Counting lock for deferring the release of additional + * untagged transactions from the untagged_queues. When + * the lock is decremented to 0, all queues in the + * untagged_queues array are run. + */ + u_int untagged_queue_lock; + + /* + * Per-target queue of untagged-transactions. The + * transaction at the head of the queue is the + * currently pending untagged transaction for the + * target. The driver only allows a single untagged + * transaction per target. + */ + struct scb_tailq untagged_queues[AHC_NUM_TARGETS]; + + /* + * Platform specific data. + */ + struct ahc_platform_data *platform_data; + + /* + * Platform specific device information. + */ + ahc_dev_softc_t dev_softc; + + /* + * Bus specific device information. + */ + ahc_bus_intr_t bus_intr; + + /* + * Target mode related state kept on a per enabled lun basis. + * Targets that are not enabled will have null entries. + * As an initiator, we keep one target entry for our initiator + * ID to store our sync/wide transfer settings. + */ + struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS]; + + /* + * The black hole device responsible for handling requests for + * disabled luns on enabled targets. + */ + struct ahc_tmode_lstate *black_hole; + + /* + * Device instance currently on the bus awaiting a continue TIO + * for a command that was not given the disconnect priveledge. + */ + struct ahc_tmode_lstate *pending_device; + + /* + * Card characteristics + */ + ahc_chip chip; + ahc_feature features; + ahc_bug bugs; + ahc_flag flags; + + /* Values to store in the SEQCTL register for pause and unpause */ + uint8_t unpause; + uint8_t pause; + + /* Command Queues */ + uint8_t qoutfifonext; + uint8_t qinfifonext; + uint8_t *qoutfifo; + uint8_t *qinfifo; + + /* Critical Section Data */ + struct cs *critical_sections; + u_int num_critical_sections; + + /* Links for chaining softcs */ + TAILQ_ENTRY(ahc_softc) links; + + /* Channel Names ('A', 'B', etc.) */ + char channel; + char channel_b; + + /* Initiator Bus ID */ + uint8_t our_id; + uint8_t our_id_b; + + /* + * PCI error detection. + */ + int unsolicited_ints; + + /* + * Target incoming command FIFO. + */ + struct target_cmd *targetcmds; + uint8_t tqinfifonext; + + /* + * Incoming and outgoing message handling. + */ + uint8_t send_msg_perror; + ahc_msg_type msg_type; + uint8_t msgout_buf[12];/* Message we are sending */ + uint8_t msgin_buf[12];/* Message we are receiving */ + u_int msgout_len; /* Length of message to send */ + u_int msgout_index; /* Current index in msgout */ + u_int msgin_index; /* Current index in msgin */ + + /* + * Mapping information for data structures shared + * between the sequencer and kernel. + */ + bus_dma_tag_t parent_dmat; + bus_dma_tag_t shared_data_dmat; + bus_dmamap_t shared_data_dmamap; + bus_addr_t shared_data_busaddr; + + /* + * Bus address of the one byte buffer used to + * work-around a DMA bug for chips <= aic7880 + * in target mode. + */ + bus_addr_t dma_bug_buf; + + /* Information saved through suspend/resume cycles */ + struct ahc_suspend_state suspend_state; + + /* Number of enabled target mode device on this card */ + u_int enabled_luns; + + /* Initialization level of this data structure */ + u_int init_level; + + /* PCI cacheline size. */ + u_int pci_cachesize; + + /* Per-Unit descriptive information */ + const char *description; + char *name; + int unit; + + /* Selection Timer settings */ + int seltime; + int seltime_b; + + uint16_t user_discenable;/* Disconnection allowed */ + uint16_t user_tagenable;/* Tagged Queuing allowed */ +}; + +TAILQ_HEAD(ahc_softc_tailq, ahc_softc); +extern struct ahc_softc_tailq ahc_tailq; + +/************************ Active Device Information ***************************/ +typedef enum { + ROLE_UNKNOWN, + ROLE_INITIATOR, + ROLE_TARGET +} role_t; + +struct ahc_devinfo { + int our_scsiid; + int target_offset; + uint16_t target_mask; + u_int target; + u_int lun; + char channel; + role_t role; /* + * Only guaranteed to be correct if not + * in the busfree state. + */ +}; + +/****************************** PCI Structures ********************************/ +typedef int (ahc_device_setup_t)(struct ahc_softc *); + +struct ahc_pci_identity { + uint64_t full_id; + uint64_t id_mask; + char *name; + ahc_device_setup_t *setup; +}; +extern struct ahc_pci_identity ahc_pci_ident_table []; +extern const u_int ahc_num_pci_devs; + +/***************************** VL/EISA Declarations ***************************/ +struct aic7770_identity { + uint32_t full_id; + uint32_t id_mask; + char *name; + ahc_device_setup_t *setup; +}; +extern struct aic7770_identity aic7770_ident_table []; +extern const int ahc_num_aic7770_devs; + +#define AHC_EISA_SLOT_OFFSET 0xc00 +#define AHC_EISA_IOSIZE 0x100 + +/*************************** Function Declarations ****************************/ +/******************************************************************************/ +u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl); +void ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl); +void ahc_busy_tcl(struct ahc_softc *ahc, + u_int tcl, u_int busyid); + +/***************************** PCI Front End *********************************/ +struct ahc_pci_identity *ahc_find_pci_device(ahc_dev_softc_t); +int ahc_pci_config(struct ahc_softc *, + struct ahc_pci_identity *); + +/*************************** EISA/VL Front End ********************************/ +struct aic7770_identity *aic7770_find_device(uint32_t); +int aic7770_config(struct ahc_softc *ahc, + struct aic7770_identity *); + +/************************** SCB and SCB queue management **********************/ +int ahc_probe_scbs(struct ahc_softc *); +void ahc_run_untagged_queues(struct ahc_softc *ahc); +void ahc_run_untagged_queue(struct ahc_softc *ahc, + struct scb_tailq *queue); +void ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, + struct scb *scb); +int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, + int target, char channel, int lun, + u_int tag, role_t role); + +/****************************** Initialization ********************************/ +struct ahc_softc *ahc_alloc(void *platform_arg, char *name); +int ahc_softc_init(struct ahc_softc *); +void ahc_controller_info(struct ahc_softc *ahc, char *buf); +int ahc_init(struct ahc_softc *ahc); +void ahc_intr_enable(struct ahc_softc *ahc, int enable); +void ahc_pause_and_flushwork(struct ahc_softc *ahc); +int ahc_suspend(struct ahc_softc *ahc); +int ahc_resume(struct ahc_softc *ahc); +void ahc_softc_insert(struct ahc_softc *); +void ahc_set_unit(struct ahc_softc *, int); +void ahc_set_name(struct ahc_softc *, char *); +void ahc_alloc_scbs(struct ahc_softc *ahc); +void ahc_free(struct ahc_softc *ahc); +int ahc_reset(struct ahc_softc *ahc); +void ahc_shutdown(void *arg); + +/*************************** Interrupt Services *******************************/ +#ifdef __OpenBSD__ +int ahc_pci_intr(struct ahc_softc *ahc); +#else +void ahc_pci_intr(struct ahc_softc *ahc); +#endif +void ahc_clear_intstat(struct ahc_softc *ahc); +void ahc_run_qoutfifo(struct ahc_softc *ahc); +#ifdef AHC_TARGET_MODE +void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused); +#endif +void ahc_handle_brkadrint(struct ahc_softc *ahc); +void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); +void ahc_handle_scsiint(struct ahc_softc *ahc, + u_int intstat); +void ahc_clear_critical_section(struct ahc_softc *ahc); + +/***************************** Error Recovery *********************************/ +typedef enum { + SEARCH_COMPLETE, + SEARCH_COUNT, + SEARCH_REMOVE +} ahc_search_action; +int ahc_search_qinfifo(struct ahc_softc *ahc, int target, + char channel, int lun, u_int tag, + role_t role, uint32_t status, + ahc_search_action action); +int ahc_search_disc_list(struct ahc_softc *ahc, int target, + char channel, int lun, u_int tag, + int stop_on_first, int remove, + int save_state); +void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb); +int ahc_reset_channel(struct ahc_softc *ahc, char channel, + int initiate_reset); +void ahc_restart(struct ahc_softc *ahc); +void ahc_calc_residual(struct scb *scb); +/*************************** Utility Functions ********************************/ +struct ahc_phase_table_entry* + ahc_lookup_phase_entry(int phase); +void ahc_compile_devinfo(struct ahc_devinfo *devinfo, + u_int our_id, u_int target, + u_int lun, char channel, + role_t role); +/************************** Transfer Negotiation ******************************/ +struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, + u_int *ppr_options, u_int maxsync); +u_int ahc_find_period(struct ahc_softc *ahc, + u_int scsirate, u_int maxsync); +void ahc_validate_offset(struct ahc_softc *ahc, + struct ahc_initiator_tinfo *tinfo, + struct ahc_syncrate *syncrate, + u_int *offset, int wide, + role_t role); +void ahc_validate_width(struct ahc_softc *ahc, + struct ahc_initiator_tinfo *tinfo, + u_int *bus_width, + role_t role); +int ahc_update_neg_request(struct ahc_softc*, + struct ahc_devinfo*, + struct ahc_tmode_tstate*, + struct ahc_initiator_tinfo*, + int /*force*/); +void ahc_set_width(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo, + u_int width, u_int type, int paused); +void ahc_set_syncrate(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo, + struct ahc_syncrate *syncrate, + u_int period, u_int offset, + u_int ppr_options, + u_int type, int paused); +typedef enum { + AHC_QUEUE_NONE, + AHC_QUEUE_BASIC, + AHC_QUEUE_TAGGED +} ahc_queue_alg; + +void ahc_set_tags(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo, + ahc_queue_alg alg); + +/**************************** Target Mode *************************************/ +#ifdef AHC_TARGET_MODE +void ahc_send_lstate_events(struct ahc_softc *, + struct ahc_tmode_lstate *); +void ahc_handle_en_lun(struct ahc_softc *ahc, + struct cam_sim *sim, union ccb *ccb); +cam_status ahc_find_tmode_devs(struct ahc_softc *ahc, + struct cam_sim *sim, union ccb *ccb, + struct ahc_tmode_tstate **tstate, + struct ahc_tmode_lstate **lstate, + int notfound_failure); +#ifndef AHC_TMODE_ENABLE +#define AHC_TMODE_ENABLE 0 +#endif +#endif +/******************************* Debug ***************************************/ +void ahc_print_scb(struct scb *scb); +void ahc_dump_card_state(struct ahc_softc *ahc); +#endif /* _AIC7XXX_H_ */ + diff --git a/sys/dev/ic/aic7xxx_inline.h b/sys/dev/ic/aic7xxx_inline.h new file mode 100644 index 00000000000..6f84f2ec548 --- /dev/null +++ b/sys/dev/ic/aic7xxx_inline.h @@ -0,0 +1,561 @@ +/* + * Inline routines shareable across OS platforms. + * + * Copyright (c) 1994-2001 Justin T. Gibbs. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU Public License ("GPL"). + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id: aic7xxx_inline.h,v 1.3 2002/06/28 00:34:54 smurph Exp $ + * + * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx_inline.h,v 1.17 2001/07/18 21:39:47 gibbs Exp $ + */ + +#ifndef _AIC7XXX_INLINE_H_ +#define _AIC7XXX_INLINE_H_ + +/************************* Sequencer Execution Control ************************/ +static __inline void ahc_pause_bug_fix(struct ahc_softc *ahc); +static __inline int ahc_is_paused(struct ahc_softc *ahc); +static __inline void ahc_pause(struct ahc_softc *ahc); +static __inline void ahc_unpause(struct ahc_softc *ahc); + +/* + * Work around any chip bugs related to halting sequencer execution. + * On Ultra2 controllers, we must clear the CIOBUS stretch signal by + * reading a register that will set this signal and deassert it. + * Without this workaround, if the chip is paused, by an interrupt or + * manual pause while accessing scb ram, accesses to certain registers + * will hang the system (infinite pci retries). + */ +static __inline void +ahc_pause_bug_fix(struct ahc_softc *ahc) +{ + if ((ahc->features & AHC_ULTRA2) != 0) + (void)ahc_inb(ahc, CCSCBCTL); +} + +/* + * Determine whether the sequencer has halted code execution. + * Returns non-zero status if the sequencer is stopped. + */ +static __inline int +ahc_is_paused(struct ahc_softc *ahc) +{ + return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); +} + +/* + * Request that the sequencer stop and wait, indefinitely, for it + * to stop. The sequencer will only acknowledge that it is paused + * once it has reached an instruction boundary and PAUSEDIS is + * cleared in the SEQCTL register. The sequencer may use PAUSEDIS + * for critical sections. + */ +static __inline void +ahc_pause(struct ahc_softc *ahc) +{ + ahc_outb(ahc, HCNTRL, ahc->pause); + + /* + * Since the sequencer can disable pausing in a critical section, we + * must loop until it actually stops. + */ + while (ahc_is_paused(ahc) == 0) + ; + + ahc_pause_bug_fix(ahc); +} + +/* + * Allow the sequencer to continue program execution. + * We check here to ensure that no additional interrupt + * sources that would cause the sequencer to halt have been + * asserted. If, for example, a SCSI bus reset is detected + * while we are fielding a different, pausing, interrupt type, + * we don't want to release the sequencer before going back + * into our interrupt handler and dealing with this new + * condition. + */ +static __inline void +ahc_unpause(struct ahc_softc *ahc) +{ + if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) + ahc_outb(ahc, HCNTRL, ahc->unpause); +} + +/*********************** Untagged Transaction Routines ************************/ +static __inline void ahc_freeze_untagged_queues(struct ahc_softc *ahc); +static __inline void ahc_release_untagged_queues(struct ahc_softc *ahc); + +/* + * Block our completion routine from starting the next untagged + * transaction for this target or target lun. + */ +static __inline void +ahc_freeze_untagged_queues(struct ahc_softc *ahc) +{ + if ((ahc->flags & AHC_SCB_BTT) == 0) + ahc->untagged_queue_lock++; +} + +/* + * Allow the next untagged transaction for this target or target lun + * to be executed. We use a counting semaphore to allow the lock + * to be acquired recursively. Once the count drops to zero, the + * transaction queues will be run. + */ +static __inline void +ahc_release_untagged_queues(struct ahc_softc *ahc) +{ + if ((ahc->flags & AHC_SCB_BTT) == 0) { + ahc->untagged_queue_lock--; + if (ahc->untagged_queue_lock == 0) + ahc_run_untagged_queues(ahc); + } +} + +/************************** Memory mapping routines ***************************/ +static __inline struct ahc_dma_seg * + ahc_sg_bus_to_virt(struct scb *scb, + uint32_t sg_busaddr); +static __inline uint32_t + ahc_sg_virt_to_bus(struct scb *scb, + struct ahc_dma_seg *sg); +static __inline uint32_t + ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index); +static __inline void ahc_sync_scb(struct ahc_softc *ahc, + struct scb *scb, int op); +static __inline void ahc_sync_sglist(struct ahc_softc *ahc, + struct scb *scb, int op); +static __inline uint32_t + ahc_targetcmd_offset(struct ahc_softc *ahc, + u_int index); + +static __inline struct ahc_dma_seg * +ahc_sg_bus_to_virt(struct scb *scb, uint32_t sg_busaddr) +{ + int sg_index; + + sg_index = (sg_busaddr - scb->sg_list_phys)/sizeof(struct ahc_dma_seg); + /* sg_list_phys points to entry 1, not 0 */ + sg_index++; + + return (&scb->sg_list[sg_index]); +} + +static __inline uint32_t +ahc_sg_virt_to_bus(struct scb *scb, struct ahc_dma_seg *sg) +{ + int sg_index; + + /* sg_list_phys points to entry 1, not 0 */ + sg_index = sg - &scb->sg_list[1]; + + return (scb->sg_list_phys + (sg_index * sizeof(*scb->sg_list))); +} + +static __inline uint32_t +ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) +{ + return (ahc->scb_data->hscb_busaddr + + (sizeof(struct hardware_scb) * index)); +} + +static __inline void +ahc_sync_scb(struct ahc_softc *ahc, struct scb *scb, int op) +{ + ahc_dmamap_sync(ahc, ahc->scb_data->hscb_dmat, + ahc->scb_data->hscb_dmamap, + /*offset*/(scb->hscb - ahc->scb_data->hscbs) * sizeof(*scb->hscb), + /*len*/sizeof(*scb->hscb), op); +} + +static __inline void +ahc_sync_sglist(struct ahc_softc *ahc, struct scb *scb, int op) +{ + if (scb->sg_count == 0) + return; + + ahc_dmamap_sync(ahc, ahc->scb_data->sg_dmat, scb->sg_map->sg_dmamap, + /*offset*/(scb->sg_list - scb->sg_map->sg_vaddr) + * sizeof(struct ahc_dma_seg), + /*len*/sizeof(struct ahc_dma_seg) * scb->sg_count, op); +} + +static __inline uint32_t +ahc_targetcmd_offset(struct ahc_softc *ahc, u_int index) +{ + return (((uint8_t *)&ahc->targetcmds[index]) - ahc->qoutfifo); +} + +/******************************** Debugging ***********************************/ +static __inline char *ahc_name(struct ahc_softc *ahc); + +static __inline char * +ahc_name(struct ahc_softc *ahc) +{ + return (ahc->name); +} + +/*********************** Miscelaneous Support Functions ***********************/ + +static __inline void ahc_update_residual(struct scb *scb); +static __inline struct ahc_initiator_tinfo * + ahc_fetch_transinfo(struct ahc_softc *ahc, + char channel, u_int our_id, + u_int remote_id, + struct ahc_tmode_tstate **tstate); +static __inline struct scb* + ahc_get_scb(struct ahc_softc *ahc); +static __inline void ahc_free_scb(struct ahc_softc *ahc, struct scb *scb); +static __inline void ahc_swap_with_next_hscb(struct ahc_softc *ahc, + struct scb *scb); +static __inline void ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb); +static __inline struct scsi_sense_data * + ahc_get_sense_buf(struct ahc_softc *ahc, + struct scb *scb); +static __inline uint32_t + ahc_get_sense_bufaddr(struct ahc_softc *ahc, + struct scb *scb); + +/* + * Determine whether the sequencer reported a residual + * for this SCB/transaction. + */ +static __inline void +ahc_update_residual(struct scb *scb) +{ + uint32_t sgptr; + + sgptr = ahc_le32toh(scb->hscb->sgptr); + if ((sgptr & SG_RESID_VALID) != 0) + ahc_calc_residual(scb); +} + +/* + * Return pointers to the transfer negotiation information + * for the specified our_id/remote_id pair. + */ +static __inline struct ahc_initiator_tinfo * +ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, + u_int remote_id, struct ahc_tmode_tstate **tstate) +{ + /* + * Transfer data structures are stored from the perspective + * of the target role. Since the parameters for a connection + * in the initiator role to a given target are the same as + * when the roles are reversed, we pretend we are the target. + */ + if (channel == 'B') + our_id += 8; + *tstate = ahc->enabled_targets[our_id]; + return (&(*tstate)->transinfo[remote_id]); +} + +/* + * Get a free scb. If there are none, see if we can allocate a new SCB. + */ +static __inline struct scb * +ahc_get_scb(struct ahc_softc *ahc) +{ + struct scb *scb; + + if ((scb = SLIST_FIRST(&ahc->scb_data->free_scbs)) == NULL) { + ahc_alloc_scbs(ahc); + scb = SLIST_FIRST(&ahc->scb_data->free_scbs); + if (scb == NULL) + return (NULL); + } + SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links.sle); + return (scb); +} + +/* + * Return an SCB resource to the free list. + */ +static __inline void +ahc_free_scb(struct ahc_softc *ahc, struct scb *scb) +{ + struct hardware_scb *hscb; + + hscb = scb->hscb; + /* Clean up for the next user */ + ahc->scb_data->scbindex[hscb->tag] = NULL; + scb->flags = SCB_FREE; + hscb->control = 0; + + SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links.sle); + + /* Notify the OSM that a resource is now available. */ + ahc_platform_scb_free(ahc, scb); +} + +static __inline struct scb * +ahc_lookup_scb(struct ahc_softc *ahc, u_int tag) +{ + struct scb* scb; + + scb = ahc->scb_data->scbindex[tag]; + if (scb != NULL) + ahc_sync_scb(ahc, scb, + BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); + return (scb); +} + +static __inline void +ahc_swap_with_next_hscb(struct ahc_softc *ahc, struct scb *scb) +{ + struct hardware_scb *q_hscb; + u_int saved_tag; + + /* + * Our queuing method is a bit tricky. The card + * knows in advance which HSCB to download, and we + * can't disappoint it. To achieve this, the next + * SCB to download is saved off in ahc->next_queued_scb. + * When we are called to queue "an arbitrary scb", + * we copy the contents of the incoming HSCB to the one + * the sequencer knows about, swap HSCB pointers and + * finally assign the SCB to the tag indexed location + * in the scb_array. This makes sure that we can still + * locate the correct SCB by SCB_TAG. + */ + q_hscb = ahc->next_queued_scb->hscb; + saved_tag = q_hscb->tag; + memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb)); + if ((scb->flags & SCB_CDB32_PTR) != 0) { + q_hscb->shared_data.cdb_ptr = + ahc_hscb_busaddr(ahc, q_hscb->tag) + + offsetof(struct hardware_scb, cdb32); + } + q_hscb->tag = saved_tag; + q_hscb->next = scb->hscb->tag; + + /* Now swap HSCB pointers. */ + ahc->next_queued_scb->hscb = scb->hscb; + scb->hscb = q_hscb; + + /* Now define the mapping from tag to SCB in the scbindex */ + ahc->scb_data->scbindex[scb->hscb->tag] = scb; +} + +/* + * Tell the sequencer about a new transaction to execute. + */ +static __inline void +ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb) +{ + ahc_swap_with_next_hscb(ahc, scb); + + if (scb->hscb->tag == SCB_LIST_NULL + || scb->hscb->next == SCB_LIST_NULL) + panic("Attempt to queue invalid SCB tag %x:%x\n", + scb->hscb->tag, scb->hscb->next); + + /* + * Keep a history of SCBs we've downloaded in the qinfifo. + */ + ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; + + /* + * Make sure our data is consistant from the + * perspective of the adapter. + */ + ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); + + /* Tell the adapter about the newly queued SCB */ + if ((ahc->features & AHC_QUEUE_REGS) != 0) { + ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); + } else { + if ((ahc->features & AHC_AUTOPAUSE) == 0) + ahc_pause(ahc); + ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); + if ((ahc->features & AHC_AUTOPAUSE) == 0) + ahc_unpause(ahc); + } +} + +static __inline struct scsi_sense_data * +ahc_get_sense_buf(struct ahc_softc *ahc, struct scb *scb) +{ + int offset; + + offset = scb - ahc->scb_data->scbarray; + return (&ahc->scb_data->sense[offset]); +} + +static __inline uint32_t +ahc_get_sense_bufaddr(struct ahc_softc *ahc, struct scb *scb) +{ + int offset; + + offset = scb - ahc->scb_data->scbarray; + return (ahc->scb_data->sense_busaddr + + (offset * sizeof(struct scsi_sense_data))); +} + +/************************** Interrupt Processing ******************************/ +static __inline void ahc_sync_qoutfifo(struct ahc_softc *ahc, int op); +static __inline void ahc_sync_tqinfifo(struct ahc_softc *ahc, int op); +static __inline u_int ahc_check_cmdcmpltqueues(struct ahc_softc *ahc); +static __inline void ahc_intr(struct ahc_softc *ahc); + +static __inline void +ahc_sync_qoutfifo(struct ahc_softc *ahc, int op) +{ + ahc_dmamap_sync(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap, + /*offset*/0, /*len*/256, op); +} + +static __inline void +ahc_sync_tqinfifo(struct ahc_softc *ahc, int op) +{ +#ifdef AHC_TARGET_MODE + if ((ahc->flags & AHC_TARGETROLE) != 0) { + ahc_dmamap_sync(ahc, ahc->shared_data_dmat, + ahc->shared_data_dmamap, + ahc_targetcmd_offset(ahc, 0), + sizeof(struct target_cmd) * AHC_TMODE_CMDS, + op); + } +#endif +} + +/* + * See if the firmware has posted any completed commands + * into our in-core command complete fifos. + */ +#define AHC_RUN_QOUTFIFO 0x1 +#define AHC_RUN_TQINFIFO 0x2 +static __inline u_int +ahc_check_cmdcmpltqueues(struct ahc_softc *ahc) +{ + u_int retval; + + retval = 0; + ahc_dmamap_sync(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap, + /*offset*/ahc->qoutfifonext, /*len*/1, + BUS_DMASYNC_POSTREAD); + if (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) + retval |= AHC_RUN_QOUTFIFO; +#ifdef AHC_TARGET_MODE + if ((ahc->flags & AHC_TARGETROLE) != 0) { + ahc_dmamap_sync(ahc, ahc->shared_data_dmat, + ahc->shared_data_dmamap, + ahc_targetcmd_offset(ahc, ahc->tqinfifofnext), + /*len*/sizeof(struct target_cmd), + BUS_DMASYNC_POSTREAD); + if (ahc->targetcmds[ahc->tqinfifonext].cmd_valid != 0) + retval |= AHC_RUN_TQINFIFO; + } +#endif + return (retval); +} + +/* + * Catch an interrupt from the adapter + */ +static __inline void +ahc_intr(struct ahc_softc *ahc) +{ + u_int intstat; + u_int queuestat; + + /* + * Instead of directly reading the interrupt status register, + * infer the cause of the interrupt by checking our in-core + * completion queues. This avoids a costly PCI bus read in + * most cases. + */ + if ((ahc->flags & (AHC_ALL_INTERRUPTS|AHC_EDGE_INTERRUPT)) == 0 + && (queuestat = ahc_check_cmdcmpltqueues(ahc)) != 0) + intstat = CMDCMPLT; + else { + intstat = ahc_inb(ahc, INTSTAT); + queuestat = AHC_RUN_QOUTFIFO; +#ifdef AHC_TARGET_MODE + if ((ahc->flags & AHC_TARGETROLE) != 0) + queuestat |= AHC_RUN_TQINFIFO; +#endif + } + + if (intstat & CMDCMPLT) { + ahc_outb(ahc, CLRINT, CLRCMDINT); + + /* + * Ensure that the chip sees that we've cleared + * this interrupt before we walk the output fifo. + * Otherwise, we may, due to posted bus writes, + * clear the interrupt after we finish the scan, + * and after the sequencer has added new entries + * and asserted the interrupt again. + */ + ahc_flush_device_writes(ahc); +#ifdef AHC_TARGET_MODE + if ((queuestat & AHC_RUN_QOUTFIFO) != 0) +#endif + ahc_run_qoutfifo(ahc); +#ifdef AHC_TARGET_MODE + if ((queuestat & AHC_RUN_TQINFIFO) != 0) + ahc_run_tqinfifo(ahc, /*paused*/FALSE); +#endif + } + + if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0) + /* Hot eject */ + return; + + if ((intstat & INT_PEND) == 0) { +#if AHC_PCI_CONFIG > 0 + if (ahc->unsolicited_ints > 500) { + ahc->unsolicited_ints = 0; + if ((ahc->chip & AHC_PCI) != 0 + && (ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0) + ahc->bus_intr(ahc); + } +#endif + ahc->unsolicited_ints++; + return; + } + ahc->unsolicited_ints = 0; + + if (intstat & BRKADRINT) { + ahc_handle_brkadrint(ahc); + /* Fatal error, no more interrupts to handle. */ + return; + } + + if ((intstat & (SEQINT|SCSIINT)) != 0) + ahc_pause_bug_fix(ahc); + + if ((intstat & SEQINT) != 0) + ahc_handle_seqint(ahc, intstat); + + if ((intstat & SCSIINT) != 0) + ahc_handle_scsiint(ahc, intstat); +} + +#endif /* _AIC7XXX_INLINE_H_ */ diff --git a/sys/dev/ic/aic7xxx_openbsd.c b/sys/dev/ic/aic7xxx_openbsd.c new file mode 100644 index 00000000000..7946d938e3f --- /dev/null +++ b/sys/dev/ic/aic7xxx_openbsd.c @@ -0,0 +1,1732 @@ +/* + * Bus independent OpenBSD shim for the aic7xxx based adaptec SCSI controllers + * + * Copyright (c) 1994-2001 Justin T. Gibbs. + * Copyright (c) 2001-2002 Steve Murphree, Jr. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU Public License ("GPL"). + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id: aic7xxx_openbsd.c,v 1.5 2002/06/28 00:34:54 smurph Exp $ + * + * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx_freebsd.c,v 1.26 2001/07/18 21:39:47 gibbs Exp $ + * $OpenBSD: aic7xxx_openbsd.c,v 1.5 2002/06/28 00:34:54 smurph Exp $ + */ + +#include <dev/ic/aic7xxx_openbsd.h> +#include <dev/ic/aic7xxx_inline.h> + +struct cfdriver ahc_cd = { + NULL, "ahc", DV_DULL +}; + +int32_t ahc_action(struct scsi_xfer *xs); +static void ahc_minphys(struct buf *bp); + +static struct scsi_adapter ahc_switch = +{ + ahc_action, + ahc_minphys, + 0, + 0, +}; + +/* the below structure is so we have a default dev struct for our link struct */ +static struct scsi_device ahc_dev = +{ + NULL, /* Use default error handler */ + NULL, /* have a queue, served by this */ + NULL, /* have no async handler */ + NULL, /* Use default 'done' routine */ +}; + +#ifndef AHC_TMODE_ENABLE +#define AHC_TMODE_ENABLE 0 +#endif + +#define ccb_scb_ptr spriv_ptr0 + +#ifdef AHC_DEBUG +int ahc_debug = AHC_DEBUG; +#endif + +#if UNUSED +static void ahc_dump_targcmd(struct target_cmd *cmd); +#endif +void ahc_build_free_scb_list(struct ahc_softc *ahc); +int ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, + int nsegments); +int ahc_poll(struct ahc_softc *ahc, int wait); +void ahc_timeout(void *); +int ahc_setup_data(struct ahc_softc *ahc, + struct scsi_xfer *xs, + struct scb *scb); +void ahc_set_recoveryscb(struct ahc_softc *ahc, + struct scb *scb); +int ahc_init_scbdata(struct ahc_softc *ahc); +void ahc_fini_scbdata(struct ahc_softc *ahc); +int ahc_istagged_device(struct ahc_softc *ahc, + struct scsi_xfer *xs, + int nocmdcheck); +void ahc_check_tags(struct ahc_softc *ahc, + struct scsi_xfer *xs); + +/* + * Routines to manage busy targets. The old driver didn't need to + * pause the sequencer because no device registers were accessed. Now + * busy targets are controlled via the device registers and thus, we + * have to pause the sequencer for chips that don't have the + * auto-pause feature. XXX smurph + */ +static __inline u_int ahc_pause_index_busy_tcl(struct ahc_softc *ahc, + u_int tcl); +static __inline void ahc_pause_unbusy_tcl(struct ahc_softc *ahc, + u_int tcl); +static __inline void ahc_pause_busy_tcl(struct ahc_softc *ahc, + u_int tcl, u_int busyid); + +static __inline u_int +ahc_pause_index_busy_tcl(ahc, tcl) + struct ahc_softc *ahc; + u_int tcl; +{ + u_int retval; + if (ahc->features & AHC_AUTOPAUSE) { + retval = ahc_index_busy_tcl(ahc, tcl); + } else { + ahc_pause(ahc); + retval = ahc_index_busy_tcl(ahc, tcl); + ahc_unpause(ahc); + } + return retval; +} + +static __inline void +ahc_pause_unbusy_tcl(ahc, tcl) + struct ahc_softc *ahc; + u_int tcl; +{ + if (ahc->features & AHC_AUTOPAUSE) { + ahc_unbusy_tcl(ahc, tcl); + } else { + ahc_pause(ahc); + ahc_unbusy_tcl(ahc, tcl); + ahc_unpause(ahc); + } +} + +static __inline void +ahc_pause_busy_tcl(ahc, tcl, busyid) + struct ahc_softc *ahc; + u_int tcl; + u_int busyid; +{ + if (ahc->features & AHC_AUTOPAUSE) { + ahc_busy_tcl(ahc, tcl, busyid); + } else { + ahc_pause(ahc); + ahc_busy_tcl(ahc, tcl, busyid); + ahc_unpause(ahc); + } +} + +/* Special routine to force negotiation for OpenBSD */ +void +ahc_force_neg(ahc) + struct ahc_softc *ahc; +{ + int num_targets = AHC_NUM_TARGETS; + int i; + + if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) + num_targets = 8; + + for (i = 0; i < num_targets; i++) { + struct ahc_initiator_tinfo *tinfo; + struct ahc_tmode_tstate *tstate; + u_int our_id; + u_int target_id; + char channel; + + channel = 'A'; + our_id = ahc->our_id; + target_id = i; + if (i > 7 && (ahc->features & AHC_TWIN) != 0) { + channel = 'B'; + our_id = ahc->our_id_b; + target_id = i % 8; + } + tinfo = ahc_fetch_transinfo(ahc, channel, our_id, + target_id, &tstate); + tinfo->goal = tinfo->user; /* force negotiation */ + tstate->discenable = ahc->user_discenable; + } +} + +int +ahc_createdmamem(ahc, dmat, size, mapp, vaddr, baddr, seg, nseg, what) + struct ahc_softc *ahc; + bus_dma_tag_t dmat; + int size; + bus_dmamap_t *mapp; + caddr_t *vaddr; + bus_addr_t *baddr; + bus_dma_segment_t *seg; + int *nseg; + const char *what; +{ + int error, level = 0; + int dma_flags = BUS_DMA_NOWAIT; + const char *myname = ahc_name(ahc); + + dmat = ahc->parent_dmat; + + if ((ahc->chip & AHC_VL) !=0) + dma_flags |= ISABUS_DMA_32BIT; + + if ((error = bus_dmamem_alloc(dmat, size, NBPG, 0, + seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { + printf("%s: failed to allocate DMA mem for %s, error = %d\n", + myname, what, error); + goto out; + } + level++; + + if ((error = bus_dmamem_map(dmat, seg, *nseg, size, vaddr, + BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { + printf("%s: failed to map DMA mem for %s, error = %d\n", + myname, what, error); + goto out; + } + level++; + + if ((error = bus_dmamap_create(dmat, size, 1, size, 0, + dma_flags, mapp)) != 0) { + printf("%s: failed to create DMA map for %s, error = %d\n", + myname, what, error); + goto out; + } + level++; + + if ((error = bus_dmamap_load(dmat, *mapp, *vaddr, size, NULL, + BUS_DMA_NOWAIT)) != 0) { + printf("%s: failed to load DMA map for %s, error = %d\n", + myname, what, error); + goto out; + } + + *baddr = (*mapp)->dm_segs[0].ds_addr; + return 0; +out: + switch (level) { + case 3: + bus_dmamap_destroy(dmat, *mapp); + /* FALLTHROUGH */ + case 2: + bus_dmamem_unmap(dmat, *vaddr, size); + /* FALLTHROUGH */ + case 1: + bus_dmamem_free(dmat, seg, *nseg); + break; + default: + break; + } + + return error; +} + +void +ahc_freedmamem(tag, size, map, vaddr, seg, nseg) + bus_dma_tag_t tag; + int size; + bus_dmamap_t map; + caddr_t vaddr; + bus_dma_segment_t *seg; + int nseg; +{ + bus_dmamap_unload(tag, map); + bus_dmamap_destroy(tag, map); + bus_dmamem_unmap(tag, vaddr, size); + bus_dmamem_free(tag, seg, nseg); +} + +void +ahc_alloc_scbs(ahc) + struct ahc_softc *ahc; +{ + struct scb_data *scb_data; + struct scb *next_scb; + struct sg_map_node *sg_map; + bus_addr_t physaddr; + struct ahc_dma_seg *segs; + int newcount; + int i; + int dma_flags = 0; + + scb_data = ahc->scb_data; + if (scb_data->numscbs >= AHC_SCB_MAX) + /* Can't allocate any more */ + return; + + next_scb = &scb_data->scbarray[scb_data->numscbs]; + + sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); + + if (sg_map == NULL) + return; + + if (ahc_createdmamem(ahc, scb_data->sg_dmat, PAGE_SIZE, + &sg_map->sg_dmamap, (caddr_t *)&sg_map->sg_vaddr, + &sg_map->sg_physaddr, &sg_map->sg_dmasegs, + &sg_map->sg_nseg, "SG space") < 0) { + free(sg_map, M_DEVBUF); + return; + } + + SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); + + segs = sg_map->sg_vaddr; + physaddr = sg_map->sg_physaddr; + + newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); + for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) { + struct scb_platform_data *pdata; + int error; + + pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), + M_DEVBUF, M_NOWAIT); + if (pdata == NULL) + break; + bzero(pdata, sizeof(*pdata)); + next_scb->platform_data = pdata; + next_scb->sg_map = sg_map; + next_scb->sg_list = segs; + /* + * The sequencer always starts with the second entry. + * The first entry is embedded in the scb. + */ + next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); + next_scb->ahc_softc = ahc; + next_scb->flags = SCB_FREE; + + /* set up AHA-284x correctly. */ + dma_flags = ((ahc->chip & AHC_VL) !=0) ? + BUS_DMA_NOWAIT|ISABUS_DMA_32BIT : + BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW; + + ahc->buffer_dmat = ahc->parent_dmat; + error = bus_dmamap_create(ahc->buffer_dmat, + AHC_MAXTRANSFER_SIZE, AHC_NSEG, + MAXBSIZE, 0, dma_flags, + &next_scb->dmamap); + if (error !=0) + break; + + next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; + next_scb->hscb->tag = ahc->scb_data->numscbs; + SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, + next_scb, links.sle); + segs += AHC_NSEG; + physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); + next_scb++; + ahc->scb_data->numscbs++; + } +} + +int +ahc_init_scbdata(ahc) + struct ahc_softc *ahc; +{ + struct scb_data *scb_data; + + scb_data = ahc->scb_data; + scb_data->init_level = 0; + SLIST_INIT(&scb_data->free_scbs); + SLIST_INIT(&scb_data->sg_maps); + + /* Allocate SCB resources */ + scb_data->scbarray = + (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX, + M_DEVBUF, M_NOWAIT); + if (scb_data->scbarray == NULL) + return (ENOMEM); + memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX); + + /* set dma tags */ + scb_data->hscb_dmat = ahc->parent_dmat; + scb_data->sense_dmat = ahc->parent_dmat; + scb_data->sg_dmat = ahc->parent_dmat; + + /* Determine the number of hardware SCBs and initialize them */ + scb_data->maxhscbs = ahc_probe_scbs(ahc); + if ((ahc->flags & AHC_PAGESCBS) != 0) { + /* SCB 0 heads the free list */ + ahc_outb(ahc, FREE_SCBH, 0); + } else { + ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); + } + + if (ahc->scb_data->maxhscbs == 0) { + printf("%s: No SCB space found\n", ahc_name(ahc)); + return (ENXIO); + } + + ahc_build_free_scb_list(ahc); + + /* + * Create our DMA mappings. These tags define the kinds of device + * accessible memory allocations and memory mappings we will + * need to perform during normal operation. + * + * Unless we need to further restrict the allocation, we rely + * on the restrictions of the parent dmat, hence the common + * use of MAXADDR and MAXSIZE. + */ + if (ahc_createdmamem(ahc, scb_data->hscb_dmat, + AHC_SCB_MAX * sizeof(struct hardware_scb), + &scb_data->hscb_dmamap, (caddr_t *)&scb_data->hscbs, + &scb_data->hscb_busaddr, &scb_data->hscb_seg, + &scb_data->hscb_nseg, "hardware SCB structures") < 0) + goto error_exit; + + scb_data->init_level++; + + /* DMA for our sense buffers */ + if (ahc_createdmamem(ahc, scb_data->sense_dmat, + AHC_SCB_MAX * sizeof(struct scsi_sense_data), + &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, + &scb_data->sense_busaddr, &scb_data->sense_seg, + &scb_data->sense_nseg, "sense buffers") < 0) + goto error_exit; + + scb_data->init_level++; + + /* Perform initial CCB allocation */ + memset(scb_data->hscbs, 0, AHC_SCB_MAX * sizeof(struct hardware_scb)); + ahc_alloc_scbs(ahc); + + if (scb_data->numscbs == 0) { + printf("%s: ahc_init_scbdata - " + "Unable to allocate initial scbs\n", + ahc_name(ahc)); + goto error_exit; + } + scb_data->init_level++; + + /* + * Tell the sequencer which SCB will be the next one it receives. + */ + ahc->next_queued_scb = ahc_get_scb(ahc); + ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); + + /* + * Note that we were successfull + */ + return (0); + +error_exit: + + return (ENOMEM); +} + +void +ahc_fini_scbdata(ahc) + struct ahc_softc *ahc; +{ + struct scb_data *scb_data; + + scb_data = ahc->scb_data; + + switch (scb_data->init_level) { + default: + case 3: + { + struct sg_map_node *sg_map; + + while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { + SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); + ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, + sg_map->sg_dmamap, + (caddr_t)sg_map->sg_vaddr, + &sg_map->sg_dmasegs, sg_map->sg_nseg); + free(sg_map, M_DEVBUF); + } + } + /*FALLTHROUGH*/ + case 2: + ahc_freedmamem(ahc->parent_dmat, + AHC_SCB_MAX * sizeof(struct scsi_sense_data), + scb_data->sense_dmamap, (caddr_t)scb_data->sense, + &scb_data->sense_seg, scb_data->sense_nseg); + /*FALLTHROUGH*/ + case 1: + ahc_freedmamem(ahc->parent_dmat, + AHC_SCB_MAX * sizeof(struct hardware_scb), + scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, + &scb_data->hscb_seg, scb_data->hscb_nseg); + /*FALLTHROUGH*/ + } + if (scb_data->scbarray != NULL) + free(scb_data->scbarray, M_DEVBUF); +} + +void +ahc_free(ahc) + struct ahc_softc *ahc; +{ + ahc_fini_scbdata(ahc); + if (ahc->init_level != 0) + ahc_freedmamem(ahc->parent_dmat, ahc->shared_data_size, + ahc->shared_data_dmamap, ahc->qoutfifo, + &ahc->shared_data_seg, ahc->shared_data_nseg); + + if (ahc->scb_data != NULL) + free(ahc->scb_data, M_DEVBUF); + return; +} + +/* + * Attach all the sub-devices we can find + */ +int +ahc_attach(ahc) + struct ahc_softc *ahc; +{ + char ahc_info[256]; + int s; + ahc_lock(ahc, &s); + + ahc_controller_info(ahc, ahc_info); + printf("%s: %s\n", ahc_name(ahc), ahc_info); + /* + * Initialize the software queue. + */ + LIST_INIT(&ahc->platform_data->sc_xxxq); + +#ifdef AHC_BROKEN_CACHE + if (cpu_class == CPUCLASS_386) /* doesn't have "wbinvd" instruction */ + ahc_broken_cache = 0; +#endif + /* + * fill in the prototype scsi_links. + */ + ahc->platform_data->sc_link.adapter_target = ahc->our_id; + if (ahc->features & AHC_WIDE) + ahc->platform_data->sc_link.adapter_buswidth = 16; + ahc->platform_data->sc_link.adapter_softc = ahc; + ahc->platform_data->sc_link.adapter = &ahc_switch; + ahc->platform_data->sc_link.openings = 2; + ahc->platform_data->sc_link.device = &ahc_dev; + ahc->platform_data->sc_link.flags = SCSIDEBUG_LEVEL; + + if (ahc->features & AHC_TWIN) { + /* Configure the second scsi bus */ + ahc->platform_data->sc_link_b = ahc->platform_data->sc_link; + ahc->platform_data->sc_link_b.adapter_target = ahc->our_id_b; + if (ahc->features & AHC_WIDE) + ahc->platform_data->sc_link.adapter_buswidth = 16; + ahc->platform_data->sc_link_b.adapter_softc = ahc; + ahc->platform_data->sc_link_b.adapter = &ahc_switch; + ahc->platform_data->sc_link_b.openings = 2; + ahc->platform_data->sc_link_b.device = &ahc_dev; + ahc->platform_data->sc_link_b.flags = SCSIDEBUG_LEVEL; + } + + /* + * ask the adapter what subunits are present + */ + if (ahc->platform_data->channel_b_primary == FALSE) { + /* make SCSI_IS_SCSIBUS_B() == false, while probing channel A */ + ahc->platform_data->sc_link_b.scsibus = 0xff; + config_found((void *)ahc, &ahc->platform_data->sc_link, scsiprint); + if (ahc->features & AHC_TWIN) + config_found((void *)ahc, &ahc->platform_data->sc_link_b, scsiprint); + } else { + /* + * if implementation of SCSI_IS_SCSIBUS_B() is changed to use + * ahc->sc_link.scsibus, then "ahc->sc_link.scsibus = 0xff;" + * is needed, here. + */ + if (ahc->features & AHC_TWIN) + config_found((void *)ahc, &ahc->platform_data->sc_link_b, scsiprint); + config_found((void *)ahc, &ahc->platform_data->sc_link, scsiprint); + } + ahc_unlock(ahc, &s); + return 1; +} + +/* + * Catch an interrupt from the adapter + */ +int +ahc_platform_intr(arg) + void *arg; +{ + struct ahc_softc *ahc; + u_int intstat; + + /* + * Any interrupts to process? + */ + ahc = (struct ahc_softc *)arg; + + intstat = ahc_inb(ahc, INTSTAT); + + if ((intstat & INT_PEND) == 0) { + if (ahc->platform_data->pci_intr_func && + (int)ahc->platform_data->pci_intr_func(ahc)) { +#ifdef AHC_DEBUG + printf("%s: bus intr: CCHADDR %x HADDR %x SEQADDR %x\n", + ahc_name(ahc), + ahc_inb(ahc, CCHADDR) | + (ahc_inb(ahc, CCHADDR+1) << 8) + | (ahc_inb(ahc, CCHADDR+2) << 16) + | (ahc_inb(ahc, CCHADDR+3) << 24), + ahc_inb(ahc, HADDR) | (ahc_inb(ahc, HADDR+1) << 8) + | (ahc_inb(ahc, HADDR+2) << 16) + | (ahc_inb(ahc, HADDR+3) << 24), + ahc_inb(ahc, SEQADDR0) | + (ahc_inb(ahc, SEQADDR1) << 8)); +#endif + return 1; + } + return 0; + } + + ahc_intr(ahc); + return 1; +} + +/* + * We have an scb which has been processed by the + * adaptor, now we look to see how the operation + * went. + */ +void +ahc_done(ahc, scb) + struct ahc_softc *ahc; + struct scb *scb; +{ + struct scsi_xfer *xs = scb->io_ctx; + struct scsi_link *sc_link = xs->sc_link; + int requeue = 0; + int target; + int lun; + + SC_DEBUG(xs->sc_link, SDEV_DB2, ("ahc_done\n")); + + LIST_REMOVE(scb, pending_links); + if ((scb->flags & SCB_UNTAGGEDQ) != 0) { + struct scb_tailq *untagged_q; + int target_offset; + + target_offset = SCB_GET_TARGET_OFFSET(ahc, scb); + untagged_q = &ahc->untagged_queues[target_offset]; + TAILQ_REMOVE(untagged_q, scb, links.tqe); + scb->flags &= ~SCB_UNTAGGEDQ; + ahc_run_untagged_queue(ahc, untagged_q); + } + + timeout_del(&xs->stimeout); + +#ifdef AHC_DEBUG + if ((ahc_debug & AHC_SHOWCMDS)) { + ahc_print_path(ahc, scb); + printf("ahc_done: opcode 0x%x tag %x flags %x status %d error %d\n", + xs->cmdstore.opcode, scb->hscb->tag, + scb->flags, xs->status, xs->error); + } +#endif + + target = sc_link->target; + lun = sc_link->lun; + + if (xs->datalen) { + int op; + + if ((xs->flags & SCSI_DATA_IN) != 0) + op = BUS_DMASYNC_POSTREAD; + else + op = BUS_DMASYNC_POSTWRITE; + ahc->buffer_dmat = ahc->parent_dmat; + bus_dmamap_sync(ahc->buffer_dmat, scb->dmamap, + 0, scb->dmamap->dm_mapsize, op); + + bus_dmamap_unload(ahc->buffer_dmat, scb->dmamap); + } + + /* + * Unbusy this target/channel/lun. + * XXX if we are holding two commands per lun, + * send the next command. + */ + if (!(scb->hscb->control & TAG_ENB)){ + ahc_pause_unbusy_tcl(ahc, XS_TCL(xs)); + } + + /* + * If the recovery SCB completes, we have to be + * out of our timeout. + */ + if ((scb->flags & SCB_RECOVERY_SCB) != 0) { + struct scb *list_scb; + + /* + * We were able to complete the command successfully, + * so reinstate the timeouts for all other pending + * commands. + */ + LIST_FOREACH(list_scb, &ahc->pending_scbs, pending_links) { + struct scsi_xfer *txs = list_scb->io_ctx; + if (!(txs->flags & SCSI_POLL)) + timeout_add(&list_scb->io_ctx->stimeout, + (list_scb->io_ctx->timeout * hz)/1000); + } + + if (xs->error != XS_NOERROR) + ahc_set_transaction_status(scb, CAM_CMD_TIMEOUT); + ahc_print_path(ahc, scb); + printf("no longer in timeout, status = %x\n", xs->status); + } + + if (xs->error != XS_NOERROR) { + /* Don't clobber any existing error state */ + } else if ((scb->flags & SCB_SENSE) != 0) { + /* + * We performed autosense retrieval. + * + * Zero the sense data before having + * the drive fill it. The SCSI spec mandates + * that any untransfered data should be + * assumed to be zero. Complete the 'bounce' + * of sense information through buffers accessible + * via bus-space by copying it into the clients + * csio. + */ + memset(&xs->sense, 0, sizeof(struct scsi_sense_data)); + memcpy(&xs->sense, ahc_get_sense_buf(ahc, scb), + ahc_le32toh((scb->sg_list->len & AHC_SG_LEN_MASK))); + xs->error = XS_SENSE; + } + + if (scb->platform_data->flags & SCB_FREEZE_QUEUE) { + /* keep negs from happening */ + if (ahc->platform_data->devqueue_blocked[target] > 0) { + ahc->platform_data->devqueue_blocked[target]--; + } + scb->platform_data->flags &= ~SCB_FREEZE_QUEUE; + } + + requeue = scb->platform_data->flags & SCB_REQUEUE; + ahc_free_scb(ahc, scb); + + if (requeue) { + /* + * Re-insert at the front of the private queue to + * preserve order. + */ + int s; + ahc_lock(ahc, &s); + ahc_list_insert_head(ahc, xs); + ahc_unlock(ahc, &s); + } else { + if ((xs->sc_link->lun == 0) && + (xs->flags & SCSI_POLL) && + (xs->error == XS_NOERROR)) + ahc_check_tags(ahc, xs); + xs->flags |= ITSDONE; + scsi_done(xs); + } + + /* + * If there are entries in the software queue, try to + * run the first one. We should be more or less guaranteed + * to succeed, since we just freed an SCB. + * + * NOTE: ahc_action() relies on our calling it with + * the first entry in the queue. + */ + if ((xs = ahc->platform_data->sc_xxxq.lh_first) != NULL) + (void) ahc_action(xs); +} + +static void +ahc_minphys(bp) + struct buf *bp; +{ + /* + * Even though the card can transfer up to 16megs per command + * we are limited by the number of segments in the dma segment + * list that we can hold. The worst case is that all pages are + * discontinuous physically, hense the "page per segment" limit + * enforced here. + */ + if (bp->b_bcount > ((AHC_NSEG - 1) * PAGE_SIZE)) { + bp->b_bcount = ((AHC_NSEG - 1) * PAGE_SIZE); + } + minphys(bp); +} + +int32_t +ahc_action(xs) + struct scsi_xfer *xs; +{ + struct scsi_xfer *first_xs, *next_xs = NULL; + struct ahc_softc *ahc; + struct scb *scb; + struct hardware_scb *hscb; + struct ahc_initiator_tinfo *tinfo; + struct ahc_tmode_tstate *tstate; + u_int target_id; + u_int our_id; + char channel; + int s, tcl; + u_int16_t mask; + int dontqueue = 0, fromqueue = 0; + + SC_DEBUG(xs->sc_link, SDEV_DB3, ("ahc_action\n")); + ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; + + /* must protect the queue */ + ahc_lock(ahc, &s); + + if (xs == ahc->platform_data->sc_xxxq.lh_first) { + /* + * Called from ahc_done. Calling with the first entry in + * the queue is really just a way of seeing where we're + * called from. Now, find the first eligible SCB to send, + * e.g. one which will be accepted immediately. + */ + if (ahc->platform_data->queue_blocked) { + ahc_unlock(ahc, &s); + return (TRY_AGAIN_LATER); + } + + xs = ahc_first_xs(ahc); + if (xs == NULL) { + ahc_unlock(ahc, &s); + return (TRY_AGAIN_LATER); + } + + next_xs = ahc_list_next(ahc, xs); + ahc_list_remove(ahc, xs); + fromqueue = 1; + goto get_scb; + } + + /* determine safety of software queueing */ + dontqueue = xs->flags & SCSI_POLL; + + /* + * If no new requests are accepted, just insert into the + * private queue to wait for our turn. + */ + tcl = XS_TCL(xs); + + if (ahc->platform_data->queue_blocked || + ahc->platform_data->devqueue_blocked[xs->sc_link->target] || + (!ahc_istagged_device(ahc, xs, 0) && + ahc_pause_index_busy_tcl(ahc, tcl) != SCB_LIST_NULL)) { + if (dontqueue) { + ahc_unlock(ahc, &s); + xs->error = XS_DRIVER_STUFFUP; + return TRY_AGAIN_LATER; + } + ahc_list_insert_tail(ahc, xs); + ahc_unlock(ahc, &s); + return SUCCESSFULLY_QUEUED; + } + + first_xs = ahc_first_xs(ahc); + + /* determine safety of software queueing */ + dontqueue = xs->flags & SCSI_POLL; + + /* + * Handle situations where there's already entries in the + * queue. + */ + if (first_xs != NULL) { + /* + * If we can't queue, we have to abort, since + * we have to preserve order. + */ + if (dontqueue) { + ahc_unlock(ahc, &s); + xs->error = XS_DRIVER_STUFFUP; + return (TRY_AGAIN_LATER); + } + + /* + * Swap with the first queue entry. + */ + ahc_list_insert_tail(ahc, xs); + xs = first_xs; + next_xs = ahc_list_next(ahc, xs); + ahc_list_remove(ahc, xs); + fromqueue = 1; + } + +get_scb: + + target_id = xs->sc_link->target; + our_id = SCSI_SCSI_ID(ahc, xs->sc_link); + + /* + * get an scb to use. + */ + if ((scb = ahc_get_scb(ahc)) == NULL) { + if (dontqueue) { + ahc_unlock(ahc, &s); + xs->error = XS_DRIVER_STUFFUP; + return (TRY_AGAIN_LATER); + } + + /* + * If we were pulled off the queue, put ourselves + * back to where we came from, otherwise tack ourselves + * onto the end. + */ + if (fromqueue && next_xs != NULL) + ahc_list_insert_before(ahc, xs, next_xs); + else + ahc_list_insert_tail(ahc, xs); + + ahc_unlock(ahc, &s); + return (SUCCESSFULLY_QUEUED); + } + + tcl = XS_TCL(xs); + +#ifdef DIAGNOSTIC + if (!ahc_istagged_device(ahc, xs, 0) && + ahc_pause_index_busy_tcl(ahc, tcl) != SCB_LIST_NULL) + panic("ahc: queuing for busy target"); +#endif + + scb->io_ctx = xs; + hscb = scb->hscb; + + hscb->control = 0; + + timeout_set(&xs->stimeout, ahc_timeout, scb); + + if (ahc_istagged_device(ahc, xs, 0)){ + hscb->control |= TAG_ENB; + } else { + ahc_pause_busy_tcl(ahc, tcl, scb->hscb->tag); + } + + ahc_unlock(ahc, &s); + + channel = SCSI_CHANNEL(ahc, xs->sc_link); + if (ahc->platform_data->inited_channels[channel - 'A'] == 0) { + if ((channel == 'A' && (ahc->flags & AHC_RESET_BUS_A)) || + (channel == 'B' && (ahc->flags & AHC_RESET_BUS_B))) { + ahc_lock(ahc, &s); + ahc_reset_channel(ahc, channel, TRUE); + ahc_unlock(ahc, &s); + } + ahc->platform_data->inited_channels[channel - 'A'] = 1; + } + + /* + * Put all the arguments for the xfer in the scb + */ + hscb->scsiid = BUILD_SCSIID(ahc, xs->sc_link, target_id, our_id); + hscb->lun = XS_LUN(xs); + + mask = SCB_GET_TARGET_MASK(ahc, scb); + tinfo = ahc_fetch_transinfo(ahc, SCSI_CHANNEL(ahc, xs->sc_link), our_id, + target_id, &tstate); + + if (ahc->platform_data->inited_targets[target_id] == 0) { + struct ahc_devinfo devinfo; + + ahc_lock(ahc, &s); + ahc_compile_devinfo(&devinfo, our_id, target_id, + XS_LUN(xs), SCSI_CHANNEL(ahc, xs->sc_link), + ROLE_INITIATOR); + ahc_update_neg_request(ahc, &devinfo, tstate, tinfo, + /*force*/TRUE); + ahc->platform_data->inited_targets[target_id] = 1; + ahc_unlock(ahc, &s); + } + + hscb->scsirate = tinfo->scsirate; + hscb->scsioffset = tinfo->curr.offset; + if ((tstate->ultraenb & mask) != 0) + hscb->control |= ULTRAENB; + + if ((tstate->discenable & mask) != 0) + hscb->control |= DISCENB; + + if ((tstate->auto_negotiate & mask) != 0) { + scb->flags |= SCB_AUTO_NEGOTIATE; + hscb->control |= MK_MESSAGE; + } + + if (xs->flags & SCSI_RESET) { + scb->flags |= SCB_DEVICE_RESET; + hscb->control |= MK_MESSAGE; + return ahc_execute_scb(scb, NULL, 0); + } + + return ahc_setup_data(ahc, xs, scb); +} + +int +ahc_execute_scb(arg, dm_segs, nsegments) + void *arg; + bus_dma_segment_t *dm_segs; + int nsegments; +{ + struct scb *scb; + struct scsi_xfer *xs; + struct ahc_softc *ahc; + struct ahc_initiator_tinfo *tinfo; + struct ahc_tmode_tstate *tstate; + u_int mask; + int s; + + scb = (struct scb *)arg; + xs = scb->io_ctx; + ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; + + if (nsegments != 0) { + struct ahc_dma_seg *sg; + bus_dma_segment_t *end_seg; + int op; + + end_seg = dm_segs + nsegments; + + /* Copy the segments into our SG list */ + sg = scb->sg_list; + while (dm_segs < end_seg) { + uint32_t len; + + sg->addr = ahc_htole32(dm_segs->ds_addr); + len = dm_segs->ds_len + | ((dm_segs->ds_addr >> 8) & 0x7F000000); + sg->len = ahc_htole32(len); + sg++; + dm_segs++; + } + + /* + * Note where to find the SG entries in bus space. + * We also set the full residual flag which the + * sequencer will clear as soon as a data transfer + * occurs. + */ + scb->hscb->sgptr = ahc_htole32(scb->sg_list_phys|SG_FULL_RESID); + + if ((xs->flags & SCSI_DATA_IN) != 0) + op = BUS_DMASYNC_PREREAD; + else + op = BUS_DMASYNC_PREWRITE; + + ahc->buffer_dmat = ahc->parent_dmat; + bus_dmamap_sync(ahc->buffer_dmat, scb->dmamap, + 0, scb->dmamap->dm_mapsize, op); + + sg--; + sg->len |= ahc_htole32(AHC_DMA_LAST_SEG); + + /* Copy the first SG into the "current" data pointer area */ + scb->hscb->dataptr = scb->sg_list->addr; + scb->hscb->datacnt = scb->sg_list->len; + } else { + scb->hscb->sgptr = SG_LIST_NULL; + scb->hscb->dataptr = 0; + scb->hscb->datacnt = 0; + } + + scb->sg_count = nsegments; + + ahc_lock(ahc, &s); + + /* + * Last time we need to check if this SCB needs to + * be aborted. + */ + if (xs->flags & ITSDONE) { + + if (!ahc_istagged_device(ahc, xs, 0)){ + ahc_pause_unbusy_tcl(ahc, XS_TCL(xs)); + } + + if (nsegments != 0) + bus_dmamap_unload(ahc->buffer_dmat, scb->dmamap); + + ahc_free_scb(ahc, scb); + ahc_unlock(ahc, &s); + return (COMPLETE); + } + +#ifdef DIAGNOSTIC + if (scb->sg_count > 255) + panic("ahc bad sg_count"); +#endif + + /* Fixup byte order */ + scb->hscb->dataptr = ahc_htole32(scb->hscb->dataptr); + scb->hscb->datacnt = ahc_htole32(scb->hscb->datacnt); + scb->hscb->sgptr = ahc_htole32(scb->hscb->sgptr); + + tinfo = ahc_fetch_transinfo(ahc, SCSIID_CHANNEL(ahc, scb->hscb->scsiid), + SCSIID_OUR_ID(scb->hscb->scsiid), + SCSIID_TARGET(ahc, scb->hscb->scsiid), + &tstate); + + mask = SCB_GET_TARGET_MASK(ahc, scb); + scb->hscb->scsirate = tinfo->scsirate; + scb->hscb->scsioffset = tinfo->curr.offset; + if ((tstate->ultraenb & mask) != 0) + scb->hscb->control |= ULTRAENB; + + if ((tstate->discenable & mask) != 0) + scb->hscb->control |= DISCENB; + + if ((tstate->auto_negotiate & mask) != 0) { + scb->flags |= SCB_AUTO_NEGOTIATE; + scb->hscb->control |= MK_MESSAGE; + } + + LIST_INSERT_HEAD(&ahc->pending_scbs, scb, pending_links); + + /* + * We only allow one untagged transaction + * per target in the initiator role unless + * we are storing a full busy target *lun* + * table in SCB space. + * + * This really should not be of any + * concern, as we take care to avoid this + * in ahc_done(). XXX smurph + */ + if ((scb->hscb->control & (TARGET_SCB|TAG_ENB)) == 0 + && (ahc->flags & AHC_SCB_BTT) == 0) { + struct scb_tailq *untagged_q; + int target_offset; + + target_offset = SCB_GET_TARGET_OFFSET(ahc, scb); + untagged_q = &(ahc->untagged_queues[target_offset]); + TAILQ_INSERT_TAIL(untagged_q, scb, links.tqe); + scb->flags |= SCB_UNTAGGEDQ; + if (TAILQ_FIRST(untagged_q) != scb) { + ahc_unlock(ahc, &s); + return (COMPLETE); + } + } + + scb->flags |= SCB_ACTIVE; + + if (!(xs->flags & SCSI_POLL)) + timeout_add(&xs->stimeout, (xs->timeout * hz) / 1000); + + if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { + /* Define a mapping from our tag to the SCB. */ + ahc->scb_data->scbindex[scb->hscb->tag] = scb; + ahc_pause(ahc); + if ((ahc->flags & AHC_PAGESCBS) == 0) + ahc_outb(ahc, SCBPTR, scb->hscb->tag); + ahc_outb(ahc, SCB_TAG, scb->hscb->tag); + ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); + ahc_unpause(ahc); + } else { + ahc_queue_scb(ahc, scb); + } + +#ifdef AHC_DEBUG + if ((ahc_debug & AHC_SHOWCMDS)) { + ahc_print_path(ahc, scb); + printf("opcode 0x%x tag %x len %d flags %x " + "control %x fpos %u rate %x\n", + xs->cmdstore.opcode, scb->hscb->tag, + scb->hscb->cdb_len, scb->flags, + scb->hscb->control, ahc->qinfifonext, + scb->hscb->scsirate); + } +#endif + + if (!(xs->flags & SCSI_POLL)) { + ahc_unlock(ahc, &s); + return (SUCCESSFULLY_QUEUED); + } + + /* + * If we can't use interrupts, poll for completion + */ + SC_DEBUG(xs->sc_link, SDEV_DB3, ("cmd_poll\n")); + do { + if (ahc_poll(ahc, xs->timeout)) { + if (!(xs->flags & SCSI_SILENT)) + printf("cmd fail\n"); + ahc_timeout(scb); + break; + } + } while (!(xs->flags & ITSDONE)); + ahc_unlock(ahc, &s); + return (COMPLETE); +} + +int +ahc_poll(ahc, wait) + struct ahc_softc *ahc; + int wait; /* in msec */ +{ + while (--wait) { + if (ahc->platform_data->pci_intr_func) + (void)ahc->platform_data->pci_intr_func(ahc); + DELAY(1000); + if (ahc_inb(ahc, INTSTAT) & INT_PEND) + break; + } + + if (wait == 0) { + printf("%s: board is not responding\n", ahc_name(ahc)); + return (EIO); + } + + ahc_intr((void *)ahc); + + return (0); +} + +int +ahc_setup_data(ahc, xs, scb) + struct ahc_softc *ahc; + struct scsi_xfer *xs; + struct scb *scb; +{ + struct hardware_scb *hscb; + + hscb = scb->hscb; + xs->resid = xs->status = 0; + xs->error = XS_NOERROR; + + hscb->cdb_len = xs->cmdlen; + + if (hscb->cdb_len > 12) { + memcpy(hscb->cdb32, xs->cmd, + hscb->cdb_len); + scb->flags |= SCB_CDB32_PTR; + } else { + memcpy(hscb->shared_data.cdb, + xs->cmd, + hscb->cdb_len); + } + + /* Only use S/G if there is a transfer */ + if (xs->datalen) { + int error; + + error = bus_dmamap_load(ahc->buffer_dmat, + scb->dmamap, xs->data, + xs->datalen, NULL, + (xs->flags & SCSI_NOSLEEP) ? + BUS_DMA_NOWAIT : BUS_DMA_WAITOK); + if (error) { + if (!ahc_istagged_device(ahc, xs, 0)){ + ahc_pause_unbusy_tcl(ahc, XS_TCL(xs)); + } + return (TRY_AGAIN_LATER); /* XXX fvdl */ + } + error = ahc_execute_scb(scb, + scb->dmamap->dm_segs, + scb->dmamap->dm_nsegs); + return error; + } else { + return ahc_execute_scb(scb, NULL, 0); + } +} + +void +ahc_set_recoveryscb(ahc, scb) + struct ahc_softc *ahc; + struct scb *scb; +{ + + if ((scb->flags & SCB_RECOVERY_SCB) == 0) { + struct scb *list_scb; + + scb->flags |= SCB_RECOVERY_SCB; + + /* + * Take all queued, but not sent SCBs out of the equation. + * Also ensure that no new CCBs are queued to us while we + * try to fix this problem. + */ + ahc->platform_data->queue_blocked = 1; + + /* + * Go through all of our pending SCBs and remove + * any scheduled timeouts for them. We will reschedule + * them after we've successfully fixed this problem. + */ + LIST_FOREACH(list_scb, &ahc->pending_scbs, pending_links) { + timeout_del(&list_scb->io_ctx->stimeout); + } + } +} + +void +ahc_timeout(arg) + void *arg; +{ + struct scb *scb; + struct ahc_softc *ahc; + int s, found; + u_int last_phase; + int target; + int lun; + int i; + char channel; + + scb = (struct scb *)arg; + ahc = (struct ahc_softc *)scb->io_ctx->sc_link->adapter_softc; + + ahc_lock(ahc, &s); + + /* + * Ensure that the card doesn't do anything + * behind our back. Also make sure that we + * didn't "just" miss an interrupt that would + * affect this timeout. + */ + ahc_pause_and_flushwork(ahc); + + if ((scb->flags & SCB_ACTIVE) == 0) { + /* Previous timeout took care of me already */ + printf("%s: Timedout SCB already complete. " + "Interrupts may not be functioning.\n", ahc_name(ahc)); + ahc_unpause(ahc); + ahc_unlock(ahc, &s); + return; + } + + target = SCB_GET_TARGET(ahc, scb); + channel = SCB_GET_CHANNEL(ahc, scb); + lun = SCB_GET_LUN(scb); + + ahc_print_path(ahc, scb); + printf("SCB 0x%x - timed out\n", scb->hscb->tag); + + /* + * Take a snapshot of the bus state and print out + * some information so we can track down driver bugs. + */ + ahc_dump_card_state(ahc); + last_phase = ahc_inb(ahc, LASTPHASE); + + if (scb->sg_count > 0) { + for (i = 0; i < scb->sg_count; i++) { + printf("sg[%d] - Addr 0x%x : Length %d\n", + i, + scb->sg_list[i].addr, + scb->sg_list[i].len & AHC_SG_LEN_MASK); + } + } + + if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { + /* + * Been down this road before. + * Do a full bus reset. + */ +bus_reset: + ahc_set_transaction_status(scb, CAM_CMD_TIMEOUT); + found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); + printf("%s: Issued Channel %c Bus Reset. " + "%d SCBs aborted\n", ahc_name(ahc), channel, found); + } else { + /* + * If we are a target, transition to bus free and report + * the timeout. + * + * The target/initiator that is holding up the bus may not + * be the same as the one that triggered this timeout + * (different commands have different timeout lengths). + * If the bus is idle and we are actiing as the initiator + * for this request, queue a BDR message to the timed out + * target. Otherwise, if the timed out transaction is + * active: + * Initiator transaction: + * Stuff the message buffer with a BDR message and assert + * ATN in the hopes that the target will let go of the bus + * and go to the mesgout phase. If this fails, we'll + * get another timeout 2 seconds later which will attempt + * a bus reset. + * + * Target transaction: + * Transition to BUS FREE and report the error. + * It's good to be the target! + */ + u_int active_scb_index; + u_int saved_scbptr; + + saved_scbptr = ahc_inb(ahc, SCBPTR); + active_scb_index = ahc_inb(ahc, SCB_TAG); + + if (last_phase != P_BUSFREE + && (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) != 0 + && (active_scb_index < ahc->scb_data->numscbs)) { + struct scb *active_scb; + + /* + * If the active SCB is not from our device, + * assume that another device is hogging the bus + * and wait for it's timeout to expire before + * taking additional action. + */ + active_scb = ahc_lookup_scb(ahc, active_scb_index); + if (active_scb != scb) { + u_int newtimeout; + + ahc_print_path(ahc, active_scb); + printf("Other SCB Timeout%s", + (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 + ? " again\n" : "\n"); + scb->flags |= SCB_OTHERTCL_TIMEOUT; + newtimeout = MAX(active_scb->io_ctx->timeout, + scb->io_ctx->timeout); + timeout_add(&scb->io_ctx->stimeout, + (newtimeout * hz) / 1000); + ahc_unpause(ahc); + ahc_unlock(ahc, &s); + return; + } + + /* It's us */ + if ((scb->hscb->control & TARGET_SCB) != 0) { + + /* + * Send back any queued up transactions + * and properly record the error condition. + */ + ahc_freeze_devq(ahc, scb); + ahc_set_transaction_status(scb, + CAM_CMD_TIMEOUT); + ahc_freeze_scb(scb); + ahc_done(ahc, scb); + + /* Will clear us from the bus */ + ahc_restart(ahc); + ahc_unlock(ahc, &s); + return; + } + + ahc_set_recoveryscb(ahc, active_scb); + ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); + ahc_outb(ahc, SCSISIGO, last_phase|ATNO); + ahc_print_path(ahc, active_scb); + printf("BDR message in message buffer\n"); + active_scb->flags |= SCB_DEVICE_RESET; + timeout_add(&active_scb->io_ctx->stimeout, 2 * hz); + ahc_unpause(ahc); + } else { + int disconnected; + + /* XXX Shouldn't panic. Just punt instead */ + if ((scb->hscb->control & TARGET_SCB) != 0) + panic("Timed-out target SCB but bus idle"); + + if (last_phase != P_BUSFREE + && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { + /* XXX What happened to the SCB? */ + /* Hung target selection. Goto busfree */ + printf("%s: Hung target selection\n", + ahc_name(ahc)); + ahc_restart(ahc); + ahc_unlock(ahc, &s); + return; + } + if (ahc_search_qinfifo(ahc, target, channel, lun, + scb->hscb->tag, ROLE_INITIATOR, + /*status*/0, SEARCH_COUNT) > 0) { + disconnected = FALSE; + } else { + disconnected = TRUE; + } + + if (disconnected) { + + ahc_set_recoveryscb(ahc, scb); + /* + * Actually re-queue this SCB in an attempt + * to select the device before it reconnects. + * In either case (selection or reselection), + * we will now issue a target reset to the + * timed-out device. + * + * Set the MK_MESSAGE control bit indicating + * that we desire to send a message. We + * also set the disconnected flag since + * in the paging case there is no guarantee + * that our SCB control byte matches the + * version on the card. We don't want the + * sequencer to abort the command thinking + * an unsolicited reselection occurred. + */ + scb->hscb->control |= MK_MESSAGE|DISCONNECTED; + scb->flags |= /*SCB_QUEUED_MSG | */ + SCB_DEVICE_RESET; + + /* + * Remove any cached copy of this SCB in the + * disconnected list in preparation for the + * queuing of our abort SCB. We use the + * same element in the SCB, SCB_NEXT, for + * both the qinfifo and the disconnected list. + */ + ahc_search_disc_list(ahc, target, channel, + lun, scb->hscb->tag, + /*stop_on_first*/TRUE, + /*remove*/TRUE, + /*save_state*/FALSE); + + /* + * In the non-paging case, the sequencer will + * never re-reference the in-core SCB. + * To make sure we are notified during + * reslection, set the MK_MESSAGE flag in + * the card's copy of the SCB. + */ + if ((ahc->flags & AHC_PAGESCBS) == 0) { + ahc_outb(ahc, SCBPTR, scb->hscb->tag); + ahc_outb(ahc, SCB_CONTROL, + ahc_inb(ahc, SCB_CONTROL) + | MK_MESSAGE); + } + /* + * Clear out any entries in the QINFIFO first + * so we are the next SCB for this target + * to run. + */ + ahc_search_qinfifo(ahc, + SCB_GET_TARGET(ahc, scb), + channel, SCB_GET_LUN(scb), + SCB_LIST_NULL, + ROLE_INITIATOR, + CAM_REQUEUE_REQ, + SEARCH_COMPLETE); + ahc_print_path(ahc, scb); + printf("Queuing a BDR SCB\n"); + ahc_qinfifo_requeue_tail(ahc, scb); + ahc_outb(ahc, SCBPTR, saved_scbptr); + timeout_add(&scb->io_ctx->stimeout, 2 * hz); + ahc_unpause(ahc); + } else { + /* Go "immediatly" to the bus reset */ + /* This shouldn't happen */ + ahc_set_recoveryscb(ahc, scb); + ahc_print_path(ahc, scb); + printf("SCB %d: Immediate reset. " + "Flags = 0x%x\n", scb->hscb->tag, + scb->flags); + goto bus_reset; + } + } + } + ahc_unlock(ahc, &s); +} + +void +ahc_send_async(ahc, channel, target, lun, code, opt_arg) + struct ahc_softc *ahc; + char channel; + u_int target, lun, code; + void *opt_arg; +{ + /* Nothing to do here for OpenBSD */ +} + +void +ahc_platform_set_tags(ahc, devinfo, alg) + struct ahc_softc *ahc; + struct ahc_devinfo *devinfo; + ahc_queue_alg alg; +{ + struct ahc_initiator_tinfo *tinfo; + struct ahc_tmode_tstate *tstate; + + tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, + devinfo->our_scsiid, + devinfo->target, + &tstate); + + switch (alg) { + case AHC_QUEUE_BASIC: + case AHC_QUEUE_TAGGED: + tstate->tagenable |= devinfo->target_mask; + break; + case AHC_QUEUE_NONE: + tstate->tagenable &= ~devinfo->target_mask; + break; + } +} + +int +ahc_platform_alloc(ahc, platform_arg) + struct ahc_softc *ahc; + void *platform_arg; +{ + ahc->platform_data = malloc(sizeof(struct ahc_platform_data), M_DEVBUF, + M_NOWAIT); + if (ahc->platform_data == NULL) + return (ENOMEM); + bzero(ahc->platform_data, sizeof(struct ahc_platform_data)); + + /* Just do some initialization... */ + ahc->scb_data = NULL; + ahc->platform_data->ih = NULL; + ahc->platform_data->pci_intr_func = NULL; + ahc->platform_data->channel_b_primary = FALSE; + + return (0); +} + +void +ahc_platform_free(ahc) + struct ahc_softc *ahc; +{ + free(ahc->platform_data, M_DEVBUF); +} + +int +ahc_softc_comp(lahc, rahc) + struct ahc_softc *lahc; + struct ahc_softc *rahc; +{ + /* We don't sort softcs under OpenBSD so report equal always */ + return (0); +} + +void +ahc_check_tags(ahc, xs) + struct ahc_softc *ahc; + struct scsi_xfer *xs; +{ + struct ahc_devinfo devinfo; + + if (ahc->scb_data->maxhscbs >= 16 || + (ahc->flags & AHC_PAGESCBS)) { + /* Default to 16 tags */ + xs->sc_link->openings += 14; + } else { + /* + * Default to 4 tags on whimpy + * cards that don't have much SCB + * space and can't page. This prevents + * a single device from hogging all + * slots. We should really have a better + * way of providing fairness. + */ + xs->sc_link->openings += 2; + } + + if (xs->sc_link->quirks & SDEV_NOTAGS) + return; + + if (ahc_istagged_device(ahc, xs, 1)) + return; + + ahc_compile_devinfo(&devinfo, + SCSI_SCSI_ID(ahc, xs->sc_link), + XS_SCSI_ID(xs), + XS_LUN(xs), + SCSI_CHANNEL(ahc, xs->sc_link), + ROLE_INITIATOR); + + ahc_set_tags(ahc, &devinfo, AHC_QUEUE_TAGGED); + + printf("%s: target %d using tagged queuing\n", + ahc_name(ahc), XS_SCSI_ID(xs)); + +} + +int +ahc_istagged_device(ahc, xs, nocmdcheck) + struct ahc_softc *ahc; + struct scsi_xfer *xs; + int nocmdcheck; +{ + char channel; + u_int our_id, target; + struct ahc_tmode_tstate *tstate; + struct ahc_devinfo devinfo; + + if (xs->sc_link->quirks & SDEV_NOTAGS) + return 0; + + /* + * XXX never do these commands with tags. Should really be + * in a higher layer. + */ + if (!nocmdcheck && (xs->cmd->opcode == INQUIRY || + xs->cmd->opcode == TEST_UNIT_READY || + xs->cmd->opcode == REQUEST_SENSE)) + return 0; + + channel = SCSI_CHANNEL(ahc, xs->sc_link); + our_id = SCSI_SCSI_ID(ahc, xs->sc_link); + target = XS_SCSI_ID(xs); + (void)ahc_fetch_transinfo(ahc, channel, our_id, target, &tstate); + + ahc_compile_devinfo(&devinfo, our_id, target, XS_LUN(xs), + channel, ROLE_INITIATOR); + + return (tstate->tagenable & devinfo.target_mask); +} + +#if UNUSED +static void +ahc_dump_targcmd(cmd) + struct target_cmd *cmd; +{ + uint8_t *byte; + uint8_t *last_byte; + int i; + + byte = &cmd->initiator_channel; + /* Debugging info for received commands */ + last_byte = &cmd[1].initiator_channel; + + i = 0; + while (byte < last_byte) { + if (i == 0) + printf("\t"); + printf("%#x", *byte++); + i++; + if (i == 8) { + printf("\n"); + i = 0; + } else { + printf(", "); + } + } +} +#endif + diff --git a/sys/dev/ic/aic7xxx_openbsd.h b/sys/dev/ic/aic7xxx_openbsd.h new file mode 100644 index 00000000000..5e70c368282 --- /dev/null +++ b/sys/dev/ic/aic7xxx_openbsd.h @@ -0,0 +1,837 @@ +/* + * OpenBSD platform specific driver option settings, data structures, + * function declarations and includes. + * + * Copyright (c) 1994-2001 Justin T. Gibbs. + * Copyright (c) 2001-2002 Steve Murphree, Jr. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. The name of the author(s) may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU Public License ("GPL"). + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id: aic7xxx_openbsd.h,v 1.5 2002/06/28 00:34:54 smurph Exp $ + * + * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx_freebsd.h,v 1.12 2001/07/18 21:39:47 gibbs Exp $ + * $OpenBSD: aic7xxx_openbsd.h,v 1.5 2002/06/28 00:34:54 smurph Exp $ + */ + +#ifndef _AIC7XXX_OPENBSD_H_ +#define _AIC7XXX_OPENBSD_H_ + +#include "pci.h" /* for config options */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/kernel.h> +#include <sys/device.h> +#include <machine/bus.h> +#include <machine/intr.h> + +#include <dev/pci/pcivar.h> + +#include <sys/malloc.h> +#include <sys/buf.h> +#include <sys/proc.h> +#include <sys/queue.h> + +#include <scsi/scsi_all.h> +#include <scsi/scsi_message.h> +#include <scsi/scsi_debug.h> +#include <scsi/scsiconf.h> + +#include <uvm/uvm_extern.h> + +#define AHC_SHOWSENSE 0x01 +#define AHC_SHOWMISC 0x02 +#define AHC_SHOWCMDS 0x04 + +#if NPCI > 0 +#define AHC_PCI_CONFIG 1 +#endif + +#if 0 +#define AHC_DEBUG AHC_SHOWSENSE | AHC_SHOWMISC | AHC_SHOWCMDS +extern int ahc_debug; +#endif + +#ifdef DEBUG +#define bootverbose 1 +#else +#define bootverbose 0 +#endif +/****************************** Platform Macros *******************************/ + +#define SCSI_IS_SCSIBUS_B(ahc, sc_link) \ + ((sc_link)->scsibus == (ahc)->platform_data->sc_link_b.scsibus) +#define SCSI_SCSI_ID(ahc, sc_link) \ + (SCSI_IS_SCSIBUS_B(ahc, sc_link) ? ahc->our_id_b : ahc->our_id) +#define SCSI_CHANNEL(ahc, sc_link) \ + (SCSI_IS_SCSIBUS_B(ahc, sc_link) ? 'B' : 'A') +#define BUILD_SCSIID(ahc, sc_link, target_id, our_id) \ + ((((target_id) << TID_SHIFT) & TID) | (our_id) \ + | (SCSI_IS_SCSIBUS_B(ahc, sc_link) ? TWIN_CHNLB : 0)) +#define XS_SCSI_ID(xs) \ + ((xs)->sc_link->target) +#define XS_LUN(xs) \ + ((xs)->sc_link->lun) +#define XS_TCL(xs) \ + BUILD_TCL(XS_SCSI_ID(xs), XS_LUN(xs)) + +#ifndef offsetof +#define offsetof(type, member) ((size_t)(&((type *)0)->member)) +#endif + +/* COMPAT CAM to XS stuff */ +#define CAM_DIR_IN SCSI_DATA_IN +#define AC_TRANSFER_NEG 0 +#define AC_SENT_BDR 0 +#define AC_BUS_RESET 0 +#define CAM_BUS_WILDCARD ((int)~0) +#define CAM_TARGET_WILDCARD ((int)~0) +#define CAM_LUN_WILDCARD ((int)~0) + +/* SPI-3 definitions */ +#ifndef MSG_SIMPLE_TASK +#define MSG_SIMPLE_TASK MSG_SIMPLE_Q_TAG +#endif +#ifndef MSG_ORDERED_TASK +#define MSG_ORDERED_TASK MSG_ORDERED_Q_TAG +#endif + +/* FreeBSD to OpenBSD message defs */ +#define MSG_EXT_PPR_QAS_REQ MSG_EXT_PPR_PROT_QAS +#define MSG_EXT_PPR_DT_REQ MSG_EXT_PPR_PROT_DT +#define MSG_EXT_PPR_IU_REQ MSG_EXT_PPR_PROT_IUS + +/* FreeBSD bus_space defines */ +#define BUS_SPACE_MAXSIZE_24BIT 0xFFFFFF +#define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFF +#define BUS_SPACE_MAXSIZE (64 * 1024) /* Maximum supported size */ +#define BUS_SPACE_MAXADDR_24BIT 0xFFFFFF +#define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFF +#define BUS_SPACE_MAXADDR 0xFFFFFFFF + +/* CAM Status field values (From FreeBSD cam.h 1.10 */ +typedef enum { + CAM_REQ_INPROG, /* CCB request is in progress */ + CAM_REQ_CMP, /* CCB request completed without error */ + CAM_REQ_ABORTED, /* CCB request aborted by the host */ + CAM_UA_ABORT, /* Unable to abort CCB request */ + CAM_REQ_CMP_ERR, /* CCB request completed with an error */ + CAM_BUSY, /* CAM subsystem is busy */ + CAM_REQ_INVALID, /* CCB request was invalid */ + CAM_PATH_INVALID, /* Supplied Path ID is invalid */ + CAM_DEV_NOT_THERE, /* SCSI Device Not Installed/there */ + CAM_UA_TERMIO, /* Unable to terminate I/O CCB request */ + CAM_SEL_TIMEOUT, /* Target Selection Timeout */ + CAM_CMD_TIMEOUT, /* Command timeout */ + CAM_SCSI_STATUS_ERROR, /* SCSI error, look at error code in CCB */ + CAM_MSG_REJECT_REC, /* Message Reject Received */ + CAM_SCSI_BUS_RESET, /* SCSI Bus Reset Sent/Received */ + CAM_UNCOR_PARITY, /* Uncorrectable parity error occurred */ + CAM_AUTOSENSE_FAIL = 0x10,/* Autosense: request sense cmd fail */ + CAM_NO_HBA, /* No HBA Detected error */ + CAM_DATA_RUN_ERR, /* Data Overrun error */ + CAM_UNEXP_BUSFREE, /* Unexpected Bus Free */ + CAM_SEQUENCE_FAIL, /* Target Bus Phase Sequence Failure */ + CAM_CCB_LEN_ERR, /* CCB length supplied is inadequate */ + CAM_PROVIDE_FAIL, /* Unable to provide requested capability */ + CAM_BDR_SENT, /* A SCSI BDR msg was sent to target */ + CAM_REQ_TERMIO, /* CCB request terminated by the host */ + CAM_UNREC_HBA_ERROR, /* Unrecoverable Host Bus Adapter Error */ + CAM_REQ_TOO_BIG, /* The request was too large for this host */ + CAM_REQUEUE_REQ, /* + * This request should be requeued to preserve + * transaction ordering. This typically occurs + * when the SIM recognizes an error that should + * freeze the queue and must place additional + * requests for the target at the sim level + * back into the XPT queue. + */ + CAM_IDE = 0x33, /* Initiator Detected Error */ + CAM_RESRC_UNAVAIL, /* Resource Unavailable */ + CAM_UNACKED_EVENT, /* Unacknowledged Event by Host */ + CAM_MESSAGE_RECV, /* Message Received in Host Target Mode */ + CAM_INVALID_CDB, /* Invalid CDB received in Host Target Mode */ + CAM_LUN_INVALID, /* Lun supplied is invalid */ + CAM_TID_INVALID, /* Target ID supplied is invalid */ + CAM_FUNC_NOTAVAIL, /* The requested function is not available */ + CAM_NO_NEXUS, /* Nexus is not established */ + CAM_IID_INVALID, /* The initiator ID is invalid */ + CAM_CDB_RECVD, /* The SCSI CDB has been received */ + CAM_LUN_ALRDY_ENA, /* The LUN is already enabled for target mode */ + CAM_SCSI_BUSY, /* SCSI Bus Busy */ + + CAM_DEV_QFRZN = 0x40, /* The DEV queue is frozen w/this err */ + + /* Autosense data valid for target */ + CAM_AUTOSNS_VALID = 0x80, + CAM_RELEASE_SIMQ = 0x100,/* SIM ready to take more commands */ + CAM_SIM_QUEUED = 0x200,/* SIM has this command in it's queue */ + + CAM_STATUS_MASK = 0x3F, /* Mask bits for just the status # */ + + /* Target Specific Adjunct Status */ + CAM_SENT_SENSE = 0x40000000 /* sent sense with status */ +} cam_status; + +/* FreeBSD to OpenBSD status defs */ +#define SCSI_STATUS_CHECK_COND SCSI_CHECK +#define SCSI_STATUS_CMD_TERMINATED SCSI_TERMINATED +#define SCSI_STATUS_OK SCSI_OK +#define SCSI_REV_2 SC_SCSI_2 + +/************************* Forward Declarations *******************************/ +typedef struct pci_attach_args * ahc_dev_softc_t; +typedef struct scsi_xfer * ahc_io_ctx_t; + +/***************************** Bus Space/DMA **********************************/ + +/* XXX Need to update Bus DMA for partial map syncs */ +#define ahc_dmamap_sync(ahc, dma_tag, dmamap, offset, len, op) \ + bus_dmamap_sync(dma_tag, dmamap, offset, len, op) + +/************************ Tunable Driver Parameters **************************/ +/* + * The number of dma segments supported. The sequencer can handle any number + * of physically contiguous S/G entrys. To reduce the driver's memory + * consumption, we limit the number supported to be sufficient to handle + * the largest mapping supported by the kernel, MAXPHYS. Assuming the + * transfer is as fragmented as possible and unaligned, this turns out to + * be the number of paged sized transfers in MAXPHYS plus an extra element + * to handle any unaligned residual. The sequencer fetches SG elements + * in cacheline sized chucks, so make the number per-transaction an even + * multiple of 16 which should align us on even the largest of cacheline + * boundaries. + */ +#define AHC_NSEG (roundup(btoc(MAXPHYS) + 1, 16)) + +/* This driver does NOT supports target mode */ +#ifdef AHC_TARGET_MODE +#undef AHC_TARGET_MODE +#endif + +/***************************** Core Includes **********************************/ +#include <dev/ic/aic7xxx.h> + +/************************** Softc/SCB Platform Data ***************************/ +struct ahc_platform_data { + bus_dma_segment_t pshared_data_seg; + int pshared_data_nseg; + int pshared_data_size; +#define shared_data_seg platform_data->pshared_data_seg +#define shared_data_nseg platform_data->pshared_data_nseg +#define shared_data_size platform_data->pshared_data_size + /* + * Hooks into the XPT. + */ + struct scsi_link sc_link; + /* Second bus for Twin channel cards */ + struct scsi_link sc_link_b; + + void *ih; + int channel_b_primary; + + /* for pci error interrupts */ + int(*pci_intr_func)(struct ahc_softc *); + + /* queue management */ + int queue_blocked; + u_int16_t devqueue_blocked[AHC_NUM_TARGETS]; + LIST_HEAD(, scsi_xfer) sc_xxxq; /* XXX software request queue */ + struct scsi_xfer *sc_xxxqlast; /* last entry in queue */ + + u_int8_t inited_targets[AHC_NUM_TARGETS]; + u_int8_t inited_channels[2]; +}; + +typedef enum { + SCB_FREEZE_QUEUE = 0x0001, + SCB_REQUEUE = 0x0002 +} scb_pflag; + +struct scb_platform_data { + scb_pflag flags; +}; + +/* + * Some ISA devices (e.g. on a VLB) can perform 32-bit DMA. This + * flag is passed to bus_dmamap_create() to indicate that fact. + */ +#ifndef ISABUS_DMA_32BIT +#define ISABUS_DMA_32BIT BUS_DMA_BUS1 +#endif + +/********************************* Byte Order *********************************/ +#define ahc_htobe16(x) htobe16(x) +#define ahc_htobe32(x) htobe32(x) +#define ahc_htobe64(x) htobe64(x) +#define ahc_htole16(x) htole16(x) +#define ahc_htole32(x) htole32(x) +#define ahc_htole64(x) htole64(x) + +#define ahc_be16toh(x) betoh16(x) +#define ahc_be32toh(x) betoh32(x) +#define ahc_be64toh(x) betoh64(x) +#define ahc_le16toh(x) letoh16(x) +#define ahc_le32toh(x) letoh32(x) +#define ahc_le64toh(x) letoh64(x) + +/*************************** Device Access ************************************/ +#define ahc_inb(ahc, port) \ + bus_space_read_1((ahc)->tag, (ahc)->bsh, port) + +#define ahc_outb(ahc, port, value) \ + bus_space_write_1((ahc)->tag, (ahc)->bsh, port, value) + +#define ahc_outsb(ahc, port, valp, count) \ + bus_space_write_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) + +#define ahc_insb(ahc, port, valp, count) \ + bus_space_read_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) + +static __inline void ahc_flush_device_writes(struct ahc_softc *); + +static __inline void +ahc_flush_device_writes(ahc) + struct ahc_softc *ahc; +{ + /* XXX Is this sufficient for all architectures??? */ + ahc_inb(ahc, INTSTAT); +} + +/**************************** Locking Primitives ******************************/ +/* Lock protecting internal data structures */ +static __inline void ahc_lockinit(struct ahc_softc *); +static __inline void ahc_lock(struct ahc_softc *, int *flags); +static __inline void ahc_unlock(struct ahc_softc *, int *flags); + +/* Lock held during command compeletion to the upper layer */ +static __inline void ahc_done_lockinit(struct ahc_softc *); +static __inline void ahc_done_lock(struct ahc_softc *, int *flags); +static __inline void ahc_done_unlock(struct ahc_softc *, int *flags); + +static __inline void +ahc_lockinit(ahc) + struct ahc_softc *ahc; +{ + /* Nothing to do here for OpenBSD */ +} + +static __inline void +ahc_lock(ahc, flags) + struct ahc_softc *ahc; + int *flags; +{ + *flags = splbio(); +} + +static __inline void +ahc_unlock(ahc, flags) + struct ahc_softc *ahc; + int *flags; +{ + splx(*flags); +} + +/* Lock held during command compeletion to the upper layer */ +static __inline void +ahc_done_lockinit(ahc) + struct ahc_softc *ahc; +{ + /* Nothing to do here for OpenBSD */ +} + +static __inline void +ahc_done_lock(ahc, flags) + struct ahc_softc *ahc; + int *flags; +{ + /* Nothing to do here for OpenBSD */ +} + +static __inline void +ahc_done_unlock(ahc, flags) + struct ahc_softc *ahc; + int *flags; +{ + /* Nothing to do here for OpenBSD */ +} + +/****************************** OS Primitives *********************************/ +#define ahc_delay delay + +/************************** Transaction Operations ****************************/ +static __inline void ahc_set_transaction_status(struct scb *, uint32_t); +static __inline void ahc_set_scsi_status(struct scb *, uint32_t); +static __inline uint32_t ahc_get_transaction_status(struct scb *); +static __inline uint32_t ahc_get_scsi_status(struct scb *); +static __inline void ahc_set_transaction_tag(struct scb *, int, u_int); +static __inline u_long ahc_get_transfer_length(struct scb *); +static __inline int ahc_get_transfer_dir(struct scb *); +static __inline void ahc_set_residual(struct scb *, u_long); +static __inline void ahc_set_sense_residual(struct scb *, u_long); +static __inline u_long ahc_get_residual(struct scb *); +static __inline int ahc_perform_autosense(struct scb *); +static __inline uint32_t ahc_get_sense_bufsize(struct ahc_softc*, struct scb*); +static __inline void ahc_freeze_scb(struct scb *scb); +static __inline void ahc_platform_freeze_devq(struct ahc_softc *, struct scb *); +static __inline int ahc_platform_abort_scbs(struct ahc_softc *ahc, int target, + char channel, int lun, u_int tag, + role_t role, uint32_t status); +static __inline void ahc_platform_scb_free(struct ahc_softc *ahc, + struct scb *scb); + +/* + * This is a hack to keep from modifying the main + * driver code as much as possible. This function + * does CAM to SCSI api stuff. + */ +static __inline +void ahc_set_transaction_status(scb, status) + struct scb *scb; + uint32_t status; +{ + /* don't wipe the error */ + if (scb->io_ctx->error == XS_NOERROR){ + switch (status) { + case CAM_CMD_TIMEOUT: + status = XS_TIMEOUT; + break; + case CAM_BDR_SENT: + case CAM_SCSI_BUS_RESET: + status = XS_RESET; + break; + case CAM_UNEXP_BUSFREE: + case CAM_REQ_TOO_BIG: + case CAM_REQ_ABORTED: + case CAM_AUTOSENSE_FAIL: + case CAM_NO_HBA: + status = XS_DRIVER_STUFFUP; + break; + case CAM_SEL_TIMEOUT: + status = XS_SELTIMEOUT; + break; + case CAM_REQUEUE_REQ: + scb->platform_data->flags |= SCB_REQUEUE; + scb->io_ctx->error = XS_NOERROR; + break; + case CAM_SCSI_STATUS_ERROR: + default: + status = scb->io_ctx->error; + break; + } + } else { + status = scb->io_ctx->error; + } + scb->io_ctx->error = status; +} + +static __inline +void ahc_set_scsi_status(scb, status) + struct scb *scb; + uint32_t status; +{ + scb->io_ctx->status = status; +} + +/* + * This is a hack to keep from modifying the main + * driver code as much as possible. + * This function ONLY needs to return weather + * a scsi_xfer is in progress or not. XXX smurph + */ +static __inline +uint32_t ahc_get_transaction_status(scb) + struct scb *scb; +{ + return (scb->io_ctx->flags & ITSDONE ? CAM_REQ_CMP : CAM_REQ_INPROG); +} + +static __inline +uint32_t ahc_get_scsi_status(scb) + struct scb *scb; +{ + return (scb->io_ctx->status); +} + +static __inline +void ahc_set_transaction_tag(scb, enabled, type) + struct scb *scb; + int enabled; + u_int type; +{ + struct scsi_xfer *xs = scb->io_ctx; + switch (type) { + case MSG_SIMPLE_TASK: + if (enabled) + xs->sc_link->quirks &= ~SDEV_NOTAGS; + else + xs->sc_link->quirks |= SDEV_NOTAGS; + break; + } +} + +static __inline +u_long ahc_get_transfer_length(scb) + struct scb *scb; +{ + return (scb->io_ctx->datalen); +} + +static __inline +int ahc_get_transfer_dir(scb) + struct scb *scb; +{ + return (scb->io_ctx->flags & (SCSI_DATA_IN | SCSI_DATA_OUT)); +} + +static __inline +void ahc_set_residual(scb, resid) + struct scb *scb; + u_long resid; +{ + scb->io_ctx->resid = resid; +} + +static __inline +void ahc_set_sense_residual(scb, resid) + struct scb *scb; + u_long resid; +{ + scb->io_ctx->resid = resid; +} + +static __inline +u_long ahc_get_residual(scb) + struct scb *scb; +{ + return (scb->io_ctx->resid); +} + +static __inline +int ahc_perform_autosense(scb) + struct scb *scb; +{ + /* Return true for OpenBSD */ + return (1); +} + +static __inline uint32_t +ahc_get_sense_bufsize(ahc, scb) + struct ahc_softc *ahc; + struct scb *scb; +{ + return (sizeof(struct scsi_sense_data)); +} + +static __inline void +ahc_freeze_scb(scb) + struct scb *scb; +{ + struct scsi_xfer *xs = scb->io_ctx; + struct ahc_softc *ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; + int target; + + target = xs->sc_link->target; + if (!(scb->platform_data->flags & SCB_FREEZE_QUEUE)) { + ahc->platform_data->devqueue_blocked[target]++; + scb->platform_data->flags |= SCB_FREEZE_QUEUE; + } +} + +static __inline void +ahc_platform_freeze_devq(ahc, scb) + struct ahc_softc *ahc; + struct scb *scb; +{ + /* Nothing to do here for OpenBSD */ +} + +static __inline int +ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status) + struct ahc_softc *ahc; + int target, lun; + char channel; + u_int tag; + role_t role; + uint32_t status; +{ + /* Nothing to do here for OpenBSD */ + return (0); +} + +static __inline void +ahc_platform_scb_free(ahc, scb) + struct ahc_softc *ahc; + struct scb *scb; +{ + int s; + + ahc_lock(ahc, &s); + + if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0 || + (scb->flags & SCB_RECOVERY_SCB) != 0) { + ahc->flags &= ~AHC_RESOURCE_SHORTAGE; + ahc->platform_data->queue_blocked = 0; + } + + timeout_del(&scb->io_ctx->stimeout); + + ahc_unlock(ahc, &s); +} + +/********************************** PCI ***************************************/ +#ifdef AHC_PCI_CONFIG +int ahc_pci_map_registers(struct ahc_softc *ahc); +int ahc_pci_map_int(struct ahc_softc *ahc); + +typedef enum +{ + AHC_POWER_STATE_D0, + AHC_POWER_STATE_D1, + AHC_POWER_STATE_D2, + AHC_POWER_STATE_D3 +} ahc_power_state; + +void ahc_power_state_change(struct ahc_softc *ahc, + ahc_power_state new_state); + +static __inline uint32_t ahc_pci_read_config(ahc_dev_softc_t pci, + int reg, int width); +static __inline void ahc_pci_write_config(ahc_dev_softc_t pci, + int reg, uint32_t value, + int width); +static __inline u_int ahc_get_pci_function(ahc_dev_softc_t); +static __inline u_int ahc_get_pci_slot(ahc_dev_softc_t); +static __inline u_int ahc_get_pci_bus(ahc_dev_softc_t); + + +static __inline uint32_t +ahc_pci_read_config(pa, reg, width) + ahc_dev_softc_t pa; + int reg, width; +{ + return (pci_conf_read(pa->pa_pc, pa->pa_tag, reg)); +} + +static __inline void +ahc_pci_write_config(pa, reg, value, width) + ahc_dev_softc_t pa; + uint32_t value; + int reg, width; +{ + pci_conf_write(pa->pa_pc, pa->pa_tag, reg, value); +} + +static __inline u_int +ahc_get_pci_function(pa) + ahc_dev_softc_t pa; +{ + return (pa->pa_function); +} + +static __inline u_int +ahc_get_pci_slot(pa) + ahc_dev_softc_t pa; +{ + return (pa->pa_device); +} + +static __inline u_int +ahc_get_pci_bus(pa) + ahc_dev_softc_t pa; +{ + return (pa->pa_bus); +} +#endif + +/******************************** VL/EISA *************************************/ +int aic7770_map_registers(struct ahc_softc *ahc); +int aic7770_map_int(struct ahc_softc *ahc, int irq); + +/********************************* Debug **************************************/ +static __inline void ahc_print_path(struct ahc_softc *, struct scb *); +static __inline void ahc_platform_dump_card_state(struct ahc_softc *ahc); + +static __inline void +ahc_print_path(ahc, scb) + struct ahc_softc *ahc; + struct scb *scb; +{ + sc_print_addr(scb->io_ctx->sc_link); +} + +static __inline void +ahc_platform_dump_card_state(ahc) + struct ahc_softc *ahc; +{ + /* Nothing to do here for OpenBSD */ +} +/**************************** Transfer Settings *******************************/ +void ahc_notify_xfer_settings_change(struct ahc_softc *, + struct ahc_devinfo *); +void ahc_platform_set_tags(struct ahc_softc *, struct ahc_devinfo *, + ahc_queue_alg); + +/************************* Initialization/Teardown ****************************/ +int ahc_platform_alloc(struct ahc_softc *ahc, void *platform_arg); +void ahc_platform_free(struct ahc_softc *ahc); +int ahc_attach(struct ahc_softc *); +int ahc_softc_comp(struct ahc_softc *lahc, struct ahc_softc *rahc); + +/****************************** Interrupts ************************************/ +int ahc_platform_intr(void *); +static __inline void ahc_platform_flushwork(struct ahc_softc *ahc); + +static __inline void +ahc_platform_flushwork(ahc) + struct ahc_softc *ahc; +{ + /* Nothing to do here for OpenBSD */ +} + +/************************ Misc Function Declarations **************************/ +void ahc_done(struct ahc_softc *ahc, struct scb *scb); +void ahc_send_async(struct ahc_softc *, char /*channel*/, + u_int /*target*/, u_int /*lun*/, u_int, void *arg); + +int ahc_createdmamem(struct ahc_softc *ahc, bus_dma_tag_t dmat, + int size, bus_dmamap_t *mapp, caddr_t *vaddr, + bus_addr_t *baddr, bus_dma_segment_t *segs, + int *nseg, const char *what); +void ahc_freedmamem(bus_dma_tag_t tag, int size, + bus_dmamap_t map, caddr_t vaddr, + bus_dma_segment_t *seg, int nseg); +void ahc_force_neg(struct ahc_softc *ahc); + +/* + * Routines to manage a scsi_xfer into the software queue. + * We overload xs->free_list to to ensure we don't run into a queue + * resource shortage, and keep a pointer to the last entry around + * to make insertion O(C). + */ +static __inline void ahc_list_insert_before(struct ahc_softc *ahc, + struct scsi_xfer *xs, + struct scsi_xfer *next_xs); +static __inline void ahc_list_insert_head(struct ahc_softc *ahc, + struct scsi_xfer *xs); +static __inline void ahc_list_insert_tail(struct ahc_softc *ahc, + struct scsi_xfer *xs); +static __inline void ahc_list_remove(struct ahc_softc *ahc, + struct scsi_xfer *xs); +static __inline struct scsi_xfer *ahc_list_next(struct ahc_softc *ahc, + struct scsi_xfer *xs); +static __inline struct scsi_xfer *ahc_first_xs(struct ahc_softc *); + +static __inline void +ahc_list_insert_before(ahc, xs, next_xs) + struct ahc_softc *ahc; + struct scsi_xfer *xs; + struct scsi_xfer *next_xs; +{ + LIST_INSERT_BEFORE(xs, next_xs, free_list); + +} + +static __inline void +ahc_list_insert_head(ahc, xs) + struct ahc_softc *ahc; + struct scsi_xfer *xs; +{ + if (ahc->platform_data->sc_xxxq.lh_first == NULL) + ahc->platform_data->sc_xxxqlast = xs; + LIST_INSERT_HEAD(&ahc->platform_data->sc_xxxq, xs, free_list); + return; +} + +static __inline void +ahc_list_insert_tail(ahc, xs) + struct ahc_softc *ahc; + struct scsi_xfer *xs; +{ + if (ahc->platform_data->sc_xxxq.lh_first == NULL){ + ahc->platform_data->sc_xxxqlast = xs; + LIST_INSERT_HEAD(&ahc->platform_data->sc_xxxq, xs, free_list); + return; + } + LIST_INSERT_AFTER(ahc->platform_data->sc_xxxqlast, xs, free_list); + ahc->platform_data->sc_xxxqlast = xs; +} + +static __inline void +ahc_list_remove(ahc, xs) + struct ahc_softc *ahc; + struct scsi_xfer *xs; +{ + struct scsi_xfer *lxs; + if (xs == ahc->platform_data->sc_xxxqlast) { + lxs = ahc->platform_data->sc_xxxq.lh_first; + while (lxs != NULL) { + if (LIST_NEXT(lxs, free_list) == ahc->platform_data->sc_xxxqlast) { + ahc->platform_data->sc_xxxqlast = lxs; + break; + } + lxs = LIST_NEXT(xs, free_list); + } + } + + LIST_REMOVE(xs, free_list); + if (ahc->platform_data->sc_xxxq.lh_first == NULL) + ahc->platform_data->sc_xxxqlast = NULL; +} + +static __inline struct scsi_xfer * +ahc_list_next(ahc, xs) + struct ahc_softc *ahc; + struct scsi_xfer *xs; +{ + return(LIST_NEXT(xs, free_list)); +} + +/* + * Pick the first xs for a non-blocked target. + */ +static __inline struct scsi_xfer * +ahc_first_xs(ahc) + struct ahc_softc *ahc; +{ + int target; + struct scsi_xfer *xs = ahc->platform_data->sc_xxxq.lh_first; + + if (ahc->platform_data->queue_blocked) + return NULL; + + while (xs != NULL) { + target = xs->sc_link->target; + if (ahc->platform_data->devqueue_blocked[target] == 0 && + ahc_index_busy_tcl(ahc, XS_TCL(xs)) == SCB_LIST_NULL) + break; + xs = LIST_NEXT(xs, free_list); + } + + return xs; +} +#endif /* _AIC7XXX_OPENBSD_H_ */ + diff --git a/sys/dev/ic/aic7xxxreg.h b/sys/dev/ic/aic7xxxreg.h index 36ae18f9d06..dd9b17fc8c9 100644 --- a/sys/dev/ic/aic7xxxreg.h +++ b/sys/dev/ic/aic7xxxreg.h @@ -1,5 +1,10 @@ +/* $OpenBSD: aic7xxxreg.h,v 1.10 2002/06/28 00:34:54 smurph Exp $ */ /* - * DO NOT EDIT - This file is automatically generated. + * DO NOT EDIT - This file is automatically generated + * from the following source files: + * + * $Id: aic7xxxreg.h,v 1.10 2002/06/28 00:34:54 smurph Exp $ + * $Id: aic7xxxreg.h,v 1.10 2002/06/28 00:34:54 smurph Exp $ */ #define SCSISEQ 0x00 @@ -23,6 +28,15 @@ #define ACTNEGEN 0x02 #define STPWEN 0x01 +#define SCSISIGI 0x03 +#define P_DATAIN_DT 0x60 +#define P_DATAOUT_DT 0x20 +#define ATNI 0x10 +#define SELI 0x08 +#define BSYI 0x04 +#define REQI 0x02 +#define ACKI 0x01 + #define SCSISIGO 0x03 #define CDO 0x80 #define IOO 0x40 @@ -33,20 +47,13 @@ #define REQO 0x02 #define ACKO 0x01 -#define SCSISIGI 0x03 -#define ATNI 0x10 -#define SELI 0x08 -#define BSYI 0x04 -#define REQI 0x02 -#define ACKI 0x01 - #define SCSIRATE 0x04 #define WIDEXFER 0x80 #define SXFR 0x70 #define ENABLE_CRC 0x40 #define SINGLE_EDGE 0x10 -#define SOFS 0x0f #define SXFR_ULTRA2 0x0f +#define SOFS 0x0f #define SCSIID 0x05 #define SCSIOFFSET 0x05 @@ -56,8 +63,6 @@ #define SCSIDATH 0x07 -#define STCNT 0x08 - #define OPTIONMODE 0x08 #define AUTORATEEN 0x80 #define AUTOACKEN 0x40 @@ -69,12 +74,15 @@ #define AUTO_MSGOUT_DE 0x02 #define DIS_MSGIN_DUALEDGE 0x01 +#define STCNT 0x08 + #define TARGCRCCNT 0x0a #define CLRSINT0 0x0b #define CLRSELDO 0x40 #define CLRSELDI 0x20 #define CLRSELINGO 0x10 +#define CLRIOERR 0x08 #define CLRSWRAP 0x08 #define CLRSPIORDY 0x02 @@ -110,15 +118,19 @@ #define SSTAT2 0x0d #define OVERRUN 0x80 +#define SHVALID 0x40 #define SFCNT 0x1f #define EXP_ACTIVE 0x10 +#define CRCVALERR 0x08 +#define CRCENDERR 0x04 +#define CRCREQERR 0x02 +#define DUAL_EDGE_ERR 0x01 #define SSTAT3 0x0e #define SCSICNT 0xf0 #define OFFCNT 0x0f #define SCSIID_ULTRA2 0x0f -#define OID 0x0f #define SIMODE0 0x10 #define ENSELDO 0x40 @@ -184,12 +196,12 @@ #define BRDDAT5 0x20 #define BRDDAT4 0x10 #define BRDSTB 0x10 -#define BRDCS 0x08 #define BRDDAT3 0x08 +#define BRDCS 0x08 #define BRDDAT2 0x04 #define BRDRW 0x04 -#define BRDRW_ULTRA2 0x02 #define BRDCTL1 0x02 +#define BRDRW_ULTRA2 0x02 #define BRDCTL0 0x01 #define BRDSTB_ULTRA2 0x01 @@ -208,36 +220,44 @@ #define DIAGLEDON 0x40 #define AUTOFLUSHDIS 0x20 #define ENAB40 0x08 +#define SELBUSB 0x08 #define ENAB20 0x04 #define SELWIDE 0x02 #define XCVR 0x01 #define SRAM_BASE 0x20 +#define BUSY_TARGETS 0x20 #define TARG_SCSIRATE 0x20 -#define CMDSIZE_TABLE 0x20 #define ULTRA_ENB 0x30 +#define CMDSIZE_TABLE 0x30 #define DISC_DSB 0x32 -#define MSG_OUT 0x34 +#define CMDSIZE_TABLE_TAIL 0x34 + +#define MWI_RESIDUAL 0x38 -#define DMAPARAMS 0x35 +#define NEXT_QUEUED_SCB 0x39 + +#define MSG_OUT 0x3a + +#define DMAPARAMS 0x3b #define PRELOADEN 0x80 #define WIDEODD 0x40 #define SCSIEN 0x20 #define SDMAENACK 0x10 #define SDMAEN 0x10 -#define HDMAEN 0x08 #define HDMAENACK 0x08 +#define HDMAEN 0x08 #define DIRECTION 0x04 #define FIFOFLUSH 0x02 #define FIFORESET 0x01 -#define SEQ_FLAGS 0x36 +#define SEQ_FLAGS 0x3c #define IDENTIFY_SEEN 0x80 -#define SCBPTR_VALID 0x40 +#define TARGET_CMD_IS_TAGGED 0x40 #define DPHASE 0x20 #define TARG_CMD_PENDING 0x10 #define CMDPHASE_PENDING 0x08 @@ -245,15 +265,13 @@ #define SPHASE_PENDING 0x02 #define NO_DISCONNECT 0x01 -#define SAVED_TCL 0x37 - -#define SG_COUNT 0x38 +#define SAVED_SCSIID 0x3d -#define SG_NEXT 0x39 +#define SAVED_LUN 0x3e -#define LASTPHASE 0x3d -#define P_MESGIN 0xe0 +#define LASTPHASE 0x3f #define PHASE_MASK 0xe0 +#define P_MESGIN 0xe0 #define P_STATUS 0xc0 #define P_MESGOUT 0xa0 #define P_COMMAND 0x80 @@ -264,30 +282,30 @@ #define P_BUSFREE 0x01 #define P_DATAOUT 0x00 -#define WAITING_SCBH 0x3e +#define WAITING_SCBH 0x40 -#define DISCONNECTED_SCBH 0x3f +#define DISCONNECTED_SCBH 0x41 -#define FREE_SCBH 0x40 +#define FREE_SCBH 0x42 -#define HSCB_ADDR 0x41 +#define COMPLETE_SCBH 0x43 -#define SCBID_ADDR 0x45 +#define HSCB_ADDR 0x44 -#define TMODE_CMDADDR 0x49 +#define SHARED_DATA_ADDR 0x48 -#define KERNEL_QINPOS 0x4d +#define KERNEL_QINPOS 0x4c -#define QINPOS 0x4e +#define QINPOS 0x4d -#define QOUTPOS 0x4f +#define QOUTPOS 0x4e -#define KERNEL_TQINPOS 0x50 +#define KERNEL_TQINPOS 0x4f -#define TQINPOS 0x51 +#define TQINPOS 0x50 -#define ARG_1 0x52 -#define RETURN_1 0x52 +#define ARG_1 0x51 +#define RETURN_1 0x51 #define SEND_MSG 0x80 #define SEND_SENSE 0x40 #define SEND_REJ 0x20 @@ -296,16 +314,12 @@ #define CONT_MSG_LOOP 0x04 #define CONT_TARG_SESSION 0x02 -#define ARG_2 0x53 -#define RETURN_2 0x53 - -#define LAST_MSG 0x54 - -#define PREFETCH_CNT 0x55 +#define ARG_2 0x52 +#define RETURN_2 0x52 -#define TARGET_MSG_REQUEST 0x56 +#define LAST_MSG 0x53 -#define SCSISEQ_TEMPLATE 0x58 +#define SCSISEQ_TEMPLATE 0x54 #define ENSELO 0x40 #define ENSELI 0x20 #define ENRSELI 0x10 @@ -313,7 +327,12 @@ #define ENAUTOATNI 0x04 #define ENAUTOATNP 0x02 -#define DATA_COUNT_ODD 0x59 +#define DATA_COUNT_ODD 0x55 + +#define INITIATOR_TAG 0x56 + +#define SEQ_FLAGS2 0x57 +#define SCB_DMA 0x01 #define SCSICONF 0x5a #define TERM_ENB 0x80 @@ -322,7 +341,9 @@ #define HWSCSIID 0x0f #define HSCSIID 0x07 -#define INITIATOR_TAG 0x5a +#define INTDEF 0x5c +#define EDGE_TRIG 0x80 +#define VECTOR 0x0f #define HOSTCONF 0x5d @@ -356,10 +377,10 @@ #define ALLONES 0x69 -#define ALLZEROS 0x6a - #define NONE 0x6a +#define ALLZEROS 0x6a + #define FLAGS 0x6b #define ZERO 0x02 #define CARRY 0x01 @@ -392,8 +413,14 @@ #define BOFF 0xf0 #define BON 0x0f +#define DSCOMMAND1 0x85 +#define DSLATT 0xfc +#define HADDLDSEL1 0x02 +#define HADDLDSEL0 0x01 + #define BUSSPD 0x86 #define DFTHRSH 0xc0 +#define DFTHRSH_75 0x80 #define STBOFF 0x38 #define STBON 0x07 @@ -412,8 +439,8 @@ #define IRQMS 0x08 #define PAUSE 0x04 #define INTEN 0x02 -#define CHIPRST 0x01 #define CHIPRSTACK 0x01 +#define CHIPRST 0x01 #define HADDR 0x88 @@ -423,15 +450,17 @@ #define INTSTAT 0x91 #define SEQINT_MASK 0xf1 -#define DATA_OVERRUN 0xf1 -#define MSGIN_PHASEMIS 0xe1 -#define TRACEPOINT 0xd1 -#define PERR_DETECTED 0xb1 -#define HOST_MSG_LOOP 0xa1 -#define TRACE_POINT 0x91 -#define RESIDUAL 0x81 +#define OUT_OF_RANGE 0xe1 +#define NO_FREE_SCB 0xd1 +#define SCB_MISMATCH 0xc1 +#define MISSED_BUSFREE 0xb1 +#define MKMSG_FAILED 0xa1 +#define DATA_OVERRUN 0x91 +#define PERR_DETECTED 0x81 #define BAD_STATUS 0x71 -#define UPDATE_TMSG_REQ 0x61 +#define HOST_MSG_LOOP 0x61 +#define PDATA_REINIT 0x51 +#define IGN_WIDE_RES 0x41 #define NO_MATCH 0x31 #define NO_IDENT 0x21 #define SEND_REJECT 0x11 @@ -439,15 +468,8 @@ #define BRKADRINT 0x08 #define SCSIINT 0x04 #define CMDCMPLT 0x02 -#define BAD_PHASE 0x01 #define SEQINT 0x01 - -#define CLRINT 0x92 -#define CLRPARERR 0x10 -#define CLRBRKADRINT 0x08 -#define CLRSCSIINT 0x04 -#define CLRCMDINT 0x02 -#define CLRSEQINT 0x01 +#define BAD_PHASE 0x01 #define ERROR 0x92 #define CIOPARERR 0x80 @@ -459,11 +481,19 @@ #define ILLSADDR 0x02 #define ILLHADDR 0x01 +#define CLRINT 0x92 +#define CLRPARERR 0x10 +#define CLRBRKADRINT 0x08 +#define CLRSCSIINT 0x04 +#define CLRCMDINT 0x02 +#define CLRSEQINT 0x01 + #define DFCNTRL 0x93 #define DFSTATUS 0x94 #define PRELOAD_AVAIL 0x80 -#define DWORDEMP 0x20 +#define DFCACHETH 0x40 +#define FIFOQWDEMP 0x20 #define MREQPEND 0x10 #define HDONE 0x08 #define DFTHRESH 0x04 @@ -501,75 +531,79 @@ #define COMMAND_PHASE 0x10 #define MSG_IN_PHASE 0x08 #define MSG_OUT_PHASE 0x04 +#define DATA_PHASE_MASK 0x03 #define DATA_IN_PHASE 0x02 #define DATA_OUT_PHASE 0x01 #define SFUNCT 0x9f #define ALT_MODE 0x80 -#define SCB_CONTROL 0xa0 -#define TARGET_SCB 0x80 -#define DISCENB 0x40 -#define TAG_ENB 0x20 -#define MK_MESSAGE 0x10 -#define ULTRAENB 0x08 -#define DISCONNECTED 0x04 -#define SCB_TAG_TYPE 0x03 +#define SCB_CDB_PTR 0xa0 +#define SCB_TARGET_INFO 0xa0 +#define SCB_RESIDUAL_DATACNT 0xa0 +#define SCB_CDB_STORE 0xa0 #define SCB_BASE 0xa0 -#define SCB_TCL 0xa1 -#define TID 0xf0 -#define SELBUSB 0x08 -#define LID 0x07 - -#define SCB_TARGET_STATUS 0xa2 +#define SCB_RESIDUAL_SGPTR 0xa4 -#define SCB_SGCOUNT 0xa3 +#define SCB_SCSI_STATUS 0xa8 -#define SCB_SGPTR 0xa4 - -#define SCB_RESID_SGCNT 0xa8 - -#define SCB_RESID_DCNT 0xa9 +#define SCB_CDB_STORE_PAD 0xa9 #define SCB_DATAPTR 0xac #define SCB_DATACNT 0xb0 +#define SG_LAST_SEG 0x80 +#define SG_HIGH_ADDR_BITS 0x7f + +#define SCB_SGPTR 0xb4 +#define SG_RESID_VALID 0x04 +#define SG_FULL_RESID 0x02 +#define SG_LIST_NULL 0x01 -#define SCB_CMDPTR 0xb4 -#define SCB_TARGET_PHASES 0xb4 -#define TARGET_DATA_IN 0x01 +#define SCB_CONTROL 0xb8 +#define TARGET_SCB 0x80 +#define DISCENB 0x40 +#define TAG_ENB 0x20 +#define MK_MESSAGE 0x10 +#define ULTRAENB 0x08 +#define DISCONNECTED 0x04 +#define SCB_TAG_TYPE 0x03 -#define SCB_CMDLEN 0xb8 -#define SCB_INITIATOR_TAG 0xb8 +#define SCB_SCSIID 0xb9 +#define TID 0xf0 +#define TWIN_CHNLB 0x80 +#define TWIN_TID 0x70 +#define OID 0x0f -#define SCB_TAG 0xb9 +#define SCB_LUN 0xba +#define LID 0xff -#define SCB_NEXT 0xba +#define SCB_TAG 0xbb -#define SCB_SCSIRATE 0xbb +#define SCB_CDB_LEN 0xbc -#define SCB_SCSIOFFSET 0xbc +#define SCB_SCSIRATE 0xbd -#define SCB_SPARE 0xbd +#define SCB_SCSIOFFSET 0xbe -#define SCB_CMDSTORE 0xc0 +#define SCB_NEXT 0xbf #define SEECTL_2840 0xc0 #define CS_2840 0x04 #define CK_2840 0x02 #define DO_2840 0x01 +#define SCB_64_SPARE 0xc0 + #define STATUS_2840 0xc1 #define EEPROM_TF 0x80 #define BIOS_SEL 0x60 #define ADSEL 0x1e #define DI_2840 0x01 -#define SCB_CMDSTORE_BUSADDR 0xd0 - -#define SCB_64BYTE_SPARE 0xd4 +#define SCB_64_BTT 0xd0 #define CCHADDR 0xe0 @@ -582,7 +616,7 @@ #define CCSGCTL 0xeb #define CCSGDONE 0x80 #define CCSGEN 0x08 -#define FLAG 0x02 +#define SG_FETCH_NEEDED 0x02 #define CCSGRESET 0x01 #define CCSCBRAM 0xec @@ -636,36 +670,48 @@ #define RD_DFTHRSH_MIN 0x00 #define WR_DFTHRSH_MIN 0x00 -#define SG_CACHEPTR 0xfc -#define SG_USER_DATA 0xfc +#define SG_CACHE_SHADOW 0xfc +#define SG_ADDR_MASK 0xf8 +#define ODD_SEG 0x04 #define LAST_SEG 0x02 #define LAST_SEG_DONE 0x01 +#define SG_CACHE_PRE 0xfc + +#define HOST_MSG 0xff +#define BUS_32_BIT 0x02 #define CMD_GROUP_CODE_SHIFT 0x05 #define BUS_8_BIT 0x00 -#define QOUTFIFO_OFFSET 0x00 #define CCSGRAM_MAXSEGS 0x10 -#define SCB_64BYTE_SIZE 0x30 +#define TARGET_DATA_IN 0x01 #define STATUS_QUEUE_FULL 0x28 #define STATUS_BUSY 0x08 -#define TQINFIFO_UPDATE_CNT 0x20 -#define TCL_TARGET_SHIFT 0x04 #define MAX_OFFSET_8BIT 0x0f #define BUS_16_BIT 0x01 -#define QINFIFO_OFFSET 0x01 -#define SCB_32BYTE_SIZE 0x1c +#define TID_SHIFT 0x04 +#define SCB_DOWNLOAD_SIZE_64 0x30 +#define SCB_UPLOAD_SIZE 0x20 #define HOST_MAILBOX_SHIFT 0x04 +#define SCB_INITIATOR_TAG 0x03 +#define SCB_TARGET_STATUS 0x02 +#define SCB_TARGET_DATA_DIR 0x01 +#define SCB_TARGET_PHASES 0x00 #define MAX_OFFSET_ULTRA2 0x7f #define MAX_OFFSET_16BIT 0x08 -#define UNTAGGEDSCB_OFFSET 0x02 #define TARGET_CMD_CMPLT 0xfe #define SCB_LIST_NULL 0xff #define SG_SIZEOF 0x08 +#define SCB_DOWNLOAD_SIZE 0x20 #define SEQ_MAILBOX_SHIFT 0x00 -#define HOST_MSG 0xff -#define BUS_32_BIT 0x02 #define CCSGADDR_MAX 0x80 /* Downloaded Constant Definitions */ +#define SG_PREFETCH_ADDR_MASK 0x06 +#define SG_PREFETCH_ALIGN_MASK 0x05 +#define QOUTFIFO_OFFSET 0x00 +#define SG_PREFETCH_CNT 0x04 +#define INVERTED_CACHESIZE_MASK 0x03 +#define CACHESIZE_MASK 0x02 +#define QINFIFO_OFFSET 0x01 diff --git a/sys/dev/ic/smc93cx6.c b/sys/dev/ic/smc93cx6.c index 564a4237007..870d58c7656 100644 --- a/sys/dev/ic/smc93cx6.c +++ b/sys/dev/ic/smc93cx6.c @@ -1,4 +1,4 @@ -/* $OpenBSD: smc93cx6.c,v 1.9 2002/03/19 02:49:20 millert Exp $ */ +/* $OpenBSD: smc93cx6.c,v 1.10 2002/06/28 00:34:54 smurph Exp $ */ /* $FreeBSD: sys/dev/aic7xxx/93cx6.c,v 1.5 2000/01/07 23:08:17 gibbs Exp $ */ /* * Interface for the 93C66/56/46/26/06 serial eeprom parts. @@ -29,7 +29,7 @@ * ------------------------------------------------------------------- * READ 1 10 A5 - A0 Reads data stored in memory, * starting at specified address - * EWEN 1 00 11XXXX Write enable must preceed + * EWEN 1 00 11XXXX Write enable must precede * all programming modes * ERASE 1 11 A5 - A0 Erase register A5A4A3A2A1A0 * WRITE 1 01 A5 - A0 D15 - D0 Writes register @@ -62,6 +62,10 @@ #include <machine/bus_pio.h> #endif #include <machine/bus.h> +#if defined(__OpenBSD__) +#include <dev/ic/aic7xxx_openbsd.h> +#endif +#include <dev/ic/aic7xxx_inline.h> #if !(defined(__NetBSD__) || defined(__OpenBSD__)) #include <dev/aic7xxx/93cx6.h> #else @@ -178,3 +182,25 @@ read_seeprom(sd, buf, start_addr, count) #endif return (1); } + +int +verify_cksum(struct seeprom_config *sc) +{ + int i; + int maxaddr; + u_int32_t checksum; + u_int16_t *scarray; + + maxaddr = (sizeof(*sc)/2) - 1; + checksum = 0; + scarray = (uint16_t *)sc; + + for (i = 0; i < maxaddr; i++) + checksum = checksum + scarray[i]; + if (checksum == 0 + || (checksum & 0xFFFF) != sc->checksum) { + return (0); + } else { + return(1); + } +} diff --git a/sys/dev/ic/smc93cx6var.h b/sys/dev/ic/smc93cx6var.h index 564c39a1bca..4272cfa31e7 100644 --- a/sys/dev/ic/smc93cx6var.h +++ b/sys/dev/ic/smc93cx6var.h @@ -1,4 +1,4 @@ -/* $OpenBSD: smc93cx6var.h,v 1.8 2002/03/19 02:49:20 millert Exp $ */ +/* $OpenBSD: smc93cx6var.h,v 1.9 2002/06/28 00:34:54 smurph Exp $ */ /* $FreeBSD: sys/dev/aic7xxx/93cx6.h,v 1.3 1999/12/29 04:35:33 peter Exp $ */ /* * Interface to the 93C46 serial EEPROM that is used to store BIOS @@ -36,6 +36,8 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ +#ifndef _SMC93CX6VAR_H_ +#define _SMC93CX6VAR_H_ #include <sys/param.h> #if !(defined(__NetBSD__) || defined(__OpenBSD__)) @@ -50,8 +52,7 @@ typedef enum { } seeprom_chip_t; struct seeprom_descriptor { - bus_space_tag_t sd_tag; - bus_space_handle_t sd_bsh; + struct ahc_softc *sd_ahc; bus_size_t sd_control_offset; bus_size_t sd_status_offset; bus_size_t sd_dataout_offset; @@ -81,15 +82,21 @@ struct seeprom_descriptor { */ #define SEEPROM_INB(sd) \ - bus_space_read_1(sd->sd_tag, sd->sd_bsh, sd->sd_control_offset) + ahc_inb(sd->sd_ahc, sd->sd_control_offset) #define SEEPROM_OUTB(sd, value) \ - bus_space_write_1(sd->sd_tag, sd->sd_bsh, sd->sd_control_offset, value) +do { \ + ahc_outb(sd->sd_ahc, sd->sd_control_offset, value); \ + ahc_flush_device_writes(sd->sd_ahc); \ +} while(0) + #define SEEPROM_STATUS_INB(sd) \ - bus_space_read_1(sd->sd_tag, sd->sd_bsh, sd->sd_status_offset) + ahc_inb(sd->sd_ahc, sd->sd_status_offset) #define SEEPROM_DATA_INB(sd) \ - bus_space_read_1(sd->sd_tag, sd->sd_bsh, sd->sd_dataout_offset) + ahc_inb(sd->sd_ahc, sd->sd_dataout_offset) int read_seeprom(struct seeprom_descriptor *sd, u_int16_t *buf, bus_size_t start_addr, bus_size_t count); +int verify_cksum(struct seeprom_config *sc); #endif /* _KERNEL */ +#endif /* SMC93CX6VAR_H_ */ |