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-rw-r--r--sys/dev/ic/ar5210.c159
-rw-r--r--sys/dev/ic/ar5210reg.h378
-rw-r--r--sys/dev/ic/ar5210var.h10
-rw-r--r--sys/dev/ic/ar5xxx.c60
-rw-r--r--sys/dev/ic/ar5xxx.h26
-rw-r--r--sys/dev/ic/ath.c6
6 files changed, 323 insertions, 316 deletions
diff --git a/sys/dev/ic/ar5210.c b/sys/dev/ic/ar5210.c
index 674b9c50e56..d5451d7ce4d 100644
--- a/sys/dev/ic/ar5210.c
+++ b/sys/dev/ic/ar5210.c
@@ -1,7 +1,7 @@
-/* $OpenBSD: ar5210.c,v 1.2 2004/11/02 09:31:59 reyk Exp $ */
+/* $OpenBSD: ar5210.c,v 1.3 2004/11/02 14:05:49 reyk Exp $ */
/*
- * Copyright (c) 2004 Reyk Floeter <reyk@vantronix.net>.
+ * Copyright (c) 2004 Reyk Floeter <reyk@vantronix.net>.
*
* All rights reserved.
*
@@ -26,7 +26,7 @@
*/
/*
- * HAL interface for the Atheros AR5000 Wireless LAN chipset
+ * HAL interface for the Atheros AR5000 Wireless LAN chipset
* (AR5210 + AR5110).
*/
@@ -45,8 +45,8 @@ void ar5k_ar5210_init_tx_queue(struct ath_hal *, u_int, HAL_BOOL);
const void ar5k_ar5210_fill(struct ath_hal *);
AR5K_HAL_FUNCTIONS(extern, ar5k_ar5210,);
-
-const void
+
+const void
ar5k_ar5210_fill(hal)
struct ath_hal *hal;
{
@@ -58,8 +58,8 @@ ar5k_ar5210_fill(hal)
AR5K_HAL_FUNCTION(hal, ar5210, getRateTable);
AR5K_HAL_FUNCTION(hal, ar5210, detach);
- /*
- * Reset functions
+ /*
+ * Reset functions
*/
AR5K_HAL_FUNCTION(hal, ar5210, reset);
AR5K_HAL_FUNCTION(hal, ar5210, setPCUConfig);
@@ -141,7 +141,7 @@ ar5k_ar5210_fill(hal)
AR5K_HAL_FUNCTION(hal, ar5210, setKeyCacheEntryMac);
/*
- * Power management functions
+ * Power management functions
*/
AR5K_HAL_FUNCTION(hal, ar5210, setPowerMode);
AR5K_HAL_FUNCTION(hal, ar5210, getPowerMode);
@@ -150,8 +150,8 @@ ar5k_ar5210_fill(hal)
AR5K_HAL_FUNCTION(hal, ar5210, enablePSPoll);
AR5K_HAL_FUNCTION(hal, ar5210, disablePSPoll);
- /*
- * Beacon functions
+ /*
+ * Beacon functions
*/
AR5K_HAL_FUNCTION(hal, ar5210, beaconInit);
AR5K_HAL_FUNCTION(hal, ar5210, setStationBeaconTimers);
@@ -159,7 +159,7 @@ ar5k_ar5210_fill(hal)
AR5K_HAL_FUNCTION(hal, ar5210, waitForBeaconDone);
/*
- * Interrupt functions
+ * Interrupt functions
*/
AR5K_HAL_FUNCTION(hal, ar5210, isInterruptPending);
AR5K_HAL_FUNCTION(hal, ar5210, getPendingInterrupts);
@@ -202,7 +202,7 @@ ar5k_ar5210_attach(device, sc, st, sh, status)
/* Get MAC, PHY and RADIO revisions */
hal->ah_mac_version = 1;
- hal->ah_mac_revision = (AR5K_REG_READ(AR5K_AR5210_SREV) &
+ hal->ah_mac_revision = (AR5K_REG_READ(AR5K_AR5210_SREV) &
AR5K_AR5210_SREV_ID_M);
hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5210_PHY_CHIP_ID) &
0x00ffffffff;
@@ -243,7 +243,7 @@ ar5k_ar5210_nic_reset(hal, val)
val &=
AR5K_AR5210_RC_PCU | AR5K_AR5210_RC_MAC |
AR5K_AR5210_RC_PHY | AR5K_AR5210_RC_DMA;
-
+
mask &=
AR5K_AR5210_RC_PCU | AR5K_AR5210_RC_MAC |
AR5K_AR5210_RC_PHY | AR5K_AR5210_RC_DMA;
@@ -265,8 +265,8 @@ ar5k_ar5210_nic_wakeup(hal, turbo, initial)
HAL_BOOL turbo;
HAL_BOOL initial;
{
- /*
- * Reset and wakeup the device
+ /*
+ * Reset and wakeup the device
*/
if(initial == AH_TRUE) {
@@ -286,7 +286,7 @@ ar5k_ar5210_nic_wakeup(hal, turbo, initial)
}
/* ...enable Atheros turbo mode if requested */
- AR5K_REG_WRITE(AR5K_AR5210_PHY_FC,
+ AR5K_REG_WRITE(AR5K_AR5210_PHY_FC,
turbo == AH_TRUE ? AR5K_AR5210_PHY_FC_TURBO_MODE : 0);
/* ...reset chipset */
@@ -352,26 +352,26 @@ ar5k_ar5210_set_channel(hal, channel)
AR5K_DELAY(1000);
/*
- * Check bounds supported by the PHY
+ * Check bounds supported by the PHY
* (don't care about regulation restrictions at this point)
*/
if(channel->channel < hal->ah_capabilities.cap_range.range_5ghz_min ||
channel->channel > hal->ah_capabilities.cap_range.range_5ghz_max) {
- AR5K_PRINTF("channel out of supported range (%u MHz)\n",
+ AR5K_PRINTF("channel out of supported range (%u MHz)\n",
channel->channel);
return(AH_FALSE);
}
/*
- * Set the channel and wait
+ * Set the channel and wait
*/
data = ar5k_ar5210_chan2athchan(channel);
AR5K_REG_WRITE(AR5K_AR5210_PHY(0x27), data);
AR5K_REG_WRITE(AR5K_AR5210_PHY(0x30), 0);
AR5K_DELAY(1000);
- /*
- * Activate phy and wait
+ /*
+ * Activate phy and wait
*/
AR5K_REG_WRITE(AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_ENABLE);
AR5K_DELAY(1000);
@@ -407,7 +407,7 @@ ar5k_ar5210_detach(hal)
struct ath_hal *hal;
{
/*
- * Free HAL structure, assume interrupts are down
+ * Free HAL structure, assume interrupts are down
*/
free(hal, M_DEVBUF);
}
@@ -423,7 +423,7 @@ ar5k_ar5210_reset(hal, op_mode, channel, change_channel, status)
int i;
struct ar5k_ini initial[] = AR5K_AR5210_INI;
- if(ar5k_ar5210_nic_wakeup(hal,
+ if(ar5k_ar5210_nic_wakeup(hal,
channel->channelFlags & IEEE80211_CHAN_T ?
AH_TRUE : AH_FALSE, AH_FALSE) == AH_FALSE)
return(AH_FALSE);
@@ -451,7 +451,7 @@ ar5k_ar5210_reset(hal, op_mode, channel, change_channel, status)
case INI_WRITE:
default:
- AR5K_REG_WRITE(initial[i].ini_register,
+ AR5K_REG_WRITE(initial[i].ini_register,
initial[i].ini_value);
}
}
@@ -461,7 +461,7 @@ ar5k_ar5210_reset(hal, op_mode, channel, change_channel, status)
/*
* Set channel and calibrate the PHY
*/
- if(ar5k_ar5210_perCalibration(hal, channel) == AH_FALSE)
+ if(ar5k_ar5210_perCalibration(hal, channel) == AH_FALSE)
return(AH_FALSE);
/*
@@ -470,7 +470,7 @@ ar5k_ar5210_reset(hal, op_mode, channel, change_channel, status)
if(hal->ah_capabilities.cap_eeprom.ee_rfkill != 0) {
if ((hal->ah_gpio[0] = ar5k_ar5210_gpioGet(hal, 0)) == 0)
ar5k_ar5210_gpioSetIntr(hal, 0, 1);
- else
+ else
ar5k_ar5210_gpioSetIntr(hal, 0, 0);
}
@@ -503,19 +503,19 @@ ar5k_ar5210_setPCUConfig(hal)
case IEEE80211_M_STA:
pcu_reg |= AR5K_AR5210_STA_ID1_NO_PSPOLL |
AR5K_AR5210_STA_ID1_DESC_ANTENNA |
- AR5K_AR5210_STA_ID1_PWR_SV;
+ AR5K_AR5210_STA_ID1_PWR_SV;
break;
case IEEE80211_M_IBSS:
- pcu_reg |= AR5K_AR5210_STA_ID1_ADHOC |
- AR5K_AR5210_STA_ID1_NO_PSPOLL |
+ pcu_reg |= AR5K_AR5210_STA_ID1_ADHOC |
+ AR5K_AR5210_STA_ID1_NO_PSPOLL |
AR5K_AR5210_STA_ID1_DESC_ANTENNA;
beacon_reg |= AR5K_AR5210_BCR_ADHOC;
break;
case IEEE80211_M_HOSTAP:
- pcu_reg |= AR5K_AR5210_STA_ID1_AP |
- AR5K_AR5210_STA_ID1_NO_PSPOLL |
+ pcu_reg |= AR5K_AR5210_STA_ID1_AP |
+ AR5K_AR5210_STA_ID1_NO_PSPOLL |
AR5K_AR5210_STA_ID1_DESC_ANTENNA;
beacon_reg |= AR5K_AR5210_BCR_AP;
break;
@@ -527,8 +527,8 @@ ar5k_ar5210_setPCUConfig(hal)
default:
return;
}
-
- /*
+
+ /*
* Set PCU and BCR registers
*/
memcpy(&low_id, &(hal->ah_sta_id[0]), 4);
@@ -747,8 +747,9 @@ ar5k_ar5210_resetTxQueue(hal, queue)
*/
if(hal->ah_software_retry == AH_TRUE) {
/* XXX Need to test this */
- retry_lg = hal->ah_limit_tx_retries;
- retry_sh = retry_lg = retry_lg > AR5K_AR5210_RETRY_LMT_SH_RETRY ?
+ retry_lg = hal->ah_limit_tx_retries;
+ retry_sh = retry_lg =
+ retry_lg > AR5K_AR5210_RETRY_LMT_SH_RETRY ?
AR5K_AR5210_RETRY_LMT_SH_RETRY : retry_lg;
} else {
retry_lg = AR5K_INIT_LG_RETRY;
@@ -863,7 +864,8 @@ ar5k_ar5210_startTxDma(hal, queue)
case HAL_TX_QUEUE_CAB:
tx_queue |= AR5K_AR5210_CR_TXE1 & ~AR5K_AR5210_CR_TXD1;
AR5K_REG_WRITE(AR5K_AR5210_BSR,
- AR5K_AR5210_BCR_TQ1FV | AR5K_AR5210_BCR_TQ1V | AR5K_AR5210_BCR_BDMAE);
+ AR5K_AR5210_BCR_TQ1FV | AR5K_AR5210_BCR_TQ1V |
+ AR5K_AR5210_BCR_BDMAE);
break;
default:
@@ -981,7 +983,7 @@ ar5k_ar5210_setupTxDesc(hal, desc, packet_length, header_length, type, tx_power,
tx_desc->clear_dest_mask = flags & HAL_TXDESC_CLRDMASK ? 1 : 0;
/*
- * WEP crap
+ * WEP crap
*/
if(key_index != HAL_TXKEYIX_INVALID) {
tx_desc->encrypt_key_valid = 1;
@@ -989,7 +991,7 @@ ar5k_ar5210_setupTxDesc(hal, desc, packet_length, header_length, type, tx_power,
}
/*
- * RTS/CTS
+ * RTS/CTS
*/
if(flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) {
tx_desc->rts_cts_enable = 1;
@@ -1074,7 +1076,7 @@ ar5k_ar5210_procTxDesc(hal, desc)
desc->ds_us.tx.ts_status = 0;
if(tx_status->frame_xmit_ok == 0) {
- if(tx_status->excessive_retries)
+ if(tx_status->excessive_retries)
desc->ds_us.tx.ts_status |= HAL_TXERR_XRETRY;
if(tx_status->fifo_underrun)
@@ -1139,7 +1141,7 @@ ar5k_ar5210_stopDmaReceive(hal)
/*
* It may take some time to disable the DMA receive unit
*/
- for(i = 2000;
+ for(i = 2000;
i > 0 && (AR5K_REG_READ(AR5K_AR5210_CR) & AR5K_AR5210_CR_RXE) != 0;
i--)
AR5K_DELAY(10);
@@ -1179,7 +1181,7 @@ ar5k_ar5210_setMulticastFilterIndex(hal, index)
{
if(index >= 64)
return(AH_FALSE);
- else if(index >= 32)
+ else if(index >= 32)
AR5K_REG_ENABLE_BITS(AR5K_AR5210_MCAST_FIL1,
(1 << (index - 32)));
else
@@ -1196,7 +1198,7 @@ ar5k_ar5210_clrMulticastFilterIndex(hal, index)
{
if(index >= 64)
return(AH_FALSE);
- else if(index >= 32)
+ else if(index >= 32)
AR5K_REG_DISABLE_BITS(AR5K_AR5210_MCAST_FIL1,
(1 << (index - 32)));
else
@@ -1270,7 +1272,7 @@ ar5k_ar5210_procRxDesc(hal, desc, phys_addr, next)
if(!rx_status->done)
return(HAL_EINPROGRESS);
- /*
+ /*
* Frame receive status
*/
now = (AR5K_REG_READ(AR5K_AR5210_TSF_L32) >> 10) & 0xffff;
@@ -1288,7 +1290,7 @@ ar5k_ar5210_procRxDesc(hal, desc, phys_addr, next)
/*
* Key table status
*/
- if(!rx_status->key_index_valid)
+ if(!rx_status->key_index_valid)
desc->ds_us.rx.rs_keyix = HAL_RXKEYIX_INVALID;
else
desc->ds_us.rx.rs_keyix = rx_status->key_index;
@@ -1322,7 +1324,7 @@ ar5k_ar5210_rxMonitor(hal)
/*
* XXX Not sure, if this works correctly.
*/
- AR5K_REG_ENABLE_BITS(AR5K_AR5210_RX_FILTER,
+ AR5K_REG_ENABLE_BITS(AR5K_AR5210_RX_FILTER,
AR5K_AR5210_RX_FILTER_PROMISC);
}
@@ -1429,7 +1431,7 @@ ar5k_ar5210_getDiagState(hal, id, device, size)
{
/*
* We'll ignore this right now. This seems to be some kind of an obscure
- * debugging interface for the binary-only HAL.
+ * debugging interface for the binary-only HAL.
*/
return(AH_FALSE);
}
@@ -1495,7 +1497,7 @@ ar5k_ar5210_setLedState(hal, state)
switch(state) {
case IEEE80211_S_SCAN:
case IEEE80211_S_INIT:
- led |=
+ led |=
AR5K_AR5210_PCICFG_LED_PEND |
AR5K_AR5210_PCICFG_LED_BCTL;
break;
@@ -1504,7 +1506,7 @@ ar5k_ar5210_setLedState(hal, state)
AR5K_AR5210_PCICFG_LED_ACT;
break;
default:
- led |=
+ led |=
AR5K_AR5210_PCICFG_LED_ACT |
AR5K_AR5210_PCICFG_LED_BCTL;
break;
@@ -1538,12 +1540,12 @@ ar5k_ar5210_writeAssocid(hal, bssid, assoc_id, tim_offset)
}
AR5K_REG_WRITE(AR5K_AR5210_BEACON,
- (AR5K_REG_READ(AR5K_AR5210_BEACON) &
+ (AR5K_REG_READ(AR5K_AR5210_BEACON) &
~AR5K_AR5210_BEACON_TIM) |
- (((tim_offset ? tim_offset + 4 : 0) <<
+ (((tim_offset ? tim_offset + 4 : 0) <<
AR5K_AR5210_BEACON_TIM_S) &
AR5K_AR5210_BEACON_TIM));
-
+
ar5k_ar5210_enablePSPoll(hal, NULL, 0);
}
@@ -1555,7 +1557,7 @@ ar5k_ar5210_gpioCfgOutput(hal, gpio)
if(gpio > AR5K_AR5210_NUM_GPIO)
return(AH_FALSE);
- AR5K_REG_WRITE(AR5K_AR5210_GPIOCR,
+ AR5K_REG_WRITE(AR5K_AR5210_GPIOCR,
(AR5K_REG_READ(AR5K_AR5210_GPIOCR) &~ AR5K_AR5210_GPIOCR_ALL(gpio))
| AR5K_AR5210_GPIOCR_OUT1(gpio));
@@ -1570,7 +1572,7 @@ ar5k_ar5210_gpioCfgInput(hal, gpio)
if(gpio > AR5K_AR5210_NUM_GPIO)
return(AH_FALSE);
- AR5K_REG_WRITE(AR5K_AR5210_GPIOCR,
+ AR5K_REG_WRITE(AR5K_AR5210_GPIOCR,
(AR5K_REG_READ(AR5K_AR5210_GPIOCR) &~ AR5K_AR5210_GPIOCR_ALL(gpio))
| AR5K_AR5210_GPIOCR_IN(gpio));
@@ -1586,7 +1588,7 @@ ar5k_ar5210_gpioGet(hal, gpio)
return(0xffffffff);
/* GPIO input magic */
- return(((AR5K_REG_READ(AR5K_AR5210_GPIODI) &
+ return(((AR5K_REG_READ(AR5K_AR5210_GPIODI) &
AR5K_AR5210_GPIOD_MASK) >> gpio) & 0x1);
}
@@ -1626,7 +1628,7 @@ ar5k_ar5210_gpioSetIntr(hal, gpio, interrupt_level)
/*
* Set the GPIO interrupt
*/
- data = (AR5K_REG_READ(AR5K_AR5210_GPIOCR) &
+ data = (AR5K_REG_READ(AR5K_AR5210_GPIOCR) &
~(AR5K_AR5210_GPIOCR_INT_SEL(gpio) | AR5K_AR5210_GPIOCR_INT_SELH |
AR5K_AR5210_GPIOCR_INT_ENA | AR5K_AR5210_GPIOCR_ALL(gpio))) |
(AR5K_AR5210_GPIOCR_INT_SEL(gpio) | AR5K_AR5210_GPIOCR_INT_ENA);
@@ -1892,7 +1894,7 @@ ar5k_ar5210_setKeyCacheEntry(hal, entry, keyval, mac, xor_notused)
offset);
offset += 4;
}
-
+
if(i == 4 && keyval->wk_len <= 13)
key_v[i] &= 0xff;
}
@@ -1926,7 +1928,8 @@ ar5k_ar5210_setKeyCacheEntryMac(hal, entry, mac)
high_id = 0x0000ffff & htole32(high_id);
- AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE(entry) + (offset++ * 4), htole32(low_id));
+ AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE(entry) + (offset++ * 4),
+ htole32(low_id));
AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE(entry) + (offset * 4), high_id);
return(AH_TRUE);
@@ -1954,7 +1957,8 @@ ar5k_ar5210_setPowerMode(hal, mode, set_chip, sleep_duration)
case HAL_PM_FULL_SLEEP:
if(set_chip)
- AR5K_REG_WRITE(AR5K_AR5210_SCR, AR5K_AR5210_SCR_SLE_SLP);
+ AR5K_REG_WRITE(AR5K_AR5210_SCR,
+ AR5K_AR5210_SCR_SLE_SLP);
break;
case HAL_PM_AWAKE:
@@ -1962,10 +1966,10 @@ ar5k_ar5210_setPowerMode(hal, mode, set_chip, sleep_duration)
goto commit;
AR5K_REG_WRITE(AR5K_AR5210_SCR, AR5K_AR5210_SCR_SLE_WAKE);
-
+
for(i = 5000; i > 0; i--) {
/* Check if the AR5210 did wake up */
- if((AR5K_REG_READ(AR5K_AR5210_PCICFG) &
+ if((AR5K_REG_READ(AR5K_AR5210_PCICFG) &
AR5K_AR5210_PCICFG_SPWR_DN) == 0)
break;
@@ -1974,7 +1978,7 @@ ar5k_ar5210_setPowerMode(hal, mode, set_chip, sleep_duration)
AR5K_REG_WRITE(AR5K_AR5210_SCR,
AR5K_AR5210_SCR_SLE_WAKE);
}
-
+
/* Fail if the AR5210 didn't wake up */
if(i <= 0)
return(AH_FALSE);
@@ -2192,7 +2196,7 @@ ar5k_ar5210_waitForBeaconDone(hal, phys_addr)
* Re-schedule the beacon queue
*/
AR5K_REG_WRITE(AR5K_AR5210_TXDP1, (u_int32_t)phys_addr);
- AR5K_REG_WRITE(AR5K_AR5210_BCR,
+ AR5K_REG_WRITE(AR5K_AR5210_BCR,
AR5K_AR5210_BCR_TQ1V | AR5K_AR5210_BCR_BDMAE);
return(AH_FALSE);
@@ -2276,7 +2280,7 @@ ar5k_ar5210_setInterrupts(hal, new_mask)
int_mask = new_mask & HAL_INT_COMMON;
if(new_mask & HAL_INT_RX)
- int_mask |=
+ int_mask |=
AR5K_AR5210_IMR_RXOK |
AR5K_AR5210_IMR_RXERR |
AR5K_AR5210_IMR_RXORN;
@@ -2359,7 +2363,8 @@ ar5k_ar5210_regulation_domain(hal, write, regdomain)
{
/* Read current value */
if(write != AH_TRUE) {
- memcpy(regdomain, &hal->ah_capabilities.cap_regdomain.reg_current,
+ memcpy(regdomain,
+ &hal->ah_capabilities.cap_regdomain.reg_current,
sizeof(ieee80211_regdomain_t));
return(AH_TRUE);
}
@@ -2369,13 +2374,13 @@ ar5k_ar5210_regulation_domain(hal, write, regdomain)
sizeof(ieee80211_regdomain_t));
if(hal->ah_capabilities.cap_eeprom.ee_protect &
- AR5K_AR5210_EEPROM_PROTECT_128_191)
+ AR5K_AR5210_EEPROM_PROTECT_128_191)
return(AH_FALSE);
- hal->ah_capabilities.cap_eeprom.ee_regdomain =
+ hal->ah_capabilities.cap_eeprom.ee_regdomain =
ar5k_regdomain_from_ieee(regdomain);
- AR5K_PRINTF("writing new regulation domain to EEPROM: 0x%04x\n",
+ AR5K_PRINTF("writing new regulation domain to EEPROM: 0x%04x\n",
hal->ah_capabilities.cap_eeprom.ee_regdomain);
if(ar5k_ar5210_eeprom_write(hal, AR5K_AR5210_EEPROM_REG_DOMAIN,
@@ -2406,7 +2411,7 @@ ar5k_ar5210_eeprom_init(hal)
&hal->ah_capabilities.cap_eeprom.ee_magic)) != 0)
return(ret);
- if(hal->ah_capabilities.cap_eeprom.ee_magic !=
+ if(hal->ah_capabilities.cap_eeprom.ee_magic !=
AR5K_AR5210_EEPROM_MAGIC_VALUE)
return(-EFTYPE);
@@ -2433,7 +2438,7 @@ ar5k_ar5210_eeprom_is_busy(hal)
AH_TRUE : AH_FALSE);
}
-int
+int
ar5k_ar5210_eeprom_read(hal, offset, data)
struct ath_hal *hal;
u_int32_t offset;
@@ -2443,12 +2448,12 @@ ar5k_ar5210_eeprom_read(hal, offset, data)
/* Enable eeprom access */
AR5K_REG_ENABLE_BITS(AR5K_AR5210_PCICFG, AR5K_AR5210_PCICFG_EEAE);
-
- /*
- * Prime read pump
+
+ /*
+ * Prime read pump
*/
(void)AR5K_REG_READ(AR5K_AR5210_EEPROM_BASE + (4 * offset));
-
+
for(timeout = 10000; timeout > 0; timeout--) {
AR5K_DELAY(1);
status = AR5K_REG_READ(AR5K_AR5210_EEPROM_STATUS);
@@ -2464,7 +2469,7 @@ ar5k_ar5210_eeprom_read(hal, offset, data)
return(-ETIMEDOUT);
}
-int
+int
ar5k_ar5210_eeprom_write(hal, offset, data)
struct ath_hal *hal;
u_int32_t offset;
@@ -2474,12 +2479,12 @@ ar5k_ar5210_eeprom_write(hal, offset, data)
/* Enable eeprom access */
AR5K_REG_ENABLE_BITS(AR5K_AR5210_PCICFG, AR5K_AR5210_PCICFG_EEAE);
-
- /*
+
+ /*
* Prime write pump
*/
AR5K_REG_WRITE(AR5K_AR5210_EEPROM_BASE + (4 * offset), data);
-
+
for(timeout = 10000; timeout > 0; timeout--) {
AR5K_DELAY(1);
status = AR5K_REG_READ(AR5K_AR5210_EEPROM_STATUS);
diff --git a/sys/dev/ic/ar5210reg.h b/sys/dev/ic/ar5210reg.h
index 79e67105360..992027e8ff9 100644
--- a/sys/dev/ic/ar5210reg.h
+++ b/sys/dev/ic/ar5210reg.h
@@ -1,7 +1,7 @@
-/* $OpenBSD: ar5210reg.h,v 1.1 2004/11/02 03:01:16 reyk Exp $ */
+/* $OpenBSD: ar5210reg.h,v 1.2 2004/11/02 14:05:49 reyk Exp $ */
/*
- * Copyright (c) 2004 Reyk Floeter <reyk@vantronix.net>.
+ * Copyright (c) 2004 Reyk Floeter <reyk@vantronix.net>.
*
* All rights reserved.
*
@@ -64,12 +64,12 @@
* Configuration and status register
*/
#define AR5K_AR5210_CFG 0x0014
-#define AR5K_AR5210_CFG_SWTD 0x00000001
-#define AR5K_AR5210_CFG_SWTB 0x00000002
-#define AR5K_AR5210_CFG_SWRD 0x00000004
-#define AR5K_AR5210_CFG_SWRB 0x00000008
-#define AR5K_AR5210_CFG_SWRG 0x00000010
-#define AR5K_AR5210_CFG_EEBS 0x00000200
+#define AR5K_AR5210_CFG_SWTD 0x00000001
+#define AR5K_AR5210_CFG_SWTB 0x00000002
+#define AR5K_AR5210_CFG_SWRD 0x00000004
+#define AR5K_AR5210_CFG_SWRB 0x00000008
+#define AR5K_AR5210_CFG_SWRG 0x00000010
+#define AR5K_AR5210_CFG_EEBS 0x00000200
#define AR5K_AR5210_CFG_TXCNT 0x00007800
#define AR5K_AR5210_CFG_TXCNT_S 11
#define AR5K_AR5210_CFG_TXFSTAT 0x00008000
@@ -78,30 +78,30 @@
/*
* Interrupt service register
*/
-#define AR5K_AR5210_ISR 0x001c
+#define AR5K_AR5210_ISR 0x001c
#define AR5K_AR5210_ISR_RXOK 0x00000001
#define AR5K_AR5210_ISR_RXDESC 0x00000002
-#define AR5K_AR5210_ISR_RXERR 0x00000004
-#define AR5K_AR5210_ISR_RXNOFRM 0x00000008
+#define AR5K_AR5210_ISR_RXERR 0x00000004
+#define AR5K_AR5210_ISR_RXNOFRM 0x00000008
#define AR5K_AR5210_ISR_RXEOL 0x00000120
-#define AR5K_AR5210_ISR_RXORN 0x00000020
-#define AR5K_AR5210_ISR_TXOK 0x00000040
-#define AR5K_AR5210_ISR_TXDESC 0x00000080
-#define AR5K_AR5210_ISR_TXERR 0x00000100
-#define AR5K_AR5210_ISR_TXNOFRM 0x00000200
-#define AR5K_AR5210_ISR_TXEOL 0x00000400
-#define AR5K_AR5210_ISR_TXURN 0x00000800
-#define AR5K_AR5210_ISR_MIB 0x00001000
-#define AR5K_AR5210_ISR_SWI 0x00002000
-#define AR5K_AR5210_ISR_RXPHY 0x00004000
-#define AR5K_AR5210_ISR_RXKCM 0x00008000
-#define AR5K_AR5210_ISR_SWBA 0x00010000
-#define AR5K_AR5210_ISR_BRSSI 0x00020000
-#define AR5K_AR5210_ISR_BMISS 0x00040000
-#define AR5K_AR5210_ISR_MCABT 0x00100000
-#define AR5K_AR5210_ISR_SSERR 0x00200000
-#define AR5K_AR5210_ISR_DPERR 0x00400000
-#define AR5K_AR5210_ISR_GPIO 0x01000000
+#define AR5K_AR5210_ISR_RXORN 0x00000020
+#define AR5K_AR5210_ISR_TXOK 0x00000040
+#define AR5K_AR5210_ISR_TXDESC 0x00000080
+#define AR5K_AR5210_ISR_TXERR 0x00000100
+#define AR5K_AR5210_ISR_TXNOFRM 0x00000200
+#define AR5K_AR5210_ISR_TXEOL 0x00000400
+#define AR5K_AR5210_ISR_TXURN 0x00000800
+#define AR5K_AR5210_ISR_MIB 0x00001000
+#define AR5K_AR5210_ISR_SWI 0x00002000
+#define AR5K_AR5210_ISR_RXPHY 0x00004000
+#define AR5K_AR5210_ISR_RXKCM 0x00008000
+#define AR5K_AR5210_ISR_SWBA 0x00010000
+#define AR5K_AR5210_ISR_BRSSI 0x00020000
+#define AR5K_AR5210_ISR_BMISS 0x00040000
+#define AR5K_AR5210_ISR_MCABT 0x00100000
+#define AR5K_AR5210_ISR_SSERR 0x00200000
+#define AR5K_AR5210_ISR_DPERR 0x00400000
+#define AR5K_AR5210_ISR_GPIO 0x01000000
#define AR5K_AR5210_ISR_FATAL ( \
AR5K_AR5210_ISR_MCABT | AR5K_AR5210_ISR_SSERR | \
AR5K_AR5210_ISR_DPERR | AR5K_AR5210_ISR_RXORN \
@@ -110,37 +110,37 @@
/*
* Interrupt mask register
*/
-#define AR5K_AR5210_IMR 0x0020
-#define AR5K_AR5210_IMR_RXOK 0x00000001
-#define AR5K_AR5210_IMR_RXDESC 0x00000002
-#define AR5K_AR5210_IMR_RXERR 0x00000004
-#define AR5K_AR5210_IMR_RXNOFRM 0x00000008
-#define AR5K_AR5210_IMR_RXEOL 0x00000010
-#define AR5K_AR5210_IMR_RXORN 0x00000020
-#define AR5K_AR5210_IMR_TXOK 0x00000040
-#define AR5K_AR5210_IMR_TXDESC 0x00000080
-#define AR5K_AR5210_IMR_TXERR 0x00000100
-#define AR5K_AR5210_IMR_TXNOFRM 0x00000200
-#define AR5K_AR5210_IMR_TXEOL 0x00000400
-#define AR5K_AR5210_IMR_TXURN 0x00000800
-#define AR5K_AR5210_IMR_MIB 0x00001000
-#define AR5K_AR5210_IMR_SWI 0x00002000
-#define AR5K_AR5210_IMR_RXPHY 0x00004000
-#define AR5K_AR5210_IMR_RXKCM 0x00008000
-#define AR5K_AR5210_IMR_SWBA 0x00010000
-#define AR5K_AR5210_IMR_BRSSI 0x00020000
-#define AR5K_AR5210_IMR_BMISS 0x00040000
-#define AR5K_AR5210_IMR_MCABT 0x00100000
-#define AR5K_AR5210_IMR_SSERR 0x00200000
-#define AR5K_AR5210_IMR_DPERR 0x00400000
-#define AR5K_AR5210_IMR_GPIO 0x01000000
+#define AR5K_AR5210_IMR 0x0020
+#define AR5K_AR5210_IMR_RXOK 0x00000001
+#define AR5K_AR5210_IMR_RXDESC 0x00000002
+#define AR5K_AR5210_IMR_RXERR 0x00000004
+#define AR5K_AR5210_IMR_RXNOFRM 0x00000008
+#define AR5K_AR5210_IMR_RXEOL 0x00000010
+#define AR5K_AR5210_IMR_RXORN 0x00000020
+#define AR5K_AR5210_IMR_TXOK 0x00000040
+#define AR5K_AR5210_IMR_TXDESC 0x00000080
+#define AR5K_AR5210_IMR_TXERR 0x00000100
+#define AR5K_AR5210_IMR_TXNOFRM 0x00000200
+#define AR5K_AR5210_IMR_TXEOL 0x00000400
+#define AR5K_AR5210_IMR_TXURN 0x00000800
+#define AR5K_AR5210_IMR_MIB 0x00001000
+#define AR5K_AR5210_IMR_SWI 0x00002000
+#define AR5K_AR5210_IMR_RXPHY 0x00004000
+#define AR5K_AR5210_IMR_RXKCM 0x00008000
+#define AR5K_AR5210_IMR_SWBA 0x00010000
+#define AR5K_AR5210_IMR_BRSSI 0x00020000
+#define AR5K_AR5210_IMR_BMISS 0x00040000
+#define AR5K_AR5210_IMR_MCABT 0x00100000
+#define AR5K_AR5210_IMR_SSERR 0x00200000
+#define AR5K_AR5210_IMR_DPERR 0x00400000
+#define AR5K_AR5210_IMR_GPIO 0x01000000
/*
* Interrupt enable register
*/
#define AR5K_AR5210_IER 0x0024
-#define AR5K_AR5210_IER_DISABLE 0x00000000
-#define AR5K_AR5210_IER_ENABLE 0x00000001
+#define AR5K_AR5210_IER_DISABLE 0x00000000
+#define AR5K_AR5210_IER_ENABLE 0x00000001
/*
* Beacon control register
@@ -148,25 +148,25 @@
#define AR5K_AR5210_BCR 0x0028
#define AR5K_AR5210_BCR_AP 0x00000000
#define AR5K_AR5210_BCR_ADHOC 0x00000001
-#define AR5K_AR5210_BCR_BDMAE 0x00000002
-#define AR5K_AR5210_BCR_TQ1FV 0x00000004
-#define AR5K_AR5210_BCR_TQ1V 0x00000008
-#define AR5K_AR5210_BCR_BCGET 0x00000010
+#define AR5K_AR5210_BCR_BDMAE 0x00000002
+#define AR5K_AR5210_BCR_TQ1FV 0x00000004
+#define AR5K_AR5210_BCR_TQ1V 0x00000008
+#define AR5K_AR5210_BCR_BCGET 0x00000010
/*
* Beacon status register
*/
-#define AR5K_AR5210_BSR 0x002c
-#define AR5K_AR5210_BSR_BDLYSW 0x00000001
-#define AR5K_AR5210_BSR_BDLYDMA 0x00000002
-#define AR5K_AR5210_BSR_TXQ1F 0x00000004
-#define AR5K_AR5210_BSR_ATIMDLY 0x00000008
-#define AR5K_AR5210_BSR_SNPBCMD 0x00000100
-#define AR5K_AR5210_BSR_SNPBDMAE 0x00000200
-#define AR5K_AR5210_BSR_SNPTQ1FV 0x00000400
-#define AR5K_AR5210_BSR_SNPTQ1V 0x00000800
-#define AR5K_AR5210_BSR_SNAPPEDBCRVALID 0x00001000
-#define AR5K_AR5210_BSR_SWBA_CNT 0x00ff0000
+#define AR5K_AR5210_BSR 0x002c
+#define AR5K_AR5210_BSR_BDLYSW 0x00000001
+#define AR5K_AR5210_BSR_BDLYDMA 0x00000002
+#define AR5K_AR5210_BSR_TXQ1F 0x00000004
+#define AR5K_AR5210_BSR_ATIMDLY 0x00000008
+#define AR5K_AR5210_BSR_SNPBCMD 0x00000100
+#define AR5K_AR5210_BSR_SNPBDMAE 0x00000200
+#define AR5K_AR5210_BSR_SNPTQ1FV 0x00000400
+#define AR5K_AR5210_BSR_SNPTQ1V 0x00000800
+#define AR5K_AR5210_BSR_SNAPPEDBCRVALID 0x00001000
+#define AR5K_AR5210_BSR_SWBA_CNT 0x00ff0000
/*
* DMA size definitions
@@ -185,27 +185,27 @@ typedef enum {
/*
* Transmit configuration register
*/
-#define AR5K_AR5210_TXCFG 0x0030
-#define AR5K_AR5210_TXCFG_SDMAMR 0x00000007
-#define AR5K_AR5210_TXCFG_TXFSTP 0x00000008
-#define AR5K_AR5210_TXCFG_TXFULL 0x00000070
-#define AR5K_AR5210_TXCFG_TXCONT_EN 0x00000080
+#define AR5K_AR5210_TXCFG 0x0030
+#define AR5K_AR5210_TXCFG_SDMAMR 0x00000007
+#define AR5K_AR5210_TXCFG_TXFSTP 0x00000008
+#define AR5K_AR5210_TXCFG_TXFULL 0x00000070
+#define AR5K_AR5210_TXCFG_TXCONT_EN 0x00000080
/*
* Receive configuration register
*/
-#define AR5K_AR5210_RXCFG 0x0034
-#define AR5K_AR5210_RXCFG_SDMAMW 0x00000007
-#define AR5K_AR5210_RXCFG_ZLFDMA 0x00000010
+#define AR5K_AR5210_RXCFG 0x0034
+#define AR5K_AR5210_RXCFG_SDMAMW 0x00000007
+#define AR5K_AR5210_RXCFG_ZLFDMA 0x00000010
/*
* MIB control register
*/
#define AR5K_AR5210_MIBC 0x0040
#define AR5K_AR5210_MIBC_COW 0x00000001
-#define AR5K_AR5210_MIBC_FMC 0x00000002
-#define AR5K_AR5210_MIBC_CMC 0x00000004
-#define AR5K_AR5210_MIBC_MCS 0x00000008
+#define AR5K_AR5210_MIBC_FMC 0x00000002
+#define AR5K_AR5210_MIBC_CMC 0x00000004
+#define AR5K_AR5210_MIBC_MCS 0x00000008
/*
* Timeout prescale register
@@ -227,28 +227,28 @@ typedef enum {
*/
#define AR5K_AR5210_RPGTO 0x0050
-/*
- * Receive frame count limit register
+/*
+ * Receive frame count limit register
*/
#define AR5K_AR5210_RFCNT 0x0054
-#define AR5K_AR5210_RFCNT_RFCL 0x0000000f
+#define AR5K_AR5210_RFCNT_RFCL 0x0000000f
/*
- * Misc settings/status register
+ * Misc settings/status register
*/
#define AR5K_AR5210_MISC 0x0058
-#define AR5K_AR5210_MISC_LED_DECAY 0x001c0000
-#define AR5K_AR5210_MISC_LED_BLINK 0x00e00000
+#define AR5K_AR5210_MISC_LED_DECAY 0x001c0000
+#define AR5K_AR5210_MISC_LED_BLINK 0x00e00000
/*
* Reset control register
*/
#define AR5K_AR5210_RC 0x4000
-#define AR5K_AR5210_RC_PCU 0x00000001
-#define AR5K_AR5210_RC_DMA 0x00000002
-#define AR5K_AR5210_RC_MAC 0x00000004
-#define AR5K_AR5210_RC_PHY 0x00000008
-#define AR5K_AR5210_RC_PCI 0x00000010
+#define AR5K_AR5210_RC_PCU 0x00000001
+#define AR5K_AR5210_RC_DMA 0x00000002
+#define AR5K_AR5210_RC_MAC 0x00000004
+#define AR5K_AR5210_RC_PHY 0x00000008
+#define AR5K_AR5210_RC_PCI 0x00000010
#define AR5K_AR5210_RC_CHIP ( \
AR5K_AR5210_RC_PCU | AR5K_AR5210_RC_DMA | \
AR5K_AR5210_RC_MAC | AR5K_AR5210_RC_PHY \
@@ -258,11 +258,11 @@ typedef enum {
* Sleep control register
*/
#define AR5K_AR5210_SCR 0x4004
-#define AR5K_AR5210_SCR_SLDUR 0x0000ffff
-#define AR5K_AR5210_SCR_SLE 0x00030000
-#define AR5K_AR5210_SCR_SLE_WAKE 0x00000000
-#define AR5K_AR5210_SCR_SLE_SLP 0x00010000
-#define AR5K_AR5210_SCR_SLE_ALLOW 0x00020000
+#define AR5K_AR5210_SCR_SLDUR 0x0000ffff
+#define AR5K_AR5210_SCR_SLE 0x00030000
+#define AR5K_AR5210_SCR_SLE_WAKE 0x00000000
+#define AR5K_AR5210_SCR_SLE_SLP 0x00010000
+#define AR5K_AR5210_SCR_SLE_ALLOW 0x00020000
/*
* Interrupt pending register
@@ -274,34 +274,34 @@ typedef enum {
* Sleep force register
*/
#define AR5K_AR5210_SFR 0x400c
-#define AR5K_AR5210_SFR_SF 0x00000001
+#define AR5K_AR5210_SFR_SF 0x00000001
/*
* PCI configuration register
*/
#define AR5K_AR5210_PCICFG 0x4010
-#define AR5K_AR5210_PCICFG_EEAE 0x00000001
-#define AR5K_AR5210_PCICFG_CLKRUNEN 0x00000004
-#define AR5K_AR5210_PCICFG_LED_PEND 0x00000020
-#define AR5K_AR5210_PCICFG_LED_ACT 0x00000040
-#define AR5K_AR5210_PCICFG_SL_INTEN 0x00000800
-#define AR5K_AR5210_PCICFG_LED_BCTL 0x00001000
-#define AR5K_AR5210_PCICFG_SL_INPEN 0x00002800
-#define AR5K_AR5210_PCICFG_SPWR_DN 0x00010000
+#define AR5K_AR5210_PCICFG_EEAE 0x00000001
+#define AR5K_AR5210_PCICFG_CLKRUNEN 0x00000004
+#define AR5K_AR5210_PCICFG_LED_PEND 0x00000020
+#define AR5K_AR5210_PCICFG_LED_ACT 0x00000040
+#define AR5K_AR5210_PCICFG_SL_INTEN 0x00000800
+#define AR5K_AR5210_PCICFG_LED_BCTL 0x00001000
+#define AR5K_AR5210_PCICFG_SL_INPEN 0x00002800
+#define AR5K_AR5210_PCICFG_SPWR_DN 0x00010000
/*
* "General Purpose Input/Output" (GPIO) control register
*/
#define AR5K_AR5210_GPIOCR 0x4014
-#define AR5K_AR5210_GPIOCR_INT_ENA 0x00008000
-#define AR5K_AR5210_GPIOCR_INT_SELL 0x00000000
-#define AR5K_AR5210_GPIOCR_INT_SELH 0x00010000
-#define AR5K_AR5210_GPIOCR_IN(n) (0 << ((n) * 2))
-#define AR5K_AR5210_GPIOCR_OUT0(n) (1 << ((n) * 2))
-#define AR5K_AR5210_GPIOCR_OUT1(n) (2 << ((n) * 2))
-#define AR5K_AR5210_GPIOCR_OUT(n) (3 << ((n) * 2))
-#define AR5K_AR5210_GPIOCR_ALL(n) (3<< ((n) * 2))
-#define AR5K_AR5210_GPIOCR_INT_SEL(n) ((n) << 12)
+#define AR5K_AR5210_GPIOCR_INT_ENA 0x00008000
+#define AR5K_AR5210_GPIOCR_INT_SELL 0x00000000
+#define AR5K_AR5210_GPIOCR_INT_SELH 0x00010000
+#define AR5K_AR5210_GPIOCR_IN(n) (0 << ((n) * 2))
+#define AR5K_AR5210_GPIOCR_OUT0(n) (1 << ((n) * 2))
+#define AR5K_AR5210_GPIOCR_OUT1(n) (2 << ((n) * 2))
+#define AR5K_AR5210_GPIOCR_OUT(n) (3 << ((n) * 2))
+#define AR5K_AR5210_GPIOCR_ALL(n) (3<< ((n) * 2))
+#define AR5K_AR5210_GPIOCR_INT_SEL(n) ((n) << 12)
#define AR5K_AR5210_NUM_GPIO 6
@@ -323,22 +323,22 @@ typedef enum {
#define AR5K_AR5210_SREV_ID_M 0x000000ff
#define AR5K_AR5210_SREV_FPGA 1
#define AR5K_AR5210_SREV_PHYPLUS 2
-#define AR5K_AR5210_SREV_PHYPLUS_MS 3
+#define AR5K_AR5210_SREV_PHYPLUS_MS 3
#define AR5K_AR5210_SREV_CRETE 4
-#define AR5K_AR5210_SREV_CRETE_MS 5
-#define AR5K_AR5210_SREV_CRETE_MS23 7
-#define AR5K_AR5210_SREV_CRETE_23 8
+#define AR5K_AR5210_SREV_CRETE_MS 5
+#define AR5K_AR5210_SREV_CRETE_MS23 7
+#define AR5K_AR5210_SREV_CRETE_23 8
/*
* EEPROM access registers
*/
-#define AR5K_AR5210_EEPROM_BASE 0x6000
-#define AR5K_AR5210_EEPROM_RDATA 0x6800
-#define AR5K_AR5210_EEPROM_STATUS 0x6c00
-#define AR5K_AR5210_EEPROM_STAT_RDERR 0x0001
-#define AR5K_AR5210_EEPROM_STAT_RDDONE 0x0002
-#define AR5K_AR5210_EEPROM_STAT_WRERR 0x0004
-#define AR5K_AR5210_EEPROM_STAT_WRDONE 0x0008
+#define AR5K_AR5210_EEPROM_BASE 0x6000
+#define AR5K_AR5210_EEPROM_RDATA 0x6800
+#define AR5K_AR5210_EEPROM_STATUS 0x6c00
+#define AR5K_AR5210_EEPROM_STAT_RDERR 0x0001
+#define AR5K_AR5210_EEPROM_STAT_RDDONE 0x0002
+#define AR5K_AR5210_EEPROM_STAT_WRERR 0x0004
+#define AR5K_AR5210_EEPROM_STAT_WRDONE 0x0008
/*
* AR5210 EEPROM data registers
@@ -370,15 +370,15 @@ typedef enum {
* Second station id register (MAC address in upper 16 bits)
*/
#define AR5K_AR5210_STA_ID1 0x8004
-#define AR5K_AR5210_STA_ID1_AP 0x00010000
-#define AR5K_AR5210_STA_ID1_ADHOC 0x00020000
-#define AR5K_AR5210_STA_ID1_PWR_SV 0x00040000
-#define AR5K_AR5210_STA_ID1_NO_KEYSRCH 0x00080000
-#define AR5K_AR5210_STA_ID1_NO_PSPOLL 0x00100000
-#define AR5K_AR5210_STA_ID1_PCF 0x00200000
-#define AR5K_AR5210_STA_ID1_DESC_ANTENNA 0x00400000
-#define AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA 0x00800000
-#define AR5K_AR5210_STA_ID1_ACKCTS_6MB 0x01000000
+#define AR5K_AR5210_STA_ID1_AP 0x00010000
+#define AR5K_AR5210_STA_ID1_ADHOC 0x00020000
+#define AR5K_AR5210_STA_ID1_PWR_SV 0x00040000
+#define AR5K_AR5210_STA_ID1_NO_KEYSRCH 0x00080000
+#define AR5K_AR5210_STA_ID1_NO_PSPOLL 0x00100000
+#define AR5K_AR5210_STA_ID1_PCF 0x00200000
+#define AR5K_AR5210_STA_ID1_DESC_ANTENNA 0x00400000
+#define AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA 0x00800000
+#define AR5K_AR5210_STA_ID1_ACKCTS_6MB 0x01000000
/*
* First BSSID register (MAC address, lower 32bits)
@@ -391,7 +391,7 @@ typedef enum {
* AID: Association ID
*/
#define AR5K_AR5210_BSS_ID1 0x800c
-#define AR5K_AR5210_BSS_ID1_AID 0xffff0000
+#define AR5K_AR5210_BSS_ID1_AID 0xffff0000
#define AR5K_AR5210_BSS_ID1_AID_S 16
/*
@@ -403,29 +403,29 @@ typedef enum {
* ACK/CTS timeout register
*/
#define AR5K_AR5210_TIME_OUT 0x8014
-#define AR5K_AR5210_TIME_OUT_ACK 0x00001fff
+#define AR5K_AR5210_TIME_OUT_ACK 0x00001fff
#define AR5K_AR5210_TIME_OUT_ACK_S 0
-#define AR5K_AR5210_TIME_OUT_CTS 0x1fff0000
+#define AR5K_AR5210_TIME_OUT_CTS 0x1fff0000
#define AR5K_AR5210_TIME_OUT_CTS_S 16
/*
* RSSI threshold register
*/
#define AR5K_AR5210_RSSI_THR 0x8018
-#define AR5K_AR5210_RSSI_THR_BM_THR 0x00000700
+#define AR5K_AR5210_RSSI_THR_BM_THR 0x00000700
#define AR5K_AR5210_RSSI_THR_BM_THR_S 8
/*
* Retry limit register
*/
#define AR5K_AR5210_RETRY_LMT 0x801c
-#define AR5K_AR5210_RETRY_LMT_SH_RETRY 0x0000000f
+#define AR5K_AR5210_RETRY_LMT_SH_RETRY 0x0000000f
#define AR5K_AR5210_RETRY_LMT_SH_RETRY_S 0
-#define AR5K_AR5210_RETRY_LMT_LG_RETRY 0x000000f0
+#define AR5K_AR5210_RETRY_LMT_LG_RETRY 0x000000f0
#define AR5K_AR5210_RETRY_LMT_LG_RETRY_S 4
-#define AR5K_AR5210_RETRY_LMT_SSH_RETRY 0x00003f00
+#define AR5K_AR5210_RETRY_LMT_SSH_RETRY 0x00003f00
#define AR5K_AR5210_RETRY_LMT_SSH_RETRY_S 8
-#define AR5K_AR5210_RETRY_LMT_SLG_RETRY 0x000fc000
+#define AR5K_AR5210_RETRY_LMT_SLG_RETRY 0x000fc000
#define AR5K_AR5210_RETRY_LMT_SLG_RETRY_S 14
#define AR5K_AR5210_RETRY_LMT_CW_MIN 0x3ff00000
#define AR5K_AR5210_RETRY_LMT_CW_MIN_S 20
@@ -434,85 +434,85 @@ typedef enum {
* Transmit latency register
*/
#define AR5K_AR5210_USEC 0x8020
-#define AR5K_AR5210_USEC_1 0x0000007f
+#define AR5K_AR5210_USEC_1 0x0000007f
#define AR5K_AR5210_USEC_1_S 0
-#define AR5K_AR5210_USEC_32 0x00003f80
+#define AR5K_AR5210_USEC_32 0x00003f80
#define AR5K_AR5210_USEC_32_S 7
-#define AR5K_AR5210_USEC_TX_LATENCY 0x000fc000
+#define AR5K_AR5210_USEC_TX_LATENCY 0x000fc000
#define AR5K_AR5210_USEC_TX_LATENCY_S 14
-#define AR5K_AR5210_USEC_RX_LATENCY 0x03f00000
+#define AR5K_AR5210_USEC_RX_LATENCY 0x03f00000
#define AR5K_AR5210_USEC_RX_LATENCY_S 20
/*
* PCU beacon control register
*/
#define AR5K_AR5210_BEACON 0x8024
-#define AR5K_AR5210_BEACON_PERIOD 0x0000ffff
+#define AR5K_AR5210_BEACON_PERIOD 0x0000ffff
#define AR5K_AR5210_BEACON_PERIOD_S 0
-#define AR5K_AR5210_BEACON_TIM 0x007f0000
+#define AR5K_AR5210_BEACON_TIM 0x007f0000
#define AR5K_AR5210_BEACON_TIM_S 16
-#define AR5K_AR5210_BEACON_EN 0x00800000
-#define AR5K_AR5210_BEACON_RESET_TSF 0x01000000
+#define AR5K_AR5210_BEACON_EN 0x00800000
+#define AR5K_AR5210_BEACON_RESET_TSF 0x01000000
/*
* CFP period register
*/
-#define AR5K_AR5210_CFP_PERIOD 0x8028
+#define AR5K_AR5210_CFP_PERIOD 0x8028
/*
* Next beacon time register
*/
-#define AR5K_AR5210_TIMER0 0x802c
+#define AR5K_AR5210_TIMER0 0x802c
/*
* Next DMA beacon alert register
*/
-#define AR5K_AR5210_TIMER1 0x8030
+#define AR5K_AR5210_TIMER1 0x8030
/*
* Next software beacon alert register
*/
-#define AR5K_AR5210_TIMER2 0x8034
+#define AR5K_AR5210_TIMER2 0x8034
/*
* Next ATIM window time register
*/
-#define AR5K_AR5210_TIMER3 0x8038
+#define AR5K_AR5210_TIMER3 0x8038
/*
* First inter frame spacing register (IFS)
*/
#define AR5K_AR5210_IFS0 0x8040
-#define AR5K_AR5210_IFS0_SIFS 0x000007ff
+#define AR5K_AR5210_IFS0_SIFS 0x000007ff
#define AR5K_AR5210_IFS0_SIFS_S 0
-#define AR5K_AR5210_IFS0_DIFS 0x007ff800
+#define AR5K_AR5210_IFS0_DIFS 0x007ff800
#define AR5K_AR5210_IFS0_DIFS_S 11
/*
* Second inter frame spacing register (IFS)
*/
#define AR5K_AR5210_IFS1 0x8044
-#define AR5K_AR5210_IFS1_PIFS 0x00000fff
+#define AR5K_AR5210_IFS1_PIFS 0x00000fff
#define AR5K_AR5210_IFS1_PIFS_S 0
-#define AR5K_AR5210_IFS1_EIFS 0x03fff000
+#define AR5K_AR5210_IFS1_EIFS 0x03fff000
#define AR5K_AR5210_IFS1_EIFS_S 12
-#define AR5K_AR5210_IFS1_CS_EN 0x04000000
+#define AR5K_AR5210_IFS1_CS_EN 0x04000000
/*
* CFP duration register
*/
-#define AR5K_AR5210_CFP_DUR 0x8048
+#define AR5K_AR5210_CFP_DUR 0x8048
/*
* Receive filter register
*/
-#define AR5K_AR5210_RX_FILTER 0x804c
-#define AR5K_AR5210_RX_FILTER_UNICAST 0x00000001
-#define AR5K_AR5210_RX_FILTER_MULTICAST 0x00000002
-#define AR5K_AR5210_RX_FILTER_BROADCAST 0x00000004
-#define AR5K_AR5210_RX_FILTER_CONTROL 0x00000008
-#define AR5K_AR5210_RX_FILTER_BEACON 0x00000010
-#define AR5K_AR5210_RX_FILTER_PROMISC 0x00000020
+#define AR5K_AR5210_RX_FILTER 0x804c
+#define AR5K_AR5210_RX_FILTER_UNICAST 0x00000001
+#define AR5K_AR5210_RX_FILTER_MULTICAST 0x00000002
+#define AR5K_AR5210_RX_FILTER_BROADCAST 0x00000004
+#define AR5K_AR5210_RX_FILTER_CONTROL 0x00000008
+#define AR5K_AR5210_RX_FILTER_BEACON 0x00000010
+#define AR5K_AR5210_RX_FILTER_PROMISC 0x00000020
/*
* Multicast filter register (lower 32 bits)
@@ -527,7 +527,7 @@ typedef enum {
/*
* Transmit mask register (lower 32 bits)
*/
-#define AR5K_AR5210_TX_MASK0 0x8058
+#define AR5K_AR5210_TX_MASK0 0x8058
/*
* Transmit mask register (higher 16 bits)
@@ -548,20 +548,20 @@ typedef enum {
* PCU control register
*/
#define AR5K_AR5210_DIAG_SW 0x8068
-#define AR5K_AR5210_DIAG_SW_DIS_WEP_ACK 0x00000001
-#define AR5K_AR5210_DIAG_SW_DIS_ACK 0x00000002
-#define AR5K_AR5210_DIAG_SW_DIS_CTS 0x00000004
-#define AR5K_AR5210_DIAG_SW_DIS_ENC 0x00000008
-#define AR5K_AR5210_DIAG_SW_DIS_DEC 0x00000010
-#define AR5K_AR5210_DIAG_SW_DIS_TX 0x00000020
-#define AR5K_AR5210_DIAG_SW_DIS_RX 0x00000040
-#define AR5K_AR5210_DIAG_SW_LOOP_BACK 0x00000080
-#define AR5K_AR5210_DIAG_SW_CORR_FCS 0x00000100
-#define AR5K_AR5210_DIAG_SW_CHAN_INFO 0x00000200
-#define AR5K_AR5210_DIAG_SW_EN_SCRAM_SEED 0x00000400
-#define AR5K_AR5210_DIAG_SW_SCVRAM_SEED 0x0003f800
-#define AR5K_AR5210_DIAG_SW_DIS_SEQ_INC 0x00040000
-#define AR5K_AR5210_DIAG_SW_FRAME_NV0 0x00080000
+#define AR5K_AR5210_DIAG_SW_DIS_WEP_ACK 0x00000001
+#define AR5K_AR5210_DIAG_SW_DIS_ACK 0x00000002
+#define AR5K_AR5210_DIAG_SW_DIS_CTS 0x00000004
+#define AR5K_AR5210_DIAG_SW_DIS_ENC 0x00000008
+#define AR5K_AR5210_DIAG_SW_DIS_DEC 0x00000010
+#define AR5K_AR5210_DIAG_SW_DIS_TX 0x00000020
+#define AR5K_AR5210_DIAG_SW_DIS_RX 0x00000040
+#define AR5K_AR5210_DIAG_SW_LOOP_BACK 0x00000080
+#define AR5K_AR5210_DIAG_SW_CORR_FCS 0x00000100
+#define AR5K_AR5210_DIAG_SW_CHAN_INFO 0x00000200
+#define AR5K_AR5210_DIAG_SW_EN_SCRAM_SEED 0x00000400
+#define AR5K_AR5210_DIAG_SW_SCVRAM_SEED 0x0003f800
+#define AR5K_AR5210_DIAG_SW_DIS_SEQ_INC 0x00040000
+#define AR5K_AR5210_DIAG_SW_FRAME_NV0 0x00080000
/*
* TSF (clock) register (lower 32 bits)
@@ -582,15 +582,15 @@ typedef enum {
* Retry count register
*/
#define AR5K_AR5210_RETRY_CNT 0x8084
-#define AR5K_AR5210_RETRY_CNT_SSH 0x0000003f
-#define AR5K_AR5210_RETRY_CNT_SLG 0x00000fc0
+#define AR5K_AR5210_RETRY_CNT_SSH 0x0000003f
+#define AR5K_AR5210_RETRY_CNT_SLG 0x00000fc0
/*
* Back-off status register
*/
#define AR5K_AR5210_BACKOFF 0x8088
-#define AR5K_AR5210_BACKOFF_CW 0x000003ff
-#define AR5K_AR5210_BACKOFF_CNT 0x03ff0000
+#define AR5K_AR5210_BACKOFF_CW 0x000003ff
+#define AR5K_AR5210_BACKOFF_CNT 0x03ff0000
/*
* NAV register (current)
@@ -635,7 +635,7 @@ typedef enum {
#define AR5K_AR5210_KEYTABLE_SIZE 64
#define AR5K_AR5210_KEYCACHE_SIZE 8
-/*
+/*
* PHY register
*/
#define AR5K_AR5210_PHY(_n) (0x9800 + ((_n) << 2))
diff --git a/sys/dev/ic/ar5210var.h b/sys/dev/ic/ar5210var.h
index 2339d316fdc..ac67c93bcdb 100644
--- a/sys/dev/ic/ar5210var.h
+++ b/sys/dev/ic/ar5210var.h
@@ -1,7 +1,7 @@
-/* $OpenBSD: ar5210var.h,v 1.1 2004/11/02 03:01:16 reyk Exp $ */
+/* $OpenBSD: ar5210var.h,v 1.2 2004/11/02 14:05:49 reyk Exp $ */
/*
- * Copyright (c) 2004 Reyk Floeter <reyk@vantronix.net>.
+ * Copyright (c) 2004 Reyk Floeter <reyk@vantronix.net>.
*
* All rights reserved.
*
@@ -74,8 +74,8 @@ struct ar5k_ar5210_rx_desc {
} __attribute__ ((__packed__));
struct ar5k_ar5210_rx_status {
- /*
- * First word
+ /*
+ * First word
*/
u_int32_t data_len:12;
u_int32_t more:1;
@@ -125,7 +125,7 @@ struct ar5k_ar5210_tx_desc {
u_int32_t inter_req:1;
u_int32_t encrypt_key_valid:1;
u_int32_t r1:1;
-
+
/*
* Second word
*/
diff --git a/sys/dev/ic/ar5xxx.c b/sys/dev/ic/ar5xxx.c
index 33b1f834864..bb3fc622e4c 100644
--- a/sys/dev/ic/ar5xxx.c
+++ b/sys/dev/ic/ar5xxx.c
@@ -1,7 +1,7 @@
-/* $OpenBSD: ar5xxx.c,v 1.1 2004/11/02 03:01:16 reyk Exp $ */
+/* $OpenBSD: ar5xxx.c,v 1.2 2004/11/02 14:05:49 reyk Exp $ */
/*
- * Copyright (c) 2004 Reyk Floeter <reyk@vantronix.net>.
+ * Copyright (c) 2004 Reyk Floeter <reyk@vantronix.net>.
*
* All rights reserved.
*
@@ -137,7 +137,7 @@ ath_hal_attach(device, sc, st, sh, status)
int i;
*status = -EINVAL;
-
+
/*
* Call the chipset-dependent attach routine by device id
*/
@@ -194,7 +194,7 @@ ath_hal_attach(device, sc, st, sh, status)
AR5K_PRINTF("unable to get device capabilities\n");
goto failed;
}
-
+
if((*status = ar5k_eeprom_read_mac(hal, mac)) != HAL_OK) {
AR5K_PRINTF("unable to read address from EEPROM\n");
goto failed;
@@ -220,7 +220,7 @@ ath_hal_attach(device, sc, st, sh, status)
return(NULL);
}
-u_int16_t
+u_int16_t
ath_hal_computetxtime(hal, rates, frame_length, rate_index, short_preamble)
struct ath_hal *hal;
const HAL_RATE_TABLE *rates;
@@ -246,13 +246,13 @@ ath_hal_computetxtime(hal, rates, frame_length, rate_index, short_preamble)
/*
* CCK / DS mode (802.11b)
*/
- value = AR5K_CCK_TX_TIME(rate->rateKbps, frame_length,
+ value = AR5K_CCK_TX_TIME(rate->rateKbps, frame_length,
(short_preamble && rate->shortPreamble));
break;
case IEEE80211_T_OFDM:
/*
- * Orthogonal Frequency Division Multiplexing
+ * Orthogonal Frequency Division Multiplexing
*/
if(AR5K_OFDM_NUM_BITS_PER_SYM(rate->rateKbps) == 0)
return(0);
@@ -261,7 +261,7 @@ ath_hal_computetxtime(hal, rates, frame_length, rate_index, short_preamble)
case IEEE80211_T_TURBO:
/*
- * Orthogonal Frequency Division Multiplexing
+ * Orthogonal Frequency Division Multiplexing
* Atheros "Turbo Mode" (doubled rates)
*/
if(AR5K_TURBO_NUM_BITS_PER_SYM(rate->rateKbps) == 0)
@@ -271,7 +271,7 @@ ath_hal_computetxtime(hal, rates, frame_length, rate_index, short_preamble)
case IEEE80211_T_XR:
/*
- * Orthogonal Frequency Division Multiplexing
+ * Orthogonal Frequency Division Multiplexing
* Atheros "eXtended Range" (XR)
*/
if(AR5K_XR_NUM_BITS_PER_SYM(rate->rateKbps) == 0)
@@ -321,15 +321,18 @@ ath_hal_init_channels(hal, channels, max_channels, channels_size, country, mode,
c = 0;
domain_current = hal->ah_getRegDomain(hal);
- domain_5ghz = ieee80211_regdomain2flag(domain_current, IEEE80211_CHANNELS_5GHZ_MIN);
- domain_2ghz = ieee80211_regdomain2flag(domain_current, IEEE80211_CHANNELS_2GHZ_MIN);
+ domain_5ghz = ieee80211_regdomain2flag(domain_current,
+ IEEE80211_CHANNELS_5GHZ_MIN);
+ domain_2ghz = ieee80211_regdomain2flag(domain_current,
+ IEEE80211_CHANNELS_2GHZ_MIN);
/*
* Create channel list based on chipset capabilities, regulation domain
* and mode. 5GHz...
*/
for(i = 0; (hal->ah_capabilities.cap_range.range_5ghz_max > 0) &&
- (i < (sizeof(ar5k_5ghz_channels) / sizeof(ar5k_5ghz_channels[0]))) &&
+ (i < (sizeof(ar5k_5ghz_channels) /
+ sizeof(ar5k_5ghz_channels[0]))) &&
(c < max_channels); i++) {
/* Check if channel is supported by the chipset */
if((ar5k_5ghz_channels[i].rc_channel <
@@ -337,20 +340,20 @@ ath_hal_init_channels(hal, channels, max_channels, channels_size, country, mode,
(ar5k_5ghz_channels[i].rc_channel >
hal->ah_capabilities.cap_range.range_5ghz_max))
continue;
-
+
/* Match regulation domain */
if((IEEE80211_DMN(ar5k_5ghz_channels[i].rc_domains) &
IEEE80211_DMN(domain_5ghz)) == 0)
continue;
-
+
/* Match modes */
if(ar5k_5ghz_channels[i].rc_mode & IEEE80211_CHAN_TURBO)
all_channels[c].channelFlags = CHANNEL_T;
else if(ar5k_5ghz_channels[i].rc_mode & IEEE80211_CHAN_OFDM)
all_channels[c].channelFlags = CHANNEL_A;
- else
+ else
continue;
-
+
/* Write channel and increment counter */
all_channels[c++].channel = ar5k_5ghz_channels[i].rc_channel;
}
@@ -358,16 +361,17 @@ ath_hal_init_channels(hal, channels, max_channels, channels_size, country, mode,
/*
* ...and 2GHz.
*/
- for(i = 0; (hal->ah_capabilities.cap_range.range_2ghz_max > 0) &&
- (i < (sizeof(ar5k_2ghz_channels) / sizeof(ar5k_2ghz_channels[0]))) &&
- (c < max_channels); i++) {
+ for (i = 0; (hal->ah_capabilities.cap_range.range_2ghz_max > 0) &&
+ (i < (sizeof(ar5k_2ghz_channels) /
+ sizeof(ar5k_2ghz_channels[0]))) &&
+ (c < max_channels); i++) {
/* Check if channel is supported by the chipset */
if((ar5k_2ghz_channels[i].rc_channel <
hal->ah_capabilities.cap_range.range_2ghz_min) ||
(ar5k_2ghz_channels[i].rc_channel >
hal->ah_capabilities.cap_range.range_2ghz_max))
continue;
-
+
/* Match regulation domain */
if((IEEE80211_DMN(ar5k_2ghz_channels[i].rc_domains) &
IEEE80211_DMN(domain_2ghz)) == 0)
@@ -380,7 +384,7 @@ ath_hal_init_channels(hal, channels, max_channels, channels_size, country, mode,
all_channels[c].channelFlags = CHANNEL_TG;
else if(ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_OFDM)
all_channels[c].channelFlags = CHANNEL_G;
- else
+ else
continue;
/* Write channel and increment counter */
@@ -402,7 +406,7 @@ ar5k_radar_alert(hal)
struct ath_hal *hal;
{
/*
- * Limit ~1/s
+ * Limit ~1/s
*/
if(hal->ah_radar.r_last_channel.channel ==
hal->ah_current_channel.channel &&
@@ -421,7 +425,7 @@ ar5k_radar_alert(hal)
int
ar5k_eeprom_read_mac(hal, mac)
- struct ath_hal *hal;
+ struct ath_hal *hal;
u_int8_t *mac;
{
u_int32_t total, offset;
@@ -454,8 +458,8 @@ ar5k_eeprom_read_mac(hal, mac)
memcpy(mac, &mac_d, IEEE80211_ADDR_LEN);
- if((!total) || total == (3 * 0xffff))
- return(-EINVAL);
+ if((!total) || total == (3 * 0xffff))
+ return(-EINVAL);
return(0);
}
@@ -486,12 +490,12 @@ ar5k_bitswap(val, bits)
u_int bits;
{
u_int32_t retval = 0, bit, i;
-
+
for (i = 0; i < bits; i++) {
bit = (val >> i) & 1;
retval = (retval << 1) | bit;
}
-
+
return(retval);
}
@@ -544,5 +548,3 @@ ar5k_register_timeout(hal, reg, flag, val, is_set)
return(AH_TRUE);
}
-
-
diff --git a/sys/dev/ic/ar5xxx.h b/sys/dev/ic/ar5xxx.h
index 6bc2b2babc7..2bafa3f9259 100644
--- a/sys/dev/ic/ar5xxx.h
+++ b/sys/dev/ic/ar5xxx.h
@@ -1,7 +1,7 @@
-/* $OpenBSD: ar5xxx.h,v 1.1 2004/11/02 03:01:16 reyk Exp $ */
+/* $OpenBSD: ar5xxx.h,v 1.2 2004/11/02 14:05:49 reyk Exp $ */
/*
- * Copyright (c) 2004 Reyk Floeter <reyk@vantronix.net>.
+ * Copyright (c) 2004 Reyk Floeter <reyk@vantronix.net>.
*
* All rights reserved.
*
@@ -29,8 +29,8 @@
* HAL interface for Atheros Wireless LAN devices.
*
* ar5k is a free replacement of the binary-only HAL used by some drivers
- * for Atheros chipsets. While using a different ABI, it tries to be
- * source-compatible with the original (non-free) HAL interface.
+ * for Atheros chipsets. While using a different ABI, it tries to be
+ * source-compatible with the original (non-free) HAL interface.
*
* Many thanks to various contributors who supported the development of
* ar5k with hard work and useful information. And, of course, for all the
@@ -42,7 +42,7 @@
#define _AR5K_H
#include <sys/param.h>
-#include <sys/systm.h>
+#include <sys/systm.h>
#include <sys/sysctl.h>
#include <sys/malloc.h>
#include <sys/lock.h>
@@ -53,7 +53,7 @@
#include <machine/endian.h>
#include <machine/bus.h>
-
+
#include <net/if.h>
#include <net/if_dl.h>
#include <net/if_media.h>
@@ -350,7 +350,7 @@ typedef struct {
#define rt_rate_code_index rateCodeToIndex
#define rt_info info
-} HAL_RATE_TABLE;
+} HAL_RATE_TABLE;
#define AR5K_RATES_11A { 8, { 0 }, { \
{ 1, IEEE80211_T_OFDM, 6000, 11, 0, 140, 0 }, \
@@ -386,7 +386,7 @@ typedef enum {
typedef struct {
u_int16_t channel; /* MHz */
- u_int16_t channelFlags;
+ u_int16_t channelFlags;
#define c_channel channel
#define c_channel_flags cnannelFlags
@@ -774,7 +774,7 @@ struct ath_hal {
ar5k_capabilities_t ah_capabilities;
HAL_TXQ_INFO ah_txq[HAL_NUM_TX_QUEUES];
-
+
struct {
HAL_BOOL r_enabled;
int r_last_alert;
@@ -802,7 +802,7 @@ struct ath_hal {
typedef struct ath_hal*(ar5k_attach_t)
(u_int16_t, void *, bus_space_tag_t, bus_space_handle_t, HAL_STATUS *);
-/*
+/*
* Some tuneable values (these should be changeable by the user)
*/
@@ -849,7 +849,7 @@ typedef struct ath_hal*(ar5k_attach_t)
#define AR5K_INIT_TXNOFRM 0
#define AR5K_INIT_BEACON_PERIOD 65535
#define AR5K_INIT_TIM_OFFSET 0
-#define AR5K_INIT_BEACON_EN 0
+#define AR5K_INIT_BEACON_EN 0
#define AR5K_INIT_RESET_TSF 0
#define AR5K_INIT_TRANSMIT_LATENCY ( \
(AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
@@ -907,8 +907,8 @@ struct ar5k_ini {
} ini_mode;
};
-/*
- * Unaligned little endian access
+/*
+ * Unaligned little endian access
*/
#define AR5K_LE_READ_2(_p) \
diff --git a/sys/dev/ic/ath.c b/sys/dev/ic/ath.c
index 74db2c1b027..0485b49c0d5 100644
--- a/sys/dev/ic/ath.c
+++ b/sys/dev/ic/ath.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: ath.c,v 1.1 2004/11/02 02:45:37 reyk Exp $ */
+/* $OpenBSD: ath.c,v 1.2 2004/11/02 14:05:49 reyk Exp $ */
/* $NetBSD: ath.c,v 1.37 2004/08/18 21:59:39 dyoung Exp $ */
/*-
@@ -434,10 +434,10 @@ ath_attach(u_int16_t devid, struct ath_softc *sc)
ah->ah_macVersion, ah->ah_macRev,
ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
if (ah->ah_analog5GhzRev != 0)
- printf(" 5ghz radio %d.%d",
+ printf(" 5GHz radio %d.%d",
ah->ah_analog5GhzRev >> 4, ah->ah_analog5GhzRev & 0xf);
if (ah->ah_analog2GhzRev != 0)
- printf(" 2ghz radio %d.%d",
+ printf(" 2GHz radio %d.%d",
ah->ah_analog2GhzRev >> 4, ah->ah_analog2GhzRev & 0xf);
sc->sc_ah = ah;
sc->sc_invalid = 0; /* ready to go, enable interrupt handling */
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 10:37:14 +0000