diff options
Diffstat (limited to 'sys/dev/isa/wdreg.h')
| -rw-r--r-- | sys/dev/isa/wdreg.h | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/sys/dev/isa/wdreg.h b/sys/dev/isa/wdreg.h index 9e3954eca8d..ad3bb8bb107 100644 --- a/sys/dev/isa/wdreg.h +++ b/sys/dev/isa/wdreg.h @@ -46,6 +46,7 @@ #define wd_precomp 0x001 /* write precompensation (W) */ #define wd_features 0x001 /* features (W) */ #define wd_seccnt 0x002 /* sector count (R/W) */ +#define wd_ireason 0x002 /* interrupt reason (R/W) (for atapi) */ #define wd_sector 0x003 /* first sector number (R/W) */ #define wd_cyl_lo 0x004 /* cylinder address, low byte (R/W) */ #define wd_cyl_hi 0x005 /* cylinder address, high byte (R/W) */ @@ -118,6 +119,52 @@ #define WDSD_CHS 0x00 /* cylinder/head/sector addressing */ #define WDSD_LBA 0x40 /* logical block addressing */ +/* Commands for ATAPI devices */ +#define ATAPI_CHECK_POWER_MODE 0xe5 +#define ATAPI_EXEC_DRIVE_DIAGS 0x90 +#define ATAPI_IDLE_IMMEDIATE 0xe1 +#define ATAPI_NOP 0x00 +#define ATAPI_PACKET_COMMAND 0xa0 +#define ATAPI_IDENTIFY_DEVICE 0xa1 +#define ATAPI_SOFT_RESET 0x08 +#define ATAPI_SET_FEATURES 0xef +#define ATAPI_SLEEP 0xe6 +#define ATAPI_STANDBY_IMMEDIATE 0xe0 + +/* ireason */ +#define WDCI_CMD 0x01 /* command(1) or data(0) */ +#define WDCI_IN 0x02 /* transfer to(1) or from(0) the host */ +#define WDCI_RELEASE 0x04 /* bus released until completion */ + +#define PHASE_CMDOUT (WDCS_DRQ | WDCI_CMD) +#define PHASE_DATAIN (WDCS_DRQ | WDCI_IN) +#define PHASE_DATAOUT WDCS_DRQ +#define PHASE_COMPLETED (WDCI_IN | WDCI_CMD) +#define PHASE_ABORTED 0 + +/* Commands for ATAPI devices */ +#define ATAPI_CHECK_POWER_MODE 0xe5 +#define ATAPI_EXEC_DRIVE_DIAGS 0x90 +#define ATAPI_IDLE_IMMEDIATE 0xe1 +#define ATAPI_NOP 0x00 +#define ATAPI_PACKET_COMMAND 0xa0 +#define ATAPI_IDENTIFY_DEVICE 0xa1 +#define ATAPI_SOFT_RESET 0x08 +#define ATAPI_SET_FEATURES 0xef +#define ATAPI_SLEEP 0xe6 +#define ATAPI_STANDBY_IMMEDIATE 0xe0 + +/* ireason */ +#define WDCI_CMD 0x01 /* command(1) or data(0) */ +#define WDCI_IN 0x02 /* transfer to(1) or from(0) the host */ +#define WDCI_RELEASE 0x04 /* bus released until completion */ + +#define PHASE_CMDOUT (WDCS_DRQ | WDCI_CMD) +#define PHASE_DATAIN (WDCS_DRQ | WDCI_IN) +#define PHASE_DATAOUT WDCS_DRQ +#define PHASE_COMPLETED (WDCI_IN | WDCI_CMD) +#define PHASE_ABORTED 0 + #ifdef _KERNEL /* |