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Diffstat (limited to 'sys/dev/microcode/aic7xxx/aic7xxx.reg')
-rw-r--r--sys/dev/microcode/aic7xxx/aic7xxx.reg310
1 files changed, 187 insertions, 123 deletions
diff --git a/sys/dev/microcode/aic7xxx/aic7xxx.reg b/sys/dev/microcode/aic7xxx/aic7xxx.reg
index bb52bdba889..6be74e809ba 100644
--- a/sys/dev/microcode/aic7xxx/aic7xxx.reg
+++ b/sys/dev/microcode/aic7xxx/aic7xxx.reg
@@ -1,9 +1,8 @@
-/* $NetBSD$ */
-
+/* $OpenBSD: aic7xxx.reg,v 1.3 2002/02/16 04:36:33 smurph Exp $ */
/*
* Aic7xxx register and scratch ram definitions.
*
- * Copyright (c) 1994-2000 Justin Gibbs.
+ * Copyright (c) 1994-2001 Justin Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -16,7 +15,7 @@
* derived from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
- * the GNU Public License ("GPL").
+ * GNU Public License ("GPL").
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
@@ -30,9 +29,11 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.reg,v 1.20 2000/02/09 21:24:59 gibbs Exp $
+ * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.reg,v 1.39 2001/07/18 21:39:47 gibbs Exp $
*/
+VERSION = "$Id: aic7xxx.reg,v 1.3 2002/02/16 04:36:33 smurph Exp $"
+
/*
* This file is processed by the aic7xxx_asm utility for use in assembling
* firmware for the aic7xxx family of SCSI host adapters as well as to generate
@@ -112,6 +113,8 @@ register SCSISIGI {
mask PHASE_MASK CDI|IOI|MSGI
mask P_DATAOUT 0x00
mask P_DATAIN IOI
+ mask P_DATAOUT_DT P_DATAOUT|MSGI
+ mask P_DATAIN_DT P_DATAIN|MSGI
mask P_COMMAND CDI
mask P_MESGOUT CDI|MSGI
mask P_STATUS CDI|IOI
@@ -174,6 +177,8 @@ register SCSIID {
address 0x005
access_mode RW
mask TID 0xf0 /* Target ID mask */
+ mask TWIN_TID 0x70
+ bit TWIN_CHNLB 0x80
mask OID 0x0f /* Our ID mask */
/*
* SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book)
@@ -246,6 +251,7 @@ register CLRSINT0 {
bit CLRSELDI 0x20
bit CLRSELINGO 0x10
bit CLRSWRAP 0x08
+ bit CLRIOERR 0x08 /* Ultra2 Only */
bit CLRSPIORDY 0x02
}
@@ -307,7 +313,12 @@ register SSTAT2 {
address 0x00d
access_mode RO
bit OVERRUN 0x80
+ bit SHVALID 0x40 /* Shaddow Layer non-zero */
bit EXP_ACTIVE 0x10 /* SCSI Expander Active */
+ bit CRCVALERR 0x08 /* CRC doesn't match (U3 only) */
+ bit CRCENDERR 0x04 /* No terminal CRC packet (U3 only) */
+ bit CRCREQERR 0x02 /* Illegal CRC packet req (U3 only) */
+ bit DUAL_EDGE_ERR 0x01 /* Incorrect data phase (U3 only) */
mask SFCNT 0x1f
}
@@ -373,12 +384,12 @@ register SIMODE1 {
*/
register SCSIBUSL {
address 0x012
- access_mode RO
+ access_mode RW
}
register SCSIBUSH {
address 0x013
- access_mode RO
+ access_mode RW
}
/*
@@ -673,8 +684,16 @@ register DSCOMMAND0 {
bit CIOPARCKEN 0x01 /* Internal bus parity error enable */
}
+register DSCOMMAND1 {
+ address 0x085
+ access_mode RW
+ mask DSLATT 0xfc /* PCI latency timer (non-ultra2) */
+ bit HADDLDSEL1 0x02 /* Host Address Load Select Bits */
+ bit HADDLDSEL0 0x01
+}
+
/*
- * Bus On/Off Time (p. 3-44)
+ * Bus On/Off Time (p. 3-44) aic7770 only
*/
register BUSTIME {
address 0x085
@@ -693,6 +712,7 @@ register BUSSPD {
mask STBOFF 0x38
mask STBON 0x07
mask DFTHRSH_100 0xc0
+ mask DFTHRSH_75 0x80
}
/* aic7850/55/60/70/80/95 only */
@@ -748,7 +768,7 @@ register HCNT {
/*
* SCB Pointer (p. 3-49)
- * Gate one of the four SCBs into the SCBARRAY window.
+ * Gate one of the SCBs into the SCBARRAY window.
*/
register SCBPTR {
address 0x090
@@ -770,11 +790,15 @@ register INTSTAT {
mask SEND_REJECT 0x10|SEQINT /* sending a message reject */
mask NO_IDENT 0x20|SEQINT /* no IDENTIFY after reconnect*/
mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */
- mask UPDATE_TMSG_REQ 0x60|SEQINT /* Update TMSG_REQ values */
- mask BAD_STATUS 0x70|SEQINT /* Bad status from target */
- mask RESIDUAL 0x80|SEQINT /* Residual byte count != 0 */
- mask TRACE_POINT 0x90|SEQINT
- mask HOST_MSG_LOOP 0xa0|SEQINT /*
+ mask IGN_WIDE_RES 0x40|SEQINT /* Complex IGN Wide Res Msg */
+ mask PDATA_REINIT 0x50|SEQINT /*
+ * Returned to data phase
+ * that requires data
+ * transfer pointers to be
+ * recalculated from the
+ * transfer residual.
+ */
+ mask HOST_MSG_LOOP 0x60|SEQINT /*
* The bus is ready for the
* host to perform another
* message transaction. This
@@ -783,22 +807,37 @@ register INTSTAT {
* that require a kernel based
* message state engine.
*/
- mask PERR_DETECTED 0xb0|SEQINT /*
+ mask BAD_STATUS 0x70|SEQINT /* Bad status from target */
+ mask PERR_DETECTED 0x80|SEQINT /*
* Either the phase_lock
* or inb_next routine has
* noticed a parity error.
*/
- mask TRACEPOINT 0xd0|SEQINT
- mask MSGIN_PHASEMIS 0xe0|SEQINT /*
- * Target changed phase on us
- * when we were expecting
- * another msgin byte.
- */
- mask DATA_OVERRUN 0xf0|SEQINT /*
+ mask DATA_OVERRUN 0x90|SEQINT /*
* Target attempted to write
* beyond the bounds of its
* command.
+ */
+ mask MKMSG_FAILED 0xa0|SEQINT /*
+ * Target completed command
+ * without honoring our ATN
+ * request to issue a message.
*/
+ mask MISSED_BUSFREE 0xb0|SEQINT /*
+ * The sequencer never saw
+ * the bus go free after
+ * either a command complete
+ * or disconnect message.
+ */
+ mask SCB_MISMATCH 0xc0|SEQINT /*
+ * Downloaded SCB's tag does
+ * not match the entry we
+ * intended to download.
+ */
+ mask NO_FREE_SCB 0xd0|SEQINT /*
+ * get_free_or_disc_scb failed.
+ */
+ mask OUT_OF_RANGE 0xe0|SEQINT
mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */
mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT)
@@ -854,7 +893,8 @@ register DFSTATUS {
address 0x094
access_mode RO
bit PRELOAD_AVAIL 0x80
- bit DWORDEMP 0x20
+ bit DFCACHETH 0x40
+ bit FIFOQWDEMP 0x20
bit MREQPEND 0x10
bit HDONE 0x08
bit DFTHRESH 0x04
@@ -946,6 +986,7 @@ register SCSIPHASE {
bit MSG_OUT_PHASE 0x04
bit DATA_IN_PHASE 0x02
bit DATA_OUT_PHASE 0x01
+ mask DATA_PHASE_MASK 0x03
}
/*
@@ -962,35 +1003,19 @@ register SFUNCT {
*/
scb {
address 0x0a0
- SCB_CONTROL {
- size 1
- bit TARGET_SCB 0x80
- bit DISCENB 0x40
- bit TAG_ENB 0x20
- bit MK_MESSAGE 0x10
- bit ULTRAENB 0x08
- bit DISCONNECTED 0x04
- mask SCB_TAG_TYPE 0x03
- }
- SCB_TCL {
- size 1
- bit SELBUSB 0x08
- mask TID 0xf0
- mask LID 0x07
+ SCB_CDB_PTR {
+ size 4
+ alias SCB_RESIDUAL_DATACNT
+ alias SCB_CDB_STORE
+ alias SCB_TARGET_INFO
}
- SCB_TARGET_STATUS {
- size 1
- }
- SCB_SGCOUNT {
- size 1
- }
- SCB_SGPTR {
+ SCB_RESIDUAL_SGPTR {
size 4
}
- SCB_RESID_SGCNT {
+ SCB_SCSI_STATUS {
size 1
}
- SCB_RESID_DCNT {
+ SCB_CDB_STORE_PAD {
size 3
}
SCB_DATAPTR {
@@ -998,24 +1023,44 @@ scb {
}
SCB_DATACNT {
/*
- * Really only 3 bytes, but padded to make
- * the kernel's job easier.
+ * The last byte is really the high address bits for
+ * the data address.
*/
size 4
+ bit SG_LAST_SEG 0x80 /* In the fourth byte */
+ mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */
}
- SCB_CMDPTR {
- alias SCB_TARGET_PHASES
- bit TARGET_DATA_IN 0x1 /* In the second byte */
+ SCB_SGPTR {
size 4
+ bit SG_RESID_VALID 0x04 /* In the first byte */
+ bit SG_FULL_RESID 0x02 /* In the first byte */
+ bit SG_LIST_NULL 0x01 /* In the first byte */
+ }
+ SCB_CONTROL {
+ size 1
+ bit TARGET_SCB 0x80
+ bit DISCENB 0x40
+ bit TAG_ENB 0x20
+ bit MK_MESSAGE 0x10
+ bit ULTRAENB 0x08
+ bit DISCONNECTED 0x04
+ mask SCB_TAG_TYPE 0x03
}
- SCB_CMDLEN {
- alias SCB_INITIATOR_TAG
+ SCB_SCSIID {
+ size 1
+ bit TWIN_CHNLB 0x80
+ mask TWIN_TID 0x70
+ mask TID 0xf0
+ mask OID 0x0f
+ }
+ SCB_LUN {
+ mask LID 0xff
size 1
}
SCB_TAG {
size 1
}
- SCB_NEXT {
+ SCB_CDB_LEN {
size 1
}
SCB_SCSIRATE {
@@ -1024,22 +1069,20 @@ scb {
SCB_SCSIOFFSET {
size 1
}
- SCB_SPARE {
- size 3
+ SCB_NEXT {
+ size 1
}
- SCB_CMDSTORE {
+ SCB_64_SPARE {
size 16
}
- SCB_CMDSTORE_BUSADDR {
- size 4
- }
- SCB_64BYTE_SPARE {
- size 12
+ SCB_64_BTT {
+ size 16
}
}
-const SCB_32BYTE_SIZE 28
-const SCB_64BYTE_SIZE 48
+const SCB_UPLOAD_SIZE 32
+const SCB_DOWNLOAD_SIZE 32
+const SCB_DOWNLOAD_SIZE_64 48
const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */
@@ -1085,7 +1128,7 @@ register CCSGCTL {
address 0x0EB
bit CCSGDONE 0x80
bit CCSGEN 0x08
- bit FLAG 0x02
+ bit SG_FETCH_NEEDED 0x02 /* Bit used for software state */
bit CCSGRESET 0x01
}
@@ -1166,14 +1209,23 @@ register DFF_THRSH {
mask WR_DFTHRSH_MAX 0x70
}
-register SG_CACHEPTR {
- access_mode RW
+register SG_CACHE_PRE {
+ access_mode WO
address 0x0fc
- mask SG_USER_DATA 0xfc
+ mask SG_ADDR_MASK 0xf8
+ bit ODD_SEG 0x04
bit LAST_SEG 0x02
bit LAST_SEG_DONE 0x01
}
+register SG_CACHE_SHADOW {
+ access_mode RO
+ address 0x0fc
+ mask SG_ADDR_MASK 0xf8
+ bit ODD_SEG 0x04
+ bit LAST_SEG 0x02
+ bit LAST_SEG_DONE 0x01
+}
/* ---------------------- Scratch RAM Offsets ------------------------- */
/* These offsets are either to values that are initialized by the board's
* BIOS or are specified by the sequencer code.
@@ -1195,21 +1247,45 @@ scratch_ram {
/*
* 1 byte per target starting at this address for configuration values
*/
- TARG_SCSIRATE {
- alias CMDSIZE_TABLE
+ BUSY_TARGETS {
+ alias TARG_SCSIRATE
size 16
}
/*
- * Bit vector of targets that have ULTRA enabled.
+ * Bit vector of targets that have ULTRA enabled as set by
+ * the BIOS. The Sequencer relies on a per-SCB field to
+ * control whether to enable Ultra transfers or not. During
+ * initialization, we read this field and reuse it for 2
+ * entries in the busy target table.
*/
ULTRA_ENB {
+ alias CMDSIZE_TABLE
size 2
}
/*
- * Bit vector of targets that have disconnection disabled.
+ * Bit vector of targets that have disconnection disabled as set by
+ * the BIOS. The Sequencer relies in a per-SCB field to control the
+ * disconnect priveldge. During initialization, we read this field
+ * and reuse it for 2 entries in the busy target table.
*/
DISC_DSB {
size 2
+ }
+ CMDSIZE_TABLE_TAIL {
+ size 4
+ }
+ /*
+ * Partial transfer past cacheline end to be
+ * transferred using an extra S/G.
+ */
+ MWI_RESIDUAL {
+ size 1
+ }
+ /*
+ * SCBID of the next SCB to be started by the controller.
+ */
+ NEXT_QUEUED_SCB {
+ size 1
}
/*
* Single byte buffer used to designate the type or message
@@ -1235,7 +1311,7 @@ scratch_ram {
SEQ_FLAGS {
size 1
bit IDENTIFY_SEEN 0x80
- bit SCBPTR_VALID 0x40
+ bit TARGET_CMD_IS_TAGGED 0x40
bit DPHASE 0x20
/* Target flags */
bit TARG_CMD_PENDING 0x10
@@ -1249,17 +1325,12 @@ scratch_ram {
* target/channel/lun of a
* reconnecting target
*/
- SAVED_TCL {
+ SAVED_SCSIID {
size 1
}
- /* Working value of the number of SG segments left */
- SG_COUNT {
+ SAVED_LUN {
size 1
}
- /* Working value of SG pointer */
- SG_NEXT {
- size 4
- }
/*
* The last bus phase as seen by the sequencer.
*/
@@ -1300,23 +1371,25 @@ scratch_ram {
size 1
}
/*
- * Address of the hardware scb array in the host.
+ * head of list of SCBs that have
+ * completed but have not been
+ * put into the qoutfifo.
*/
- HSCB_ADDR {
- size 4
+ COMPLETE_SCBH {
+ size 1
}
/*
- * Address of the 256 byte array storing the SCBID of outstanding
- * untagged SCBs indexed by TCL.
+ * Address of the hardware scb array in the host.
*/
- SCBID_ADDR {
+ HSCB_ADDR {
size 4
}
/*
- * Address of the array of command descriptors used to store
- * information about incoming selections.
+ * Base address of our shared data with the kernel driver in host
+ * memory. This includes the qoutfifo and target mode
+ * incoming command queue.
*/
- TMODE_CMDADDR {
+ SHARED_DATA_ADDR {
size 4
}
KERNEL_QINPOS {
@@ -1363,23 +1436,6 @@ scratch_ram {
}
/*
- * Number of times we have filled the CCSGRAM with prefetched
- * SG elements.
- */
- PREFETCH_CNT {
- size 1
- }
-
- /*
- * Interrupt kernel for a message to this target on
- * the next transaction. This is usually used for
- * negotiation requests.
- */
- TARGET_MSG_REQUEST {
- size 2
- }
-
- /*
* Sequences the kernel driver has okayed for us. This allows
* the driver to do things like prevent initiator or target
* operations.
@@ -1409,6 +1465,10 @@ scratch_ram {
size 1
}
+ SEQ_FLAGS2 {
+ size 1
+ bit SCB_DMA 0x01
+ }
/*
* These are reserved registers in the card's scratch ram. Some of
* the values are specified in the AHA2742 technical reference manual
@@ -1422,6 +1482,12 @@ scratch_ram {
bit ENSPCHK 0x20
mask HSCSIID 0x07 /* our SCSI ID */
mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */
+ }
+ INTDEF {
+ address 0x05c
+ size 1
+ bit EDGE_TRIG 0x80
+ mask VECTOR 0x0f
}
HOSTCONF {
address 0x05d
@@ -1443,17 +1509,13 @@ scratch_ram {
}
}
+const TID_SHIFT 4
const SCB_LIST_NULL 0xff
const TARGET_CMD_CMPLT 0xfe
const CCSGADDR_MAX 0x80
const CCSGRAM_MAXSEGS 16
-/* Offsets into the SCBID array where different data is stored */
-const QOUTFIFO_OFFSET 0
-const QINFIFO_OFFSET 1
-const UNTAGGEDSCB_OFFSET 2
-
/* WDTR Message values */
const BUS_8_BIT 0x00
const BUS_16_BIT 0x01
@@ -1468,20 +1530,22 @@ const HOST_MSG 0xff
/* Target mode command processing constants */
const CMD_GROUP_CODE_SHIFT 0x05
-const TCL_TARGET_SHIFT 4
-/* The update interval must be a power of 2 */
-const TQINFIFO_UPDATE_CNT 32
-
const STATUS_BUSY 0x08
const STATUS_QUEUE_FULL 0x28
+const SCB_TARGET_PHASES 0
+const SCB_TARGET_DATA_DIR 1
+const SCB_TARGET_STATUS 2
+const SCB_INITIATOR_TAG 3
+const TARGET_DATA_IN 1
/*
* Downloaded (kernel inserted) constants
*/
-
-/*
- * Number of command descriptors in the command descriptor array.
- * No longer used, but left here as an example for how downloaded
- * constantants can be defined.
-const TMODE_NUMCMDS download
- */
+/* Offsets into the SCBID array where different data is stored */
+const QOUTFIFO_OFFSET download
+const QINFIFO_OFFSET download
+const CACHESIZE_MASK download
+const INVERTED_CACHESIZE_MASK download
+const SG_PREFETCH_CNT download
+const SG_PREFETCH_ALIGN_MASK download
+const SG_PREFETCH_ADDR_MASK download
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-11 22:16:15 +0000