diff options
Diffstat (limited to 'sys/dev/microcode/aic7xxx/aic7xxx.seq')
| -rw-r--r-- | sys/dev/microcode/aic7xxx/aic7xxx.seq | 2167 |
1 files changed, 849 insertions, 1318 deletions
diff --git a/sys/dev/microcode/aic7xxx/aic7xxx.seq b/sys/dev/microcode/aic7xxx/aic7xxx.seq index 8f753eb1902..152194f9815 100644 --- a/sys/dev/microcode/aic7xxx/aic7xxx.seq +++ b/sys/dev/microcode/aic7xxx/aic7xxx.seq @@ -1,8 +1,7 @@ -/* $OpenBSD: aic7xxx.seq,v 1.9 2002/02/16 04:36:33 smurph Exp $ */ /* * Adaptec 274x/284x/294x device driver firmware for Linux and FreeBSD. * - * Copyright (c) 1994-2001 Justin Gibbs. + * Copyright (c) 1994-2000 Justin Gibbs. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -15,7 +14,7 @@ * derived from this software without specific prior written permission. * * Alternatively, this software may be distributed under the terms of the - * GNU Public License ("GPL"). + * the GNU Public License ("GPL"). * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE @@ -29,13 +28,14 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.seq,v 1.119 2001/08/05 22:20:12 gibbs Exp $ + * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.seq,v 1.93 2000/01/07 23:08:20 gibbs Exp $ */ -VERSION = "$Id: aic7xxx.seq,v 1.9 2002/02/16 04:36:33 smurph Exp $" - #include <dev/microcode/aic7xxx/aic7xxx.reg> #include <scsi/scsi_message.h> +/* +#include <cam/scsi/scsi_message.h> +*/ /* * A few words on the waiting SCB list: @@ -55,122 +55,172 @@ VERSION = "$Id: aic7xxx.seq,v 1.9 2002/02/16 04:36:33 smurph Exp $" * automatically consume the entries. */ -bus_free_sel: - /* - * Turn off the selection hardware. We need to reset the - * selection request in order to perform a new selection. - */ - and SCSISEQ, TEMODE|ENSELI|ENRSELI|ENAUTOATNP, SCSISEQ; - and SIMODE1, ~ENBUSFREE; +reset: + clr SCSISIGO; /* De-assert BSY */ + mvi MSG_OUT, MSG_NOOP; /* No message to send */ + and SXFRCTL1, ~BITBUCKET; + /* Always allow reselection */ + and SCSISEQ, ENSELI|ENRSELI|ENAUTOATNP, SCSISEQ_TEMPLATE; + if ((ahc->features & AHC_CMD_CHAN) != 0) { + /* Ensure that no DMA operations are in progress */ + clr CCSGCTL; + clr CCSCBCTL; + } + poll_for_work: call clear_target_state; and SXFRCTL0, ~SPIOEN; - if ((ahc->features & AHC_ULTRA2) != 0) { - clr SCSIBUSL; - } - test SCSISEQ, ENSELO jnz poll_for_selection; - if ((ahc->features & AHC_TWIN) != 0) { - xor SBLKCTL,SELBUSB; /* Toggle to the other bus */ - test SCSISEQ, ENSELO jnz poll_for_selection; + if ((ahc->features & AHC_QUEUE_REGS) == 0) { + mov A, QINPOS; } - cmp WAITING_SCBH,SCB_LIST_NULL jne start_waiting; poll_for_work_loop: + if ((ahc->features & AHC_QUEUE_REGS) == 0) { + and SEQCTL, ~PAUSEDIS; + } + test SSTAT0, SELDO|SELDI jnz selection; + test SCSISEQ, ENSELO jnz poll_for_work_loop; if ((ahc->features & AHC_TWIN) != 0) { + /* + * Twin channel devices cannot handle things like SELTO + * interrupts on the "background" channel. So, if we + * are selecting, keep polling the current channel util + * either a selection or reselection occurs. + */ xor SBLKCTL,SELBUSB; /* Toggle to the other bus */ - } - test SSTAT0, SELDO|SELDI jnz selection; + test SSTAT0, SELDO|SELDI jnz selection; + test SCSISEQ, ENSELO jnz poll_for_work; + xor SBLKCTL,SELBUSB; /* Toggle back */ + } + cmp WAITING_SCBH,SCB_LIST_NULL jne start_waiting; test_queue: /* Has the driver posted any work for us? */ -BEGIN_CRITICAL if ((ahc->features & AHC_QUEUE_REGS) != 0) { test QOFF_CTLSTA, SCB_AVAIL jz poll_for_work_loop; + mov NONE, SNSCB_QOFF; + inc QINPOS; } else { - mov A, QINPOS; + or SEQCTL, PAUSEDIS; cmp KERNEL_QINPOS, A je poll_for_work_loop; + inc QINPOS; + and SEQCTL, ~PAUSEDIS; } - mov ARG_1, NEXT_QUEUED_SCB; - /* - * We have at least one queued SCB now and we don't have any - * SCBs in the list of SCBs awaiting selection. Allocate a - * card SCB for the host's SCB and get to work on it. - */ +/* + * We have at least one queued SCB now and we don't have any + * SCBs in the list of SCBs awaiting selection. If we have + * any SCBs available for use, pull the tag from the QINFIFO + * and get to work on it. + */ if ((ahc->flags & AHC_PAGESCBS) != 0) { mov ALLZEROS call get_free_or_disc_scb; - } else { + } + +dequeue_scb: + add A, -1, QINPOS; + mvi QINFIFO_OFFSET call fetch_byte; + + if ((ahc->flags & AHC_PAGESCBS) == 0) { /* In the non-paging case, the SCBID == hardware SCB index */ - mov SCBPTR, ARG_1; + mov SCBPTR, RETURN_2; } - or SEQ_FLAGS2, SCB_DMA; -END_CRITICAL dma_queued_scb: - /* - * DMA the SCB from host ram into the current SCB location. - */ +/* + * DMA the SCB from host ram into the current SCB location. + */ mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET; - mov ARG_1 call dma_scb; - /* - * Check one last time to see if this SCB was canceled - * before we completed the DMA operation. If it was, - * the QINFIFO next pointer will not match our saved - * value. - */ - mov A, ARG_1; -BEGIN_CRITICAL - cmp NEXT_QUEUED_SCB, A jne abort_qinscb; - if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { - cmp SCB_TAG, A je . + 2; - mvi SCB_MISMATCH call set_seqint; + mov RETURN_2 call dma_scb; + +/* + * Preset the residual fields in case we never go through a data phase. + * This isn't done by the host so we can avoid a DMA to clear these + * fields for the normal case of I/O that completes without underrun + * or overrun conditions. + */ + if ((ahc->features & AHC_CMD_CHAN) != 0) { + bmov SCB_RESID_DCNT, SCB_DATACNT, 3; + } else { + mov SCB_RESID_DCNT[0],SCB_DATACNT[0]; + mov SCB_RESID_DCNT[1],SCB_DATACNT[1]; + mov SCB_RESID_DCNT[2],SCB_DATACNT[2]; } - mov NEXT_QUEUED_SCB, SCB_NEXT; + mov SCB_RESID_SGCNT, SCB_SGCOUNT; + +start_scb: + /* + * Place us on the waiting list in case our selection + * doesn't win during bus arbitration. + */ mov SCB_NEXT,WAITING_SCBH; mov WAITING_SCBH, SCBPTR; - if ((ahc->features & AHC_QUEUE_REGS) != 0) { - mov NONE, SNSCB_QOFF; - } else { - inc QINPOS; - } - and SEQ_FLAGS2, ~SCB_DMA; -END_CRITICAL start_waiting: /* - * Start the first entry on the waiting SCB list. + * Pull the first entry off of the waiting SCB list. */ mov SCBPTR, WAITING_SCBH; call start_selection; + jmp poll_for_work; + +start_selection: + if ((ahc->features & AHC_TWIN) != 0) { + and SINDEX,~SELBUSB,SBLKCTL;/* Clear channel select bit */ + and A,SELBUSB,SCB_TCL; /* Get new channel bit */ + or SINDEX,A; + mov SBLKCTL,SINDEX; /* select channel */ + } +initialize_scsiid: + mov SINDEX, SCSISEQ_TEMPLATE; + if ((ahc->flags & AHC_TARGETMODE) != 0) { + test SCB_CONTROL, TARGET_SCB jz . + 4; + if ((ahc->features & AHC_ULTRA2) != 0) { + mov SCSIID_ULTRA2, SCB_CMDPTR[2]; + } else { + mov SCSIID, SCB_CMDPTR[2]; + } + or SINDEX, TEMODE; + jmp initialize_scsiid_fini; + } + if ((ahc->features & AHC_ULTRA2) != 0) { + and A, TID, SCB_TCL; /* Get target ID */ + and SCSIID_ULTRA2, OID; /* Clear old target */ + or SCSIID_ULTRA2, A; + } else { + and A, TID, SCB_TCL; /* Get target ID */ + and SCSIID, OID; /* Clear old target */ + or SCSIID, A; + } +initialize_scsiid_fini: + mov SCSISEQ, SINDEX ret; -poll_for_selection: - /* - * Twin channel devices cannot handle things like SELTO - * interrupts on the "background" channel. So, while - * selecting, keep polling the current channel until - * either a selection or reselection occurs. - */ - test SSTAT0, SELDO|SELDI jz poll_for_selection; +/* + * Initialize transfer settings and clear the SCSI channel. + * SINDEX should contain any additional bit's the client wants + * set in SXFRCTL0. We also assume that the current SCB is + * a valid SCB for the target we wish to talk to. + */ +initialize_channel: + or SXFRCTL0, CLRSTCNT|CLRCHN, SINDEX; +set_transfer_settings: + if ((ahc->features & AHC_ULTRA) != 0) { + test SCB_CONTROL, ULTRAENB jz . + 2; + or SXFRCTL0, FAST20; + } +/* + * Initialize SCSIRATE with the appropriate value for this target. + */ + if ((ahc->features & AHC_ULTRA2) != 0) { + bmov SCSIRATE, SCB_SCSIRATE, 2 ret; + } else { + mov SCSIRATE, SCB_SCSIRATE ret; + } selection: - /* - * We aren't expecting a bus free, so interrupt - * the kernel driver if it happens. - */ - mvi CLRSINT1,CLRBUSFREE; - if ((ahc->features & AHC_DT) == 0) { - or SIMODE1, ENBUSFREE; - } - - /* - * Guard against a bus free after (re)selection - * but prior to enabling the busfree interrupt. SELDI - * and SELDO will be cleared in that case. - */ - test SSTAT0, SELDI|SELDO jz bus_free_sel; test SSTAT0,SELDO jnz select_out; + mvi CLRSINT0, CLRSELDI; select_in: - if ((ahc->flags & AHC_TARGETROLE) != 0) { - if ((ahc->flags & AHC_INITIATORROLE) != 0) { + if ((ahc->flags & AHC_TARGETMODE) != 0) { + if ((ahc->flags & AHC_INITIATORMODE) != 0) { test SSTAT0, TARGET jz initiator_reselect; } - mvi CLRSINT0, CLRSELDI; /* * We've just been selected. Assert BSY and @@ -178,6 +228,7 @@ select_in: * from the target. */ mvi SCSISIGO, P_MESGOUT|BSYO; + mvi CLRSINT1, CLRBUSFREE; /* * Setup the DMA for sending the identify and @@ -188,40 +239,47 @@ select_in: mov A, TQINPOS; if ((ahc->features & AHC_CMD_CHAN) != 0) { mvi DINDEX, CCHADDR; - mvi SHARED_DATA_ADDR call set_32byte_addr; + mvi TMODE_CMDADDR call set_32byte_addr; mvi CCSCBCTL, CCSCBRESET; } else { mvi DINDEX, HADDR; - mvi SHARED_DATA_ADDR call set_32byte_addr; + mvi TMODE_CMDADDR call set_32byte_addr; mvi DFCNTRL, FIFORESET; } /* Initiator that selected us */ - and SAVED_SCSIID, SELID_MASK, SELID; + and SAVED_TCL, SELID_MASK, SELID; + if ((ahc->features & AHC_CMD_CHAN) != 0) { + mov CCSCBRAM, SAVED_TCL; + } else { + mov DFDAT, SAVED_TCL; + } + /* The Target ID we were selected at */ - if ((ahc->features & AHC_MULTI_TID) != 0) { - and A, OID, TARGIDIN; - } else if ((ahc->features & AHC_ULTRA2) != 0) { - and A, OID, SCSIID_ULTRA2; - } else { - and A, OID, SCSIID; - } - or SAVED_SCSIID, A; - if ((ahc->features & AHC_TWIN) != 0) { - test SBLKCTL, SELBUSB jz . + 2; - or SAVED_SCSIID, TWIN_CHNLB; - } - if ((ahc->features & AHC_CMD_CHAN) != 0) { - mov CCSCBRAM, SAVED_SCSIID; + if ((ahc->features & AHC_CMD_CHAN) != 0) { + if ((ahc->features & AHC_MULTI_TID) != 0) { + and CCSCBRAM, OID, TARGIDIN; + } else if ((ahc->features & AHC_ULTRA2) != 0) { + and CCSCBRAM, OID, SCSIID_ULTRA2; + } else { + and CCSCBRAM, OID, SCSIID; + } } else { - mov DFDAT, SAVED_SCSIID; - } + if ((ahc->features & AHC_MULTI_TID) != 0) { + and DFDAT, OID, TARGIDIN; + } else if ((ahc->features & AHC_ULTRA2) != 0) { + and DFDAT, OID, SCSIID_ULTRA2; + } else { + and DFDAT, OID, SCSIID; + } + } + + /* No tag yet */ + mvi INITIATOR_TAG, SCB_LIST_NULL; /* * If ATN isn't asserted, the target isn't interested * in talking to us. Go directly to bus free. - * XXX SCSI-1 may require us to assume lun 0 if - * ATN is false. */ test SCSISIGI, ATNI jz target_busfree; @@ -236,6 +294,7 @@ select_in: * Our first message must be one of IDENTIFY, ABORT, or * BUS_DEVICE_RESET. */ + /* XXX May need to be more lax here for older initiators... */ test DINDEX, MSG_IDENTIFYFLAG jz host_target_message_loop; /* Store for host */ if ((ahc->features & AHC_CMD_CHAN) != 0) { @@ -285,10 +344,6 @@ select_in: mov DFDAT, DINDEX; } mov INITIATOR_TAG, DINDEX; - or SEQ_FLAGS, TARGET_CMD_IS_TAGGED; - test SCSISIGI, ATNI jz . + 2; - /* Initiator still wants to give us messages */ - call target_inb; jmp ident_messages_done; /* @@ -296,7 +351,8 @@ select_in: * run it's own target mode message state engine. */ host_target_message_loop: - mvi HOST_MSG_LOOP call set_seqint; + mvi INTSTAT, HOST_MSG_LOOP; + nop; cmp RETURN_1, EXIT_MSG_LOOP je target_ITloop; test SSTAT0, SPIORDY jz .; jmp host_target_message_loop; @@ -306,11 +362,11 @@ ident_messages_done: if ((ahc->features & AHC_HS_MAILBOX) != 0) { and A, HOST_TQINPOS, HS_MAILBOX; } else { - mov A, KERNEL_TQINPOS; + mov A, KERNEL_TQINPOS; } cmp TQINPOS, A jne tqinfifo_has_space; mvi P_STATUS|BSYO call change_phase; - test SEQ_FLAGS, TARGET_CMD_IS_TAGGED jz . + 3; + cmp INITIATOR_TAG, SCB_LIST_NULL je . + 3; mvi STATUS_QUEUE_FULL call target_outb; jmp target_busfree_wait; mvi STATUS_BUSY call target_outb; @@ -323,110 +379,48 @@ tqinfifo_has_space: mvi DFDAT, SCB_LIST_NULL; } or SEQ_FLAGS, TARG_CMD_PENDING|IDENTIFY_SEEN; - test SCSISIGI, ATNI jnz target_mesgout_pending; + test SCSISIGI, ATNI jnz target_mesgout_pending_msg; jmp target_ITloop; - } - -if ((ahc->flags & AHC_INITIATORROLE) != 0) { -/* - * Reselection has been initiated by a target. Make a note that we've been - * reselected, but haven't seen an IDENTIFY message from the target yet. - */ -initiator_reselect: - /* XXX test for and handle ONE BIT condition */ - or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN; - and SAVED_SCSIID, SELID_MASK, SELID; - if ((ahc->features & AHC_ULTRA2) != 0) { - and A, OID, SCSIID_ULTRA2; - } else { - and A, OID, SCSIID; - } - or SAVED_SCSIID, A; - if ((ahc->features & AHC_TWIN) != 0) { - test SBLKCTL, SELBUSB jz . + 2; - or SAVED_SCSIID, TWIN_CHNLB; - } - mvi CLRSINT0, CLRSELDI; - jmp ITloop; -} - -abort_qinscb: - call add_scb_to_free_list; - jmp poll_for_work_loop; - -start_selection: - /* - * If bus reset interrupts have been disabled (from a previous - * reset), re-enable them now. Resets are only of interest - * when we have outstanding transactions, so we can safely - * defer re-enabling the interrupt until, as an initiator, - * we start sending out transactions again. - */ - test SIMODE1, ENSCSIRST jnz . + 3; - mvi CLRSINT1, CLRSCSIRSTI; - or SIMODE1, ENSCSIRST; - if ((ahc->features & AHC_TWIN) != 0) { - and SINDEX,~SELBUSB,SBLKCTL;/* Clear channel select bit */ - test SCB_SCSIID, TWIN_CHNLB jz . + 2; - or SINDEX, SELBUSB; - mov SBLKCTL,SINDEX; /* select channel */ - } -initialize_scsiid: - if ((ahc->features & AHC_ULTRA2) != 0) { - mov SCSIID_ULTRA2, SCB_SCSIID; - } else if ((ahc->features & AHC_TWIN) != 0) { - and SCSIID, TWIN_TID|OID, SCB_SCSIID; - } else { - mov SCSIID, SCB_SCSIID; - } - if ((ahc->flags & AHC_TARGETROLE) != 0) { - mov SINDEX, SCSISEQ_TEMPLATE; - test SCB_CONTROL, TARGET_SCB jz . + 2; - or SINDEX, TEMODE; - mov SCSISEQ, SINDEX ret; - } else { - mov SCSISEQ, SCSISEQ_TEMPLATE ret; - } - -/* - * Initialize transfer settings and clear the SCSI channel. - * SINDEX should contain any additional bit's the client wants - * set in SXFRCTL0. We also assume that the current SCB is - * a valid SCB for the target we wish to talk to. - */ -initialize_channel: - or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN; -set_transfer_settings: - if ((ahc->features & AHC_ULTRA) != 0) { - test SCB_CONTROL, ULTRAENB jz . + 2; - or SXFRCTL0, FAST20; - } - /* - * Initialize SCSIRATE with the appropriate value for this target. - */ - if ((ahc->features & AHC_ULTRA2) != 0) { - bmov SCSIRATE, SCB_SCSIRATE, 2 ret; - } else { - mov SCSIRATE, SCB_SCSIRATE ret; - } - -if ((ahc->flags & AHC_TARGETROLE) != 0) { + /* * We carefully toggle SPIOEN to allow us to return the * message byte we receive so it can be checked prior to * driving REQ on the bus for the next byte. */ target_inb: - /* - * Drive REQ on the bus by enabling SCSI PIO. - */ - or SXFRCTL0, SPIOEN; - /* Wait for the byte */ - test SSTAT0, SPIORDY jz .; - /* Prevent our read from triggering another REQ */ - and SXFRCTL0, ~SPIOEN; - /* Save latched contents */ - mov DINDEX, SCSIDATL ret; + /* + * Drive REQ on the bus by enabling SCSI PIO. + */ + or SXFRCTL0, SPIOEN; + /* Wait for the byte */ + test SSTAT0, SPIORDY jz .; + /* Prevent our read from triggering another REQ */ + and SXFRCTL0, ~SPIOEN; + /* Save latched contents */ + mov DINDEX, SCSIDATL ret; + } + +if ((ahc->flags & AHC_INITIATORMODE) != 0) { +/* + * Reselection has been initiated by a target. Make a note that we've been + * reselected, but haven't seen an IDENTIFY message from the target yet. + */ +initiator_reselect: + /* XXX test for and handle ONE BIT condition */ + and SAVED_TCL, SELID_MASK, SELID; + if ((ahc->features & AHC_TWIN) != 0) { + test SBLKCTL, SELBUSB jz . + 2; + or SAVED_TCL, SELBUSB; + } + or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN; + mvi CLRSINT1,CLRBUSFREE; + or SIMODE1, ENBUSFREE; /* + * We aren't expecting a + * bus free, so interrupt + * the kernel driver if it + * happens. + */ + jmp ITloop; } /* @@ -438,13 +432,12 @@ target_inb: select_out: /* Turn off the selection hardware */ and SCSISEQ, TEMODE|ENSELI|ENRSELI|ENAUTOATNP, SCSISEQ; +/*and SCSISEQ, ENSELI|ENRSELI|ENAUTOATNP,SCSISEQ_TEMPLATE;*/ mvi CLRSINT0, CLRSELDO; mov SCBPTR, WAITING_SCBH; mov WAITING_SCBH,SCB_NEXT; - mov SAVED_SCSIID, SCB_SCSIID; - mov SAVED_LUN, SCB_LUN; - call initialize_channel; - if ((ahc->flags & AHC_TARGETROLE) != 0) { + mov SAVED_TCL, SCB_TCL; + if ((ahc->flags & AHC_TARGETMODE) != 0) { test SSTAT0, TARGET jz initiator_select; /* @@ -453,11 +446,13 @@ select_out: * sending our identify messages. */ mvi P_MESGIN|BSYO call change_phase; + mvi CLRSINT1,CLRBUSFREE; /* * Start out with a simple identify message. */ - or SCB_LUN, MSG_IDENTIFYFLAG call target_outb; + and A, LID, SCB_TCL; + or A, MSG_IDENTIFYFLAG call target_outb; /* * If we are the result of a tagged command, send @@ -465,17 +460,16 @@ select_out: */ test SCB_CONTROL, TAG_ENB jz . + 3; mvi MSG_SIMPLE_Q_TAG call target_outb; - mov SCB_TARGET_INFO[SCB_INITIATOR_TAG] call target_outb; + mov SCB_INITIATOR_TAG call target_outb; + mov INITIATOR_TAG, SCB_INITIATOR_TAG; target_synccmd: /* * Now determine what phases the host wants us * to go through. */ - mov SEQ_FLAGS, SCB_TARGET_INFO[SCB_TARGET_PHASES]; + mov SEQ_FLAGS, SCB_TARGET_PHASES; - test SCB_CONTROL, MK_MESSAGE jz target_ITloop; - mvi P_MESGIN|BSYO call change_phase; - jmp host_target_message_loop; + target_ITloop: /* * Start honoring ATN signals now that @@ -491,22 +485,21 @@ target_ITloop: * on the state of NO_DISCONNECT. */ test SEQ_FLAGS, NO_DISCONNECT jz target_disconnect; - mov RETURN_1, ALLZEROS; - call complete_target_cmd; - cmp RETURN_1, CONT_MSG_LOOP jne .; if ((ahc->flags & AHC_PAGESCBS) != 0) { mov ALLZEROS call get_free_or_disc_scb; } + mov RETURN_1, ALLZEROS; + call complete_target_cmd; + cmp RETURN_1, CONT_MSG_LOOP jne .; mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET; mov SCB_TAG call dma_scb; jmp target_synccmd; target_mesgout: mvi SCSISIGO, P_MESGOUT|BSYO; -target_mesgout_continue: call target_inb; -target_mesgout_pending: /* Local Processing goes here... */ +target_mesgout_pending_msg: jmp host_target_message_loop; target_disconnect: @@ -516,13 +509,9 @@ target_disconnect: mvi MSG_DISCONNECT call target_outb; target_busfree_wait: - /* Wait for preceding I/O session to complete. */ + /* Wait for preceeding I/O session to complete. */ test SCSISIGI, ACKI jnz .; target_busfree: - and SIMODE1, ~ENBUSFREE; - if ((ahc->features & AHC_ULTRA2) != 0) { - clr SCSIBUSL; - } clr SCSISIGO; mvi LASTPHASE, P_BUSFREE; call complete_target_cmd; @@ -548,12 +537,12 @@ target_cmdphase: * the first byte. */ shr A, CMD_GROUP_CODE_SHIFT; - add SINDEX, CMDSIZE_TABLE, A; + add SINDEX, TARG_SCSIRATE, A; mov A, SINDIR; test A, 0xFF jz command_phase_done; - or SXFRCTL0, SPIOEN; command_loop: + or SXFRCTL0, SPIOEN; test SSTAT0, SPIORDY jz .; cmp A, 1 jne . + 2; and SXFRCTL0, ~SPIOEN; /* Last Byte */ @@ -571,21 +560,22 @@ command_phase_done: target_dphase: /* - * Data phases on the bus are from the - * perspective of the initiator. The dma - * code looks at LASTPHASE to determine the - * data direction of the DMA. Toggle it for - * target transfers. + * Data direction flags are from the + * perspective of the initiator. */ - xor LASTPHASE, IOI, SCB_TARGET_INFO[SCB_TARGET_DATA_DIR]; - or SCB_TARGET_INFO[SCB_TARGET_DATA_DIR], BSYO - call change_phase; + test SCB_TARGET_PHASES[1], TARGET_DATA_IN jz . + 4; + mvi LASTPHASE, P_DATAOUT; + mvi P_DATAIN|BSYO call change_phase; + jmp . + 3; + mvi LASTPHASE, P_DATAIN; + mvi P_DATAOUT|BSYO call change_phase; + mov ALLZEROS call initialize_channel; jmp p_data; target_sphase: mvi P_STATUS|BSYO call change_phase; mvi LASTPHASE, P_STATUS; - mov SCB_TARGET_INFO[SCB_TARGET_STATUS] call target_outb; + mov SCB_TARGET_STATUS call target_outb; /* XXX Watch for ATN or parity errors??? */ mvi SCSISIGO, P_MESGIN|BSYO; /* MSG_CMDCMPLT is 0, but we can't do an immediate of 0 */ @@ -608,7 +598,9 @@ complete_target_cmd: or DFCNTRL, FIFORESET; mvi DFWADDR, 3; /* Third 64bit word or byte 24 */ mov DFDAT, ALLONES; - mvi 28 call set_hcnt; + mvi HCNT[0], 28; + clr HCNT[1]; + clr HCNT[2]; or DFCNTRL, HDMAEN|FIFOFLUSH; call dma_finish; } @@ -616,8 +608,17 @@ complete_target_cmd: mvi INTSTAT,CMDCMPLT ret; } -if ((ahc->flags & AHC_INITIATORROLE) != 0) { +if ((ahc->flags & AHC_INITIATORMODE) != 0) { initiator_select: + mvi SPIOEN call initialize_channel; + + /* + * We aren't expecting a bus free, so interrupt + * the kernel driver if it happens. + */ + mvi CLRSINT1,CLRBUSFREE; + or SIMODE1, ENBUSFREE; + /* * As soon as we get a successful selection, the target * should go into the message out phase since we have ATN @@ -631,7 +632,6 @@ initiator_select: * target to assert REQ before checking MSG, C/D and I/O for * the bus phase. */ -mesgin_phasemis: ITloop: call phase_lock; @@ -643,19 +643,16 @@ ITloop: cmp A,P_STATUS je p_status; cmp A,P_MESGIN je p_mesgin; - mvi BAD_PHASE call set_seqint; + mvi INTSTAT,BAD_PHASE; jmp ITloop; /* Try reading the bus again. */ await_busfree: and SIMODE1, ~ENBUSFREE; mov NONE, SCSIDATL; /* Ack the last byte */ - if ((ahc->features & AHC_ULTRA2) != 0) { - clr SCSIBUSL; /* Prevent bit leakage durint SELTO */ - } and SXFRCTL0, ~SPIOEN; test SSTAT1,REQINIT|BUSFREE jz .; test SSTAT1, BUSFREE jnz poll_for_work; - mvi MISSED_BUSFREE call set_seqint; + mvi INTSTAT, BAD_PHASE; } clear_target_state: @@ -665,7 +662,6 @@ clear_target_state: * clear DFCNTRL too. */ clr DFCNTRL; - or SXFRCTL0, CLRSTCNT|CLRCHN; /* * We don't know the target we will connect to, @@ -676,129 +672,35 @@ clear_target_state: bmov SCSIRATE, ALLZEROS, 2; } else { clr SCSIRATE; - if ((ahc->features & AHC_ULTRA) != 0) { - and SXFRCTL0, ~(FAST20); - } + and SXFRCTL0, ~(FAST20); } mvi LASTPHASE, P_BUSFREE; /* clear target specific flags */ clr SEQ_FLAGS ret; -sg_advance: - clr A; /* add sizeof(struct scatter) */ - add SCB_RESIDUAL_SGPTR[0],SG_SIZEOF; - adc SCB_RESIDUAL_SGPTR[1],A; - adc SCB_RESIDUAL_SGPTR[2],A; - adc SCB_RESIDUAL_SGPTR[3],A ret; - -if ((ahc->features & AHC_CMD_CHAN) != 0) { -disable_ccsgen: - test CCSGCTL, CCSGEN jz return; - test CCSGCTL, CCSGDONE jz .; -disable_ccsgen_fetch_done: - clr CCSGCTL; - test CCSGCTL, CCSGEN jnz .; - ret; -idle_loop: - /* - * Do we need any more segments for this transfer? - */ - test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jnz return; - - /* Did we just finish fetching segs? */ - cmp CCSGCTL, CCSGEN|CCSGDONE je idle_sgfetch_complete; - - /* Are we actively fetching segments? */ - test CCSGCTL, CCSGEN jnz return; - - /* - * Do we have any prefetch left??? - */ - cmp CCSGADDR, SG_PREFETCH_CNT jne idle_sg_avail; - - /* - * Need to fetch segments, but we can only do that - * if the command channel is completely idle. Make - * sure we don't have an SCB prefetch going on. - */ - test CCSCBCTL, CCSCBEN jnz return; - - /* - * We fetch a "cacheline aligned" and sized amount of data - * so we don't end up referencing a non-existant page. - * Cacheline aligned is in quotes because the kernel will - * set the prefetch amount to a reasonable level if the - * cacheline size is unknown. - */ - mvi CCHCNT, SG_PREFETCH_CNT; - and CCHADDR[0], SG_PREFETCH_ALIGN_MASK, SCB_RESIDUAL_SGPTR; - bmov CCHADDR[1], SCB_RESIDUAL_SGPTR[1], 3; - mvi CCSGCTL, CCSGEN|CCSGRESET ret; -idle_sgfetch_complete: - call disable_ccsgen_fetch_done; - and CCSGADDR, SG_PREFETCH_ADDR_MASK, SCB_RESIDUAL_SGPTR; -idle_sg_avail: - if ((ahc->features & AHC_ULTRA2) != 0) { - /* Does the hardware have space for another SG entry? */ - test DFSTATUS, PRELOAD_AVAIL jz return; - bmov HADDR, CCSGRAM, 7; - test HCNT[0], 0x1 jz . + 2; - xor DATA_COUNT_ODD, 0x1; - bmov SCB_RESIDUAL_DATACNT[3], CCSGRAM, 1; - if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { - mov SCB_RESIDUAL_DATACNT[3] call set_hhaddr; - } - call sg_advance; - mov SINDEX, SCB_RESIDUAL_SGPTR[0]; - test DATA_COUNT_ODD, 0x1 jz . + 2; - or SINDEX, ODD_SEG; - test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2; - or SINDEX, LAST_SEG; - mov SG_CACHE_PRE, SINDEX; - /* Load the segment */ - or DFCNTRL, PRELOADEN; - } - ret; -} - -if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) { /* - * Calculate the trailing portion of this S/G segment that cannot - * be transferred using memory write and invalidate PCI transactions. - * XXX Can we optimize this for PCI writes only??? + * If we re-enter the data phase after going through another phase, the + * STCNT may have been cleared, so restore it from the residual field. */ -calc_mwi_residual: - /* - * If the ending address is on a cacheline boundary, - * there is no need for an extra segment. - */ - mov A, HCNT[0]; - add A, A, HADDR[0]; - and A, CACHESIZE_MASK; - test A, 0xFF jz return; - - /* - * If the transfer is less than a cachline, - * there is no need for an extra segment. - */ - test HCNT[1], 0xFF jnz calc_mwi_residual_final; - test HCNT[2], 0xFF jnz calc_mwi_residual_final; - add NONE, INVERTED_CACHESIZE_MASK, HCNT[0]; - jnc return; - -calc_mwi_residual_final: - mov MWI_RESIDUAL, A; - not A; - inc A; - add HCNT[0], A; - adc HCNT[1], -1; - adc HCNT[2], -1 ret; -} +data_phase_reinit: + if ((ahc->features & AHC_ULTRA2) != 0) { + /* + * The preload circuitry requires us to + * reload the address too, so pull it from + * the shaddow address. + */ + bmov HADDR, SHADDR, 4; + bmov HCNT, SCB_RESID_DCNT, 3; + } else if ((ahc->features & AHC_CMD_CHAN) != 0) { + bmov STCNT, SCB_RESID_DCNT, 3; + } else { + mvi DINDEX, STCNT; + mvi SCB_RESID_DCNT call bcopy_3; + } + and DATA_COUNT_ODD, 0x1, SCB_RESID_DCNT[0]; + jmp data_phase_loop; p_data: - test SEQ_FLAGS,IDENTIFY_SEEN jnz p_data_okay; - mvi NO_IDENT jmp set_seqint; -p_data_okay: if ((ahc->features & AHC_ULTRA2) != 0) { mvi DMAPARAMS, PRELOADEN|SCSIEN|HDMAEN; } else { @@ -806,515 +708,213 @@ p_data_okay: } test LASTPHASE, IOI jnz . + 2; or DMAPARAMS, DIRECTION; + call assert; /* + * Ensure entering a data + * phase is okay - seen identify, etc. + */ if ((ahc->features & AHC_CMD_CHAN) != 0) { - /* We don't have any valid S/G elements */ - mvi CCSGADDR, SG_PREFETCH_CNT; + mvi CCSGADDR, CCSGADDR_MAX; } - test SEQ_FLAGS, DPHASE jz data_phase_initialize; - - /* - * If we re-enter the data phase after going through another - * phase, our transfer location has almost certainly been - * corrupted by the interveining, non-data, transfers. Ask - * the host driver to fix us up based on the transfer residual. - */ - mvi PDATA_REINIT call set_seqint; - jmp data_phase_loop; - -data_phase_initialize: - /* We have seen a data phase for the first time */ + test SEQ_FLAGS, DPHASE jnz data_phase_reinit; + + /* We have seen a data phase */ or SEQ_FLAGS, DPHASE; /* * Initialize the DMA address and counter from the SCB. - * Also set SCB_RESIDUAL_SGPTR, including the LAST_SEG - * flag in the highest byte of the data count. We cannot - * modify the saved values in the SCB until we see a save - * data pointers message. + * Also set SG_COUNT and SG_NEXT in memory since we cannot + * modify the values in the SCB itself until we see a + * save data pointers message. */ - if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { - /* The lowest address byte must be loaded last. */ - mov SCB_DATACNT[3] call set_hhaddr; - } if ((ahc->features & AHC_CMD_CHAN) != 0) { bmov HADDR, SCB_DATAPTR, 7; - bmov SCB_RESIDUAL_DATACNT[3], SCB_DATACNT[3], 5; } else { mvi DINDEX, HADDR; mvi SCB_DATAPTR call bcopy_7; - mvi DINDEX, SCB_RESIDUAL_DATACNT + 3; - mvi SCB_DATACNT + 3 call bcopy_5; } - if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) { - call calc_mwi_residual; - } - and SCB_RESIDUAL_SGPTR[0], ~SG_FULL_RESID; - and DATA_COUNT_ODD, 0x1, HCNT[0]; + and DATA_COUNT_ODD, 0x1, SCB_DATACNT[0]; if ((ahc->features & AHC_ULTRA2) == 0) { if ((ahc->features & AHC_CMD_CHAN) != 0) { bmov STCNT, HCNT, 3; } else { call set_stcnt_from_hcnt; - } + } + } + + if ((ahc->features & AHC_CMD_CHAN) != 0) { + bmov SG_COUNT, SCB_SGCOUNT, 5; + } else { + mvi DINDEX, SG_COUNT; + mvi SCB_SGCOUNT call bcopy_5; } data_phase_loop: - /* Guard against overruns */ - test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz data_phase_inbounds; - - /* - * Turn on `Bit Bucket' mode, wait until the target takes - * us to another phase, and then notify the host. - */ - and DMAPARAMS, DIRECTION; - mov DFCNTRL, DMAPARAMS; +/* Guard against overruns */ + test SG_COUNT, 0xff jnz data_phase_inbounds; +/* + * Turn on 'Bit Bucket' mode, set the transfer count to + * 16meg and let the target run until it changes phase. + * When the transfer completes, notify the host that we + * had an overrun. + */ or SXFRCTL1,BITBUCKET; - if ((ahc->features & AHC_DT) == 0) { - test SSTAT1,PHASEMIS jz .; + and DMAPARAMS, ~(HDMAEN|SDMAEN); + if ((ahc->features & AHC_ULTRA2) != 0) { + bmov HCNT, ALLONES, 3; + } else if ((ahc->features & AHC_CMD_CHAN) != 0) { + bmov STCNT, ALLONES, 3; } else { - test SCSIPHASE, DATA_PHASE_MASK jnz .; + mvi STCNT[0], 0xFF; + mvi STCNT[1], 0xFF; + mvi STCNT[2], 0xFF; } - and SXFRCTL1, ~BITBUCKET; - mvi DATA_OVERRUN call set_seqint; - jmp ITloop; - data_phase_inbounds: +/* If we are the last SG block, tell the hardware. */ + cmp SG_COUNT,0x01 jne data_phase_wideodd; if ((ahc->features & AHC_ULTRA2) != 0) { - mov SINDEX, SCB_RESIDUAL_SGPTR[0]; - test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2; - or SINDEX, LAST_SEG; - test DATA_COUNT_ODD, 0x1 jz . + 2; - or SINDEX, ODD_SEG; - mov SG_CACHE_PRE, SINDEX; - mov DFCNTRL, DMAPARAMS; -ultra2_dma_loop: - call idle_loop; - /* - * The transfer is complete if either the last segment - * completes or the target changes phase. - */ - test SG_CACHE_SHADOW, LAST_SEG_DONE jnz ultra2_dmafinish; - if ((ahc->features & AHC_DT) == 0) { - if ((ahc->flags & AHC_TARGETROLE) != 0) { - /* - * As a target, we control the phases, - * so ignore PHASEMIS. - */ - test SSTAT0, TARGET jnz ultra2_dma_loop; - } - if ((ahc->flags & AHC_INITIATORROLE) != 0) { - test SSTAT1,PHASEMIS jz ultra2_dma_loop; - } - } else { - test DFCNTRL, SCSIEN jnz ultra2_dma_loop; - } - -ultra2_dmafinish: - /* - * The transfer has terminated either due to a phase - * change, and/or the completion of the last segment. - * We have two goals here. Do as much other work - * as possible while the data fifo drains on a read - * and respond as quickly as possible to the standard - * messages (save data pointers/disconnect and command - * complete) that usually follow a data phase. - */ - if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) { - /* - * On chips with broken auto-flush, start - * the flushing process now. We'll poke - * the chip from time to time to keep the - * flush process going as we complete the - * data phase. - */ - or DFCNTRL, FIFOFLUSH; - } - /* - * We assume that, even though data may still be - * transferring to the host, that the SCSI side of - * the DMA engine is now in a static state. This - * allows us to update our notion of where we are - * in this transfer. - * - * If, by chance, we stopped before being able - * to fetch additional segments for this transfer, - * yet the last S/G was completely exhausted, - * call our idle loop until it is able to load - * another segment. This will allow us to immediately - * pickup on the next segment on the next data phase. - * - * If we happened to stop on the last segment, then - * our residual information is still correct from - * the idle loop and there is no need to perform - * any fixups. - */ -ultra2_ensure_sg: - test SG_CACHE_SHADOW, LAST_SEG jz ultra2_shvalid; - /* Record if we've consumed all S/G entries */ - test SSTAT2, SHVALID jnz residuals_correct; - or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL; - jmp residuals_correct; - -ultra2_shvalid: - test SSTAT2, SHVALID jnz sgptr_fixup; - call idle_loop; - jmp ultra2_ensure_sg; - -sgptr_fixup: - /* - * Fixup the residual next S/G pointer. The S/G preload - * feature of the chip allows us to load two elements - * in addition to the currently active element. We - * store the bottom byte of the next S/G pointer in - * the SG_CACEPTR register so we can restore the - * correct value when the DMA completes. If the next - * sg ptr value has advanced to the point where higher - * bytes in the address have been affected, fix them - * too. - */ - test SG_CACHE_SHADOW, 0x80 jz sgptr_fixup_done; - test SCB_RESIDUAL_SGPTR[0], 0x80 jnz sgptr_fixup_done; - add SCB_RESIDUAL_SGPTR[1], -1; - adc SCB_RESIDUAL_SGPTR[2], -1; - adc SCB_RESIDUAL_SGPTR[3], -1; -sgptr_fixup_done: - and SCB_RESIDUAL_SGPTR[0], SG_ADDR_MASK, SG_CACHE_SHADOW; - clr DATA_COUNT_ODD; - test SG_CACHE_SHADOW, ODD_SEG jz . + 2; - or DATA_COUNT_ODD, 0x1; - clr SCB_RESIDUAL_DATACNT[3]; /* We are not the last seg */ -residuals_correct: - /* - * Go ahead and shut down the DMA engine now. - * In the future, we'll want to handle end of - * transfer messages prior to doing this, but this - * requires similar restructuring for pre-ULTRA2 - * controllers. - */ - test DMAPARAMS, DIRECTION jnz ultra2_fifoempty; -ultra2_fifoflush: - if ((ahc->features & AHC_DT) == 0) { - if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) { - /* - * On Rev A of the aic7890, the autoflush - * feature doesn't function correctly. - * Perform an explicit manual flush. During - * a manual flush, the FIFOEMP bit becomes - * true every time the PCI FIFO empties - * regardless of the state of the SCSI FIFO. - * It can take up to 4 clock cycles for the - * SCSI FIFO to get data into the PCI FIFO - * and for FIFOEMP to de-assert. Here we - * guard against this condition by making - * sure the FIFOEMP bit stays on for 5 full - * clock cycles. - */ - or DFCNTRL, FIFOFLUSH; - test DFSTATUS, FIFOEMP jz ultra2_fifoflush; - test DFSTATUS, FIFOEMP jz ultra2_fifoflush; - test DFSTATUS, FIFOEMP jz ultra2_fifoflush; - test DFSTATUS, FIFOEMP jz ultra2_fifoflush; - } - test DFSTATUS, FIFOEMP jz ultra2_fifoflush; - } else { - /* - * We enable the auto-ack feature on DT capable - * controllers. This means that the controller may - * have already transferred some overrun bytes into - * the data FIFO and acked them on the bus. The only - * way to detect this situation is to wait for - * LAST_SEG_DONE to come true on a completed transfer - * and then test to see if the data FIFO is non-empty. - */ - test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 4; - test SG_CACHE_SHADOW, LAST_SEG_DONE jz .; - test DFSTATUS, FIFOEMP jnz ultra2_fifoempty; - /* Overrun */ - jmp data_phase_loop; - test DFSTATUS, FIFOEMP jz .; - } -ultra2_fifoempty: - /* Don't clobber an inprogress host data transfer */ - test DFSTATUS, MREQPEND jnz ultra2_fifoempty; -ultra2_dmahalt: - and DFCNTRL, ~(SCSIEN|HDMAEN); - test DFCNTRL, SCSIEN|HDMAEN jnz .; - if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { - /* - * Keep HHADDR cleared for future, 32bit addressed - * only, DMA operations. - * - * Due to bayonette style S/G handling, our residual - * data must be "fixed up" once the transfer is halted. - * Here we fixup the HSHADDR stored in the high byte - * of the residual data cnt. By postponing the fixup, - * we can batch the clearing of HADDR with the fixup. - * If we halted on the last segment, the residual is - * already correct. If we are not on the last - * segment, copy the high address directly from HSHADDR. - * We don't need to worry about maintaining the - * SG_LAST_SEG flag as it will always be false in the - * case where an update is required. - */ - or DSCOMMAND1, HADDLDSEL0; - test SG_CACHE_SHADOW, LAST_SEG jnz . + 2; - mov SCB_RESIDUAL_DATACNT[3], SHADDR; - clr HADDR; - and DSCOMMAND1, ~HADDLDSEL0; - } + or SG_CACHEPTR, LAST_SEG; } else { - /* If we are the last SG block, tell the hardware. */ - if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 - && ahc->pci_cachesize != 0) { - test MWI_RESIDUAL, 0xFF jnz dma_mid_sg; - } - test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz dma_mid_sg; - if ((ahc->flags & AHC_TARGETROLE) != 0) { - test SSTAT0, TARGET jz dma_last_sg; - if ((ahc->flags & AHC_TMODE_WIDEODD_BUG) != 0) { - test DMAPARAMS, DIRECTION jz dma_mid_sg; - } + if ((ahc->flags & AHC_TARGETMODE) != 0) { + test SSTAT0, TARGET jz . + 2; + test DMAPARAMS, DIRECTION jz data_phase_wideodd; } -dma_last_sg: and DMAPARAMS, ~WIDEODD; -dma_mid_sg: - /* Start DMA data transfer. */ + } +data_phase_wideodd: + if ((ahc->features & AHC_ULTRA2) != 0) { + mov SINDEX, ALLONES; mov DFCNTRL, DMAPARAMS; -dma_loop: - if ((ahc->features & AHC_CMD_CHAN) != 0) { - call idle_loop; - } - test SSTAT0,DMADONE jnz dma_dmadone; - test SSTAT1,PHASEMIS jz dma_loop; /* ie. underrun */ -dma_phasemis: - /* - * We will be "done" DMAing when the transfer count goes to - * zero, or the target changes the phase (in light of this, - * it makes sense that the DMA circuitry doesn't ACK when - * PHASEMIS is active). If we are doing a SCSI->Host transfer, - * the data FIFO should be flushed auto-magically on STCNT=0 - * or a phase change, so just wait for FIFO empty status. - */ -dma_checkfifo: - test DFCNTRL,DIRECTION jnz dma_fifoempty; -dma_fifoflush: - test DFSTATUS,FIFOEMP jz dma_fifoflush; -dma_fifoempty: - /* Don't clobber an inprogress host data transfer */ - test DFSTATUS, MREQPEND jnz dma_fifoempty; - - /* - * Now shut off the DMA and make sure that the DMA - * hardware has actually stopped. Touching the DMA - * counters, etc. while a DMA is active will result - * in an ILLSADDR exception. - */ -dma_dmadone: - and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN); -dma_halt: - /* - * Some revisions of the aic78XX have a problem where, if the - * data fifo is full, but the PCI input latch is not empty, - * HDMAEN cannot be cleared. The fix used here is to drain - * the prefetched but unused data from the data fifo until - * there is space for the input latch to drain. - */ - if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) { - mov NONE, DFDAT; - } - test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz dma_halt; - - /* See if we have completed this last segment */ - test STCNT[0], 0xff jnz data_phase_finish; - test STCNT[1], 0xff jnz data_phase_finish; - test STCNT[2], 0xff jnz data_phase_finish; - - /* - * Advance the scatter-gather pointers if needed - */ - if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 - && ahc->pci_cachesize != 0) { - test MWI_RESIDUAL, 0xFF jz no_mwi_resid; - /* - * Reload HADDR from SHADDR and setup the - * count to be the size of our residual. - */ - if ((ahc->features & AHC_CMD_CHAN) != 0) { - bmov HADDR, SHADDR, 4; - mov HCNT, MWI_RESIDUAL; - bmov HCNT[1], ALLZEROS, 2; - } else { - mvi DINDEX, HADDR; - mvi SHADDR call bcopy_4; - mov MWI_RESIDUAL call set_hcnt; - } - clr MWI_RESIDUAL; - jmp sg_load_done; -no_mwi_resid: - } - test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz sg_load; - or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL; - jmp data_phase_finish; + test SSTAT0, SDONE jnz .;/* Wait for preload to complete */ +data_phase_dma_loop: + test SSTAT0, SDONE jnz data_phase_dma_done; + test SSTAT1,PHASEMIS jz data_phase_dma_loop; /* ie. underrun */ + } else { + mov DMAPARAMS call dma; + } + +data_phase_dma_done: +/* Go tell the host about any overruns */ + test SXFRCTL1,BITBUCKET jnz data_phase_overrun; + +/* See if we completed this segment */ + test STCNT[0], 0xff jnz data_phase_finish; + test STCNT[1], 0xff jnz data_phase_finish; + test STCNT[2], 0xff jnz data_phase_finish; + +/* + * Advance the scatter-gather pointers if needed + */ +sg_advance: + dec SG_COUNT; /* one less segment to go */ + + test SG_COUNT, 0xff jz data_phase_finish; /* Are we done? */ +/* + * Load a struct scatter and set up the data address and length. + * If the working value of the SG count is nonzero, then + * we need to load a new set of values. + * + * This, like all DMA's, assumes little-endian host data storage. + */ sg_load: + if ((ahc->features & AHC_CMD_CHAN) != 0) { /* - * Load the next SG element's data address and length - * into the DMA engine. If we don't have hardware - * to perform a prefetch, we'll have to fetch the - * segment from host memory first. + * Do we have any prefetch left??? */ - if ((ahc->features & AHC_CMD_CHAN) != 0) { - /* Wait for the idle loop to complete */ - test CCSGCTL, CCSGEN jz . + 3; - call idle_loop; - test CCSGCTL, CCSGEN jnz . - 1; - bmov HADDR, CCSGRAM, 7; - /* - * Workaround for flaky external SCB RAM - * on certain aic7895 setups. It seems - * unable to handle direct transfers from - * S/G ram to certain SCB locations. - */ - mov SINDEX, CCSGRAM; - mov SCB_RESIDUAL_DATACNT[3], SINDEX; - } else { - if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { - mov ALLZEROS call set_hhaddr; - } - mvi DINDEX, HADDR; - mvi SCB_RESIDUAL_SGPTR call bcopy_4; - - mvi SG_SIZEOF call set_hcnt; - - or DFCNTRL, HDMAEN|DIRECTION|FIFORESET; - - call dma_finish; - - mvi DINDEX, HADDR; - call dfdat_in_7; - mov SCB_RESIDUAL_DATACNT[3], DFDAT; - } - - if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { - mov SCB_RESIDUAL_DATACNT[3] call set_hhaddr; - - /* - * The lowest address byte must be loaded - * last as it triggers the computation of - * some items in the PCI block. The ULTRA2 - * chips do this on PRELOAD. - */ - mov HADDR, HADDR; - } - if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 - && ahc->pci_cachesize != 0) { - call calc_mwi_residual; - } - - /* Point to the new next sg in memory */ - call sg_advance; - -sg_load_done: + cmp CCSGADDR, CCSGADDR_MAX jne prefetched_segs_avail; + + /* + * Fetch MIN(CCSGADDR_MAX, (SG_COUNT * 8)) bytes. + */ + add A, -(CCSGRAM_MAXSEGS + 1), SG_COUNT; + mvi A, CCSGADDR_MAX; + jc . + 2; + shl A, 3, SG_COUNT; + mov CCHCNT, A; + bmov CCHADDR, SG_NEXT, 4; + mvi CCSGCTL, CCSGEN|CCSGRESET; + test CCSGCTL, CCSGDONE jz .; + and CCSGCTL, ~CCSGEN; + test CCSGCTL, CCSGEN jnz .; + mvi CCSGCTL, CCSGRESET; +prefetched_segs_avail: + bmov HADDR, CCSGRAM, 8; + } else { + mvi DINDEX, HADDR; + mvi SG_NEXT call bcopy_4; + + mvi HCNT[0],SG_SIZEOF; + clr HCNT[1]; + clr HCNT[2]; + + or DFCNTRL, HDMAEN|DIRECTION|FIFORESET; + + call dma_finish; + + /* + * Copy data from FIFO into SCB data pointer and data count. + * This assumes that the SG segments are of the form: + * struct ahc_dma_seg { + * u_int32_t addr; four bytes, little-endian order + * u_int32_t len; four bytes, little endian order + * }; + */ + mvi HADDR call dfdat_in_7; + } + + /* Track odd'ness */ + test HCNT[0], 0x1 jz . + 2; + xor DATA_COUNT_ODD, 0x1; + + if ((ahc->features & AHC_ULTRA2) == 0) { + /* Load STCNT as well. It is a mirror of HCNT */ if ((ahc->features & AHC_CMD_CHAN) != 0) { bmov STCNT, HCNT, 3; } else { call set_stcnt_from_hcnt; } - /* Track odd'ness */ - test HCNT[0], 0x1 jz . + 2; - xor DATA_COUNT_ODD, 0x1; - - if ((ahc->flags & AHC_TARGETROLE) != 0) { - test SSTAT0, TARGET jnz data_phase_loop; - } } -data_phase_finish: - /* - * If the target has left us in data phase, loop through - * the dma code again. In the case of ULTRA2 adapters, - * we should only loop if there is a data overrun. For - * all other adapters, we'll loop after each S/G element - * is loaded as well as if there is an overrun. - */ - if ((ahc->flags & AHC_TARGETROLE) != 0) { - test SSTAT0, TARGET jnz data_phase_done; - } - if ((ahc->flags & AHC_INITIATORROLE) != 0) { - test SSTAT1, REQINIT jz .; - if ((ahc->features & AHC_DT) == 0) { - test SSTAT1,PHASEMIS jz data_phase_loop; - } else { - test SCSIPHASE, DATA_PHASE_MASK jnz data_phase_loop; - } - } - -data_phase_done: - /* - * After a DMA finishes, save the SG and STCNT residuals back into - * the SCB. We use STCNT instead of HCNT, since it's a reflection - * of how many bytes were transferred on the SCSI (as opposed to the - * host) bus. - */ - if ((ahc->features & AHC_CMD_CHAN) != 0) { - /* Kill off any pending prefetch */ - call disable_ccsgen; + +/* Advance the SG pointer */ + clr A; /* add sizeof(struct scatter) */ + add SG_NEXT[0],SG_SIZEOF; + adc SG_NEXT[1],A; + + if ((ahc->flags & AHC_TARGETMODE) != 0) { + test SSTAT0, TARGET jnz data_phase_loop; } + test SSTAT1, REQINIT jz .; + test SSTAT1,PHASEMIS jz data_phase_loop; - if ((ahc->features & AHC_ULTRA2) == 0) { - /* - * Clear the high address byte so that all other DMA - * operations, which use 32bit addressing, can assume - * HHADDR is 0. - */ - if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { - mov ALLZEROS call set_hhaddr; - } + /* Ensure the last seg is visable at the shaddow layer */ + if ((ahc->features & AHC_ULTRA2) != 0) { + mov DFCNTRL, DMAPARAMS; + test SSTAT0, SDONE jnz .;/* Wait for preload to complete */ } - /* - * Update our residual information before the information is - * lost by some other type of SCSI I/O (e.g. PIO). If we have - * transferred all data, no update is needed. - * - */ - test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jnz residual_update_done; - if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 - && ahc->pci_cachesize != 0) { - if ((ahc->features & AHC_CMD_CHAN) != 0) { - test MWI_RESIDUAL, 0xFF jz bmov_resid; - } - mov A, MWI_RESIDUAL; - add SCB_RESIDUAL_DATACNT[0], A, STCNT[0]; - clr A; - adc SCB_RESIDUAL_DATACNT[1], A, STCNT[1]; - adc SCB_RESIDUAL_DATACNT[2], A, STCNT[2]; - clr MWI_RESIDUAL; - if ((ahc->features & AHC_CMD_CHAN) != 0) { - jmp . + 2; -bmov_resid: - bmov SCB_RESIDUAL_DATACNT, STCNT, 3; - } - } else if ((ahc->features & AHC_CMD_CHAN) != 0) { - bmov SCB_RESIDUAL_DATACNT, STCNT, 3; +data_phase_finish: + if ((ahc->features & AHC_ULTRA2) != 0) { + call ultra2_dmafinish; + } +/* + * After a DMA finishes, save the SG and STCNT residuals back into the SCB + * We use STCNT instead of HCNT, since it's a reflection of how many bytes + * were transferred on the SCSI (as opposed to the host) bus. + */ + if ((ahc->features & AHC_CMD_CHAN) != 0) { + bmov SCB_RESID_DCNT, STCNT, 3; } else { - mov SCB_RESIDUAL_DATACNT[0], STCNT[0]; - mov SCB_RESIDUAL_DATACNT[1], STCNT[1]; - mov SCB_RESIDUAL_DATACNT[2], STCNT[2]; + mov SCB_RESID_DCNT[0],STCNT[0]; + mov SCB_RESID_DCNT[1],STCNT[1]; + mov SCB_RESID_DCNT[2],STCNT[2]; } -residual_update_done: - /* - * Since we've been through a data phase, the SCB_RESID* fields - * are now initialized. Clear the full residual flag. - */ - and SCB_SGPTR[0], ~SG_FULL_RESID; + mov SCB_RESID_SGCNT, SG_COUNT; if ((ahc->features & AHC_ULTRA2) != 0) { - /* Clear the channel in case we return to data phase later */ - or SXFRCTL0, CLRSTCNT|CLRCHN; or SXFRCTL0, CLRSTCNT|CLRCHN; } - if ((ahc->flags & AHC_TARGETROLE) != 0) { + if ((ahc->flags & AHC_TARGETMODE) != 0) { test SEQ_FLAGS, DPHASE_PENDING jz ITloop; and SEQ_FLAGS, ~DPHASE_PENDING; /* @@ -1324,104 +924,112 @@ residual_update_done: test DFCNTRL, DIRECTION jz target_ITloop; test SSTAT1, REQINIT jnz .; jmp target_ITloop; - } else { - jmp ITloop; + } + jmp ITloop; + +data_phase_overrun: + if ((ahc->features & AHC_ULTRA2) != 0) { + call ultra2_dmafinish; + or SXFRCTL0, CLRSTCNT|CLRCHN; + } +/* + * Turn off BITBUCKET mode and notify the host + */ + and SXFRCTL1, ~BITBUCKET; + mvi INTSTAT,DATA_OVERRUN; + jmp ITloop; + +ultra2_dmafinish: + if ((ahc->features & AHC_ULTRA2) != 0) { + test DFCNTRL, DIRECTION jnz ultra2_dmafifoempty; + and DFCNTRL, ~SCSIEN; + test DFCNTRL, SCSIEN jnz .; +ultra2_dmafifoflush: + or DFCNTRL, FIFOFLUSH; + /* + * The FIFOEMP status bit on the Ultra2 class + * of controllers seems to be a bit flaky. + * It appears that if the FIFO is full and the + * transfer ends with some data in the REQ/ACK + * FIFO, FIFOEMP will fall temporarily + * as the data is transferred to the PCI bus. + * This glitch lasts for fewer than 5 clock cycles, + * so we work around the problem by ensuring the + * status bit stays false through a full glitch + * window. + */ + test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush; + test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush; + test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush; + test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush; + test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush; + +ultra2_dmafifoempty: + /* Don't clobber an inprogress host data transfer */ + test DFSTATUS, MREQPEND jnz ultra2_dmafifoempty; + +ultra2_dmahalt: + and DFCNTRL, ~(SCSIEN|HDMAEN); + test DFCNTRL, HDMAEN jnz .; + ret; } -if ((ahc->flags & AHC_INITIATORROLE) != 0) { +if ((ahc->flags & AHC_INITIATORMODE) != 0) { /* * Command phase. Set up the DMA registers and let 'er rip. */ p_command: - test SEQ_FLAGS,IDENTIFY_SEEN jnz p_command_okay; - mvi NO_IDENT jmp set_seqint; -p_command_okay: - - if ((ahc->features & AHC_ULTRA2) != 0) { - bmov HCNT[0], SCB_CDB_LEN, 1; - bmov HCNT[1], ALLZEROS, 2; - mvi SG_CACHE_PRE, LAST_SEG; - } else if ((ahc->features & AHC_CMD_CHAN) != 0) { - bmov STCNT[0], SCB_CDB_LEN, 1; - bmov STCNT[1], ALLZEROS, 2; - } else { - mov STCNT[0], SCB_CDB_LEN; - clr STCNT[1]; - clr STCNT[2]; - } - add NONE, -13, SCB_CDB_LEN; - mvi SCB_CDB_STORE jnc p_command_embedded; -p_command_from_host: - if ((ahc->features & AHC_ULTRA2) != 0) { - bmov HADDR[0], SCB_CDB_PTR, 4; - mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN|DIRECTION); - } else { - if ((ahc->features & AHC_CMD_CHAN) != 0) { - bmov HADDR[0], SCB_CDB_PTR, 4; - bmov HCNT, STCNT, 3; - } else { - mvi DINDEX, HADDR; - mvi SCB_CDB_PTR call bcopy_4; - mov SCB_CDB_LEN call set_hcnt; - } - mvi DFCNTRL, (SCSIEN|SDMAEN|HDMAEN|DIRECTION|FIFORESET); - } - jmp p_command_loop; -p_command_embedded: - /* - * The data fifo seems to require 4 byte aligned - * transfers from the sequencer. Force this to - * be the case by clearing HADDR[0] even though - * we aren't going to touch host memeory. - */ - clr HADDR[0]; - if ((ahc->features & AHC_ULTRA2) != 0) { - mvi DFCNTRL, (PRELOADEN|SCSIEN|DIRECTION); - bmov DFDAT, SCB_CDB_STORE, 12; - } else if ((ahc->features & AHC_CMD_CHAN) != 0) { - if ((ahc->flags & AHC_SCB_BTT) != 0) { - /* - * On the 7895 the data FIFO will - * get corrupted if you try to dump - * data from external SCB memory into - * the FIFO while it is enabled. So, - * fill the fifo and then enable SCSI - * transfers. - */ - mvi DFCNTRL, (DIRECTION|FIFORESET); + call assert; + + if ((ahc->features & AHC_CMD_CHAN) != 0) { + mov HCNT[0], SCB_CMDLEN; + bmov HCNT[1], ALLZEROS, 2; + if ((ahc->features & AHC_ULTRA2) == 0) { + bmov STCNT, HCNT, 3; + } + add NONE, -17, SCB_CMDLEN; + jc dma_cmd_data; + /* + * The data fifo seems to require 4 byte alligned + * transfers from the sequencer. Force this to + * be the case by clearing HADDR[0] even though + * we aren't going to touch host memeory. + */ + bmov HADDR[0], ALLZEROS, 1; + if ((ahc->features & AHC_ULTRA2) != 0) { + mvi DFCNTRL, (PRELOADEN|SCSIEN|DIRECTION); } else { mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET); } - bmov DFDAT, SCB_CDB_STORE, 12; - if ((ahc->flags & AHC_SCB_BTT) != 0) { - mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFOFLUSH); - } else { - or DFCNTRL, FIFOFLUSH; + bmov DFDAT, SCB_CMDSTORE, 16; + jmp cmd_loop; +dma_cmd_data: + bmov HADDR, SCB_CMDPTR, 4; + } else { + mvi DINDEX, HADDR; + mvi SCB_CMDPTR call bcopy_5; + clr HCNT[1]; + clr HCNT[2]; + } + + if ((ahc->features & AHC_ULTRA2) == 0) { + if ((ahc->features & AHC_CMD_CHAN) == 0) { + call set_stcnt_from_hcnt; } + mvi DFCNTRL, (SCSIEN|SDMAEN|HDMAEN|DIRECTION|FIFORESET); } else { - mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET); - call copy_to_fifo_6; - call copy_to_fifo_6; - or DFCNTRL, FIFOFLUSH; + mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN|DIRECTION); } -p_command_loop: - if ((ahc->features & AHC_DT) == 0) { - test SSTAT0, SDONE jnz . + 2; - test SSTAT1, PHASEMIS jz p_command_loop; - /* - * Wait for our ACK to go-away on it's own - * instead of being killed by SCSIEN getting cleared. - */ - test SCSISIGI, ACKI jnz .; - } else { - test DFCNTRL, SCSIEN jnz p_command_loop; - } +cmd_loop: + test SSTAT0, SDONE jnz . + 2; + test SSTAT1, PHASEMIS jz cmd_loop; + /* + * Wait for our ACK to go-away on it's own + * instead of being killed by SCSIEN getting cleared. + */ + test SCSISIGI, ACKI jnz .; and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN); test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz .; - if ((ahc->features & AHC_ULTRA2) != 0) { - /* Drop any residual from the S/G Preload queue */ - or SXFRCTL0, CLRSTCNT; - } jmp ITloop; /* @@ -1429,10 +1037,9 @@ p_command_loop: * and store it into the SCB. */ p_status: - test SEQ_FLAGS,IDENTIFY_SEEN jnz p_status_okay; - mvi NO_IDENT jmp set_seqint; -p_status_okay: - mov SCB_SCSI_STATUS, SCSIDATL; + call assert; + + mov SCB_TARGET_STATUS, SCSIDATL; jmp ITloop; /* @@ -1460,20 +1067,41 @@ p_status_okay: * reason. */ p_mesgout_retry: - /* Turn on ATN for the retry */ - if ((ahc->features & AHC_DT) == 0) { - or SCSISIGO, ATNO, LASTPHASE; - } else { - mvi SCSISIGO, ATNO; - } + or SCSISIGO,ATNO,LASTPHASE;/* turn on ATN for the retry */ p_mesgout: mov SINDEX, MSG_OUT; cmp SINDEX, MSG_IDENTIFYFLAG jne p_mesgout_from_host; test SCB_CONTROL,MK_MESSAGE jnz host_message_loop; + mov FUNCTION1, SCB_TCL; + mov A, FUNCTION1; + if ((ahc->features & AHC_HS_MAILBOX) != 0) { + /* + * Work around a pausing bug in at least the aic7890. + * If the host needs to update the TARGET_MSG_REQUEST + * bit field, it will set the HS_MAILBOX to 1. In + * response, we pause with a specific interrupt code + * asking for the mask to be updated before we continue. + * Ugh. + */ + test HS_MAILBOX, 0xF0 jz . + 2; + mvi INTSTAT, UPDATE_TMSG_REQ; + nop; + } + mov SINDEX, TARGET_MSG_REQUEST[0]; + if ((ahc->features & AHC_TWIN) != 0) { + /* Second Channel uses high byte bits */ + test SCB_TCL, SELBUSB jz . + 2; + mov SINDEX, TARGET_MSG_REQUEST[1]; + } else if ((ahc->features & AHC_WIDE) != 0) { + test SCB_TCL, 0x80 jz . + 2; /* target > 7 */ + mov SINDEX, TARGET_MSG_REQUEST[1]; + } + test SINDEX, A jnz host_message_loop; p_mesgout_identify: - or SINDEX, MSG_IDENTIFYFLAG|DISCENB, SCB_LUN; - test SCB_CONTROL, DISCENB jnz . + 2; - and SINDEX, ~DISCENB; + and SINDEX,LID,SCB_TCL; /* lun */ + and A,DISCENB,SCB_CONTROL; /* mask off disconnect privledge */ + or SINDEX,A; /* or in disconnect privledge */ + or SINDEX,MSG_IDENTIFYFLAG; /* * Send a tag message if TAG_ENB is set in the SCB control block. * Use SCB_TAG (the position in the kernel's SCB array) as the tag value. @@ -1523,7 +1151,6 @@ p_mesgin: cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs; cmp ALLZEROS,A je mesgin_complete; cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs; - cmp A,MSG_IGN_WIDE_RESIDUE je mesgin_ign_wide_residue; cmp A,MSG_NOOP je mesgin_done; /* @@ -1536,78 +1163,70 @@ p_mesgin: * shouldn't hurt, but why do it twice... */ host_message_loop: - mvi HOST_MSG_LOOP call set_seqint; + mvi INTSTAT, HOST_MSG_LOOP; call phase_lock; cmp RETURN_1, EXIT_MSG_LOOP je ITloop + 1; jmp host_message_loop; -mesgin_ign_wide_residue: -if ((ahc->features & AHC_WIDE) != 0) { - test SCSIRATE, WIDEXFER jz mesgin_reject; - /* Pull the residue byte */ - mvi ARG_1 call inb_next; - cmp ARG_1, 0x01 jne mesgin_reject; - test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 2; - test DATA_COUNT_ODD, 0x1 jz mesgin_done; - mvi IGN_WIDE_RES call set_seqint; - jmp mesgin_done; -} - -mesgin_reject: - mvi MSG_MESSAGE_REJECT call mk_mesg; mesgin_done: mov NONE,SCSIDATL; /*dummy read from latch to ACK*/ jmp ITloop; + mesgin_complete: /* - * We received a "command complete" message. Put the SCB_TAG into the QOUTFIFO, + * We got a "command complete" message, so put the SCB_TAG into the QOUTFIFO, * and trigger a completion interrupt. Before doing so, check to see if there * is a residual or the status byte is something other than STATUS_GOOD (0). * In either of these conditions, we upload the SCB back to the host so it can * process this information. In the case of a non zero status byte, we * additionally interrupt the kernel driver synchronously, allowing it to * decide if sense should be retrieved. If the kernel driver wishes to request - * sense, it will fill the kernel SCB with a request sense command, requeue - * it to the QINFIFO and tell us not to post to the QOUTFIFO by setting - * RETURN_1 to SEND_SENSE. - */ - -/* - * If ATN is raised, we still want to give the target a message. - * Perhaps there was a parity error on this last message byte. - * Either way, the target should take us to message out phase - * and then attempt to complete the command again. We should use a - * critical section here to guard against a timeout triggering - * for this command and setting ATN while we are still processing - * the completion. - test SCSISIGI, ATNI jnz mesgin_done; - */ - -/* - * See if we attempted to deliver a message but the target ingnored us. + * sense, it will fill the kernel SCB with a request sense command and set + * RETURN_1 to SEND_SENSE. If RETURN_1 is set to SEND_SENSE we redownload + * the SCB, and process it as the next command by adding it to the waiting list. + * If the kernel driver does not wish to request sense, it need only clear + * RETURN_1, and the command is allowed to complete normally. We don't bother + * to post to the QOUTFIFO in the error cases since it would require extra + * work in the kernel driver to ensure that the entry was removed before the + * command complete code tried processing it. */ - test SCB_CONTROL, MK_MESSAGE jz . + 2; - mvi MKMSG_FAILED call set_seqint; /* - * Check for residuals + * First check for residuals */ - test SCB_SGPTR, SG_LIST_NULL jnz check_status;/* No xfer */ - test SCB_SGPTR, SG_FULL_RESID jnz upload_scb;/* Never xfered */ - test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jz upload_scb; -check_status: - test SCB_SCSI_STATUS,0xff jz complete; /* Good Status? */ + test SCB_RESID_SGCNT,0xff jnz upload_scb; + test SCB_TARGET_STATUS,0xff jz complete; /* Good Status? */ upload_scb: - or SCB_SGPTR, SG_RESID_VALID; mvi DMAPARAMS, FIFORESET; mov SCB_TAG call dma_scb; - test SCB_SCSI_STATUS, 0xff jz complete; /* Just a residual? */ - mvi BAD_STATUS call set_seqint; /* let driver know */ +check_status: + test SCB_TARGET_STATUS,0xff jz complete; /* Just a residual? */ + mvi INTSTAT,BAD_STATUS; /* let driver know */ + nop; cmp RETURN_1, SEND_SENSE jne complete; - call add_scb_to_free_list; + /* This SCB becomes the next to execute as it will retrieve sense */ + mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET; + mov SCB_TAG call dma_scb; +add_to_waiting_list: + mov SCB_NEXT,WAITING_SCBH; + mov WAITING_SCBH, SCBPTR; + /* + * Prepare our selection hardware before the busfree so we have a + * high probability of winning arbitration. + */ + call start_selection; jmp await_busfree; + complete: + /* If we are untagged, clear our address up in host ram */ + test SCB_CONTROL, TAG_ENB jnz complete_queue; + mov A, SAVED_TCL; + /* fvdl - let ahc_intr clear this to avoid race conditions */ + /* mvi UNTAGGEDSCB_OFFSET call post_byte_setup; */ + /* mvi SCB_LIST_NULL call post_byte; */ + +complete_queue: mov SCB_TAG call complete_post; jmp await_busfree; } @@ -1628,32 +1247,14 @@ complete_post: } mvi INTSTAT,CMDCMPLT ret; -if ((ahc->flags & AHC_INITIATORROLE) != 0) { +if ((ahc->flags & AHC_INITIATORMODE) != 0) { /* * Is it a disconnect message? Set a flag in the SCB to remind us - * and await the bus going free. If this is an untagged transaction - * store the SCB id for it in our untagged target table for lookup on - * a reselction. + * and await the bus going free. */ mesgin_disconnect: - /* - * If ATN is raised, we still want to give the target a message. - * Perhaps there was a parity error on this last message byte - * or we want to abort this command. Either way, the target - * should take us to message out phase and then attempt to - * disconnect again. - * XXX - Wait for more testing. - test SCSISIGI, ATNI jnz mesgin_done; - */ - or SCB_CONTROL,DISCONNECTED; - if ((ahc->flags & AHC_PAGESCBS) != 0) { - call add_scb_to_disc_list; - } - test SCB_CONTROL, TAG_ENB jnz await_busfree; - mov ARG_1, SCB_TAG; - mov SAVED_LUN, SCB_LUN; - mov SCB_SCSIID call set_busy_target; + call add_scb_to_disc_list; jmp await_busfree; /* @@ -1662,52 +1263,29 @@ mesgin_disconnect: * only if we've actually been into a data phase to change them. This * protects against bogus data in scratch ram and the residual counts * since they are only initialized when we go into data_in or data_out. - * Ack the message as soon as possible. For chips without S/G pipelining, - * we can only ack the message after SHADDR has been saved. On these - * chips, SHADDR increments with every bus transaction, even PIO. */ mesgin_sdptrs: - if ((ahc->features & AHC_ULTRA2) != 0) { - mov NONE,SCSIDATL; /*dummy read from latch to ACK*/ - test SEQ_FLAGS, DPHASE jz ITloop; - } else { - test SEQ_FLAGS, DPHASE jz mesgin_done; - } + test SEQ_FLAGS, DPHASE jz mesgin_done; /* - * If we are asked to save our position at the end of the - * transfer, just mark us at the end rather than perform a - * full save. - */ - test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz mesgin_sdptrs_full; - or SCB_SGPTR, SG_LIST_NULL; - if ((ahc->features & AHC_ULTRA2) != 0) { - jmp ITloop; - } else { - jmp mesgin_done; - } - -mesgin_sdptrs_full: - - /* - * The SCB_SGPTR becomes the next one we'll download, - * and the SCB_DATAPTR becomes the current SHADDR. + * The SCB SGPTR becomes the next one we'll download, + * and the SCB DATAPTR becomes the current SHADDR. * Use the residual number since STCNT is corrupted by * any message transfer. */ if ((ahc->features & AHC_CMD_CHAN) != 0) { + bmov SCB_SGCOUNT, SG_COUNT, 5; bmov SCB_DATAPTR, SHADDR, 4; - if ((ahc->features & AHC_ULTRA2) == 0) { - mov NONE,SCSIDATL; /*dummy read from latch to ACK*/ - } - bmov SCB_DATACNT, SCB_RESIDUAL_DATACNT, 8; + bmov SCB_DATACNT, SCB_RESID_DCNT, 3; } else { + mvi DINDEX, SCB_SGCOUNT; + mvi SG_COUNT call bcopy_5; + mvi DINDEX, SCB_DATAPTR; - mvi SHADDR call bcopy_4; - mov NONE,SCSIDATL; /*dummy read from latch to ACK*/ - mvi SCB_RESIDUAL_DATACNT call bcopy_8; + mvi SHADDR call bcopy_4; + mvi SCB_RESID_DCNT call bcopy_3; } - jmp ITloop; + jmp mesgin_done; /* * Restore pointers message? Data pointers are recopied from the @@ -1724,172 +1302,87 @@ mesgin_rdptrs: jmp mesgin_done; /* - * Index into our Busy Target table. SINDEX and DINDEX are modified - * upon return. SCBPTR may be modified by this action. - */ -set_busy_target: - shr DINDEX, 4, SINDEX; - if ((ahc->flags & AHC_SCB_BTT) != 0) { - mov SCBPTR, SAVED_LUN; - add DINDEX, SCB_64_BTT; - } else { - add DINDEX, BUSY_TARGETS; - } - mov DINDIR, ARG_1 ret; - -/* * Identify message? For a reconnecting target, this tells us the lun * that the reconnection is for - find the correct SCB and switch to it, * clearing the "disconnected" bit so we don't "find" it by accident later. */ mesgin_identify: - /* - * Determine whether a target is using tagged or non-tagged - * transactions by first looking at the transaction stored in - * the busy target array. If there is no untagged transaction - * for this target or the transaction is for a different lun, then - * this must be an untagged transaction. - */ - shr SINDEX, 4, SAVED_SCSIID; - and SAVED_LUN, MSG_IDENTIFY_LUNMASK, A; - if ((ahc->flags & AHC_SCB_BTT) != 0) { - add SINDEX, SCB_64_BTT; - mov SCBPTR, SAVED_LUN; - if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { - add NONE, -SCB_64_BTT, SINDEX; - jc . + 2; - mvi INTSTAT, OUT_OF_RANGE; - nop; - add NONE, -(SCB_64_BTT + 16), SINDEX; - jnc . + 2; - mvi INTSTAT, OUT_OF_RANGE; - nop; - } + if ((ahc->features & AHC_WIDE) != 0) { + and A,0x0f; /* lun in lower four bits */ } else { - add SINDEX, BUSY_TARGETS; - if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { - add NONE, -BUSY_TARGETS, SINDEX; - jc . + 2; - mvi INTSTAT, OUT_OF_RANGE; - nop; - add NONE, -(BUSY_TARGETS + 16), SINDEX; - jnc . + 2; - mvi INTSTAT, OUT_OF_RANGE; - nop; - } + and A,0x07; /* lun in lower three bits */ } - mov ARG_1, SINDIR; + or SAVED_TCL,A; /* SAVED_TCL should be complete now */ + + mvi ARG_2, SCB_LIST_NULL; /* SCBID of prev SCB in disc List */ + call get_untagged_SCBID; cmp ARG_1, SCB_LIST_NULL je snoop_tag; if ((ahc->flags & AHC_PAGESCBS) != 0) { - mov ARG_1 call findSCB; - } else { - mov SCBPTR, ARG_1; + test SEQ_FLAGS, SCBPTR_VALID jz use_retrieveSCB; } - if ((ahc->flags & AHC_SCB_BTT) != 0) { - jmp setup_SCB_id_lun_okay; - } else { - /* - * We only allow one untagged command per-target - * at a time. So, if the lun doesn't match, look - * for a tag message. - */ - mov A, SCB_LUN; - cmp SAVED_LUN, A je setup_SCB_id_lun_okay; - if ((ahc->flags & AHC_PAGESCBS) != 0) { - /* - * findSCB removes the SCB from the - * disconnected list, so we must replace - * it there should this SCB be for another - * lun. - */ - call cleanup_scb; - } - } - + /* + * If the SCB was found in the disconnected list (as is + * always the case in non-paging scenarios), SCBPTR is already + * set to the correct SCB. So, simply setup the SCB and get + * on with things. + */ + call rem_scb_from_disc_list; + jmp setup_SCB; /* * Here we "snoop" the bus looking for a SIMPLE QUEUE TAG message. * If we get one, we use the tag returned to find the proper - * SCB. With SCB paging, we must search for non-tagged - * transactions since the SCB may exist in any slot. If we're not - * using SCB paging, we can use the tag as the direct index to the - * SCB. + * SCB. With SCB paging, this requires using search for both tagged + * and non-tagged transactions since the SCB may exist in any slot. + * If we're not using SCB paging, we can use the tag as the direct + * index to the SCB. */ snoop_tag: - if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { - or SEQ_FLAGS, 0x80; - } mov NONE,SCSIDATL; /* ACK Identify MSG */ +snoop_tag_loop: call phase_lock; - if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { - or SEQ_FLAGS, 0x1; - } cmp LASTPHASE, P_MESGIN jne not_found; - if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { - or SEQ_FLAGS, 0x2; - } cmp SCSIBUSL,MSG_SIMPLE_Q_TAG jne not_found; get_tag: - if ((ahc->flags & AHC_PAGESCBS) != 0) { - mvi ARG_1 call inb_next; /* tag value */ - mov ARG_1 call findSCB; - } else { - mvi ARG_1 call inb_next; /* tag value */ - mov SCBPTR, ARG_1; - } + mvi ARG_1 call inb_next; /* tag value */ -/* - * Ensure that the SCB the tag points to is for - * an SCB transaction to the reconnecting target. - */ + /* + * Ensure that the SCB the tag points to is for + * an SCB transaction to the reconnecting target. + */ +use_retrieveSCB: + call retrieveSCB; setup_SCB: - if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { - or SEQ_FLAGS, 0x4; - } - mov A, SCB_SCSIID; - cmp SAVED_SCSIID, A jne not_found_cleanup_scb; - if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { - or SEQ_FLAGS, 0x8; - } -setup_SCB_id_okay: - mov A, SCB_LUN; - cmp SAVED_LUN, A jne not_found_cleanup_scb; -setup_SCB_id_lun_okay: - if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { - or SEQ_FLAGS, 0x10; - } + mov A, SAVED_TCL; + cmp SCB_TCL, A jne not_found_cleanup_scb; test SCB_CONTROL,DISCONNECTED jz not_found_cleanup_scb; and SCB_CONTROL,~DISCONNECTED; - test SCB_CONTROL, TAG_ENB jnz setup_SCB_tagged; - if ((ahc->flags & AHC_SCB_BTT) != 0) { - mov A, SCBPTR; - } - mvi ARG_1, SCB_LIST_NULL; - mov SAVED_SCSIID call set_busy_target; - if ((ahc->flags & AHC_SCB_BTT) != 0) { - mov SCBPTR, A; - } -setup_SCB_tagged: - mvi SEQ_FLAGS,IDENTIFY_SEEN; /* make note of IDENTIFY */ + or SEQ_FLAGS,IDENTIFY_SEEN; /* make note of IDENTIFY */ call set_transfer_settings; /* See if the host wants to send a message upon reconnection */ test SCB_CONTROL, MK_MESSAGE jz mesgin_done; + and SCB_CONTROL, ~MK_MESSAGE; mvi HOST_MSG call mk_mesg; jmp mesgin_done; not_found_cleanup_scb: - if ((ahc->flags & AHC_PAGESCBS) != 0) { - call cleanup_scb; - } + test SCB_CONTROL, DISCONNECTED jz . + 3; + call add_scb_to_disc_list; + jmp not_found; + call add_scb_to_free_list; not_found: - mvi NO_MATCH call set_seqint; + mvi INTSTAT, NO_MATCH; jmp mesgin_done; +/* + * [ ADD MORE MESSAGE HANDLING HERE ] + */ + +/* + * Locking the driver out, build a one-byte message passed in SINDEX + * if there is no active message already. SINDEX is returned intact. + */ mk_mesg: - if ((ahc->features & AHC_DT) == 0) { - or SCSISIGO, ATNO, LASTPHASE; - } else { - mvi SCSISIGO, ATNO; - } + or SCSISIGO,ATNO,LASTPHASE;/* turn on ATNO */ mov MSG_OUT,SINDEX ret; /* @@ -1908,7 +1401,7 @@ mk_mesg: * use the same calling convention as inb. */ inb_next_wait_perr: - mvi PERR_DETECTED call set_seqint; + mvi INTSTAT, PERR_DETECTED; jmp inb_next_wait; inb_next: mov NONE,SCSIDATL; /*dummy read from latch to ACK*/ @@ -1930,7 +1423,7 @@ inb_last: mov NONE,SCSIDATL ret; /*dummy read from latch to ACK*/ } -if ((ahc->flags & AHC_TARGETROLE) != 0) { +if ((ahc->flags & AHC_TARGETMODE) != 0) { /* * Change to a new phase. If we are changing the state of the I/O signal, * from out to in, wait an additional data release delay before continuing. @@ -1947,7 +1440,7 @@ change_phase: /* * If the data direction has changed, from * out (initiator driving) to in (target driving), - * we must wait at least a data release delay plus + * we must waitat least a data release delay plus * the normal bus settle delay. [SCSI III SPI 10.11.0] */ cmp DINDEX, A je change_phase_wait; @@ -1970,62 +1463,197 @@ target_outb: and SXFRCTL0, ~SPIOEN ret; } +mesgin_phasemis: /* - * Locate a disconnected SCB by SCBID. Upon return, SCBPTR and SINDEX will - * be set to the position of the SCB. If the SCB cannot be found locally, - * it will be paged in from host memory. RETURN_2 stores the address of the - * preceding SCB in the disconnected list which can be used to speed up - * removal of the found SCB from the disconnected list. + * We expected to receive another byte, but the target changed phase + */ + mvi INTSTAT, MSGIN_PHASEMIS; + jmp ITloop; + +/* + * DMA data transfer. HADDR and HCNT must be loaded first, and + * SINDEX should contain the value to load DFCNTRL with - 0x3d for + * host->scsi, or 0x39 for scsi->host. The SCSI channel is cleared + * during initialization. + */ +dma: + mov DFCNTRL,SINDEX; +dma_loop: + test SSTAT0,DMADONE jnz dma_dmadone; + test SSTAT1,PHASEMIS jz dma_loop; /* ie. underrun */ +dma_phasemis: + +/* + * We will be "done" DMAing when the transfer count goes to zero, or + * the target changes the phase (in light of this, it makes sense that + * the DMA circuitry doesn't ACK when PHASEMIS is active). If we are + * doing a SCSI->Host transfer, the data FIFO should be flushed auto- + * magically on STCNT=0 or a phase change, so just wait for FIFO empty + * status. + */ +dma_checkfifo: + test DFCNTRL,DIRECTION jnz dma_fifoempty; +dma_fifoflush: + test DFSTATUS,FIFOEMP jz dma_fifoflush; + +dma_fifoempty: + /* Don't clobber an inprogress host data transfer */ + test DFSTATUS, MREQPEND jnz dma_fifoempty; +/* + * Now shut the DMA enables off and make sure that the DMA enables are + * actually off first lest we get an ILLSADDR. + */ +dma_dmadone: + and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN); +dma_halt: + /* + * Some revisions of the aic7880 have a problem where, if the + * data fifo is full, but the PCI input latch is not empty, + * HDMAEN cannot be cleared. The fix used here is to attempt + * to drain the data fifo until there is space for the input + * latch to drain and HDMAEN de-asserts. + */ + if ((ahc->features & AHC_ULTRA2) == 0) { + mov NONE, DFDAT; + } + test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz dma_halt; +return: + ret; + +/* + * Assert that if we've been reselected, then we've seen an IDENTIFY + * message. + */ +assert: + test SEQ_FLAGS,IDENTIFY_SEEN jnz return; /* seen IDENTIFY? */ + + mvi INTSTAT,NO_IDENT ret; /* no - tell the kernel */ + +/* + * Locate a disconnected SCB either by SAVED_TCL (ARG_1 is SCB_LIST_NULL) + * or by the SCBID ARG_1. The search begins at the SCB index passed in + * via SINDEX which is an SCB that must be on the disconnected list. If + * the SCB cannot be found, SINDEX will be SCB_LIST_NULL, otherwise, SCBPTR + * is set to the proper SCB. */ -if ((ahc->flags & AHC_PAGESCBS) != 0) { -BEGIN_CRITICAL findSCB: - mov A, SINDEX; /* Tag passed in SINDEX */ - cmp DISCONNECTED_SCBH, SCB_LIST_NULL je findSCB_notFound; - mov SCBPTR, DISCONNECTED_SCBH; /* Initialize SCBPTR */ - mvi ARG_2, SCB_LIST_NULL; /* Head of list */ - jmp findSCB_loop; + mov SCBPTR,SINDEX; /* Initialize SCBPTR */ + cmp ARG_1, SCB_LIST_NULL jne findSCB_by_SCBID; + mov A, SAVED_TCL; + mvi SCB_TCL jmp findSCB_loop; /* &SCB_TCL -> SINDEX */ +findSCB_by_SCBID: + mov A, ARG_1; /* Tag passed in ARG_1 */ + mvi SCB_TAG jmp findSCB_loop; /* &SCB_TAG -> SINDEX */ findSCB_next: - cmp SCB_NEXT, SCB_LIST_NULL je findSCB_notFound; mov ARG_2, SCBPTR; + cmp SCB_NEXT, SCB_LIST_NULL je notFound; mov SCBPTR,SCB_NEXT; + dec SINDEX; /* Last comparison moved us too far */ findSCB_loop: - cmp SCB_TAG, A jne findSCB_next; + cmp SINDIR, A jne findSCB_next; + mov SINDEX, SCBPTR ret; +notFound: + mvi SINDEX, SCB_LIST_NULL ret; + +/* + * Retrieve an SCB by SCBID first searching the disconnected list falling + * back to DMA'ing the SCB down from the host. This routine assumes that + * ARG_1 is the SCBID of interrest and that SINDEX is the position in the + * disconnected list to start the search from. If SINDEX is SCB_LIST_NULL, + * we go directly to the host for the SCB. + */ +retrieveSCB: + test SEQ_FLAGS, SCBPTR_VALID jz retrieve_from_host; + mov SCBPTR call findSCB; /* Continue the search */ + cmp SINDEX, SCB_LIST_NULL je retrieve_from_host; + +/* + * This routine expects SINDEX to contain the index of the SCB to be + * removed, SCBPTR to be pointing to that SCB, and ARG_2 to be the + * SCBID of the SCB just previous to this one in the list or SCB_LIST_NULL + * if it is at the head. + */ rem_scb_from_disc_list: +/* Remove this SCB from the disconnection list */ cmp ARG_2, SCB_LIST_NULL je rHead; mov DINDEX, SCB_NEXT; - mov SINDEX, SCBPTR; mov SCBPTR, ARG_2; mov SCB_NEXT, DINDEX; mov SCBPTR, SINDEX ret; rHead: mov DISCONNECTED_SCBH,SCB_NEXT ret; -END_CRITICAL -findSCB_notFound: - /* - * We didn't find it. Page in the SCB. - */ - mov ARG_1, A; /* Save tag */ - mov ALLZEROS call get_free_or_disc_scb; + +retrieve_from_host: +/* + * We didn't find it. Pull an SCB and DMA down the one we want. + * We should never get here in the non-paging case. + */ + mov ALLZEROS call get_free_or_disc_scb; mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET; + /* Jump instead of call as we want to return anyway */ mov ARG_1 jmp dma_scb; -} + +/* + * Determine whether a target is using tagged or non-tagged transactions + * by first looking for a matching transaction based on the TCL and if + * that fails, looking up this device in the host's untagged SCB array. + * The TCL to search for is assumed to be in SAVED_TCL. The value is + * returned in ARG_1 (SCB_LIST_NULL for tagged, SCBID for non-tagged). + * The SCBPTR_VALID bit is set in SEQ_FLAGS if we found the information + * in an SCB instead of having to go to the host. + */ +get_untagged_SCBID: + cmp DISCONNECTED_SCBH, SCB_LIST_NULL je get_SCBID_from_host; + mvi ARG_1, SCB_LIST_NULL; + mov DISCONNECTED_SCBH call findSCB; + cmp SINDEX, SCB_LIST_NULL je get_SCBID_from_host; + or SEQ_FLAGS, SCBPTR_VALID;/* Was in disconnected list */ + test SCB_CONTROL, TAG_ENB jnz . + 2; + mov ARG_1, SCB_TAG ret; + mvi ARG_1, SCB_LIST_NULL ret; + +/* + * Fetch a byte from host memory given an index of (A + (256 * SINDEX)) + * and a base address of SCBID_ADDR. The byte is returned in RETURN_2. + */ +fetch_byte: + mov ARG_2, SINDEX; + if ((ahc->features & AHC_CMD_CHAN) != 0) { + mvi DINDEX, CCHADDR; + mvi SCBID_ADDR call set_1byte_addr; + mvi CCHCNT, 1; + mvi CCSGCTL, CCSGEN|CCSGRESET; + test CCSGCTL, CCSGDONE jz .; + mvi CCSGCTL, CCSGRESET; + bmov RETURN_2, CCSGRAM, 1 ret; + } else { + mvi DINDEX, HADDR; + mvi SCBID_ADDR call set_1byte_addr; + mvi HCNT[0], 1; + clr HCNT[1]; + clr HCNT[2]; + mvi DFCNTRL, HDMAEN|DIRECTION|FIFORESET; + call dma_finish; + mov RETURN_2, DFDAT ret; + } /* * Prepare the hardware to post a byte to host memory given an - * index of (A + (256 * SINDEX)) and a base address of SHARED_DATA_ADDR. + * index of (A + (256 * SINDEX)) and a base address of SCBID_ADDR. */ post_byte_setup: mov ARG_2, SINDEX; if ((ahc->features & AHC_CMD_CHAN) != 0) { mvi DINDEX, CCHADDR; - mvi SHARED_DATA_ADDR call set_1byte_addr; + mvi SCBID_ADDR call set_1byte_addr; mvi CCHCNT, 1; mvi CCSCBCTL, CCSCBRESET ret; } else { mvi DINDEX, HADDR; - mvi SHARED_DATA_ADDR call set_1byte_addr; - mvi 1 call set_hcnt; + mvi SCBID_ADDR call set_1byte_addr; + mvi HCNT[0], 1; + clr HCNT[1]; + clr HCNT[2]; mvi DFCNTRL, FIFORESET ret; } @@ -2041,8 +1669,13 @@ post_byte: jmp dma_finish; } +get_SCBID_from_host: + mov A, SAVED_TCL; + mvi UNTAGGEDSCB_OFFSET call fetch_byte; + mov RETURN_1, RETURN_2 ret; + phase_lock_perr: - mvi PERR_DETECTED call set_seqint; + mvi INTSTAT, PERR_DETECTED; phase_lock: /* * If there is a parity error, wait for the kernel to @@ -2052,25 +1685,15 @@ phase_lock: test SSTAT1, REQINIT jz phase_lock; test SSTAT1, SCSIPERR jnz phase_lock_perr; phase_lock_latch_phase: - if ((ahc->features & AHC_DT) == 0) { - and SCSISIGO, PHASE_MASK, SCSISIGI; - } + and SCSISIGO, PHASE_MASK, SCSISIGI; and LASTPHASE, PHASE_MASK, SCSISIGI ret; if ((ahc->features & AHC_CMD_CHAN) == 0) { -set_hcnt: - mov HCNT[0], SINDEX; -clear_hcnt: - clr HCNT[1]; - clr HCNT[2] ret; - set_stcnt_from_hcnt: mov STCNT[0], HCNT[0]; mov STCNT[1], HCNT[1]; mov STCNT[2], HCNT[2] ret; -bcopy_8: - mov DINDIR, SINDIR; bcopy_7: mov DINDIR, SINDIR; mov DINDIR, SINDIR; @@ -2084,7 +1707,7 @@ bcopy_3: mov DINDIR, SINDIR ret; } -if ((ahc->flags & AHC_TARGETROLE) != 0) { +if ((ahc->flags & AHC_TARGETMODE) != 0) { /* * Setup addr assuming that A is an index into * an array of 32byte objects, SINDEX contains @@ -2110,7 +1733,7 @@ set_64byte_addr: shl A, 6; /* - * Setup addr assuming that A + (ARG_2 * 256) is an + * Setup addr assuming that A + (ARG_1 * 256) is an * index into an array of 1byte objects, SINDEX contains * the base address of that array, and DINDEX contains * the base address of the location to store the computed @@ -2135,27 +1758,17 @@ dma_scb: mvi HSCB_ADDR call set_64byte_addr; mov CCSCBPTR, SCBPTR; test DMAPARAMS, DIRECTION jz dma_scb_tohost; - if ((ahc->flags & AHC_SCB_BTT) != 0) { - mvi CCHCNT, SCB_DOWNLOAD_SIZE_64; - } else { - mvi CCHCNT, SCB_DOWNLOAD_SIZE; - } + mvi CCHCNT, SCB_64BYTE_SIZE; mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBDIR|CCSCBRESET; cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN|CCSCBDIR jne .; jmp dma_scb_finish; dma_scb_tohost: - mvi CCHCNT, SCB_UPLOAD_SIZE; - if ((ahc->features & AHC_ULTRA2) == 0) { + mvi CCHCNT, SCB_32BYTE_SIZE; + if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { mvi CCSCBCTL, CCSCBRESET; - bmov CCSCBRAM, SCB_BASE, SCB_UPLOAD_SIZE; + bmov CCSCBRAM, SCB_CONTROL, SCB_32BYTE_SIZE; or CCSCBCTL, CCSCBEN|CCSCBRESET; test CCSCBCTL, CCSCBDONE jz .; - } else if ((ahc->bugs & AHC_SCBCHAN_UPLOAD_BUG) != 0) { - mvi CCSCBCTL, CCARREN|CCSCBRESET; - cmp CCSCBCTL, ARRDONE|CCARREN jne .; - mvi CCHCNT, SCB_UPLOAD_SIZE; - mvi CCSCBCTL, CCSCBEN|CCSCBRESET; - cmp CCSCBCTL, CCSCBDONE|CCSCBEN jne .; } else { mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBRESET; cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN jne .; @@ -2167,97 +1780,45 @@ dma_scb_finish: } else { mvi DINDEX, HADDR; mvi HSCB_ADDR call set_64byte_addr; - mvi SCB_DOWNLOAD_SIZE call set_hcnt; + mvi HCNT[0], SCB_32BYTE_SIZE; + clr HCNT[1]; + clr HCNT[2]; mov DFCNTRL, DMAPARAMS; test DMAPARAMS, DIRECTION jnz dma_scb_fromhost; /* Fill it with the SCB data */ copy_scb_tofifo: - mvi SINDEX, SCB_BASE; - add A, SCB_DOWNLOAD_SIZE, SINDEX; + mvi SINDEX, SCB_CONTROL; + add A, SCB_32BYTE_SIZE, SINDEX; copy_scb_tofifo_loop: - call copy_to_fifo_8; + mov DFDAT,SINDIR; + mov DFDAT,SINDIR; + mov DFDAT,SINDIR; + mov DFDAT,SINDIR; + mov DFDAT,SINDIR; + mov DFDAT,SINDIR; + mov DFDAT,SINDIR; cmp SINDEX, A jne copy_scb_tofifo_loop; or DFCNTRL, HDMAEN|FIFOFLUSH; - jmp dma_finish; dma_scb_fromhost: - mvi DINDEX, SCB_BASE; - if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) { - /* - * The PCI module will only issue a PCI - * retry if the data FIFO is empty. If the - * host disconnects in the middle of a - * transfer, we must empty the fifo of all - * available data to force the chip to - * continue the transfer. This does not - * happen for SCSI transfers as the SCSI module - * will drain the FIFO as data is made available. - * When the hang occurs, we know that a multiple - * of 8 bytes are in the FIFO because the PCI - * module has an 8 byte input latch that only - * dumps to the FIFO when HCNT == 0 or the - * latch is full. - */ - clr A; - /* Wait for at least 8 bytes of data to arrive. */ -dma_scb_hang_fifo: - test DFSTATUS, FIFOQWDEMP jnz dma_scb_hang_fifo; -dma_scb_hang_wait: - test DFSTATUS, MREQPEND jnz dma_scb_hang_wait; - test DFSTATUS, HDONE jnz dma_scb_hang_dma_done; - test DFSTATUS, HDONE jnz dma_scb_hang_dma_done; - test DFSTATUS, HDONE jnz dma_scb_hang_dma_done; - /* - * The PCI module no longer intends to perform - * a PCI transaction. Drain the fifo. - */ -dma_scb_hang_dma_drain_fifo: - not A, HCNT; - add A, SCB_DOWNLOAD_SIZE+SCB_BASE+1; - and A, ~0x7; - mov DINDIR,DFDAT; - cmp DINDEX, A jne . - 1; - cmp DINDEX, SCB_DOWNLOAD_SIZE+SCB_BASE - je dma_finish_nowait; - /* Restore A as the lines left to transfer. */ - add A, -SCB_BASE, DINDEX; - shr A, 3; - jmp dma_scb_hang_fifo; -dma_scb_hang_dma_done: - and DFCNTRL, ~HDMAEN; - test DFCNTRL, HDMAEN jnz .; - add SEQADDR0, A; - } else { - call dma_finish; - } + call dma_finish; /* If we were putting the SCB, we are done */ - call dfdat_in_8; - call dfdat_in_8; - call dfdat_in_8; -dfdat_in_8: - mov DINDIR,DFDAT; + test DMAPARAMS, DIRECTION jz return; + mvi SCB_CONTROL call dfdat_in_7; + call dfdat_in_7_continued; + call dfdat_in_7_continued; + jmp dfdat_in_7_continued; dfdat_in_7: + mov DINDEX,SINDEX; +dfdat_in_7_continued: mov DINDIR,DFDAT; mov DINDIR,DFDAT; mov DINDIR,DFDAT; mov DINDIR,DFDAT; mov DINDIR,DFDAT; -dfdat_in_2: mov DINDIR,DFDAT; mov DINDIR,DFDAT ret; } -copy_to_fifo_8: - mov DFDAT,SINDIR; - mov DFDAT,SINDIR; -copy_to_fifo_6: - mov DFDAT,SINDIR; -copy_to_fifo_5: - mov DFDAT,SINDIR; -copy_to_fifo_4: - mov DFDAT,SINDIR; - mov DFDAT,SINDIR; - mov DFDAT,SINDIR; - mov DFDAT,SINDIR ret; /* * Wait for DMA from host memory to data FIFO to complete, then disable @@ -2265,59 +1826,37 @@ copy_to_fifo_4: */ dma_finish: test DFSTATUS,HDONE jz dma_finish; -dma_finish_nowait: /* Turn off DMA */ and DFCNTRL, ~HDMAEN; test DFCNTRL, HDMAEN jnz .; ret; -/* - * Restore an SCB that failed to match an incoming reselection - * to the correct/safe state. If the SCB is for a disconnected - * transaction, it must be returned to the disconnected list. - * If it is not in the disconnected state, it must be free. - */ -cleanup_scb: - if ((ahc->flags & AHC_PAGESCBS) != 0) { - test SCB_CONTROL,DISCONNECTED jnz add_scb_to_disc_list; - } add_scb_to_free_list: if ((ahc->flags & AHC_PAGESCBS) != 0) { -BEGIN_CRITICAL mov SCB_NEXT, FREE_SCBH; mvi SCB_TAG, SCB_LIST_NULL; mov FREE_SCBH, SCBPTR ret; -END_CRITICAL } else { mvi SCB_TAG, SCB_LIST_NULL ret; } -if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { -set_hhaddr: - or DSCOMMAND1, HADDLDSEL0; - and HADDR, SG_HIGH_ADDR_BITS, SINDEX; - and DSCOMMAND1, ~HADDLDSEL0 ret; -} - if ((ahc->flags & AHC_PAGESCBS) != 0) { get_free_or_disc_scb: -BEGIN_CRITICAL cmp FREE_SCBH, SCB_LIST_NULL jne dequeue_free_scb; cmp DISCONNECTED_SCBH, SCB_LIST_NULL jne dequeue_disc_scb; return_error: - mvi NO_FREE_SCB call set_seqint; mvi SINDEX, SCB_LIST_NULL ret; dequeue_disc_scb: mov SCBPTR, DISCONNECTED_SCBH; - mov DISCONNECTED_SCBH, SCB_NEXT; -END_CRITICAL +dma_up_scb: mvi DMAPARAMS, FIFORESET; - mov SCB_TAG jmp dma_scb; -BEGIN_CRITICAL + mov SCB_TAG call dma_scb; +unlink_disc_scb: + mov DISCONNECTED_SCBH, SCB_NEXT ret; dequeue_free_scb: mov SCBPTR, FREE_SCBH; mov FREE_SCBH, SCB_NEXT ret; -END_CRITICAL +} add_scb_to_disc_list: /* @@ -2325,13 +1864,5 @@ add_scb_to_disc_list: * candidates for paging out an SCB if one is needed for a new command. * Modifying the disconnected list is a critical(pause dissabled) section. */ -BEGIN_CRITICAL mov SCB_NEXT, DISCONNECTED_SCBH; mov DISCONNECTED_SCBH, SCBPTR ret; -END_CRITICAL -} -set_seqint: - mov INTSTAT, SINDEX; - nop; -return: - ret; |