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path: root/sys/dev/pci/drm/i915/intel_ringbuffer.c
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Diffstat (limited to 'sys/dev/pci/drm/i915/intel_ringbuffer.c')
-rw-r--r--sys/dev/pci/drm/i915/intel_ringbuffer.c34
1 files changed, 17 insertions, 17 deletions
diff --git a/sys/dev/pci/drm/i915/intel_ringbuffer.c b/sys/dev/pci/drm/i915/intel_ringbuffer.c
index 8c8b23035c1..3d6ad536950 100644
--- a/sys/dev/pci/drm/i915/intel_ringbuffer.c
+++ b/sys/dev/pci/drm/i915/intel_ringbuffer.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: intel_ringbuffer.c,v 1.12 2013/11/30 20:03:32 kettenis Exp $ */
+/* $OpenBSD: intel_ringbuffer.c,v 1.13 2013/11/30 20:13:36 kettenis Exp $ */
/*
* Copyright © 2008-2010 Intel Corporation
*
@@ -761,13 +761,13 @@ gen5_ring_get_irq(struct intel_ring_buffer *ring)
if (!dev->irq_enabled)
return false;
- mtx_enter(&dev_priv->irq_lock);
+// mtx_enter(&dev_priv->irq_lock);
if (ring->irq_refcount++ == 0) {
dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
POSTING_READ(GTIMR);
}
- mtx_leave(&dev_priv->irq_lock);
+// mtx_leave(&dev_priv->irq_lock);
return true;
}
@@ -778,13 +778,13 @@ gen5_ring_put_irq(struct intel_ring_buffer *ring)
struct drm_device *dev = ring->dev;
drm_i915_private_t *dev_priv = dev->dev_private;
- mtx_enter(&dev_priv->irq_lock);
+// mtx_enter(&dev_priv->irq_lock);
if (--ring->irq_refcount == 0) {
dev_priv->gt_irq_mask |= ring->irq_enable_mask;
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
POSTING_READ(GTIMR);
}
- mtx_leave(&dev_priv->irq_lock);
+// mtx_leave(&dev_priv->irq_lock);
}
static bool
@@ -796,13 +796,13 @@ i9xx_ring_get_irq(struct intel_ring_buffer *ring)
if (!dev->irq_enabled)
return false;
- mtx_enter(&dev_priv->irq_lock);
+// mtx_enter(&dev_priv->irq_lock);
if (ring->irq_refcount++ == 0) {
dev_priv->irq_mask &= ~ring->irq_enable_mask;
I915_WRITE(IMR, dev_priv->irq_mask);
POSTING_READ(IMR);
}
- mtx_leave(&dev_priv->irq_lock);
+// mtx_leave(&dev_priv->irq_lock);
return true;
}
@@ -813,13 +813,13 @@ i9xx_ring_put_irq(struct intel_ring_buffer *ring)
struct drm_device *dev = ring->dev;
drm_i915_private_t *dev_priv = dev->dev_private;
- mtx_enter(&dev_priv->irq_lock);
+// mtx_enter(&dev_priv->irq_lock);
if (--ring->irq_refcount == 0) {
dev_priv->irq_mask |= ring->irq_enable_mask;
I915_WRITE(IMR, dev_priv->irq_mask);
POSTING_READ(IMR);
}
- mtx_leave(&dev_priv->irq_lock);
+// mtx_leave(&dev_priv->irq_lock);
}
static bool
@@ -831,13 +831,13 @@ i8xx_ring_get_irq(struct intel_ring_buffer *ring)
if (!dev->irq_enabled)
return false;
- mtx_enter(&dev_priv->irq_lock);
+// mtx_enter(&dev_priv->irq_lock);
if (ring->irq_refcount++ == 0) {
dev_priv->irq_mask &= ~ring->irq_enable_mask;
I915_WRITE16(IMR, dev_priv->irq_mask);
POSTING_READ16(IMR);
}
- mtx_leave(&dev_priv->irq_lock);
+// mtx_leave(&dev_priv->irq_lock);
return true;
}
@@ -848,13 +848,13 @@ i8xx_ring_put_irq(struct intel_ring_buffer *ring)
struct drm_device *dev = ring->dev;
drm_i915_private_t *dev_priv = dev->dev_private;
- mtx_enter(&dev_priv->irq_lock);
+// mtx_enter(&dev_priv->irq_lock);
if (--ring->irq_refcount == 0) {
dev_priv->irq_mask |= ring->irq_enable_mask;
I915_WRITE16(IMR, dev_priv->irq_mask);
POSTING_READ16(IMR);
}
- mtx_leave(&dev_priv->irq_lock);
+// mtx_leave(&dev_priv->irq_lock);
}
void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
@@ -937,7 +937,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring)
* blt/bsd rings on ivb. */
gen6_gt_force_wake_get(dev_priv);
- mtx_enter(&dev_priv->irq_lock);
+// mtx_enter(&dev_priv->irq_lock);
if (ring->irq_refcount++ == 0) {
if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
@@ -948,7 +948,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring)
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
POSTING_READ(GTIMR);
}
- mtx_leave(&dev_priv->irq_lock);
+// mtx_leave(&dev_priv->irq_lock);
return true;
}
@@ -959,7 +959,7 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
struct drm_device *dev = ring->dev;
drm_i915_private_t *dev_priv = dev->dev_private;
- mtx_enter(&dev_priv->irq_lock);
+// mtx_enter(&dev_priv->irq_lock);
if (--ring->irq_refcount == 0) {
if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
@@ -969,7 +969,7 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
POSTING_READ(GTIMR);
}
- mtx_leave(&dev_priv->irq_lock);
+// mtx_leave(&dev_priv->irq_lock);
gen6_gt_force_wake_put(dev_priv);
}