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path: root/sys/dev/pci/drm/i915_drv.c
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Diffstat (limited to 'sys/dev/pci/drm/i915_drv.c')
-rw-r--r--sys/dev/pci/drm/i915_drv.c50
1 files changed, 36 insertions, 14 deletions
diff --git a/sys/dev/pci/drm/i915_drv.c b/sys/dev/pci/drm/i915_drv.c
index e73fa152573..394d92fb5d2 100644
--- a/sys/dev/pci/drm/i915_drv.c
+++ b/sys/dev/pci/drm/i915_drv.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: i915_drv.c,v 1.122 2012/05/26 19:30:53 kettenis Exp $ */
+/* $OpenBSD: i915_drv.c,v 1.123 2012/09/25 10:19:46 jsg Exp $ */
/*
* Copyright (c) 2008-2009 Owain G. Ainsworth <oga@openbsd.org>
*
@@ -267,6 +267,18 @@ const static struct drm_pcidev inteldrm_pciidlist[] = {
CHIP_SANDYBRIDGE|CHIP_I965|CHIP_I9XX|CHIP_HWS|CHIP_GEN6},
{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE2G_M_GT2_PLUS,
CHIP_SANDYBRIDGE|CHIP_M|CHIP_I965|CHIP_I9XX|CHIP_HWS|CHIP_GEN6},
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE3G_D_GT1,
+ CHIP_IVYBRIDGE|CHIP_I965|CHIP_I9XX|CHIP_HWS|CHIP_GEN7},
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE3G_M_GT1,
+ CHIP_IVYBRIDGE|CHIP_M|CHIP_I965|CHIP_I9XX|CHIP_HWS|CHIP_GEN7},
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE3G_S_GT1,
+ CHIP_IVYBRIDGE|CHIP_I965|CHIP_I9XX|CHIP_HWS|CHIP_GEN7},
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE3G_D_GT2,
+ CHIP_IVYBRIDGE|CHIP_I965|CHIP_I9XX|CHIP_HWS|CHIP_GEN7},
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE3G_M_GT2,
+ CHIP_IVYBRIDGE|CHIP_M|CHIP_I965|CHIP_I9XX|CHIP_HWS|CHIP_GEN7},
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE3G_S_GT2,
+ CHIP_IVYBRIDGE|CHIP_I965|CHIP_I9XX|CHIP_HWS|CHIP_GEN7},
{0, 0, 0}
};
@@ -344,6 +356,8 @@ inteldrm_attach(struct device *parent, struct device *self, void *aux)
dev_priv->gen = 5;
else if (dev_priv->flags & CHIP_GEN6)
dev_priv->gen = 6;
+ else if (dev_priv->flags & CHIP_GEN7)
+ dev_priv->gen = 7;
KASSERT(dev_priv->gen != 0);
dev_priv->pc = pa->pa_pc;
@@ -442,7 +456,7 @@ inteldrm_attach(struct device *parent, struct device *self, void *aux)
dev_priv->num_fence_regs = 8;
/* Initialise fences to zero, else on some macs we'll get corruption */
- if (IS_GEN6(dev_priv)) {
+ if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
for (i = 0; i < 16; i++)
I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
} else if (IS_I965G(dev_priv)) {
@@ -683,7 +697,7 @@ inteldrm_ironlake_intr(void *arg)
struct inteldrm_softc *dev_priv = arg;
struct drm_device *dev = (struct drm_device *)dev_priv->drmdev;
u_int32_t de_iir, gt_iir, de_ier, pch_iir;
- int ret = 0;
+ int ret = 0, i;
de_ier = I915_READ(DEIER);
I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
@@ -705,10 +719,17 @@ inteldrm_ironlake_intr(void *arg)
if (gt_iir & GT_MASTER_ERROR)
inteldrm_error(dev_priv);
- if (de_iir & DE_PIPEA_VBLANK)
- drm_handle_vblank(dev, 0);
- if (de_iir & DE_PIPEB_VBLANK)
- drm_handle_vblank(dev, 1);
+ if (IS_GEN7(dev_priv)) {
+ for (i = 0; i < 3; i++) {
+ if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
+ drm_handle_vblank(dev, i);
+ }
+ } else {
+ if (de_iir & DE_PIPEA_VBLANK)
+ drm_handle_vblank(dev, 0);
+ if (de_iir & DE_PIPEB_VBLANK)
+ drm_handle_vblank(dev, 1);
+ }
/* should clear PCH hotplug event before clearing CPU irq */
I915_WRITE(SDEIIR, pch_iir);
@@ -1638,7 +1659,7 @@ i915_add_request(struct inteldrm_softc *dev_priv)
if (dev_priv->mm.next_gem_seqno == 0)
dev_priv->mm.next_gem_seqno++;
- if (IS_GEN6(dev_priv))
+ if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
BEGIN_LP_RING(10);
else
BEGIN_LP_RING(4);
@@ -2392,7 +2413,7 @@ again:
reg->obj = obj;
TAILQ_INSERT_TAIL(&dev_priv->mm.fence_list, reg, list);
- if (IS_GEN6(dev_priv))
+ if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
sandybridge_write_fence_reg(reg);
else if (IS_I965G(dev_priv))
i965_write_fence_reg(reg);
@@ -3237,7 +3258,7 @@ i915_dispatch_gem_execbuffer(struct drm_device *dev,
} else {
BEGIN_LP_RING(4);
if (IS_I965G(dev_priv)) {
- if (IS_GEN6(dev_priv))
+ if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
OUT_RING(MI_BATCH_BUFFER_START |
MI_BATCH_NON_SECURE_I965);
else
@@ -4184,7 +4205,7 @@ inteldrm_start_ring(struct inteldrm_softc *dev_priv)
/* Update our cache of the ring state */
inteldrm_update_ring(dev_priv);
- if (IS_GEN6(dev_priv))
+ if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
I915_WRITE(MI_MODE | MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE,
(VS_TIMER_DISPATCH) << 15 | VS_TIMER_DISPATCH);
else if (IS_I9XX(dev_priv) && !IS_GEN3(dev_priv))
@@ -4218,7 +4239,7 @@ i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
int ret;
/* XXX until we have support for the rings on sandybridge */
- if (IS_GEN6(dev_priv))
+ if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
return (0);
if (dev_priv->mm.wedged) {
@@ -4294,7 +4315,7 @@ inteldrm_error(struct inteldrm_softc *dev_priv)
}
printf("render error detected, EIR: %b\n", eir, errbitstr);
- if (IS_IRONLAKE(dev_priv) || IS_GEN6(dev_priv)) {
+ if (IS_IRONLAKE(dev_priv) || IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
if (eir & I915_ERROR_PAGE_TABLE) {
dev_priv->mm.wedged = 1;
reset = GRDOM_FULL;
@@ -4380,7 +4401,8 @@ inteldrm_error(struct inteldrm_softc *dev_priv)
if (dev_priv->mm.wedged == 0)
DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
I915_WRITE(EMR, I915_READ(EMR) | eir);
- if (IS_IRONLAKE(dev_priv) || IS_GEN6(dev_priv)) {
+ if (IS_IRONLAKE(dev_priv) || IS_GEN6(dev_priv) ||
+ IS_GEN7(dev_priv)) {
I915_WRITE(GTIIR, GT_MASTER_ERROR);
} else {
I915_WRITE(IIR,
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 04:05:20 +0000