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path: root/sys/dev/pci/drm/radeon/ni.c
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Diffstat (limited to 'sys/dev/pci/drm/radeon/ni.c')
-rw-r--r--sys/dev/pci/drm/radeon/ni.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/sys/dev/pci/drm/radeon/ni.c b/sys/dev/pci/drm/radeon/ni.c
index 4d31acf1023..6517606e9d2 100644
--- a/sys/dev/pci/drm/radeon/ni.c
+++ b/sys/dev/pci/drm/radeon/ni.c
@@ -269,7 +269,7 @@ int ni_mc_load_microcode(struct radeon_device *rdev)
for (i = 0; i < rdev->usec_timeout; i++) {
if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
break;
- DRM_UDELAY(1);
+ udelay(1);
}
if (running)
@@ -733,7 +733,7 @@ static void cayman_gpu_init(struct radeon_device *rdev)
WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
- DRM_UDELAY(50);
+ udelay(50);
}
/*
@@ -1080,7 +1080,7 @@ static int cayman_cp_resume(struct radeon_device *rdev)
SOFT_RESET_SPI |
SOFT_RESET_SX));
RREG32(GRBM_SOFT_RESET);
- DRM_MDELAY(15);
+ mdelay(15);
WREG32(GRBM_SOFT_RESET, 0);
RREG32(GRBM_SOFT_RESET);
@@ -1130,7 +1130,7 @@ static int cayman_cp_resume(struct radeon_device *rdev)
WREG32(ring->rptr_reg, ring->rptr);
WREG32(ring->wptr_reg, ring->wptr);
- DRM_MDELAY(1);
+ mdelay(1);
WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
}
@@ -1244,7 +1244,7 @@ int cayman_dma_resume(struct radeon_device *rdev)
/* Reset dma */
WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
RREG32(SRBM_SOFT_RESET);
- DRM_UDELAY(50);
+ udelay(50);
WREG32(SRBM_SOFT_RESET, 0);
for (i = 0; i < 2; i++) {
@@ -1375,7 +1375,7 @@ static void cayman_gpu_soft_reset_gfx(struct radeon_device *rdev)
dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
WREG32(GRBM_SOFT_RESET, grbm_reset);
(void)RREG32(GRBM_SOFT_RESET);
- DRM_UDELAY(50);
+ udelay(50);
WREG32(GRBM_SOFT_RESET, 0);
(void)RREG32(GRBM_SOFT_RESET);
@@ -1421,7 +1421,7 @@ static void cayman_gpu_soft_reset_dma(struct radeon_device *rdev)
/* Reset dma */
WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
RREG32(SRBM_SOFT_RESET);
- DRM_UDELAY(50);
+ udelay(50);
WREG32(SRBM_SOFT_RESET, 0);
dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
@@ -1465,7 +1465,7 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
cayman_gpu_soft_reset_dma(rdev);
/* Wait a little for things to settle down */
- DRM_UDELAY(50);
+ udelay(50);
evergreen_mc_resume(rdev, &save);
return 0;