diff options
Diffstat (limited to 'sys/dev/pci/ubsecreg.h')
| -rw-r--r-- | sys/dev/pci/ubsecreg.h | 33 |
1 files changed, 26 insertions, 7 deletions
diff --git a/sys/dev/pci/ubsecreg.h b/sys/dev/pci/ubsecreg.h index aa0c6f011a3..9e881f6b877 100644 --- a/sys/dev/pci/ubsecreg.h +++ b/sys/dev/pci/ubsecreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: ubsecreg.h,v 1.29 2009/03/25 12:17:30 reyk Exp $ */ +/* $OpenBSD: ubsecreg.h,v 1.30 2009/03/27 13:31:30 reyk Exp $ */ /* * Copyright (c) 2000 Theo de Raadt @@ -54,11 +54,15 @@ /* * DMA Control & Status Registers (offset from BS_BAR) */ -#define BS_MCR1 0x00 /* DMA Master Command Record 1 */ -#define BS_CTRL 0x04 /* DMA Control */ -#define BS_STAT 0x08 /* DMA Status */ -#define BS_ERR 0x0c /* DMA Error Address */ -#define BS_MCR2 0x10 /* DMA Master Command Record 2 */ +#define BS_MCR1 0x0000 /* DMA Master Command Record 1 */ +#define BS_CTRL 0x0004 /* DMA Control */ +#define BS_STAT 0x0008 /* DMA Status */ +#define BS_ERR 0x000c /* DMA Error Address */ +#define BS_MCR2 0x0010 /* DMA Master Command Record 2 */ +#define BS_MCR3 0x0014 /* 5827+, DMA Master Command Record 3 */ +#define BS_MCR4 0x001c /* 5827+, DMA Master Command Record 4 */ +#define BS_CFG 0x0700 /* 5827+, Configuration Register */ +#define BS_INT 0x0f00 /* 5827+, Interrupt Register */ /* BS_CTRL - DMA Control */ #define BS_CTRL_RESET 0x80000000 /* hardware reset, 5805/5820 */ @@ -74,11 +78,14 @@ #define BS_CTRL_RNG_8 0x01000000 /* 1bit rn/eight slow clocks */ #define BS_CTRL_RNG_16 0x01800000 /* 1bit rn/16 slow clocks */ #define BS_CTRL_SWNORM 0x00400000 /* 582[01], sw normalization */ +#define BS_CTRL_MCR3INT 0x00400000 /* 5827+, intr for MCR3 */ +#define BS_CTRL_MCR4INT 0x00200000 /* 5827+, intr for MCR4 */ +#define BS_CTRL_BSIZE240 0x000f0000 /* 5827+, burst size 240 */ #define BS_CTRL_FRAG_M 0x0000ffff /* output fragment size mask */ #define BS_CTRL_LITTLE_ENDIAN (BS_CTRL_BE32 | BS_CTRL_BE64) /* BS_STAT - DMA Status */ -#define BS_STAT_MCR1_BUSY 0x80000000 /* MCR1 is busy */ +#define BS_STAT_MCR_BUSY 0x80000000 /* MCR is busy */ #define BS_STAT_MCR1_FULL 0x40000000 /* MCR1 is full */ #define BS_STAT_MCR1_DONE 0x20000000 /* MCR1 is done */ #define BS_STAT_DMAERR 0x10000000 /* DMA error */ @@ -86,11 +93,23 @@ #define BS_STAT_MCR2_DONE 0x04000000 /* MCR2 is done */ #define BS_STAT_MCR1_ALLEMPTY 0x02000000 /* 5821, MCR1 is empty */ #define BS_STAT_MCR2_ALLEMPTY 0x01000000 /* 5821, MCR2 is empty */ +#define BS_STAT_MCR3_ALLEMPTY 0x00800000 /* 5827+, MCR3 is empty */ +#define BS_STAT_MCR4_ALLEMPTY 0x00400000 /* 5827+, MCR4 is empty */ +#define BS_STAT_MCR3_FULL 0x00080000 /* 5827+, MCR3 is full */ +#define BS_STAT_MCR3_DONE 0x00040000 /* 5827+, MCR3 is done */ +#define BS_STAT_MCR4_FULL 0x00020000 /* 5827+, MCR4 is full */ +#define BS_STAT_MCR4_DONE 0x00010000 /* 5827+, MCR4 is done */ /* BS_ERR - DMA Error Address */ #define BS_ERR_ADDR 0xfffffffc /* error address mask */ #define BS_ERR_READ 0x00000002 /* fault was on read */ +/* BS_CFG */ +#define BS_CFG_RNG 0x00000001 /* 5827+, enable RNG */ + +/* BS_INT */ +#define BS_INT_DMAINT 0x80000000 /* 5827+, enable DMA intr */ + /* DES/3DES */ struct ubsec_pktctx { u_int32_t pc_deskey[6]; /* 3DES key */ |