diff options
Diffstat (limited to 'sys/dev/sbus')
| -rw-r--r-- | sys/dev/sbus/files.sbus | 14 | ||||
| -rw-r--r-- | sys/dev/sbus/qe.c | 1262 | ||||
| -rw-r--r-- | sys/dev/sbus/qec.c | 426 | ||||
| -rw-r--r-- | sys/dev/sbus/qecreg.h | 121 | ||||
| -rw-r--r-- | sys/dev/sbus/qecvar.h | 78 | ||||
| -rw-r--r-- | sys/dev/sbus/qereg.h | 389 |
6 files changed, 2289 insertions, 1 deletions
diff --git a/sys/dev/sbus/files.sbus b/sys/dev/sbus/files.sbus index 4b1fa3d3861..231c2386fbc 100644 --- a/sys/dev/sbus/files.sbus +++ b/sys/dev/sbus/files.sbus @@ -1,4 +1,4 @@ -# $OpenBSD: files.sbus,v 1.2 2001/08/20 19:48:33 jason Exp $ +# $OpenBSD: files.sbus,v 1.3 2001/08/20 22:09:27 jason Exp $ # $NetBSD: files.sbus,v 1.16 2000/12/08 17:29:12 martin Exp $ # # Config file and device description for machine-independent SBUS code. @@ -25,3 +25,15 @@ attach le at ledma with le_ledma file dev/sbus/if_le.c le_sbus file dev/sbus/if_le_lebuffer.c le_lebuffer file dev/sbus/if_le_ledma.c le_ledma + +device qec {} +attach qec at sbus +file dev/sbus/qec.c qec + +device be: ether, ifnet, mii, ifmedia +attach be at qec +file dev/sbus/be.c be + +device qe: ether, ifnet, ifmedia +attach qe at qec +file dev/sbus/qe.c qe diff --git a/sys/dev/sbus/qe.c b/sys/dev/sbus/qe.c new file mode 100644 index 00000000000..f5a0c4491be --- /dev/null +++ b/sys/dev/sbus/qe.c @@ -0,0 +1,1262 @@ +/* $OpenBSD: qe.c,v 1.1 2001/08/20 22:09:27 jason Exp $ */ +/* $NetBSD: qe.c,v 1.16 2001/03/30 17:30:18 christos Exp $ */ + +/*- + * Copyright (c) 1999 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Paul Kranenburg. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Copyright (c) 1998 Jason L. Wright. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the authors may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Driver for the SBus qec+qe QuadEthernet board. + * + * This driver was written using the AMD MACE Am79C940 documentation, some + * ideas gleaned from the S/Linux driver for this card, Solaris header files, + * and a loan of a card from Paul Southworth of the Internet Engineering + * Group (www.ieng.com). + */ + +#define QEDEBUG + +#include "bpfilter.h" + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/kernel.h> +#include <sys/errno.h> +#include <sys/ioctl.h> +#include <sys/mbuf.h> +#include <sys/socket.h> +#include <sys/syslog.h> +#include <sys/device.h> +#include <sys/malloc.h> + +#include <net/if.h> +#include <net/if_dl.h> +#include <net/if_types.h> +#include <net/netisr.h> +#include <net/if_media.h> + +#ifdef INET +#include <netinet/in.h> +#include <netinet/in_systm.h> +#include <netinet/in_var.h> +#include <netinet/ip.h> +#include <netinet/if_ether.h> +#endif + +#ifdef NS +#include <netns/ns.h> +#include <netns/ns_if.h> +#endif + +#if NBPFILTER > 0 +#include <net/bpf.h> +#include <net/bpfdesc.h> +#endif + +#include <machine/bus.h> +#include <machine/intr.h> +#include <machine/autoconf.h> + +#include <dev/sbus/sbusvar.h> +#include <dev/sbus/qecreg.h> +#include <dev/sbus/qecvar.h> +#include <dev/sbus/qereg.h> + +struct qe_softc { + struct device sc_dev; /* base device */ + struct sbusdev sc_sd; /* sbus device */ + bus_space_tag_t sc_bustag; /* bus & dma tags */ + bus_dma_tag_t sc_dmatag; + bus_dmamap_t sc_dmamap; + struct arpcom sc_arpcom; + struct ifmedia sc_ifmedia; /* interface media */ + + struct qec_softc *sc_qec; /* QEC parent */ + + bus_space_handle_t sc_qr; /* QEC registers */ + bus_space_handle_t sc_mr; /* MACE registers */ + bus_space_handle_t sc_cr; /* channel registers */ + + int sc_channel; /* channel number */ + u_int sc_rev; /* board revision */ + + int sc_burst; + + struct qec_ring sc_rb; /* Packet Ring Buffer */ + + /* MAC address */ + u_int8_t sc_enaddr[6]; + +#ifdef QEDEBUG + int sc_debug; +#endif +}; + +int qematch __P((struct device *, void *, void *)); +void qeattach __P((struct device *, struct device *, void *)); + +void qeinit __P((struct qe_softc *)); +void qestart __P((struct ifnet *)); +void qestop __P((struct qe_softc *)); +void qewatchdog __P((struct ifnet *)); +int qeioctl __P((struct ifnet *, u_long, caddr_t)); +void qereset __P((struct qe_softc *)); + +int qeintr __P((void *)); +int qe_eint __P((struct qe_softc *, u_int32_t)); +int qe_rint __P((struct qe_softc *)); +int qe_tint __P((struct qe_softc *)); +void qe_mcreset __P((struct qe_softc *)); + +static int qe_put __P((struct qe_softc *, int, struct mbuf *)); +static void qe_read __P((struct qe_softc *, int, int)); +static struct mbuf *qe_get __P((struct qe_softc *, int, int)); + +/* ifmedia callbacks */ +void qe_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); +int qe_ifmedia_upd __P((struct ifnet *)); + +struct cfattach qe_ca = { + sizeof(struct qe_softc), qematch, qeattach +}; + +struct cfdriver qe_cd = { + NULL, "qe", DV_IFNET +}; + +int +qematch(parent, vcf, aux) + struct device *parent; + void *vcf; + void *aux; +{ + struct cfdata *cf = vcf; + struct sbus_attach_args *sa = aux; + + return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); +} + +void +qeattach(parent, self, aux) + struct device *parent, *self; + void *aux; +{ + struct sbus_attach_args *sa = aux; + struct qec_softc *qec = (struct qec_softc *)parent; + struct qe_softc *sc = (struct qe_softc *)self; + struct ifnet *ifp = &sc->sc_arpcom.ac_if; + int node = sa->sa_node; + bus_dma_tag_t dmatag = sa->sa_dmatag; + bus_dma_segment_t seg; + bus_size_t size; + int rseg, error; + struct bootpath *bp; + extern void myetheraddr __P((u_char *)); + + if (sa->sa_nreg < 2) { + printf("%s: only %d register sets\n", + self->dv_xname, sa->sa_nreg); + return; + } + + if (bus_space_map2(sa->sa_bustag, + (bus_type_t)sa->sa_reg[0].sbr_slot, + (bus_addr_t)sa->sa_reg[0].sbr_offset, + (bus_size_t)sa->sa_reg[0].sbr_size, + BUS_SPACE_MAP_LINEAR, 0, &sc->sc_cr) != 0) { + printf("%s: cannot map registers\n", self->dv_xname); + return; + } + + if (bus_space_map2(sa->sa_bustag, + (bus_type_t)sa->sa_reg[1].sbr_slot, + (bus_addr_t)sa->sa_reg[1].sbr_offset, + (bus_size_t)sa->sa_reg[1].sbr_size, + BUS_SPACE_MAP_LINEAR, 0, &sc->sc_mr) != 0) { + printf("%s: cannot map registers\n", self->dv_xname); + return; + } + + sc->sc_rev = getpropint(node, "mace-version", -1); + printf(" rev %x", sc->sc_rev); + + sc->sc_qec = qec; + sc->sc_qr = qec->sc_regs; + + sc->sc_channel = getpropint(node, "channel#", -1); + sc->sc_burst = qec->sc_burst; + + qestop(sc); + + /* Note: no interrupt level passed */ + (void)bus_intr_establish(sa->sa_bustag, 0, IPL_NET, 0, qeintr, sc); + myetheraddr(sc->sc_enaddr); + + /* + * Allocate descriptor ring and buffers. + */ + + /* for now, allocate as many bufs as there are ring descriptors */ + sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; + sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; + + size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + + QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + + sc->sc_rb.rb_ntbuf * QE_PKT_BUF_SZ + + sc->sc_rb.rb_nrbuf * QE_PKT_BUF_SZ; + + /* Get a DMA handle */ + if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, + BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { + printf("%s: DMA map create error %d\n", self->dv_xname, error); + return; + } + + /* Allocate DMA buffer */ + if ((error = bus_dmamem_alloc(dmatag, size, 0, 0, + &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { + printf("%s: DMA buffer alloc error %d\n", + self->dv_xname, error); + return; + } + sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; + + /* Map DMA buffer in CPU addressable space */ + if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, + &sc->sc_rb.rb_membase, + BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { + printf("%s: DMA buffer map error %d\n", + self->dv_xname, error); + bus_dmamem_free(dmatag, &seg, rseg); + return; + } + + /* Load the buffer */ + if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, + sc->sc_rb.rb_membase, size, NULL, + BUS_DMA_NOWAIT)) != 0) { + printf("%s: DMA buffer map load error %d\n", + self->dv_xname, error); + bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); + bus_dmamem_free(dmatag, &seg, rseg); + return; + } + + /* Initialize media properties */ + ifmedia_init(&sc->sc_ifmedia, 0, qe_ifmedia_upd, qe_ifmedia_sts); + ifmedia_add(&sc->sc_ifmedia, + IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,0), + 0, NULL); + ifmedia_add(&sc->sc_ifmedia, + IFM_MAKEWORD(IFM_ETHER,IFM_10_5,0,0), + 0, NULL); + ifmedia_add(&sc->sc_ifmedia, + IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,0), + 0, NULL); + ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); + + bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); + ifp->if_softc = sc; + ifp->if_start = qestart; + ifp->if_ioctl = qeioctl; + ifp->if_watchdog = qewatchdog; + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | + IFF_MULTICAST; + IFQ_SET_READY(&ifp->if_snd); + + /* Attach the interface. */ + if_attach(ifp); + ether_ifattach(ifp); + + printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); + + bp = sa->sa_bp; + if (bp != NULL && strcmp(bp->name, qe_cd.cd_name) == 0 && + sc->sc_dev.dv_unit == bp->val[1]) + bp->dev = &sc->sc_dev; +} + +/* + * Pull data off an interface. + * Len is the length of data, with local net header stripped. + * We copy the data into mbufs. When full cluster sized units are present, + * we copy into clusters. + */ +static __inline__ struct mbuf * +qe_get(sc, idx, totlen) + struct qe_softc *sc; + int idx, totlen; +{ + struct ifnet *ifp = &sc->sc_arpcom.ac_if; + struct mbuf *m; + struct mbuf *top, **mp; + int len, pad, boff = 0; + caddr_t bp; + + bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * QE_PKT_BUF_SZ; + + MGETHDR(m, M_DONTWAIT, MT_DATA); + if (m == NULL) + return (NULL); + m->m_pkthdr.rcvif = ifp; + m->m_pkthdr.len = totlen; + pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); + m->m_data += pad; + len = MHLEN - pad; + top = NULL; + mp = ⊤ + + while (totlen > 0) { + if (top) { + MGET(m, M_DONTWAIT, MT_DATA); + if (m == NULL) { + m_freem(top); + return (NULL); + } + len = MLEN; + } + if (top && totlen >= MINCLSIZE) { + MCLGET(m, M_DONTWAIT); + if (m->m_flags & M_EXT) + len = MCLBYTES; + } + m->m_len = len = min(totlen, len); + bcopy(bp + boff, mtod(m, caddr_t), len); + boff += len; + totlen -= len; + *mp = m; + mp = &m->m_next; + } + + return (top); +} + +/* + * Routine to copy from mbuf chain to transmit buffer in + * network buffer memory. + */ +__inline__ int +qe_put(sc, idx, m) + struct qe_softc *sc; + int idx; + struct mbuf *m; +{ + struct mbuf *n; + int len, tlen = 0, boff = 0; + caddr_t bp; + + bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * QE_PKT_BUF_SZ; + + for (; m; m = n) { + len = m->m_len; + if (len == 0) { + MFREE(m, n); + continue; + } + bcopy(mtod(m, caddr_t), bp+boff, len); + boff += len; + tlen += len; + MFREE(m, n); + } + return (tlen); +} + +/* + * Pass a packet to the higher levels. + */ +__inline__ void +qe_read(sc, idx, len) + struct qe_softc *sc; + int idx, len; +{ + struct ifnet *ifp = &sc->sc_arpcom.ac_if; + struct mbuf *m; + + if (len <= sizeof(struct ether_header) || + len > ETHERMTU + sizeof(struct ether_header)) { + + printf("%s: invalid packet size %d; dropping\n", + ifp->if_xname, len); + + ifp->if_ierrors++; + return; + } + + /* + * Pull packet off interface. + */ + m = qe_get(sc, idx, len); + if (m == NULL) { + ifp->if_ierrors++; + return; + } + ifp->if_ipackets++; + +#if NBPFILTER > 0 + /* + * Check if there's a BPF listener on this interface. + * If so, hand off the raw packet to BPF. + */ + if (ifp->if_bpf) + bpf_mtap(ifp->if_bpf, m); +#endif + /* Pass the packet up. */ + ether_input_mbuf(ifp, m); +} + +/* + * Start output on interface. + * We make two assumptions here: + * 1) that the current priority is set to splnet _before_ this code + * is called *and* is returned to the appropriate priority after + * return + * 2) that the IFF_OACTIVE flag is checked before this code is called + * (i.e. that the output part of the interface is idle) + */ +void +qestart(ifp) + struct ifnet *ifp; +{ + struct qe_softc *sc = (struct qe_softc *)ifp->if_softc; + struct qec_xd *txd = sc->sc_rb.rb_txd; + struct mbuf *m; + unsigned int bix, len; + unsigned int ntbuf = sc->sc_rb.rb_ntbuf; + + if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) + return; + + bix = sc->sc_rb.rb_tdhead; + + for (;;) { + IFQ_DEQUEUE(&ifp->if_snd, m); + if (m == 0) + break; + +#if NBPFILTER > 0 + /* + * If BPF is listening on this interface, let it see the + * packet before we commit it to the wire. + */ + if (ifp->if_bpf) + bpf_mtap(ifp->if_bpf, m); +#endif + + /* + * Copy the mbuf chain into the transmit buffer. + */ + len = qe_put(sc, bix, m); + + /* + * Initialize transmit registers and start transmission + */ + txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | + (len & QEC_XD_LENGTH); + bus_space_write_4(sc->sc_bustag, sc->sc_cr, QE_CRI_CTRL, + QE_CR_CTRL_TWAKEUP); + + if (++bix == QEC_XD_RING_MAXSIZE) + bix = 0; + + if (++sc->sc_rb.rb_td_nbusy == ntbuf) { + ifp->if_flags |= IFF_OACTIVE; + break; + } + } + + sc->sc_rb.rb_tdhead = bix; +} + +void +qestop(sc) + struct qe_softc *sc; +{ + bus_space_tag_t t = sc->sc_bustag; + bus_space_handle_t mr = sc->sc_mr; + bus_space_handle_t cr = sc->sc_cr; + int n; + +#if defined(SUN4U) || defined(__GNUC__) + (void)&t; +#endif + /* Stop the schwurst */ + bus_space_write_1(t, mr, QE_MRI_BIUCC, QE_MR_BIUCC_SWRST); + for (n = 200; n > 0; n--) { + if ((bus_space_read_1(t, mr, QE_MRI_BIUCC) & + QE_MR_BIUCC_SWRST) == 0) + break; + DELAY(20); + } + + /* then reset */ + bus_space_write_4(t, cr, QE_CRI_CTRL, QE_CR_CTRL_RESET); + for (n = 200; n > 0; n--) { + if ((bus_space_read_4(t, cr, QE_CRI_CTRL) & + QE_CR_CTRL_RESET) == 0) + break; + DELAY(20); + } +} + +/* + * Reset interface. + */ +void +qereset(sc) + struct qe_softc *sc; +{ + int s; + + s = splnet(); + qestop(sc); + qeinit(sc); + splx(s); +} + +void +qewatchdog(ifp) + struct ifnet *ifp; +{ + struct qe_softc *sc = ifp->if_softc; + + log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); + ifp->if_oerrors++; + + qereset(sc); +} + +/* + * Interrupt dispatch. + */ +int +qeintr(arg) + void *arg; +{ + struct qe_softc *sc = (struct qe_softc *)arg; + bus_space_tag_t t = sc->sc_bustag; + u_int32_t qecstat, qestat; + int r = 0; + +#if defined(SUN4U) || defined(__GNUC__) + (void)&t; +#endif + /* Read QEC status and channel status */ + qecstat = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); +#ifdef QEDEBUG + if (sc->sc_debug) { + printf("qe%d: intr: qecstat=%x\n", sc->sc_channel, qecstat); + } +#endif + + /* Filter out status for this channel */ + qecstat = qecstat >> (4 * sc->sc_channel); + if ((qecstat & 0xf) == 0) + return (r); + + qestat = bus_space_read_4(t, sc->sc_cr, QE_CRI_STAT); + +#ifdef QEDEBUG + if (sc->sc_debug) { + int i; + bus_space_tag_t t = sc->sc_bustag; + bus_space_handle_t mr = sc->sc_mr; + + printf("qe%d: intr: qestat=%b\n", sc->sc_channel, + qestat, QE_CR_STAT_BITS); + + printf("MACE registers:\n"); + for (i = 0 ; i < 32; i++) { + printf(" m[%d]=%x,", i, bus_space_read_1(t, mr, i)); + if (((i+1) & 7) == 0) + printf("\n"); + } + } +#endif + + if (qestat & QE_CR_STAT_ALLERRORS) { +#ifdef QEDEBUG + if (sc->sc_debug) + printf("qe%d: eint: qestat=%b\n", sc->sc_channel, + qestat, QE_CR_STAT_BITS); +#endif + r |= qe_eint(sc, qestat); + if (r == -1) + return (1); + } + + if (qestat & QE_CR_STAT_TXIRQ) + r |= qe_tint(sc); + + if (qestat & QE_CR_STAT_RXIRQ) + r |= qe_rint(sc); + + return (r); +} + +/* + * Transmit interrupt. + */ +int +qe_tint(sc) + struct qe_softc *sc; +{ + struct ifnet *ifp = &sc->sc_arpcom.ac_if; + unsigned int bix, txflags; + + bix = sc->sc_rb.rb_tdtail; + + for (;;) { + if (sc->sc_rb.rb_td_nbusy <= 0) + break; + + txflags = sc->sc_rb.rb_txd[bix].xd_flags; + + if (txflags & QEC_XD_OWN) + break; + + ifp->if_flags &= ~IFF_OACTIVE; + ifp->if_opackets++; + + if (++bix == QEC_XD_RING_MAXSIZE) + bix = 0; + + --sc->sc_rb.rb_td_nbusy; + } + + sc->sc_rb.rb_tdtail = bix; + + qestart(ifp); + + if (sc->sc_rb.rb_td_nbusy == 0) + ifp->if_timer = 0; + + return (1); +} + +/* + * Receive interrupt. + */ +int +qe_rint(sc) + struct qe_softc *sc; +{ + struct qec_xd *xd = sc->sc_rb.rb_rxd; + unsigned int bix, len; + unsigned int nrbuf = sc->sc_rb.rb_nrbuf; +#ifdef QEDEBUG + int npackets = 0; +#endif + + bix = sc->sc_rb.rb_rdtail; + + /* + * Process all buffers with valid data. + */ + for (;;) { + len = xd[bix].xd_flags; + if (len & QEC_XD_OWN) + break; + +#ifdef QEDEBUG + npackets++; +#endif + + len &= QEC_XD_LENGTH; + len -= 4; + qe_read(sc, bix, len); + + /* ... */ + xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = + QEC_XD_OWN | (QE_PKT_BUF_SZ & QEC_XD_LENGTH); + + if (++bix == QEC_XD_RING_MAXSIZE) + bix = 0; + } +#ifdef QEDEBUG + if (npackets == 0 && sc->sc_debug) + printf("%s: rint: no packets; rb index %d; status 0x%x\n", + sc->sc_dev.dv_xname, bix, len); +#endif + + sc->sc_rb.rb_rdtail = bix; + + return (1); +} + +/* + * Error interrupt. + */ +int +qe_eint(sc, why) + struct qe_softc *sc; + u_int32_t why; +{ + struct ifnet *ifp = &sc->sc_arpcom.ac_if; + int r = 0, rst = 0; + + if (why & QE_CR_STAT_EDEFER) { + printf("%s: excessive tx defers.\n", sc->sc_dev.dv_xname); + r |= 1; + ifp->if_oerrors++; + } + + if (why & QE_CR_STAT_CLOSS) { + printf("%s: no carrier, link down?\n", sc->sc_dev.dv_xname); + ifp->if_oerrors++; + r |= 1; + } + + if (why & QE_CR_STAT_ERETRIES) { + printf("%s: excessive tx retries\n", sc->sc_dev.dv_xname); + ifp->if_oerrors++; + r |= 1; + rst = 1; + } + + + if (why & QE_CR_STAT_LCOLL) { + printf("%s: late tx transmission\n", sc->sc_dev.dv_xname); + ifp->if_oerrors++; + r |= 1; + rst = 1; + } + + if (why & QE_CR_STAT_FUFLOW) { + printf("%s: tx fifo underflow\n", sc->sc_dev.dv_xname); + ifp->if_oerrors++; + r |= 1; + rst = 1; + } + + if (why & QE_CR_STAT_JERROR) { + printf("%s: jabber seen\n", sc->sc_dev.dv_xname); + r |= 1; + } + + if (why & QE_CR_STAT_BERROR) { + printf("%s: babble seen\n", sc->sc_dev.dv_xname); + r |= 1; + } + + if (why & QE_CR_STAT_TCCOFLOW) { + ifp->if_collisions += 256; + ifp->if_oerrors += 256; + r |= 1; + } + + if (why & QE_CR_STAT_TXDERROR) { + printf("%s: tx descriptor is bad\n", sc->sc_dev.dv_xname); + rst = 1; + r |= 1; + } + + if (why & QE_CR_STAT_TXLERR) { + printf("%s: tx late error\n", sc->sc_dev.dv_xname); + ifp->if_oerrors++; + rst = 1; + r |= 1; + } + + if (why & QE_CR_STAT_TXPERR) { + printf("%s: tx dma parity error\n", sc->sc_dev.dv_xname); + ifp->if_oerrors++; + rst = 1; + r |= 1; + } + + if (why & QE_CR_STAT_TXSERR) { + printf("%s: tx dma sbus error ack\n", sc->sc_dev.dv_xname); + ifp->if_oerrors++; + rst = 1; + r |= 1; + } + + if (why & QE_CR_STAT_RCCOFLOW) { + ifp->if_collisions += 256; + ifp->if_ierrors += 256; + r |= 1; + } + + if (why & QE_CR_STAT_RUOFLOW) { + ifp->if_ierrors += 256; + r |= 1; + } + + if (why & QE_CR_STAT_MCOFLOW) { + ifp->if_ierrors += 256; + r |= 1; + } + + if (why & QE_CR_STAT_RXFOFLOW) { + printf("%s: rx fifo overflow\n", sc->sc_dev.dv_xname); + ifp->if_ierrors++; + r |= 1; + } + + if (why & QE_CR_STAT_RLCOLL) { + printf("%s: rx late collision\n", sc->sc_dev.dv_xname); + ifp->if_ierrors++; + ifp->if_collisions++; + r |= 1; + } + + if (why & QE_CR_STAT_FCOFLOW) { + ifp->if_ierrors += 256; + r |= 1; + } + + if (why & QE_CR_STAT_CECOFLOW) { + ifp->if_ierrors += 256; + r |= 1; + } + + if (why & QE_CR_STAT_RXDROP) { + printf("%s: rx packet dropped\n", sc->sc_dev.dv_xname); + ifp->if_ierrors++; + r |= 1; + } + + if (why & QE_CR_STAT_RXSMALL) { + printf("%s: rx buffer too small\n", sc->sc_dev.dv_xname); + ifp->if_ierrors++; + r |= 1; + rst = 1; + } + + if (why & QE_CR_STAT_RXLERR) { + printf("%s: rx late error\n", sc->sc_dev.dv_xname); + ifp->if_ierrors++; + r |= 1; + rst = 1; + } + + if (why & QE_CR_STAT_RXPERR) { + printf("%s: rx dma parity error\n", sc->sc_dev.dv_xname); + ifp->if_ierrors++; + r |= 1; + rst = 1; + } + + if (why & QE_CR_STAT_RXSERR) { + printf("%s: rx dma sbus error ack\n", sc->sc_dev.dv_xname); + ifp->if_ierrors++; + r |= 1; + rst = 1; + } + + if (r == 0) + printf("%s: unexpected interrupt error: %08x\n", + sc->sc_dev.dv_xname, why); + + if (rst) { + printf("%s: resetting...\n", sc->sc_dev.dv_xname); + qereset(sc); + return (-1); + } + + return (r); +} + +int +qeioctl(ifp, cmd, data) + struct ifnet *ifp; + u_long cmd; + caddr_t data; +{ + struct qe_softc *sc = ifp->if_softc; + struct ifaddr *ifa = (struct ifaddr *)data; + struct ifreq *ifr = (struct ifreq *)data; + int s, error = 0; + + s = splnet(); + + switch (cmd) { + case SIOCSIFADDR: + ifp->if_flags |= IFF_UP; + switch (ifa->ifa_addr->sa_family) { +#ifdef INET + case AF_INET: + qeinit(sc); + arp_ifinit(&sc->sc_arpcom, ifa); + break; +#endif /* INET */ +#ifdef NS + case AF_NS: + { + struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; + + if (ns_nullhost(*ina)) + ina->x_host = + *(union ns_host *)LLADDR(ifp->if_sadl); + else + bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), + sizeof(sc->sc_enaddr)); + /* Set new address. */ + qeinit(sc); + break; + } +#endif /* NS */ + default: + qeinit(sc); + break; + } + break; + + case SIOCSIFFLAGS: + if ((ifp->if_flags & IFF_UP) == 0 && + (ifp->if_flags & IFF_RUNNING) != 0) { + /* + * If interface is marked down and it is running, then + * stop it. + */ + qestop(sc); + ifp->if_flags &= ~IFF_RUNNING; + + } else if ((ifp->if_flags & IFF_UP) != 0 && + (ifp->if_flags & IFF_RUNNING) == 0) { + /* + * If interface is marked up and it is stopped, then + * start it. + */ + qeinit(sc); + + } else { + /* + * Reset the interface to pick up changes in any other + * flags that affect hardware registers. + */ + qestop(sc); + qeinit(sc); + } +#ifdef QEDEBUG + sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; +#endif + break; + + case SIOCADDMULTI: + case SIOCDELMULTI: + error = (cmd == SIOCADDMULTI) ? + ether_addmulti(ifr, &sc->sc_arpcom): + ether_delmulti(ifr, &sc->sc_arpcom); + + if (error == ENETRESET) { + /* + * Multicast list has changed; set the hardware filter + * accordingly. + */ + qe_mcreset(sc); + error = 0; + } + break; + + case SIOCGIFMEDIA: + case SIOCSIFMEDIA: + error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd); + break; + + default: + error = EINVAL; + break; + } + + splx(s); + return (error); +} + + +void +qeinit(sc) + struct qe_softc *sc; +{ + struct ifnet *ifp = &sc->sc_arpcom.ac_if; + bus_space_tag_t t = sc->sc_bustag; + bus_space_handle_t cr = sc->sc_cr; + bus_space_handle_t mr = sc->sc_mr; + struct qec_softc *qec = sc->sc_qec; + u_int32_t qecaddr; + u_int8_t *ea; + int s; + +#if defined(SUN4U) || defined(__GNUC__) + (void)&t; +#endif + s = splnet(); + + qestop(sc); + + /* + * Allocate descriptor ring and buffers + */ + qec_meminit(&sc->sc_rb, QE_PKT_BUF_SZ); + + /* Channel registers: */ + bus_space_write_4(t, cr, QE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); + bus_space_write_4(t, cr, QE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); + + bus_space_write_4(t, cr, QE_CRI_RIMASK, 0); + bus_space_write_4(t, cr, QE_CRI_TIMASK, 0); + bus_space_write_4(t, cr, QE_CRI_QMASK, 0); + bus_space_write_4(t, cr, QE_CRI_MMASK, QE_CR_MMASK_RXCOLL); + bus_space_write_4(t, cr, QE_CRI_CCNT, 0); + bus_space_write_4(t, cr, QE_CRI_PIPG, 0); + + qecaddr = sc->sc_channel * qec->sc_msize; + bus_space_write_4(t, cr, QE_CRI_RXWBUF, qecaddr); + bus_space_write_4(t, cr, QE_CRI_RXRBUF, qecaddr); + bus_space_write_4(t, cr, QE_CRI_TXWBUF, qecaddr + qec->sc_rsize); + bus_space_write_4(t, cr, QE_CRI_TXRBUF, qecaddr + qec->sc_rsize); + + /* + * When switching from mace<->qec always guarantee an sbus + * turnaround (if last op was read, perform a dummy write, and + * vice versa). + */ + bus_space_read_4(t, cr, QE_CRI_QMASK); + + /* MACE registers: */ + bus_space_write_1(t, mr, QE_MRI_PHYCC, QE_MR_PHYCC_ASEL); + bus_space_write_1(t, mr, QE_MRI_XMTFC, QE_MR_XMTFC_APADXMT); + bus_space_write_1(t, mr, QE_MRI_RCVFC, 0); + + /* + * Mask MACE's receive interrupt, since we're being notified + * by the QEC after DMA completes. + */ + bus_space_write_1(t, mr, QE_MRI_IMR, + QE_MR_IMR_CERRM | QE_MR_IMR_RCVINTM); + + bus_space_write_1(t, mr, QE_MRI_BIUCC, + QE_MR_BIUCC_BSWAP | QE_MR_BIUCC_64TS); + + bus_space_write_1(t, mr, QE_MRI_FIFOFC, + QE_MR_FIFOCC_TXF16 | QE_MR_FIFOCC_RXF32 | + QE_MR_FIFOCC_RFWU | QE_MR_FIFOCC_TFWU); + + bus_space_write_1(t, mr, QE_MRI_PLSCC, QE_MR_PLSCC_TP); + + /* + * Station address + */ + ea = sc->sc_enaddr; + bus_space_write_1(t, mr, QE_MRI_IAC, + QE_MR_IAC_ADDRCHG | QE_MR_IAC_PHYADDR); + bus_space_write_multi_1(t, mr, QE_MRI_PADR, ea, 6); + + /* Apply media settings */ + qe_ifmedia_upd(ifp); + + /* + * Clear Logical address filter + */ + bus_space_write_1(t, mr, QE_MRI_IAC, + QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); + bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0, 8); + bus_space_write_1(t, mr, QE_MRI_IAC, 0); + + /* Clear missed packet count (register cleared on read) */ + (void)bus_space_read_1(t, mr, QE_MRI_MPC); + +#if 0 + /* test register: */ + bus_space_write_1(t, mr, QE_MRI_UTR, 0); +#endif + + /* Reset multicast filter */ + qe_mcreset(sc); + + ifp->if_flags |= IFF_RUNNING; + ifp->if_flags &= ~IFF_OACTIVE; + splx(s); +} + +/* + * Reset multicast filter. + */ +void +qe_mcreset(sc) + struct qe_softc *sc; +{ + struct arpcom *ac = &sc->sc_arpcom; + struct ifnet *ifp = &sc->sc_arpcom.ac_if; + bus_space_tag_t t = sc->sc_bustag; + bus_space_handle_t mr = sc->sc_mr; + struct ether_multi *enm; + struct ether_multistep step; + u_int32_t crc; + u_int16_t hash[4]; + u_int8_t octet, maccc, *ladrp = (u_int8_t *)&hash[0]; + int i, j; + +#if defined(SUN4U) || defined(__GNUC__) + (void)&t; +#endif + + /* We also enable transmitter & receiver here */ + maccc = QE_MR_MACCC_ENXMT | QE_MR_MACCC_ENRCV; + + if (ifp->if_flags & IFF_PROMISC) { + maccc |= QE_MR_MACCC_PROM; + bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); + return; + } + + if (ifp->if_flags & IFF_ALLMULTI) { + bus_space_write_1(t, mr, QE_MRI_IAC, + QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); + bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); + bus_space_write_1(t, mr, QE_MRI_IAC, 0); + bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); + return; + } + + hash[3] = hash[2] = hash[1] = hash[0] = 0; + + ETHER_FIRST_MULTI(step, ac, enm); + while (enm != NULL) { + if (bcmp(enm->enm_addrlo, enm->enm_addrhi, + ETHER_ADDR_LEN) != 0) { + /* + * We must listen to a range of multicast + * addresses. For now, just accept all + * multicasts, rather than trying to set only + * those filter bits needed to match the range. + * (At this time, the only use of address + * ranges is for IP multicast routing, for + * which the range is big enough to require + * all bits set.) + */ + bus_space_write_1(t, mr, QE_MRI_IAC, + QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); + bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); + bus_space_write_1(t, mr, QE_MRI_IAC, 0); + ifp->if_flags |= IFF_ALLMULTI; + break; + } + + crc = 0xffffffff; + + for (i = 0; i < ETHER_ADDR_LEN; i++) { + octet = enm->enm_addrlo[i]; + + for (j = 0; j < 8; j++) { + if ((crc & 1) ^ (octet & 1)) { + crc >>= 1; + crc ^= MC_POLY_LE; + } + else + crc >>= 1; + octet >>= 1; + } + } + + crc >>= 26; + hash[crc >> 4] |= 1 << (crc & 0xf); + ETHER_NEXT_MULTI(step, enm); + } + + bus_space_write_1(t, mr, QE_MRI_IAC, + QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); + bus_space_write_multi_1(t, mr, QE_MRI_LADRF, ladrp, 8); + bus_space_write_1(t, mr, QE_MRI_IAC, 0); + bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); +} + +/* + * Get current media settings. + */ +void +qe_ifmedia_sts(ifp, ifmr) + struct ifnet *ifp; + struct ifmediareq *ifmr; +{ + struct qe_softc *sc = ifp->if_softc; + u_int8_t phycc; + + ifmr->ifm_active = IFM_ETHER | IFM_10_T; + phycc = bus_space_read_1(sc->sc_bustag, sc->sc_mr, QE_MRI_PHYCC); + if ((phycc & QE_MR_PHYCC_DLNKTST) == 0) { + ifmr->ifm_status |= IFM_AVALID; + if (phycc & QE_MR_PHYCC_LNKFL) + ifmr->ifm_status &= ~IFM_ACTIVE; + else + ifmr->ifm_status |= IFM_ACTIVE; + } +} + +/* + * Set media options. + */ +int +qe_ifmedia_upd(ifp) + struct ifnet *ifp; +{ + struct qe_softc *sc = ifp->if_softc; + int media = sc->sc_ifmedia.ifm_media; + + if (IFM_TYPE(media) != IFM_ETHER) + return (EINVAL); + + if (IFM_SUBTYPE(media) != IFM_10_T) + return (EINVAL); + + return (0); +} diff --git a/sys/dev/sbus/qec.c b/sys/dev/sbus/qec.c new file mode 100644 index 00000000000..e2d4a8a10ba --- /dev/null +++ b/sys/dev/sbus/qec.c @@ -0,0 +1,426 @@ +/* $OpenBSD: qec.c,v 1.1 2001/08/20 22:09:27 jason Exp $ */ +/* $NetBSD: qec.c,v 1.12 2000/12/04 20:12:55 fvdl Exp $ */ + +/*- + * Copyright (c) 1998 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Paul Kranenburg. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <sys/types.h> +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/kernel.h> +#include <sys/errno.h> +#include <sys/device.h> +#include <sys/malloc.h> + +#include <machine/bus.h> +#include <machine/intr.h> +#include <machine/autoconf.h> + +#include <dev/sbus/sbusvar.h> +#include <dev/sbus/qecreg.h> +#include <dev/sbus/qecvar.h> + +static int qecprint __P((void *, const char *)); +static int qecmatch __P((struct device *, void *, void *)); +static void qecattach __P((struct device *, struct device *, void *)); +void qec_init __P((struct qec_softc *)); + +static int qec_bus_map __P(( + bus_space_tag_t, + bus_type_t, /*slot*/ + bus_addr_t, /*offset*/ + bus_size_t, /*size*/ + int, /*flags*/ + vaddr_t, /*preferred virtual address */ + bus_space_handle_t *)); +static void *qec_intr_establish __P(( + bus_space_tag_t, + int, /*bus interrupt priority*/ + int, /*`device class' interrupt level*/ + int, /*flags*/ + int (*) __P((void *)), /*handler*/ + void *)); /*arg*/ + +struct cfattach qec_ca = { + sizeof(struct qec_softc), qecmatch, qecattach +}; + +struct cfdriver qec_cd = { + NULL, "qec", DV_DULL +}; + +int +qecprint(aux, busname) + void *aux; + const char *busname; +{ + struct sbus_attach_args *sa = aux; + bus_space_tag_t t = sa->sa_bustag; + struct qec_softc *sc = t->cookie; + + sa->sa_bustag = sc->sc_bustag; /* XXX */ + sbus_print(aux, busname); /* XXX */ + sa->sa_bustag = t; /* XXX */ + return (UNCONF); +} + +int +qecmatch(parent, vcf, aux) + struct device *parent; + void *vcf; + void *aux; +{ + struct cfdata *cf = vcf; + struct sbus_attach_args *sa = aux; + + return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); +} + +/* + * Attach all the sub-devices we can find + */ +void +qecattach(parent, self, aux) + struct device *parent, *self; + void *aux; +{ + struct sbus_attach_args *sa = aux; + struct qec_softc *sc = (void *)self; + int node; + int sbusburst; + bus_space_tag_t sbt; + bus_space_handle_t bh; + struct bootpath *bp; + int error; + + sc->sc_bustag = sa->sa_bustag; + sc->sc_dmatag = sa->sa_dmatag; + node = sa->sa_node; + + if (sa->sa_nreg < 2) { + printf("%s: only %d register sets\n", + self->dv_xname, sa->sa_nreg); + return; + } + + if (sbus_bus_map(sa->sa_bustag, + sa->sa_reg[0].sbr_slot, + sa->sa_reg[0].sbr_offset, + sa->sa_reg[0].sbr_size, + BUS_SPACE_MAP_LINEAR, 0, &sc->sc_regs) != 0) { + printf("%s: attach: cannot map registers\n", self->dv_xname); + return; + } + + /* + * This device's "register space 1" is just a buffer where the + * Lance ring-buffers can be stored. Note the buffer's location + * and size, so the child driver can pick them up. + */ + if (sbus_bus_map(sa->sa_bustag, + sa->sa_reg[1].sbr_slot, + sa->sa_reg[1].sbr_offset, + sa->sa_reg[1].sbr_size, + BUS_SPACE_MAP_LINEAR, 0, &bh) != 0) { + printf("%s: attach: cannot map registers\n", self->dv_xname); + return; + } + sc->sc_buffer = (caddr_t)(u_long)bh; + sc->sc_bufsiz = (bus_size_t)sa->sa_reg[1].sbr_size; + + /* Get number of on-board channels */ + sc->sc_nchannels = getpropint(node, "#channels", -1); + if (sc->sc_nchannels == -1) { + printf(": no channels\n"); + return; + } + + /* + * Get transfer burst size from PROM + */ + sbusburst = ((struct sbus_softc *)parent)->sc_burst; + if (sbusburst == 0) + sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ + + sc->sc_burst = getpropint(node, "burst-sizes", -1); + if (sc->sc_burst == -1) + /* take SBus burst sizes */ + sc->sc_burst = sbusburst; + + /* Clamp at parent's burst sizes */ + sc->sc_burst &= sbusburst; + + sbus_establish(&sc->sc_sd, &sc->sc_dev); + + /* + * Collect address translations from the OBP. + */ + error = getprop(node, "ranges", sizeof(struct sbus_range), + &sc->sc_nrange, (void **)&sc->sc_range); + switch (error) { + case 0: + break; + case ENOENT: + default: + panic("%s: error getting ranges property", self->dv_xname); + } + + /* Allocate a bus tag */ + sbt = (bus_space_tag_t) + malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); + if (sbt == NULL) { + printf("%s: attach: out of memory\n", self->dv_xname); + return; + } + + bzero(sbt, sizeof *sbt); + sbt->cookie = sc; + sbt->parent = sc->sc_bustag; + sbt->sparc_bus_map = qec_bus_map; + sbt->sparc_intr_establish = qec_intr_establish; + + /* + * Save interrupt information for use in our qec_intr_establish() + * function below. Apparently, the intr level for the quad + * ethernet board (qe) is stored in the QEC node rather then + * separately in each of the QE nodes. + * + * XXX - qe.c should call bus_intr_establish() with `level = 0'.. + * XXX - maybe we should have our own attach args for all that. + */ + sc->sc_intr = sa->sa_intr; + + printf(": %dK memory\n", sc->sc_bufsiz / 1024); + + qec_init(sc); + + bp = sa->sa_bp; + if (bp != NULL && strcmp(bp->name, qec_cd.cd_name) == 0) + bp = bp + 1; + else + bp = NULL; + + /* search through children */ + for (node = firstchild(node); node; node = nextsibling(node)) { + struct sbus_attach_args sa; + + sbus_setup_attach_args((struct sbus_softc *)parent, + sbt, sc->sc_dmatag, node, &sa); + sa.sa_bp = bp; + (void)config_found(&sc->sc_dev, (void *)&sa, qecprint); + sbus_destroy_attach_args(&sa); + } +} + +int +qec_bus_map(t, btype, offset, size, flags, vaddr, hp) + bus_space_tag_t t; + bus_type_t btype; + bus_addr_t offset; + bus_size_t size; + int flags; + vaddr_t vaddr; + bus_space_handle_t *hp; +{ + struct qec_softc *sc = t->cookie; + int slot = btype; + int i; + + for (i = 0; i < sc->sc_nrange; i++) { + bus_addr_t paddr; + bus_type_t iospace; + + if (sc->sc_range[i].cspace != slot) + continue; + + /* We've found the connection to the parent bus */ + paddr = sc->sc_range[i].poffset + offset; + iospace = sc->sc_range[i].pspace; + return (bus_space_map2(sc->sc_bustag, iospace, paddr, + size, flags, vaddr, hp)); + } + + return (EINVAL); +} + +void * +qec_intr_establish(t, pri, level, flags, handler, arg) + bus_space_tag_t t; + int pri; + int level; + int flags; + int (*handler) __P((void *)); + void *arg; +{ + struct qec_softc *sc = t->cookie; + + if (pri == 0) { + /* + * qe.c calls bus_intr_establish() with `pri == 0' + * XXX - see also comment in qec_attach(). + */ + if (sc->sc_intr == NULL) { + printf("%s: warning: no interrupts\n", + sc->sc_dev.dv_xname); + return (NULL); + } + pri = sc->sc_intr->sbi_pri; + } + + return (bus_intr_establish(t->parent, pri, level, flags, handler, arg)); +} + +void +qec_init(sc) + struct qec_softc *sc; +{ + bus_space_tag_t t = sc->sc_bustag; + bus_space_handle_t qr = sc->sc_regs; + u_int32_t v, burst = 0, psize; + int i; + + /* First, reset the controller */ + bus_space_write_4(t, qr, QEC_QRI_CTRL, QEC_CTRL_RESET); + for (i = 0; i < 1000; i++) { + DELAY(100); + v = bus_space_read_4(t, qr, QEC_QRI_CTRL); + if ((v & QEC_CTRL_RESET) == 0) + break; + } + + /* + * Cut available buffer size into receive and transmit buffers. + * XXX - should probably be done in be & qe driver... + */ + v = sc->sc_msize = sc->sc_bufsiz / sc->sc_nchannels; + bus_space_write_4(t, qr, QEC_QRI_MSIZE, v); + + v = sc->sc_rsize = sc->sc_bufsiz / (sc->sc_nchannels * 2); + bus_space_write_4(t, qr, QEC_QRI_RSIZE, v); + bus_space_write_4(t, qr, QEC_QRI_TSIZE, v); + + psize = sc->sc_nchannels == 1 ? QEC_PSIZE_2048 : 0; + bus_space_write_4(t, qr, QEC_QRI_PSIZE, psize); + + if (sc->sc_burst & SBUS_BURST_64) + burst = QEC_CTRL_B64; + else if (sc->sc_burst & SBUS_BURST_32) + burst = QEC_CTRL_B32; + else + burst = QEC_CTRL_B16; + + v = bus_space_read_4(t, qr, QEC_QRI_CTRL); + v = (v & QEC_CTRL_MODEMASK) | burst; + bus_space_write_4(t, qr, QEC_QRI_CTRL, v); +} + +/* + * Common routine to initialize the QEC packet ring buffer. + * Called from be & qe drivers. + */ +void +qec_meminit(qr, pktbufsz) + struct qec_ring *qr; + unsigned int pktbufsz; +{ + bus_addr_t txbufdma, rxbufdma; + bus_addr_t dma; + caddr_t p; + unsigned int ntbuf, nrbuf, i; + + p = qr->rb_membase; + dma = qr->rb_dmabase; + + ntbuf = qr->rb_ntbuf; + nrbuf = qr->rb_nrbuf; + + /* + * Allocate transmit descriptors + */ + qr->rb_txd = (struct qec_xd *)p; + qr->rb_txddma = dma; + p += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); + dma += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); + + /* + * Allocate receive descriptors + */ + qr->rb_rxd = (struct qec_xd *)p; + qr->rb_rxddma = dma; + p += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); + dma += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); + + + /* + * Allocate transmit buffers + */ + qr->rb_txbuf = p; + txbufdma = dma; + p += ntbuf * pktbufsz; + dma += ntbuf * pktbufsz; + + /* + * Allocate receive buffers + */ + qr->rb_rxbuf = p; + rxbufdma = dma; + p += nrbuf * pktbufsz; + dma += nrbuf * pktbufsz; + + /* + * Initialize transmit buffer descriptors + */ + for (i = 0; i < QEC_XD_RING_MAXSIZE; i++) { + qr->rb_txd[i].xd_addr = (u_int32_t) + (txbufdma + (i % ntbuf) * pktbufsz); + qr->rb_txd[i].xd_flags = 0; + } + + /* + * Initialize receive buffer descriptors + */ + for (i = 0; i < QEC_XD_RING_MAXSIZE; i++) { + qr->rb_rxd[i].xd_addr = (u_int32_t) + (rxbufdma + (i % nrbuf) * pktbufsz); + qr->rb_rxd[i].xd_flags = (i < nrbuf) + ? QEC_XD_OWN | (pktbufsz & QEC_XD_LENGTH) + : 0; + } + + qr->rb_tdhead = qr->rb_tdtail = 0; + qr->rb_td_nbusy = 0; + qr->rb_rdtail = 0; +} diff --git a/sys/dev/sbus/qecreg.h b/sys/dev/sbus/qecreg.h new file mode 100644 index 00000000000..e97fd542f5f --- /dev/null +++ b/sys/dev/sbus/qecreg.h @@ -0,0 +1,121 @@ +/* $OpenBSD: qecreg.h,v 1.1 2001/08/20 22:09:27 jason Exp $ */ +/* $NetBSD: qecreg.h,v 1.2 1999/01/16 12:46:08 pk Exp $ */ + +/*- + * Copyright (c) 1998 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Paul Kranenburg. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the authors may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * QEC registers layout + *- +struct qecregs { + u_int32_t qec_ctrl; // control + u_int32_t qec_stat; // status + u_int32_t qec_psize; // packet size + u_int32_t qec_msize; // local-mem size (64K) + u_int32_t qec_rsize; // receive partition size + u_int32_t qec_tsize; // transmit partition size +}; + */ +#define QEC_QRI_CTRL (0*4) +#define QEC_QRI_STAT (1*4) +#define QEC_QRI_PSIZE (2*4) +#define QEC_QRI_MSIZE (3*4) +#define QEC_QRI_RSIZE (4*4) +#define QEC_QRI_TSIZE (5*4) + +#define QEC_CTRL_MODEMASK 0xf0000000 /* QEC mode: */ +#define QEC_CTRL_MMODE 0x40000000 /* MACE qec mode */ +#define QEC_CTRL_BMODE 0x10000000 /* BE qec mode */ +#define QEC_CTRL_EPAR 0x00000020 /* enable parity */ +#define QEC_CTRL_ACNTRL 0x00000018 /* sbus arbitration control */ +#define QEC_CTRL_B64 0x00000004 /* 64 byte dvma bursts */ +#define QEC_CTRL_B32 0x00000002 /* 32 byte dvma bursts */ +#define QEC_CTRL_B16 0x00000000 /* 16 byte dvma bursts */ +#define QEC_CTRL_RESET 0x00000001 /* reset the qec */ + +#define QEC_STAT_TX 0x00000008 /* bigmac transmit irq */ +#define QEC_STAT_RX 0x00000004 /* bigmac receive irq */ +#define QEC_STAT_BM 0x00000002 /* bigmac qec irq */ +#define QEC_STAT_ER 0x00000001 /* bigmac error irq */ + +#define QEC_PSIZE_2048 0x00 /* 2k packet size */ +#define QEC_PSIZE_4096 0x01 /* 4k packet size */ +#define QEC_PSIZE_6144 0x10 /* 6k packet size */ +#define QEC_PSIZE_8192 0x11 /* 8k packet size */ + + + +/* + * Transmit & receive buffer descriptor. + */ +struct qec_xd { + volatile u_int32_t xd_flags; /* see below */ + volatile u_int32_t xd_addr; /* Buffer address (DMA) */ +}; +#define QEC_XD_OWN 0x80000000 /* ownership: 1=hw, 0=sw */ +#define QEC_XD_SOP 0x40000000 /* start of packet marker (xmit) */ +#define QEC_XD_EOP 0x20000000 /* end of packet marker (xmit) */ +#define QEC_XD_UPDATE 0x10000000 /* being updated? */ +#define QEC_XD_LENGTH 0x00001fff /* packet length mask */ +/* Descriptor ring size is fixed */ +#define QEC_XD_RING_MAXSIZE 256 /* maximum ring size */ diff --git a/sys/dev/sbus/qecvar.h b/sys/dev/sbus/qecvar.h new file mode 100644 index 00000000000..1e6f5f5ada4 --- /dev/null +++ b/sys/dev/sbus/qecvar.h @@ -0,0 +1,78 @@ +/* $OpenBSD: qecvar.h,v 1.1 2001/08/20 22:09:27 jason Exp $ */ +/* $NetBSD: qecvar.h,v 1.4 1999/01/17 20:47:50 pk Exp $ */ + +/*- + * Copyright (c) 1998 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Paul Kranenburg. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +struct qec_softc { + struct device sc_dev; /* us as a device */ + struct sbusdev sc_sd; /* sbus device */ + bus_space_tag_t sc_bustag; /* bus & dma tags */ + bus_dma_tag_t sc_dmatag; + struct sbus_range *sc_range; /* PROM ranges */ + int sc_nrange; /* */ + struct sbus_intr *sc_intr; /* interrupt info */ + + bus_space_handle_t sc_regs; /* QEC registers */ + int sc_nchannels; /* # of channels on board */ + int sc_burst; /* DVMA burst size in effect */ + caddr_t sc_buffer; /* VA of the buffer we provide */ + int sc_bufsiz; /* Size of buffer */ + + u_int sc_msize; /* QEC buffer offset per channel */ + u_int sc_rsize; /* QEC buffer size for receive */ +}; + +struct qec_ring { + /* Ring Descriptors */ + caddr_t rb_membase; /* Packet buffer: CPU address */ + bus_addr_t rb_dmabase; /* Packet buffer: DMA address */ + struct qec_xd *rb_txd; /* Transmit descriptors */ + bus_addr_t rb_txddma; /* DMA address of same */ + struct qec_xd *rb_rxd; /* Receive descriptors */ + bus_addr_t rb_rxddma; /* DMA address of same */ + caddr_t rb_txbuf; /* Transmit buffers */ + caddr_t rb_rxbuf; /* Receive buffers */ + int rb_ntbuf; /* # of transmit buffers */ + int rb_nrbuf; /* # of receive buffers */ + + /* Ring Descriptor state */ + int rb_tdhead, rb_tdtail; + int rb_rdtail; + int rb_td_nbusy; +}; + +void qec_meminit __P((struct qec_ring *, unsigned int)); diff --git a/sys/dev/sbus/qereg.h b/sys/dev/sbus/qereg.h new file mode 100644 index 00000000000..b4d39fe0706 --- /dev/null +++ b/sys/dev/sbus/qereg.h @@ -0,0 +1,389 @@ +/* $OpenBSD: qereg.h,v 1.1 2001/08/20 22:09:27 jason Exp $ */ +/* $NetBSD: qereg.h,v 1.3 2000/07/24 04:28:51 mycroft Exp $ */ + +/*- + * Copyright (c) 1999 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Paul Kranenburg. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Copyright (c) 1998 Jason L. Wright. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the authors may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * QE Channel registers + */ +#if 0 +struct qe_cregs { + u_int32_t ctrl; /* control */ + u_int32_t stat; /* status */ + u_int32_t rxds; /* rx descriptor ring ptr */ + u_int32_t txds; /* tx descriptor ring ptr */ + u_int32_t rimask; /* rx interrupt mask */ + u_int32_t timask; /* tx interrupt mask */ + u_int32_t qmask; /* qec error interrupt mask */ + u_int32_t mmask; /* mace error interrupt mask */ + u_int32_t rxwbufptr; /* local memory rx write ptr */ + u_int32_t rxrbufptr; /* local memory rx read ptr */ + u_int32_t txwbufptr; /* local memory tx write ptr */ + u_int32_t txrbufptr; /* local memory tx read ptr */ + u_int32_t ccnt; /* collision counter */ + u_int32_t pipg; /* inter-frame gap */ +}; +#endif +/* register indices: */ +#define QE_CRI_CTRL (0*4) +#define QE_CRI_STAT (1*4) +#define QE_CRI_RXDS (2*4) +#define QE_CRI_TXDS (3*4) +#define QE_CRI_RIMASK (4*4) +#define QE_CRI_TIMASK (5*4) +#define QE_CRI_QMASK (6*4) +#define QE_CRI_MMASK (7*4) +#define QE_CRI_RXWBUF (8*4) +#define QE_CRI_RXRBUF (9*4) +#define QE_CRI_TXWBUF (10*4) +#define QE_CRI_TXRBUF (11*4) +#define QE_CRI_CCNT (12*4) +#define QE_CRI_PIPG (13*4) + +/* qe_cregs.ctrl: control. */ +#define QE_CR_CTRL_RXOFF 0x00000004 /* disable receiver */ +#define QE_CR_CTRL_RESET 0x00000002 /* reset this channel */ +#define QE_CR_CTRL_TWAKEUP 0x00000001 /* tx dma wakeup */ + +/* qe_cregs.stat: status. */ +#define QE_CR_STAT_EDEFER 0x10000000 /* excessive defers */ +#define QE_CR_STAT_CLOSS 0x08000000 /* loss of carrier */ +#define QE_CR_STAT_ERETRIES 0x04000000 /* >16 retries */ +#define QE_CR_STAT_LCOLL 0x02000000 /* late tx collision */ +#define QE_CR_STAT_FUFLOW 0x01000000 /* fifo underflow */ +#define QE_CR_STAT_JERROR 0x00800000 /* jabber error */ +#define QE_CR_STAT_BERROR 0x00400000 /* babble error */ +#define QE_CR_STAT_TXIRQ 0x00200000 /* tx interrupt */ +#define QE_CR_STAT_TCCOFLOW 0x00100000 /* tx collision cntr expired */ +#define QE_CR_STAT_TXDERROR 0x00080000 /* tx descriptor is bad */ +#define QE_CR_STAT_TXLERR 0x00040000 /* tx late error */ +#define QE_CR_STAT_TXPERR 0x00020000 /* tx parity error */ +#define QE_CR_STAT_TXSERR 0x00010000 /* tx sbus error ack */ +#define QE_CR_STAT_RCCOFLOW 0x00001000 /* rx collision cntr expired */ +#define QE_CR_STAT_RUOFLOW 0x00000800 /* rx runt counter expired */ +#define QE_CR_STAT_MCOFLOW 0x00000400 /* rx missed counter expired */ +#define QE_CR_STAT_RXFOFLOW 0x00000200 /* rx fifo over flow */ +#define QE_CR_STAT_RLCOLL 0x00000100 /* rx late collision */ +#define QE_CR_STAT_FCOFLOW 0x00000080 /* rx frame counter expired */ +#define QE_CR_STAT_CECOFLOW 0x00000040 /* rx crc error cntr expired */ +#define QE_CR_STAT_RXIRQ 0x00000020 /* rx interrupt */ +#define QE_CR_STAT_RXDROP 0x00000010 /* rx dropped packet */ +#define QE_CR_STAT_RXSMALL 0x00000008 /* rx buffer too small */ +#define QE_CR_STAT_RXLERR 0x00000004 /* rx late error */ +#define QE_CR_STAT_RXPERR 0x00000002 /* rx parity error */ +#define QE_CR_STAT_RXSERR 0x00000001 /* rx sbus error ack */ +#define QE_CR_STAT_BITS "\177\020" \ + "b\0RXSERR\0b\1RXPERR\0b\2RXLERR\0" \ + "b\3RXSMALL\0b\4RXDROP\0b\5RXIRQ\0" \ + "b\6CECOFLOW\0b\7FCOFLOW\0b\10RLCOLL\0" \ + "b\11RXFOFLOW\0b\12MCOFLOW\0b\13RUOFLOW\0" \ + "b\14RCCOFLOW\0b\20TXSERR\0b\21TXPERR\0" \ + "b\22TXLERR\0b\23TXDERROR\0b\24TCCOFLOW\0" \ + "b\25TXIRQ\0b\26BERROR\0b\27JERROR\0" \ + "b\30FUFLOW\0b\31LCOLL\0b\32ERETRIES\0" \ + "b\33CLOSS\0b\32EDEFER\0\0" + +/* + * Errors: all status bits except for TX/RX IRQ + */ +#define QE_CR_STAT_ALLERRORS \ + ( QE_CR_STAT_EDEFER | QE_CR_STAT_CLOSS | QE_CR_STAT_ERETRIES \ + | QE_CR_STAT_LCOLL | QE_CR_STAT_FUFLOW | QE_CR_STAT_JERROR \ + | QE_CR_STAT_BERROR | QE_CR_STAT_TCCOFLOW | QE_CR_STAT_TXDERROR \ + | QE_CR_STAT_TXLERR | QE_CR_STAT_TXPERR | QE_CR_STAT_TXSERR \ + | QE_CR_STAT_RCCOFLOW | QE_CR_STAT_RUOFLOW | QE_CR_STAT_MCOFLOW \ + | QE_CR_STAT_RXFOFLOW | QE_CR_STAT_RLCOLL | QE_CR_STAT_FCOFLOW \ + | QE_CR_STAT_CECOFLOW | QE_CR_STAT_RXDROP | QE_CR_STAT_RXSMALL \ + | QE_CR_STAT_RXLERR | QE_CR_STAT_RXPERR | QE_CR_STAT_RXSERR) + +/* qe_cregs.qmask: qec error interrupt mask. */ +#define QE_CR_QMASK_COFLOW 0x00100000 /* collision cntr overflow */ +#define QE_CR_QMASK_TXDERROR 0x00080000 /* tx descriptor error */ +#define QE_CR_QMASK_TXLERR 0x00040000 /* tx late error */ +#define QE_CR_QMASK_TXPERR 0x00020000 /* tx parity error */ +#define QE_CR_QMASK_TXSERR 0x00010000 /* tx sbus error ack */ +#define QE_CR_QMASK_RXDROP 0x00000010 /* rx packet dropped */ +#define QE_CR_QMASK_RXSMALL 0x00000008 /* rx buffer too small */ +#define QE_CR_QMASK_RXLERR 0x00000004 /* rx late error */ +#define QE_CR_QMASK_RXPERR 0x00000002 /* rx parity error */ +#define QE_CR_QMASK_RXSERR 0x00000001 /* rx sbus error ack */ + +/* qe_cregs.mmask: MACE error interrupt mask. */ +#define QE_CR_MMASK_EDEFER 0x10000000 /* excess defer */ +#define QE_CR_MMASK_CLOSS 0x08000000 /* carrier loss */ +#define QE_CR_MMASK_ERETRY 0x04000000 /* excess retry */ +#define QE_CR_MMASK_LCOLL 0x02000000 /* late collision error */ +#define QE_CR_MMASK_UFLOW 0x01000000 /* underflow */ +#define QE_CR_MMASK_JABBER 0x00800000 /* jabber error */ +#define QE_CR_MMASK_BABBLE 0x00400000 /* babble error */ +#define QE_CR_MMASK_OFLOW 0x00000800 /* overflow */ +#define QE_CR_MMASK_RXCOLL 0x00000400 /* rx coll-cntr overflow */ +#define QE_CR_MMASK_RPKT 0x00000200 /* runt pkt overflow */ +#define QE_CR_MMASK_MPKT 0x00000100 /* missed pkt overflow */ + +/* qe_cregs.pipg: inter-frame gap. */ +#define QE_CR_PIPG_TENAB 0x00000020 /* enable throttle */ +#define QE_CR_PIPG_MMODE 0x00000010 /* manual mode */ +#define QE_CR_PIPG_WMASK 0x0000000f /* sbus wait mask */ + +/* + * MACE registers + */ +#if 0 +struct qe_mregs { + u_int8_t rcvfifo; [0] /* receive fifo */ + u_int8_t xmtfifo; [1] /* transmit fifo */ + u_int8_t xmtfc; [2] /* transmit frame control */ + u_int8_t xmtfs; [3] /* transmit frame status */ + u_int8_t xmtrc; [4] /* tx retry count */ + u_int8_t rcvfc; [5] /* receive frame control */ + u_int8_t rcvfs; [6] /* receive frame status */ + u_int8_t fifofc; [7] /* fifo frame count */ + u_int8_t ir; [8] /* interrupt register */ + u_int8_t imr; [9] /* interrupt mask register */ + u_int8_t pr; [10] /* poll register */ + u_int8_t biucc; [11] /* biu config control */ + u_int8_t fifocc; [12] /* fifo config control */ + u_int8_t maccc; [13] /* mac config control */ + u_int8_t plscc; [14] /* pls config control */ + u_int8_t phycc; [15] /* phy config control */ + u_int8_t chipid1; [16] /* chipid, low byte */ + u_int8_t chipid2; [17] /* chipid, high byte */ + u_int8_t iac; [18] /* internal address config */ + u_int8_t _reserved0; [19] /* reserved */ + u_int8_t ladrf; [20] /* logical address filter */ + u_int8_t padr; [21] /* physical address */ + u_int8_t _reserved1; [22] /* reserved */ + u_int8_t _reserved2; [23] /* reserved */ + u_int8_t mpc; [24] /* missed packet count */ + u_int8_t _reserved3; [25] /* reserved */ + u_int8_t rntpc; [26] /* runt packet count */ + u_int8_t rcvcc; [27] /* receive collision count */ + u_int8_t _reserved4; [28] /* reserved */ + u_int8_t utr; [29] /* user test register */ + u_int8_t rtr1; [30] /* reserved test register 1 */ + u_int8_t rtr2; [31] /* reserved test register 2 */ +}; +#endif +/* register indices: */ +#define QE_MRI_RCVFIFO 0 /* receive fifo */ +#define QE_MRI_XMTFIFO 1 /* transmit fifo */ +#define QE_MRI_XMTFC 2 /* transmit frame control */ +#define QE_MRI_XMTFS 3 /* transmit frame status */ +#define QE_MRI_XMTRC 4 /* tx retry count */ +#define QE_MRI_RCVFC 5 /* receive frame control */ +#define QE_MRI_RCVFS 6 /* receive frame status */ +#define QE_MRI_FIFOFC 7 /* fifo frame count */ +#define QE_MRI_IR 8 /* interrupt register */ +#define QE_MRI_IMR 9 /* interrupt mask register */ +#define QE_MRI_PR 10 /* poll register */ +#define QE_MRI_BIUCC 11 /* biu config control */ +#define QE_MRI_FIFOCC 12 /* fifo config control */ +#define QE_MRI_MACCC 13 /* mac config control */ +#define QE_MRI_PLSCC 14 /* pls config control */ +#define QE_MRI_PHYCC 15 /* phy config control */ +#define QE_MRI_CHIPID1 16 /* chipid, low byte */ +#define QE_MRI_CHIPID2 17 /* chipid, high byte */ +#define QE_MRI_IAC 18 /* internal address config */ +#define QE_MRI_LADRF 20 /* logical address filter */ +#define QE_MRI_PADR 21 /* physical address */ +#define QE_MRI_MPC 24 /* missed packet count */ +#define QE_MRI_RNTPC 26 /* runt packet count */ +#define QE_MRI_RCVCC 27 /* receive collision count */ +#define QE_MRI_UTR 29 /* user test register */ +#define QE_MRI_RTR1 30 /* reserved test register 1 */ +#define QE_MRI_RTR2 31 /* reserved test register 2 */ + +/* qe_mregs.xmtfc: transmit frame control. */ +#define QE_MR_XMTFC_DRETRY 0x80 /* disable retries */ +#define QE_MR_XMTFC_DXMTFCS 0x08 /* disable tx fcs */ +#define QE_MR_XMTFC_APADXMT 0x01 /* enable auto padding */ + +/* qe_mregs.xmtfs: transmit frame status. */ +#define QE_MR_XMTFS_XMTSV 0x80 /* tx valid */ +#define QE_MR_XMTFS_UFLO 0x40 /* tx underflow */ +#define QE_MR_XMTFS_LCOL 0x20 /* tx late collision */ +#define QE_MR_XMTFS_MORE 0x10 /* tx > 1 retries */ +#define QE_MR_XMTFS_ONE 0x08 /* tx 1 retry */ +#define QE_MR_XMTFS_DEFER 0x04 /* tx pkt deferred */ +#define QE_MR_XMTFS_LCAR 0x02 /* tx carrier lost */ +#define QE_MR_XMTFS_RTRY 0x01 /* tx retry error */ + +/* qe_mregs.xmtrc: transmit retry count. */ +#define QE_MR_XMTRC_EXDEF 0x80 /* tx excess defers */ +#define QE_MR_XMTRC_XMTRC 0x0f /* tx retry count mask */ + +/* qe_mregs.rcvfc: receive frame control. */ +#define QE_MR_RCVFC_LLRCV 0x08 /* rx low latency */ +#define QE_MR_RCVFC_MR 0x04 /* rx addr match/reject */ +#define QE_MR_RCVFC_ASTRPRCV 0x01 /* rx auto strip */ + +/* qe_mregs.rcvfs: receive frame status. */ +#define QE_MR_RCVFS_OFLO 0x80 /* rx overflow */ +#define QE_MR_RCVFS_CLSN 0x40 /* rx late collision */ +#define QE_MR_RCVFS_FRAM 0x20 /* rx framing error */ +#define QE_MR_RCVFS_FCS 0x10 /* rx fcs error */ +#define QE_MR_RCVFS_RCVCNT 0x0f /* rx msg byte count mask */ + +/* qe_mregs.fifofc: fifo frame count. */ +#define QE_MR_FIFOFC_RCVFC 0xf0 /* rx fifo frame count */ +#define QE_MR_FIFOFC_XMTFC 0x0f /* tx fifo frame count */ + +/* qe_mregs.ir: interrupt register. */ +#define QE_MR_IR_JAB 0x80 /* jabber error */ +#define QE_MR_IR_BABL 0x40 /* babble error */ +#define QE_MR_IR_CERR 0x20 /* collision error */ +#define QE_MR_IR_RCVCCO 0x10 /* collision cnt overflow */ +#define QE_MR_IR_RNTPCO 0x08 /* runt pkt cnt overflow */ +#define QE_MR_IR_MPCO 0x04 /* miss pkt cnt overflow */ +#define QE_MR_IR_RCVINT 0x02 /* packet received */ +#define QE_MR_IR_XMTINT 0x01 /* packet transmitted */ + +/* qe_mregs.imr: interrupt mask register. */ +#define QE_MR_IMR_JABM 0x80 /* jabber errors */ +#define QE_MR_IMR_BABLM 0x40 /* babble errors */ +#define QE_MR_IMR_CERRM 0x20 /* collision errors */ +#define QE_MR_IMR_RCVCCOM 0x10 /* rx collision count oflow */ +#define QE_MR_IMR_RNTPCOM 0x08 /* runt pkt cnt ovrflw */ +#define QE_MR_IMR_MPCOM 0x04 /* miss pkt cnt ovrflw */ +#define QE_MR_IMR_RCVINTM 0x02 /* rx interrupts */ +#define QE_MR_IMR_XMTINTM 0x01 /* tx interrupts */ + +/* qe_mregs.pr: poll register. */ +#define QE_MR_PR_XMTSV 0x80 /* tx status is valid */ +#define QE_MR_PR_TDTREQ 0x40 /* tx data xfer request */ +#define QE_MR_PR_RDTREQ 0x20 /* rx data xfer request */ + +/* qe_mregs.biucc: biu config control. */ +#define QE_MR_BIUCC_BSWAP 0x40 /* byte swap */ +#define QE_MR_BIUCC_4TS 0x00 /* 4byte xmit start point */ +#define QE_MR_BIUCC_16TS 0x10 /* 16byte xmit start point */ +#define QE_MR_BIUCC_64TS 0x20 /* 64byte xmit start point */ +#define QE_MR_BIUCC_112TS 0x30 /* 112byte xmit start point */ +#define QE_MR_BIUCC_SWRST 0x01 /* sw-reset mace */ + +/* qe_mregs.fifocc: fifo config control. */ +#define QE_MR_FIFOCC_TXF8 0x00 /* tx fifo 8 write cycles */ +#define QE_MR_FIFOCC_TXF32 0x80 /* tx fifo 32 write cycles */ +#define QE_MR_FIFOCC_TXF16 0x40 /* tx fifo 16 write cycles */ +#define QE_MR_FIFOCC_RXF64 0x20 /* rx fifo 64 write cycles */ +#define QE_MR_FIFOCC_RXF32 0x10 /* rx fifo 32 write cycles */ +#define QE_MR_FIFOCC_RXF16 0x00 /* rx fifo 16 write cycles */ +#define QE_MR_FIFOCC_TFWU 0x08 /* tx fifo watermark update */ +#define QE_MR_FIFOCC_RFWU 0x04 /* rx fifo watermark update */ +#define QE_MR_FIFOCC_XMTBRST 0x02 /* tx burst enable */ +#define QE_MR_FIFOCC_RCVBRST 0x01 /* rx burst enable */ + +/* qe_mregs.maccc: mac config control. */ +#define QE_MR_MACCC_PROM 0x80 /* promiscuous mode enable */ +#define QE_MR_MACCC_DXMT2PD 0x40 /* tx 2part deferral enable */ +#define QE_MR_MACCC_EMBA 0x20 /* modified backoff enable */ +#define QE_MR_MACCC_DRCVPA 0x08 /* rx physical addr disable */ +#define QE_MR_MACCC_DRCVBC 0x04 /* rx broadcast disable */ +#define QE_MR_MACCC_ENXMT 0x02 /* enable transmitter */ +#define QE_MR_MACCC_ENRCV 0x01 /* enable receiver */ + +/* qe_mregs.plscc: pls config control. */ +#define QE_MR_PLSCC_XMTSEL 0x08 /* tx mode select */ +#define QE_MR_PLSCC_PORTMASK 0x06 /* port selection bits */ +#define QE_MR_PLSCC_GPSI 0x06 /* use gpsi connector */ +#define QE_MR_PLSCC_DAI 0x04 /* use dai connector */ +#define QE_MR_PLSCC_TP 0x02 /* use twistedpair connector */ +#define QE_MR_PLSCC_AUI 0x00 /* use aui connector */ +#define QE_MR_PLSCC_ENPLSIO 0x01 /* pls i/o enable */ + +/* qe_mregs.phycc: phy config control. */ +#define QE_MR_PHYCC_LNKFL 0x80 /* link fail */ +#define QE_MR_PHYCC_DLNKTST 0x40 /* disable link test logic */ +#define QE_MR_PHYCC_REVPOL 0x20 /* rx polarity */ +#define QE_MR_PHYCC_DAPC 0x10 /* autopolaritycorrect disab */ +#define QE_MR_PHYCC_LRT 0x08 /* select low threshold */ +#define QE_MR_PHYCC_ASEL 0x04 /* connector port auto-sel */ +#define QE_MR_PHYCC_RWAKE 0x02 /* remote wakeup */ +#define QE_MR_PHYCC_AWAKE 0x01 /* auto wakeup */ + +/* qe_mregs.iac: internal address config. */ +#define QE_MR_IAC_ADDRCHG 0x80 /* start address change */ +#define QE_MR_IAC_PHYADDR 0x04 /* physical address reset */ +#define QE_MR_IAC_LOGADDR 0x02 /* logical address reset */ + +/* qe_mregs.utr: user test register. */ +#define QE_MR_UTR_RTRE 0x80 /* enable resv test register */ +#define QE_MR_UTR_RTRD 0x40 /* disab resv test register */ +#define QE_MR_UTR_RPA 0x20 /* accept runt packets */ +#define QE_MR_UTR_FCOLL 0x10 /* force collision status */ +#define QE_MR_UTR_RCVSFCSE 0x08 /* enable fcs on rx */ +#define QE_MR_UTR_INTLOOPM 0x06 /* Internal loopback w/mandec */ +#define QE_MR_UTR_INTLOOP 0x04 /* Internal loopback */ +#define QE_MR_UTR_EXTLOOP 0x02 /* external loopback */ +#define QE_MR_UTR_NOLOOP 0x00 /* no loopback */ + +/* Buffer and Ring sizes: fixed ring size */ +#define QE_TX_RING_MAXSIZE 256 /* maximum tx ring size */ +#define QE_RX_RING_MAXSIZE 256 /* maximum rx ring size */ +#define QE_TX_RING_SIZE 16 +#define QE_RX_RING_SIZE 16 +#define QE_PKT_BUF_SZ 2048 + +#define MC_POLY_LE 0xedb88320 /* mcast crc, little endian */ |