diff options
Diffstat (limited to 'sys/dev')
| -rw-r--r-- | sys/dev/ic/ar5210.c | 595 | ||||
| -rw-r--r-- | sys/dev/ic/ar5210reg.h | 498 | ||||
| -rw-r--r-- | sys/dev/ic/ar5210var.h | 189 | ||||
| -rw-r--r-- | sys/dev/ic/ar5xxx.c | 175 | ||||
| -rw-r--r-- | sys/dev/ic/ar5xxx.h | 506 |
5 files changed, 978 insertions, 985 deletions
diff --git a/sys/dev/ic/ar5210.c b/sys/dev/ic/ar5210.c index d5451d7ce4d..6c678942542 100644 --- a/sys/dev/ic/ar5210.c +++ b/sys/dev/ic/ar5210.c @@ -1,4 +1,4 @@ -/* $OpenBSD: ar5210.c,v 1.3 2004/11/02 14:05:49 reyk Exp $ */ +/* $OpenBSD: ar5210.c,v 1.4 2004/11/03 16:40:46 reyk Exp $ */ /* * Copyright (c) 2004 Reyk Floeter <reyk@vantronix.net>. @@ -31,17 +31,14 @@ */ #include <dev/ic/ar5xxx.h> - -#ifdef AR5K_SUPPORT_AR5210 - #include <dev/ic/ar5210reg.h> #include <dev/ic/ar5210var.h> HAL_BOOL ar5k_ar5210_nic_reset(struct ath_hal *, u_int32_t); -HAL_BOOL ar5k_ar5210_nic_wakeup(struct ath_hal *, HAL_BOOL, HAL_BOOL); -u_int32_t ar5k_ar5210_chan2athchan(HAL_CHANNEL *); -HAL_BOOL ar5k_ar5210_set_channel(struct ath_hal *, HAL_CHANNEL *); -void ar5k_ar5210_init_tx_queue(struct ath_hal *, u_int, HAL_BOOL); +HAL_BOOL ar5k_ar5210_nic_wakeup(struct ath_hal *, HAL_BOOL, HAL_BOOL); +u_int32_t ar5k_ar5210_chan2athchan(HAL_CHANNEL *); +HAL_BOOL ar5k_ar5210_set_channel(struct ath_hal *, HAL_CHANNEL *); +void ar5k_ar5210_init_tx_queue(struct ath_hal *, u_int, HAL_BOOL); const void ar5k_ar5210_fill(struct ath_hal *); AR5K_HAL_FUNCTIONS(extern, ar5k_ar5210,); @@ -197,8 +194,8 @@ ar5k_ar5210_attach(device, sc, st, sh, status) ar5k_ar5210_fill(hal); /* Bring device out of sleep and reset it's units */ - if(ar5k_ar5210_nic_wakeup(hal, AH_FALSE, AH_TRUE) != AH_TRUE) - return(NULL); + if (ar5k_ar5210_nic_wakeup(hal, AH_FALSE, AH_TRUE) != AH_TRUE) + return (NULL); /* Get MAC, PHY and RADIO revisions */ hal->ah_mac_version = 1; @@ -209,7 +206,7 @@ ar5k_ar5210_attach(device, sc, st, sh, status) /* ...wait until PHY is ready and read RADIO revision */ AR5K_REG_WRITE(AR5K_AR5210_PHY(0x34), 0x00001c16); - for(i = 0; i < 4; i++) + for (i = 0; i < 4; i++) AR5K_REG_WRITE(AR5K_AR5210_PHY(0x20), 0x00010000); hal->ah_radio_5ghz_revision = (u_int16_t) (ar5k_bitswap((AR5K_REG_READ(AR5K_AR5210_PHY(256) >> 28) & @@ -221,7 +218,7 @@ ar5k_ar5210_attach(device, sc, st, sh, status) ar5k_ar5210_getMacAddress(hal, mac); ar5k_ar5210_setPCUConfig(hal); - return(hal); + return (hal); } HAL_BOOL @@ -253,10 +250,10 @@ ar5k_ar5210_nic_reset(hal, val) /* * Reset configuration register */ - if((val & AR5K_AR5210_RC_MAC) == 0) + if ((val & AR5K_AR5210_RC_MAC) == 0) AR5K_REG_WRITE(AR5K_AR5210_CFG, AR5K_AR5210_INIT_CFG); - return(ret); + return (ret); } HAL_BOOL @@ -269,20 +266,22 @@ ar5k_ar5210_nic_wakeup(hal, turbo, initial) * Reset and wakeup the device */ - if(initial == AH_TRUE) { + if (initial == AH_TRUE) { /* ...reset hardware */ - if(ar5k_ar5210_nic_reset(hal, AR5K_AR5210_RC_PCI) == AH_FALSE) { + if (ar5k_ar5210_nic_reset(hal, + AR5K_AR5210_RC_PCI) == AH_FALSE) { AR5K_PRINTF("failed to reset the PCI chipset\n"); - return(AH_FALSE); + return (AH_FALSE); } AR5K_DELAY(1000); } /* ...wakeup the device */ - if(ar5k_ar5210_setPowerMode(hal, HAL_PM_AWAKE, AH_TRUE, 0) == AH_FALSE) { + if (ar5k_ar5210_setPowerMode(hal, + HAL_PM_AWAKE, AH_TRUE, 0) == AH_FALSE) { AR5K_PRINTF("failed to resume the AR5210 chipset\n"); - return(AH_FALSE); + return (AH_FALSE); } /* ...enable Atheros turbo mode if requested */ @@ -290,35 +289,36 @@ ar5k_ar5210_nic_wakeup(hal, turbo, initial) turbo == AH_TRUE ? AR5K_AR5210_PHY_FC_TURBO_MODE : 0); /* ...reset chipset */ - if(ar5k_ar5210_nic_reset(hal, AR5K_AR5210_RC_CHIP) == AH_FALSE) { + if (ar5k_ar5210_nic_reset(hal, AR5K_AR5210_RC_CHIP) == AH_FALSE) { AR5K_PRINTF("failed to reset the AR5210 chipset\n"); - return(AH_FALSE); + return (AH_FALSE); } AR5K_DELAY(1000); /* ...reset chipset and PCI device */ - if(ar5k_ar5210_nic_reset(hal, AR5K_AR5210_RC_CHIP | - AR5K_AR5210_RC_PCI) == AH_FALSE) { + if (ar5k_ar5210_nic_reset(hal, + AR5K_AR5210_RC_CHIP | AR5K_AR5210_RC_PCI) == AH_FALSE) { AR5K_PRINTF("failed to reset the AR5210 + PCI chipset\n"); - return(AH_FALSE); + return (AH_FALSE); } AR5K_DELAY(2300); /* ...wakeup (again) */ - if(ar5k_ar5210_setPowerMode(hal, HAL_PM_AWAKE, AH_TRUE, 0) == AH_FALSE) { + if (ar5k_ar5210_setPowerMode(hal, + HAL_PM_AWAKE, AH_TRUE, 0) == AH_FALSE) { AR5K_PRINTF("failed to resume the AR5210 (again)\n"); - return(AH_FALSE); + return (AH_FALSE); } /* ...final warm reset */ - if(ar5k_ar5210_nic_reset(hal, 0) == AH_FALSE) { + if (ar5k_ar5210_nic_reset(hal, 0) == AH_FALSE) { AR5K_PRINTF("failed to warm reset the AR5210\n"); - return(AH_FALSE); + return (AH_FALSE); } - return(AH_TRUE); + return (AH_TRUE); } u_int32_t @@ -337,7 +337,7 @@ ar5k_ar5210_chan2athchan(channel) channel->channelFlags) - 24) / 2, 5) << 1) | (1 << 6) | 0x1; - return(athchan); + return (athchan); } HAL_BOOL @@ -355,11 +355,11 @@ ar5k_ar5210_set_channel(hal, channel) * Check bounds supported by the PHY * (don't care about regulation restrictions at this point) */ - if(channel->channel < hal->ah_capabilities.cap_range.range_5ghz_min || + if (channel->channel < hal->ah_capabilities.cap_range.range_5ghz_min || channel->channel > hal->ah_capabilities.cap_range.range_5ghz_max) { AR5K_PRINTF("channel out of supported range (%u MHz)\n", channel->channel); - return(AH_FALSE); + return (AH_FALSE); } /* @@ -380,7 +380,7 @@ ar5k_ar5210_set_channel(hal, channel) hal->ah_current_channel.channelFlags = channel->channelFlags; hal->ah_turbo = channel->channelFlags == CHANNEL_T ? AH_TRUE : AH_FALSE; - return(AH_TRUE); + return (AH_TRUE); } const HAL_RATE_TABLE * @@ -388,18 +388,18 @@ ar5k_ar5210_getRateTable(hal, mode) struct ath_hal *hal; u_int mode; { - switch(mode) { + switch (mode) { case HAL_MODE_11A: - return(&hal->ah_rt_11a); + return (&hal->ah_rt_11a); case HAL_MODE_TURBO: - return(&hal->ah_rt_turbo); + return (&hal->ah_rt_turbo); case HAL_MODE_11B: case HAL_MODE_11G: default: - return(NULL); + return (NULL); } - return(NULL); + return (NULL); } void @@ -423,10 +423,10 @@ ar5k_ar5210_reset(hal, op_mode, channel, change_channel, status) int i; struct ar5k_ini initial[] = AR5K_AR5210_INI; - if(ar5k_ar5210_nic_wakeup(hal, - channel->channelFlags & IEEE80211_CHAN_T ? - AH_TRUE : AH_FALSE, AH_FALSE) == AH_FALSE) - return(AH_FALSE); + if (ar5k_ar5210_nic_wakeup(hal, + channel->channelFlags & IEEE80211_CHAN_T ? + AH_TRUE : AH_FALSE, AH_FALSE) == AH_FALSE) + return (AH_FALSE); /* * Initialize operating mode @@ -437,13 +437,13 @@ ar5k_ar5210_reset(hal, op_mode, channel, change_channel, status) /* * Write initial mode register settings */ - for(i = 0; i < AR5K_ELEMENTS(initial); i++) { - if(change_channel == AH_TRUE && + for (i = 0; i < AR5K_ELEMENTS(initial); i++) { + if (change_channel == AH_TRUE && initial[i].ini_register >= AR5K_AR5210_PCU_MIN && initial[i].ini_register <= AR5K_AR5210_PCU_MAX) continue; - switch(initial[i].ini_mode) { + switch (initial[i].ini_mode) { case INI_READ: /* Cleared on read */ AR5K_REG_READ(initial[i].ini_register); @@ -461,13 +461,13 @@ ar5k_ar5210_reset(hal, op_mode, channel, change_channel, status) /* * Set channel and calibrate the PHY */ - if(ar5k_ar5210_perCalibration(hal, channel) == AH_FALSE) - return(AH_FALSE); + if (ar5k_ar5210_perCalibration(hal, channel) == AH_FALSE) + return (AH_FALSE); /* * Set RF kill flags if supported by the device (read from the EEPROM) */ - if(hal->ah_capabilities.cap_eeprom.ee_rfkill != 0) { + if (hal->ah_capabilities.cap_eeprom.ee_rfkill != 0) { if ((hal->ah_gpio[0] = ar5k_ar5210_gpioGet(hal, 0)) == 0) ar5k_ar5210_gpioSetIntr(hal, 0, 1); else @@ -477,17 +477,17 @@ ar5k_ar5210_reset(hal, op_mode, channel, change_channel, status) /* * Reset queues and start beacon timers at the end of the reset routine */ - for(i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) { - if(ar5k_ar5210_resetTxQueue(hal, i) == AH_FALSE) { + for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) { + if (ar5k_ar5210_resetTxQueue(hal, i) == AH_FALSE) { AR5K_PRINTF("failed to reset TX queue #%d\n", i); - return(AH_FALSE); + return (AH_FALSE); } } AR5K_REG_ENABLE_BITS(AR5K_AR5210_BEACON, AR5K_AR5210_BEACON_EN | AR5K_AR5210_BEACON_RESET_TSF); - return(AH_TRUE); + return (AH_TRUE); } void @@ -499,7 +499,7 @@ ar5k_ar5210_setPCUConfig(hal) beacon_reg = 0; pcu_reg = 0; - switch(hal->ah_op_mode) { + switch (hal->ah_op_mode) { case IEEE80211_M_STA: pcu_reg |= AR5K_AR5210_STA_ID1_NO_PSPOLL | AR5K_AR5210_STA_ID1_DESC_ANTENNA | @@ -559,8 +559,8 @@ ar5k_ar5210_perCalibration(hal, channel) */ AR5K_REG_ENABLE_BITS(AR5K_AR5210_PHY_AGC, AR5K_AR5210_PHY_AGC_DISABLE); - if(ar5k_ar5210_set_channel(hal, channel) != AH_TRUE) - return(AH_FALSE); + if (ar5k_ar5210_set_channel(hal, channel) != AH_TRUE) + return (AH_FALSE); AR5K_REG_DISABLE_BITS(AR5K_AR5210_PHY_AGC, AR5K_AR5210_PHY_AGC_DISABLE); @@ -570,10 +570,10 @@ ar5k_ar5210_perCalibration(hal, channel) AR5K_REG_ENABLE_BITS(AR5K_AR5210_PHY_AGCCTL, AR5K_AR5210_PHY_AGC_CAL); - if(ar5k_register_timeout(hal, AR5K_AR5210_PHY_AGCCTL, - AR5K_AR5210_PHY_AGC_CAL, 0, AH_FALSE) == AH_FALSE) { + if (ar5k_register_timeout(hal, AR5K_AR5210_PHY_AGCCTL, + AR5K_AR5210_PHY_AGC_CAL, 0, AH_FALSE) == AH_FALSE) { AR5K_PRINTF("calibration timeout\n"); - return(AH_FALSE); + return (AH_FALSE); } /* @@ -589,7 +589,7 @@ ar5k_ar5210_perCalibration(hal, channel) AR5K_AR5210_DIAG_SW_DIS_TX | AR5K_AR5210_DIAG_SW_DIS_RX); AR5K_REG_ENABLE_BITS(AR5K_AR5210_BEACON, AR5K_AR5210_BEACON_EN); - return(AH_TRUE); + return (AH_TRUE); } /* @@ -611,8 +611,8 @@ ar5k_ar5210_updateTxTrigLevel(hal, increase) trigger_level = AR5K_REG_READ(AR5K_AR5210_TRIG_LVL); - if(increase == AH_FALSE) { - if(--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) + if (increase == AH_FALSE) { + if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) goto done; } else trigger_level += @@ -630,7 +630,7 @@ ar5k_ar5210_updateTxTrigLevel(hal, increase) */ AR5K_REG_ENABLE_BITS(AR5K_AR5210_IMR, HAL_INT_GLOBAL); - return(status); + return (status); } int @@ -644,7 +644,7 @@ ar5k_ar5210_setupTxQueue(hal, queue_type, queue_info) /* * Get queue by type */ - switch(queue_type) { + switch (queue_type) { case HAL_TX_QUEUE_DATA: queue = 0; break; @@ -653,7 +653,7 @@ ar5k_ar5210_setupTxQueue(hal, queue_type, queue_info) queue = 1; break; default: - return(-EINVAL); + return (EINVAL); } /* @@ -662,12 +662,13 @@ ar5k_ar5210_setupTxQueue(hal, queue_type, queue_info) bzero(&hal->ah_txq[queue], sizeof(HAL_TXQ_INFO)); hal->ah_txq[queue].tqi_type = queue_type; - if(queue_info != NULL) { - if(ar5k_ar5210_setTxQueueProps(hal, queue, queue_info) != AH_TRUE) - return(AH_FALSE); + if (queue_info != NULL) { + if (ar5k_ar5210_setTxQueueProps(hal, + queue, queue_info) != AH_TRUE) + return (AH_FALSE); } - return(0); + return (0); } HAL_BOOL @@ -678,15 +679,15 @@ ar5k_ar5210_setTxQueueProps(hal, queue, queue_info) { AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); - if(hal->ah_txq[queue].tqi_type == HAL_TX_QUEUE_INACTIVE) - return(AH_FALSE); + if (hal->ah_txq[queue].tqi_type == HAL_TX_QUEUE_INACTIVE) + return (AH_FALSE); hal->ah_txq[queue].tqi_aifs = queue_info->tqi_aifs; hal->ah_txq[queue].tqi_cw_max = queue_info->tqi_cw_max; hal->ah_txq[queue].tqi_cw_min = queue_info->tqi_cw_min; hal->ah_txq[queue].tqi_flags = queue_info->tqi_flags; - return(AH_TRUE); + return (AH_TRUE); } HAL_BOOL @@ -699,7 +700,7 @@ ar5k_ar5210_releaseTxQueue(hal, queue) /* This queue will be skipped in further operations */ hal->ah_txq[queue].tqi_type = HAL_TX_QUEUE_INACTIVE; - return(AH_FALSE); + return (AH_FALSE); } void @@ -717,7 +718,7 @@ ar5k_ar5210_init_tx_queue(hal, aifs, turbo) /* * Write initial mode register settings */ - for(i = 0; i < AR5K_ELEMENTS(initial); i++) + for (i = 0; i < AR5K_ELEMENTS(initial); i++) AR5K_REG_WRITE(initial[i].mode_register, turbo == AH_TRUE ? initial[i].mode_turbo : initial[i].mode_base); } @@ -735,8 +736,8 @@ ar5k_ar5210_resetTxQueue(hal, queue) tq = &hal->ah_txq[queue]; /* Only handle data queues, others will be ignored */ - if(tq->tqi_type != HAL_TX_QUEUE_DATA) - return(AH_TRUE); + if (tq->tqi_type != HAL_TX_QUEUE_DATA) + return (AH_TRUE); /* Set turbo/base mode parameters */ ar5k_ar5210_init_tx_queue(hal, hal->ah_aifs + tq->tqi_aifs, @@ -745,7 +746,7 @@ ar5k_ar5210_resetTxQueue(hal, queue) /* * Set retry limits */ - if(hal->ah_software_retry == AH_TRUE) { + if (hal->ah_software_retry == AH_TRUE) { /* XXX Need to test this */ retry_lg = hal->ah_limit_tx_retries; retry_sh = retry_lg = @@ -760,7 +761,7 @@ ar5k_ar5210_resetTxQueue(hal, queue) * Set initial content window (cw_min/cw_max) */ cw_min = 1; - while(cw_min < hal->ah_cw_min) + while (cw_min < hal->ah_cw_min) cw_min = (cw_min << 1) | 1; cw_min = tq->tqi_cw_min < 0 ? @@ -775,7 +776,7 @@ ar5k_ar5210_resetTxQueue(hal, queue) | AR5K_REG_SM(retry_lg, AR5K_AR5210_RETRY_LMT_LG_RETRY) | AR5K_REG_SM(retry_sh, AR5K_AR5210_RETRY_LMT_SH_RETRY)); - return(AH_TRUE); + return (AH_TRUE); } u_int32_t @@ -790,7 +791,7 @@ ar5k_ar5210_getTxDP(hal, queue) /* * Get the transmit queue descriptor pointer register by type */ - switch(hal->ah_txq[queue].tqi_type) { + switch (hal->ah_txq[queue].tqi_type) { case HAL_TX_QUEUE_DATA: tx_reg = AR5K_AR5210_TXDP0; break; @@ -799,10 +800,10 @@ ar5k_ar5210_getTxDP(hal, queue) tx_reg = AR5K_AR5210_TXDP1; break; default: - return(0xffffffff); + return (0xffffffff); } - return(AR5K_REG_READ(tx_reg)); + return (AR5K_REG_READ(tx_reg)); } HAL_BOOL @@ -818,7 +819,7 @@ ar5k_ar5210_setTxDP(hal, queue, phys_addr) /* * Get the transmit queue descriptor pointer register by type */ - switch(hal->ah_txq[queue].tqi_type) { + switch (hal->ah_txq[queue].tqi_type) { case HAL_TX_QUEUE_DATA: tx_reg = AR5K_AR5210_TXDP0; break; @@ -827,13 +828,13 @@ ar5k_ar5210_setTxDP(hal, queue, phys_addr) tx_reg = AR5K_AR5210_TXDP1; break; default: - return(AH_FALSE); + return (AH_FALSE); } /* Set descriptor pointer */ AR5K_REG_WRITE(tx_reg, phys_addr); - return(AH_TRUE); + return (AH_TRUE); } HAL_BOOL @@ -850,7 +851,7 @@ ar5k_ar5210_startTxDma(hal, queue) /* * Set the queue type */ - switch(hal->ah_txq[queue].tqi_type) { + switch (hal->ah_txq[queue].tqi_type) { case HAL_TX_QUEUE_DATA: tx_queue |= AR5K_AR5210_CR_TXE0 & ~AR5K_AR5210_CR_TXD0; break; @@ -869,13 +870,13 @@ ar5k_ar5210_startTxDma(hal, queue) break; default: - return(AH_FALSE); + return (AH_FALSE); } /* Start queue */ AR5K_REG_WRITE(AR5K_AR5210_CR, tx_queue); - return(AH_TRUE); + return (AH_TRUE); } HAL_BOOL @@ -892,7 +893,7 @@ ar5k_ar5210_stopTxDma(hal, queue) /* * Set by queue type */ - switch(hal->ah_txq[queue].tqi_type) { + switch (hal->ah_txq[queue].tqi_type) { case HAL_TX_QUEUE_DATA: tx_queue |= AR5K_AR5210_CR_TXD0 & ~AR5K_AR5210_CR_TXE0; break; @@ -905,13 +906,13 @@ ar5k_ar5210_stopTxDma(hal, queue) break; default: - return(AH_FALSE); + return (AH_FALSE); } /* Stop queue */ AR5K_REG_WRITE(AR5K_AR5210_CR, tx_queue); - return(AH_TRUE); + return (AH_TRUE); } HAL_BOOL @@ -942,10 +943,10 @@ ar5k_ar5210_setupTxDesc(hal, desc, packet_length, header_length, type, tx_power, /* * Validate input */ - if(tx_tries0 == 0) - return(AH_FALSE); + if (tx_tries0 == 0) + return (AH_FALSE); - switch(type) { + switch (type) { case HAL_PKT_TYPE_NORMAL: tx_desc->frame_type = AR5K_AR5210_DESC_TX_FRAME_TYPE_NORMAL; break; @@ -969,14 +970,14 @@ ar5k_ar5210_setupTxDesc(hal, desc, packet_length, header_length, type, tx_power, default: /* Invalid packet type (possibly not supported) */ - return(AH_FALSE); + return (AH_FALSE); } - if((tx_desc->frame_len = packet_length) != packet_length) - return(AH_FALSE); + if ((tx_desc->frame_len = packet_length) != packet_length) + return (AH_FALSE); - if((tx_desc->header_len = header_length) != header_length) - return(AH_FALSE); + if ((tx_desc->header_len = header_length) != header_length) + return (AH_FALSE); tx_desc->xmit_rate = tx_rate0; tx_desc->ant_mode_xmit = antenna_mode ? 1 : 0; @@ -985,7 +986,7 @@ ar5k_ar5210_setupTxDesc(hal, desc, packet_length, header_length, type, tx_power, /* * WEP crap */ - if(key_index != HAL_TXKEYIX_INVALID) { + if (key_index != HAL_TXKEYIX_INVALID) { tx_desc->encrypt_key_valid = 1; tx_desc->encrypt_key_index = key_index; } @@ -993,12 +994,12 @@ ar5k_ar5210_setupTxDesc(hal, desc, packet_length, header_length, type, tx_power, /* * RTS/CTS */ - if(flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { + if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { tx_desc->rts_cts_enable = 1; tx_desc->rts_duration = rtscts_duration; } - return(AH_TRUE); + return (AH_TRUE); } HAL_BOOL @@ -1017,15 +1018,15 @@ ar5k_ar5210_fillTxDesc(hal, desc, segment_length, first_segment, last_segment) desc->ds_hw[0] = desc->ds_hw[1] = 0; /* Validate segment length and initialize the descriptor */ - if((tx_desc->buf_len = segment_length) != segment_length) - return(AH_FALSE); + if ((tx_desc->buf_len = segment_length) != segment_length) + return (AH_FALSE); - if(first_segment != AH_TRUE) + if (first_segment != AH_TRUE) tx_desc->frame_len = 0; tx_desc->more = last_segment == AH_TRUE ? 0 : 1; - return(AH_TRUE); + return (AH_TRUE); } HAL_BOOL @@ -1045,7 +1046,7 @@ ar5k_ar5210_setupXTxDesc(hal, desc, tx_rate1, tx_tries1, tx_rate2, tx_tries2, * Nevertheless, I didn't find any information about XR support * by the AR5210. This seems to be a slightly new feature. */ - return(AH_FALSE); + return (AH_FALSE); } HAL_STATUS @@ -1060,8 +1061,8 @@ ar5k_ar5210_procTxDesc(hal, desc) tx_status = (struct ar5k_ar5210_tx_status*)&desc->ds_hw[0]; /* No frame has been send or error */ - if(tx_status->done == 0) - return(HAL_EINPROGRESS); + if (tx_status->done == 0) + return (HAL_EINPROGRESS); /* * Get descriptor status @@ -1075,14 +1076,14 @@ ar5k_ar5210_procTxDesc(hal, desc) desc->ds_us.tx.ts_antenna = 0; desc->ds_us.tx.ts_status = 0; - if(tx_status->frame_xmit_ok == 0) { - if(tx_status->excessive_retries) + if (tx_status->frame_xmit_ok == 0) { + if (tx_status->excessive_retries) desc->ds_us.tx.ts_status |= HAL_TXERR_XRETRY; - if(tx_status->fifo_underrun) + if (tx_status->fifo_underrun) desc->ds_us.tx.ts_status |= HAL_TXERR_FIFO; - if(tx_status->filtered) + if (tx_status->filtered) desc->ds_us.tx.ts_status |= HAL_TXERR_FILT; } @@ -1094,14 +1095,14 @@ ar5k_ar5210_procTxDesc(hal, desc) bzero(tx_status, sizeof(struct ar5k_ar5210_tx_status)); #endif - return(HAL_OK); + return (HAL_OK); } HAL_BOOL ar5k_ar5210_hasVEOL(hal) struct ath_hal *hal; { - return(AH_FALSE); + return (AH_FALSE); } /* @@ -1112,7 +1113,7 @@ u_int32_t ar5k_ar5210_getRxDP(hal) struct ath_hal *hal; { - return(AR5K_REG_READ(AR5K_AR5210_RXDP)); + return (AR5K_REG_READ(AR5K_AR5210_RXDP)); } void @@ -1141,12 +1142,12 @@ ar5k_ar5210_stopDmaReceive(hal) /* * It may take some time to disable the DMA receive unit */ - for(i = 2000; - i > 0 && (AR5K_REG_READ(AR5K_AR5210_CR) & AR5K_AR5210_CR_RXE) != 0; - i--) + for (i = 2000; + i > 0 && (AR5K_REG_READ(AR5K_AR5210_CR) & AR5K_AR5210_CR_RXE) != 0; + i--) AR5K_DELAY(10); - return(i > 0 ? AH_TRUE : AH_FALSE); + return (i > 0 ? AH_TRUE : AH_FALSE); } void @@ -1179,16 +1180,16 @@ ar5k_ar5210_setMulticastFilterIndex(hal, index) struct ath_hal *hal; u_int32_t index; { - if(index >= 64) - return(AH_FALSE); - else if(index >= 32) + if (index >= 64) + return (AH_FALSE); + else if (index >= 32) AR5K_REG_ENABLE_BITS(AR5K_AR5210_MCAST_FIL1, (1 << (index - 32))); else AR5K_REG_ENABLE_BITS(AR5K_AR5210_MCAST_FIL0, (1 << index)); - return(AH_TRUE); + return (AH_TRUE); } HAL_BOOL @@ -1196,23 +1197,23 @@ ar5k_ar5210_clrMulticastFilterIndex(hal, index) struct ath_hal *hal; u_int32_t index; { - if(index >= 64) - return(AH_FALSE); - else if(index >= 32) + if (index >= 64) + return (AH_FALSE); + else if (index >= 32) AR5K_REG_DISABLE_BITS(AR5K_AR5210_MCAST_FIL1, (1 << (index - 32))); else AR5K_REG_DISABLE_BITS(AR5K_AR5210_MCAST_FIL0, (1 << index)); - return(AH_TRUE); + return (AH_TRUE); } u_int32_t ar5k_ar5210_getRxFilter(hal) struct ath_hal *hal; { - return(AR5K_REG_READ(AR5K_AR5210_RX_FILTER)); + return (AR5K_REG_READ(AR5K_AR5210_RX_FILTER)); } void @@ -1223,7 +1224,7 @@ ar5k_ar5210_setRxFilter(hal, filter) /* * The AR5210 uses promiscous mode to detect radar activity */ - if(filter & HAL_RX_FILTER_PHYRADAR) { + if (filter & HAL_RX_FILTER_PHYRADAR) { filter &= ~HAL_RX_FILTER_PHYRADAR; filter |= AR5K_AR5210_RX_FILTER_PROMISC; } @@ -1247,13 +1248,13 @@ ar5k_ar5210_setupRxDesc(hal, desc, size, flags) rx_desc = (struct ar5k_ar5210_rx_desc*)&desc->ds_ctl0; - if((rx_desc->buf_len = size) != size) - return(AH_FALSE); + if ((rx_desc->buf_len = size) != size) + return (AH_FALSE); - if(flags & HAL_RXDESC_INTREQ) + if (flags & HAL_RXDESC_INTREQ) rx_desc->inter_req = 1; - return(AH_TRUE); + return (AH_TRUE); } HAL_STATUS @@ -1269,16 +1270,17 @@ ar5k_ar5210_procRxDesc(hal, desc, phys_addr, next) rx_status = (struct ar5k_ar5210_rx_status*)&desc->ds_hw[0]; /* No frame received / not ready */ - if(!rx_status->done) - return(HAL_EINPROGRESS); + if (!rx_status->done) + return (HAL_EINPROGRESS); /* * Frame receive status */ now = (AR5K_REG_READ(AR5K_AR5210_TSF_L32) >> 10) & 0xffff; tstamp = ((now & 0x1fff) < rx_status->receive_timestamp) ? - (((now - 0x2000) & 0xffff) | (u_int32_t) rx_status->receive_timestamp) : - (now | (u_int32_t) rx_status->receive_timestamp); + (((now - 0x2000) & 0xffff) | + (u_int32_t)rx_status->receive_timestamp) : + (now | (u_int32_t)rx_status->receive_timestamp); desc->ds_us.rx.rs_tstamp = rx_status->receive_timestamp & 0x7fff; desc->ds_us.rx.rs_datalen = rx_status->data_len; desc->ds_us.rx.rs_rssi = rx_status->receive_sig_strength; @@ -1290,7 +1292,7 @@ ar5k_ar5210_procRxDesc(hal, desc, phys_addr, next) /* * Key table status */ - if(!rx_status->key_index_valid) + if (!rx_status->key_index_valid) desc->ds_us.rx.rs_keyix = HAL_RXKEYIX_INVALID; else desc->ds_us.rx.rs_keyix = rx_status->key_index; @@ -1298,23 +1300,23 @@ ar5k_ar5210_procRxDesc(hal, desc, phys_addr, next) /* * Receive/descriptor errors */ - if(!rx_status->frame_receive_ok) { - if(rx_status->crc_error) + if (!rx_status->frame_receive_ok) { + if (rx_status->crc_error) desc->ds_us.rx.rs_status |= HAL_RXERR_CRC; - if(rx_status->phy_error) { + if (rx_status->phy_error) { desc->ds_us.rx.rs_status |= HAL_RXERR_PHY; desc->ds_us.rx.rs_phyerr = rx_status->phy_error; } - if(rx_status->fifo_overrun) + if (rx_status->fifo_overrun) desc->ds_us.rx.rs_status |= HAL_RXERR_FIFO; - if(rx_status->decrypt_crc_error) + if (rx_status->decrypt_crc_error) desc->ds_us.rx.rs_status |= HAL_RXERR_DECRYPT; } - return(HAL_OK); + return (HAL_OK); } void @@ -1336,7 +1338,7 @@ void ar5k_ar5210_dumpState(hal) struct ath_hal *hal; { -#define AR5K_PRINT_REGISTER(_x) \ +#define AR5K_PRINT_REGISTER(_x) \ printf("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_AR5210_##_x)); printf("DMA registers:\n"); @@ -1433,7 +1435,7 @@ ar5k_ar5210_getDiagState(hal, id, device, size) * We'll ignore this right now. This seems to be some kind of an obscure * debugging interface for the binary-only HAL. */ - return(AH_FALSE); + return (AH_FALSE); } void @@ -1461,7 +1463,7 @@ ar5k_ar5210_setMacAddress(hal, mac) AR5K_REG_WRITE(AR5K_AR5210_STA_ID0, htole32(low_id)); AR5K_REG_WRITE(AR5K_AR5210_STA_ID1, high_id); - return(AH_TRUE); + return (AH_TRUE); } HAL_BOOL @@ -1471,15 +1473,15 @@ ar5k_ar5210_setRegulatoryDomain(hal, regdomain, status) HAL_STATUS *status; { - if(ar5k_ar5210_regulation_domain(hal, AH_TRUE, - ar5k_regdomain_to_ieee((u_int8_t)regdomain)) == AH_TRUE) { + if (ar5k_ar5210_regulation_domain(hal, AH_TRUE, + ar5k_regdomain_to_ieee((u_int8_t)regdomain)) == AH_TRUE) { *status = HAL_OK; - return(AH_TRUE); + return (AH_TRUE); } - *status = -EIO; + *status = EIO; - return(AH_FALSE); + return (AH_FALSE); } void @@ -1494,7 +1496,7 @@ ar5k_ar5210_setLedState(hal, state) /* * Some blinking values, define at your wish */ - switch(state) { + switch (state) { case IEEE80211_S_SCAN: case IEEE80211_S_INIT: led |= @@ -1534,7 +1536,7 @@ ar5k_ar5210_writeAssocid(hal, bssid, assoc_id, tim_offset) ((assoc_id & 0x3fff) << AR5K_AR5210_BSS_ID1_AID_S)); memcpy(&hal->ah_bssid, bssid, IEEE80211_ADDR_LEN); - if(assoc_id == 0) { + if (assoc_id == 0) { ar5k_ar5210_disablePSPoll(hal); return; } @@ -1554,14 +1556,14 @@ ar5k_ar5210_gpioCfgOutput(hal, gpio) struct ath_hal *hal; u_int32_t gpio; { - if(gpio > AR5K_AR5210_NUM_GPIO) - return(AH_FALSE); + if (gpio > AR5K_AR5210_NUM_GPIO) + return (AH_FALSE); AR5K_REG_WRITE(AR5K_AR5210_GPIOCR, (AR5K_REG_READ(AR5K_AR5210_GPIOCR) &~ AR5K_AR5210_GPIOCR_ALL(gpio)) | AR5K_AR5210_GPIOCR_OUT1(gpio)); - return(AH_TRUE); + return (AH_TRUE); } HAL_BOOL @@ -1569,14 +1571,14 @@ ar5k_ar5210_gpioCfgInput(hal, gpio) struct ath_hal *hal; u_int32_t gpio; { - if(gpio > AR5K_AR5210_NUM_GPIO) - return(AH_FALSE); + if (gpio > AR5K_AR5210_NUM_GPIO) + return (AH_FALSE); AR5K_REG_WRITE(AR5K_AR5210_GPIOCR, (AR5K_REG_READ(AR5K_AR5210_GPIOCR) &~ AR5K_AR5210_GPIOCR_ALL(gpio)) | AR5K_AR5210_GPIOCR_IN(gpio)); - return(AH_TRUE); + return (AH_TRUE); } u_int32_t @@ -1584,12 +1586,12 @@ ar5k_ar5210_gpioGet(hal, gpio) struct ath_hal *hal; u_int32_t gpio; { - if(gpio > AR5K_AR5210_NUM_GPIO) - return(0xffffffff); + if (gpio > AR5K_AR5210_NUM_GPIO) + return (0xffffffff); /* GPIO input magic */ - return(((AR5K_REG_READ(AR5K_AR5210_GPIODI) & - AR5K_AR5210_GPIOD_MASK) >> gpio) & 0x1); + return (((AR5K_REG_READ(AR5K_AR5210_GPIODI) & + AR5K_AR5210_GPIOD_MASK) >> gpio) & 0x1); } HAL_BOOL @@ -1600,8 +1602,8 @@ ar5k_ar5210_gpioSet(hal, gpio, val) { u_int32_t data; - if(gpio > AR5K_AR5210_NUM_GPIO) - return(0xffffffff); + if (gpio > AR5K_AR5210_NUM_GPIO) + return (0xffffffff); /* GPIO output magic */ data = AR5K_REG_READ(AR5K_AR5210_GPIODO); @@ -1611,7 +1613,7 @@ ar5k_ar5210_gpioSet(hal, gpio, val) AR5K_REG_WRITE(AR5K_AR5210_GPIODO, data); - return(AH_TRUE); + return (AH_TRUE); } void @@ -1622,7 +1624,7 @@ ar5k_ar5210_gpioSetIntr(hal, gpio, interrupt_level) { u_int32_t data; - if(gpio > AR5K_AR5210_NUM_GPIO) + if (gpio > AR5K_AR5210_NUM_GPIO) return; /* @@ -1646,7 +1648,7 @@ u_int32_t ar5k_ar5210_getTsf32(hal) struct ath_hal *hal; { - return(AR5K_REG_READ(AR5K_AR5210_TSF_L32)); + return (AR5K_REG_READ(AR5K_AR5210_TSF_L32)); } u_int64_t @@ -1654,7 +1656,7 @@ ar5k_ar5210_getTsf64(hal) struct ath_hal *hal; { u_int64_t tsf = AR5K_REG_READ(AR5K_AR5210_TSF_U32); - return(AR5K_REG_READ(AR5K_AR5210_TSF_L32) | (tsf << 32)); + return (AR5K_REG_READ(AR5K_AR5210_TSF_L32) | (tsf << 32)); } void @@ -1672,12 +1674,13 @@ ar5k_ar5210_getRegDomain(hal) u_int16_t regdomain; ieee80211_regdomain_t ieee_regdomain; - if(ar5k_ar5210_regulation_domain(hal, AH_FALSE, &ieee_regdomain) == AH_TRUE) { + if (ar5k_ar5210_regulation_domain(hal, + AH_FALSE, &ieee_regdomain) == AH_TRUE) { regdomain = ar5k_regdomain_from_ieee(&ieee_regdomain); - return(regdomain > 0 ? regdomain : hal->ah_regdomain); + return (regdomain > 0 ? regdomain : hal->ah_regdomain); } - return(0); + return (0); } HAL_BOOL @@ -1691,10 +1694,10 @@ ar5k_ar5210_detectCardPresent(hal) * if the card is still present. I didn't find another suitable * way to do this. */ - if(ar5k_ar5210_eeprom_read(hal, AR5K_AR5210_EEPROM_MAGIC, &magic) != 0) - return(AH_FALSE); + if (ar5k_ar5210_eeprom_read(hal, AR5K_AR5210_EEPROM_MAGIC, &magic) != 0) + return (AH_FALSE); - return(magic == AR5K_AR5210_EEPROM_MAGIC_VALUE ? AH_TRUE : AH_FALSE); + return (magic == AR5K_AR5210_EEPROM_MAGIC_VALUE ? AH_TRUE : AH_FALSE); } void @@ -1713,7 +1716,7 @@ HAL_RFGAIN ar5k_ar5210_getRfGain(hal) struct ath_hal *hal; { - return(HAL_RFGAIN_INACTIVE); + return (HAL_RFGAIN_INACTIVE); } HAL_BOOL @@ -1722,21 +1725,21 @@ ar5k_ar5210_setSlotTime(hal, slot_time) u_int slot_time; { - if(slot_time < HAL_SLOT_TIME_9 || slot_time > HAL_SLOT_TIME_MAX) - return(AH_FALSE); + if (slot_time < HAL_SLOT_TIME_9 || slot_time > HAL_SLOT_TIME_MAX) + return (AH_FALSE); AR5K_REG_WRITE(AR5K_AR5210_SLOT_TIME, ar5k_htoclock(slot_time, hal->ah_turbo)); - return(AH_TRUE); + return (AH_TRUE); } u_int ar5k_ar5210_getSlotTime(hal) struct ath_hal *hal; { - return(ar5k_clocktoh(AR5K_REG_READ(AR5K_AR5210_SLOT_TIME) & 0xffff, - hal->ah_turbo)); + return (ar5k_clocktoh(AR5K_REG_READ(AR5K_AR5210_SLOT_TIME) & + 0xffff, hal->ah_turbo)); } HAL_BOOL @@ -1744,22 +1747,22 @@ ar5k_ar5210_setAckTimeout(hal, timeout) struct ath_hal *hal; u_int timeout; { - if(ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5210_TIME_OUT_ACK), - hal->ah_turbo) <= timeout) - return(AH_FALSE); + if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5210_TIME_OUT_ACK), + hal->ah_turbo) <= timeout) + return (AH_FALSE); AR5K_REG_WRITE_BITS(AR5K_AR5210_TIME_OUT, AR5K_AR5210_TIME_OUT_ACK, ar5k_htoclock(timeout, hal->ah_turbo)); - return(AH_TRUE); + return (AH_TRUE); } u_int ar5k_ar5210_getAckTimeout(hal) struct ath_hal *hal; { - return(ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5210_TIME_OUT), - AR5K_AR5210_TIME_OUT_ACK), hal->ah_turbo)); + return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5210_TIME_OUT), + AR5K_AR5210_TIME_OUT_ACK), hal->ah_turbo)); } HAL_BOOL @@ -1767,22 +1770,22 @@ ar5k_ar5210_setCTSTimeout(hal, timeout) struct ath_hal *hal; u_int timeout; { - if(ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5210_TIME_OUT_CTS), - hal->ah_turbo) <= timeout) - return(AH_FALSE); + if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5210_TIME_OUT_CTS), + hal->ah_turbo) <= timeout) + return (AH_FALSE); AR5K_REG_WRITE_BITS(AR5K_AR5210_TIME_OUT, AR5K_AR5210_TIME_OUT_CTS, ar5k_htoclock(timeout, hal->ah_turbo)); - return(AH_TRUE); + return (AH_TRUE); } u_int ar5k_ar5210_getCTSTimeout(hal) struct ath_hal *hal; { - return(ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5210_TIME_OUT), - AR5K_AR5210_TIME_OUT_CTS), hal->ah_turbo)); + return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5210_TIME_OUT), + AR5K_AR5210_TIME_OUT_CTS), hal->ah_turbo)); } /* @@ -1797,17 +1800,17 @@ ar5k_ar5210_isHwCipherSupported(hal, cipher) /* * The AR5210 only supports WEP */ - if(cipher == HAL_CIPHER_WEP) - return(AH_TRUE); + if (cipher == HAL_CIPHER_WEP) + return (AH_TRUE); - return(AH_FALSE); + return (AH_FALSE); } u_int32_t ar5k_ar5210_getKeyCacheSize(hal) struct ath_hal *hal; { - return(AR5K_AR5210_KEYTABLE_SIZE); + return (AR5K_AR5210_KEYTABLE_SIZE); } HAL_BOOL @@ -1819,10 +1822,10 @@ ar5k_ar5210_resetKeyCacheEntry(hal, entry) AR5K_ASSERT_ENTRY(entry, AR5K_AR5210_KEYTABLE_SIZE); - for(i = 0; i < AR5K_AR5210_KEYCACHE_SIZE; i++) + for (i = 0; i < AR5K_AR5210_KEYCACHE_SIZE; i++) AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE(entry) + (i * 4), 0); - return(AH_FALSE); + return (AH_FALSE); } HAL_BOOL @@ -1838,11 +1841,11 @@ ar5k_ar5210_isKeyCacheEntryValid(hal, entry) * Check the validation flag at the end of the entry */ offset = (AR5K_AR5210_KEYCACHE_SIZE - 1) * 4; - if(AR5K_REG_READ(AR5K_AR5210_KEYTABLE(entry) + offset) & + if (AR5K_REG_READ(AR5K_AR5210_KEYTABLE(entry) + offset) & AR5K_AR5210_KEYTABLE_VALID) return AH_TRUE; - return(AH_FALSE); + return (AH_FALSE); } HAL_BOOL @@ -1862,7 +1865,7 @@ ar5k_ar5210_setKeyCacheEntry(hal, entry, keyval, mac, xor_notused) /* * Store the key type in the last field */ - switch(keyval->wk_len) { + switch (keyval->wk_len) { case 5: key_v[elements - 1] = AR5K_AR5210_KEYTABLE_TYPE_40; break; @@ -1877,15 +1880,15 @@ ar5k_ar5210_setKeyCacheEntry(hal, entry, keyval, mac, xor_notused) default: /* Unsupported key length (not WEP40/104/128) */ - return(AH_FALSE); + return (AH_FALSE); } /* * Write key cache entry */ - for(i = 0; i < elements; i++) { - if(elements < 5) { - if(i % 2) { + for (i = 0; i < elements; i++) { + if (elements < 5) { + if (i % 2) { key_v[i] = AR5K_LE_READ_2(keyval->wk_key + offset) & 0xffff; offset += 2; @@ -1895,7 +1898,7 @@ ar5k_ar5210_setKeyCacheEntry(hal, entry, keyval, mac, xor_notused) offset += 4; } - if(i == 4 && keyval->wk_len <= 13) + if (i == 4 && keyval->wk_len <= 13) key_v[i] &= 0xff; } @@ -1903,7 +1906,7 @@ ar5k_ar5210_setKeyCacheEntry(hal, entry, keyval, mac, xor_notused) AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE(entry) + (i * 4), key_v[i]); } - return(ar5k_ar5210_setKeyCacheEntryMac(hal, entry, mac)); + return (ar5k_ar5210_setKeyCacheEntryMac(hal, entry, mac)); } HAL_BOOL @@ -1932,7 +1935,7 @@ ar5k_ar5210_setKeyCacheEntryMac(hal, entry, mac) htole32(low_id)); AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE(entry) + (offset * 4), high_id); - return(AH_TRUE); + return (AH_TRUE); } /* @@ -1948,29 +1951,29 @@ ar5k_ar5210_setPowerMode(hal, mode, set_chip, sleep_duration) { int i; - switch(mode) { + switch (mode) { case HAL_PM_AUTO: - if(set_chip) + if (set_chip) AR5K_REG_WRITE(AR5K_AR5210_SCR, AR5K_AR5210_SCR_SLE | sleep_duration); break; case HAL_PM_FULL_SLEEP: - if(set_chip) + if (set_chip) AR5K_REG_WRITE(AR5K_AR5210_SCR, AR5K_AR5210_SCR_SLE_SLP); break; case HAL_PM_AWAKE: - if(!set_chip) + if (!set_chip) goto commit; AR5K_REG_WRITE(AR5K_AR5210_SCR, AR5K_AR5210_SCR_SLE_WAKE); - for(i = 5000; i > 0; i--) { + for (i = 5000; i > 0; i--) { /* Check if the AR5210 did wake up */ - if((AR5K_REG_READ(AR5K_AR5210_PCICFG) & - AR5K_AR5210_PCICFG_SPWR_DN) == 0) + if ((AR5K_REG_READ(AR5K_AR5210_PCICFG) & + AR5K_AR5210_PCICFG_SPWR_DN) == 0) break; /* Wait a bit and retry */ @@ -1980,14 +1983,14 @@ ar5k_ar5210_setPowerMode(hal, mode, set_chip, sleep_duration) } /* Fail if the AR5210 didn't wake up */ - if(i <= 0) - return(AH_FALSE); + if (i <= 0) + return (AH_FALSE); break; case HAL_PM_NETWORK_SLEEP: case HAL_PM_UNDEFINED: default: - return(AH_FALSE); + return (AH_FALSE); } commit: @@ -1998,14 +2001,14 @@ ar5k_ar5210_setPowerMode(hal, mode, set_chip, sleep_duration) AR5K_REG_ENABLE_BITS(AR5K_AR5210_STA_ID1, AR5K_AR5210_STA_ID1_PWR_SV); - return(AH_TRUE); + return (AH_TRUE); } HAL_POWER_MODE ar5k_ar5210_getPowerMode(hal) struct ath_hal *hal; { - return(hal->ah_power_mode); + return (hal->ah_power_mode); } HAL_BOOL @@ -2013,7 +2016,7 @@ ar5k_ar5210_queryPSPollSupport(hal) struct ath_hal *hal; { /* I think so, why not? */ - return(AH_TRUE); + return (AH_TRUE); } HAL_BOOL @@ -2023,7 +2026,7 @@ ar5k_ar5210_initPSPoll(hal) /* * Not used on the AR5210 */ - return(AH_FALSE); + return (AH_FALSE); } HAL_BOOL @@ -2036,7 +2039,7 @@ ar5k_ar5210_enablePSPoll(hal, bssid, assoc_id) AR5K_AR5210_STA_ID1_NO_PSPOLL | AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA); - return(AH_TRUE); + return (AH_TRUE); } HAL_BOOL @@ -2047,7 +2050,7 @@ ar5k_ar5210_disablePSPoll(hal) AR5K_AR5210_STA_ID1_NO_PSPOLL | AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA); - return(AH_TRUE); + return (AH_TRUE); } /* @@ -2065,7 +2068,7 @@ ar5k_ar5210_beaconInit(hal, next_beacon, interval) /* * Set the additional timers by mode */ - switch(hal->ah_op_mode) { + switch (hal->ah_op_mode) { case HAL_M_STA: timer1 = 0xffffffff; timer2 = 0xffffffff; @@ -2106,13 +2109,13 @@ ar5k_ar5210_setStationBeaconTimers(hal, state, tsf, dtim_count, cfp_count) u_int32_t cfp_period, next_cfp; /* Return on an invalid beacon state */ - if(state->bs_interval > 0) + if (state->bs_interval > 0) return; /* * PCF support? */ - if(state->bs_cfp_period > 0) { + if (state->bs_cfp_period > 0) { /* Enable CFP mode and set the CFP and timer registers */ cfp_period = state->bs_cfp_period * state->bs_dtim_period * state->bs_interval; @@ -2141,8 +2144,9 @@ ar5k_ar5210_setStationBeaconTimers(hal, state, tsf, dtim_count, cfp_count) /* * Start the beacon timers */ - AR5K_REG_WRITE(AR5K_AR5210_BEACON, (AR5K_REG_READ(AR5K_AR5210_BEACON) &~ - (AR5K_AR5210_BEACON_PERIOD | AR5K_AR5210_BEACON_TIM)) | + AR5K_REG_WRITE(AR5K_AR5210_BEACON, + (AR5K_REG_READ(AR5K_AR5210_BEACON) &~ + (AR5K_AR5210_BEACON_PERIOD | AR5K_AR5210_BEACON_TIM)) | AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, AR5K_AR5210_BEACON_TIM) | AR5K_REG_SM(state->bs_interval, AR5K_AR5210_BEACON_PERIOD)); @@ -2150,8 +2154,8 @@ ar5k_ar5210_setStationBeaconTimers(hal, state, tsf, dtim_count, cfp_count) /* * Write new beacon miss threshold, if it appears to be valid */ - if((state->bs_bmiss_threshold > - (AR5K_AR5210_RSSI_THR_BM_THR >> AR5K_AR5210_RSSI_THR_BM_THR_S)) && + if ((state->bs_bmiss_threshold > (AR5K_AR5210_RSSI_THR_BM_THR >> + AR5K_AR5210_RSSI_THR_BM_THR_S)) && (state->bs_bmiss_threshold & 0x00007) != 0) AR5K_REG_WRITE_BITS(AR5K_AR5210_RSSI_THR, AR5K_AR5210_RSSI_THR_BM_THR, state->bs_bmiss_threshold); @@ -2184,14 +2188,14 @@ ar5k_ar5210_waitForBeaconDone(hal, phys_addr) /* * Wait for beaconn queue to be done */ - for(i = (AR5K_TUNE_BEACON_INTERVAL / 2); i > 0 && - (AR5K_REG_READ(AR5K_AR5210_BSR) & - AR5K_AR5210_BSR_TXQ1F) != 0 && - (AR5K_REG_READ(AR5K_AR5210_CR) & - AR5K_AR5210_CR_TXE1) != 0; i--); + for (i = (AR5K_TUNE_BEACON_INTERVAL / 2); i > 0 && + (AR5K_REG_READ(AR5K_AR5210_BSR) & + AR5K_AR5210_BSR_TXQ1F) != 0 && + (AR5K_REG_READ(AR5K_AR5210_CR) & + AR5K_AR5210_CR_TXE1) != 0; i--); /* Timeout... */ - if(i <= 0) { + if (i <= 0) { /* * Re-schedule the beacon queue */ @@ -2199,10 +2203,10 @@ ar5k_ar5210_waitForBeaconDone(hal, phys_addr) AR5K_REG_WRITE(AR5K_AR5210_BCR, AR5K_AR5210_BCR_TQ1V | AR5K_AR5210_BCR_BDMAE); - return(AH_FALSE); + return (AH_FALSE); } - return(AH_TRUE); + return (AH_TRUE); } /* @@ -2213,7 +2217,7 @@ HAL_BOOL ar5k_ar5210_isInterruptPending(hal) struct ath_hal *hal; { - return(AR5K_REG_READ(AR5K_AR5210_INTPEND) == 0 ? AH_FALSE : AH_TRUE); + return (AR5K_REG_READ(AR5K_AR5210_INTPEND) == 0 ? AH_FALSE : AH_TRUE); } HAL_BOOL @@ -2223,9 +2227,9 @@ ar5k_ar5210_getPendingInterrupts(hal, interrupt_mask) { u_int32_t data; - if((data = AR5K_REG_READ(AR5K_AR5210_ISR)) == HAL_INT_NOCARD) { + if ((data = AR5K_REG_READ(AR5K_AR5210_ISR)) == HAL_INT_NOCARD) { *interrupt_mask = data; - return(AH_FALSE); + return (AH_FALSE); } /* @@ -2233,21 +2237,21 @@ ar5k_ar5210_getPendingInterrupts(hal, interrupt_mask) */ *interrupt_mask = (data & HAL_INT_COMMON) & hal->ah_imr; - if(data & (AR5K_AR5210_ISR_RXOK | AR5K_AR5210_ISR_RXERR)) + if (data & (AR5K_AR5210_ISR_RXOK | AR5K_AR5210_ISR_RXERR)) *interrupt_mask |= HAL_INT_RX; - if(data & (AR5K_AR5210_ISR_TXOK | AR5K_AR5210_ISR_TXERR)) + if (data & (AR5K_AR5210_ISR_TXOK | AR5K_AR5210_ISR_TXERR)) *interrupt_mask |= HAL_INT_TX; - if(data & AR5K_AR5210_ISR_FATAL) + if (data & AR5K_AR5210_ISR_FATAL) *interrupt_mask |= HAL_INT_FATAL; /* * Special interrupt handling (not catched by the driver) */ - if(((*interrupt_mask) & AR5K_AR5210_ISR_RXPHY) && + if (((*interrupt_mask) & AR5K_AR5210_ISR_RXPHY) && hal->ah_radar.r_enabled == AH_TRUE) ar5k_radar_alert(hal); - return(AH_TRUE); + return (AH_TRUE); } u_int32_t @@ -2255,7 +2259,7 @@ ar5k_ar5210_getInterrupts(hal) struct ath_hal *hal; { /* Return the interrupt mask stored previously */ - return(hal->ah_imr); + return (hal->ah_imr); } HAL_INT @@ -2279,13 +2283,13 @@ ar5k_ar5210_setInterrupts(hal, new_mask) */ int_mask = new_mask & HAL_INT_COMMON; - if(new_mask & HAL_INT_RX) + if (new_mask & HAL_INT_RX) int_mask |= AR5K_AR5210_IMR_RXOK | AR5K_AR5210_IMR_RXERR | AR5K_AR5210_IMR_RXORN; - if(new_mask & HAL_INT_TX) + if (new_mask & HAL_INT_TX) int_mask |= AR5K_AR5210_IMR_TXOK | AR5K_AR5210_IMR_TXERR | @@ -2299,7 +2303,7 @@ ar5k_ar5210_setInterrupts(hal, new_mask) /* ..re-enable interrupts */ AR5K_REG_WRITE(AR5K_AR5210_IER, AR5K_AR5210_IER_ENABLE); - return(old_mask); + return (old_mask); } /* @@ -2313,8 +2317,8 @@ ar5k_ar5210_get_capabilities(hal) /* * Get the value stored in the EEPROM */ - if(ar5k_ar5210_eeprom_init(hal) != 0) - return(AH_FALSE); + if (ar5k_ar5210_eeprom_init(hal) != 0) + return (AH_FALSE); /* Set number of supported TX queues */ hal->ah_capabilities.cap_queues.q_tx_num = AR5K_AR5210_TX_NUM_QUEUES; @@ -2331,7 +2335,7 @@ ar5k_ar5210_get_capabilities(hal) /* Set supported modes */ hal->ah_capabilities.cap_mode = HAL_MODE_11A | HAL_MODE_TURBO; - return(AH_TRUE); + return (AH_TRUE); } void @@ -2345,7 +2349,7 @@ ar5k_ar5210_radar_alert(hal, enable) */ AR5K_REG_WRITE(AR5K_AR5210_IER, AR5K_AR5210_IER_DISABLE); - if(enable == AH_TRUE) + if (enable == AH_TRUE) AR5K_REG_ENABLE_BITS(AR5K_AR5210_IMR, AR5K_AR5210_IMR_RXPHY); else @@ -2362,20 +2366,20 @@ ar5k_ar5210_regulation_domain(hal, write, regdomain) ieee80211_regdomain_t *regdomain; { /* Read current value */ - if(write != AH_TRUE) { + if (write != AH_TRUE) { memcpy(regdomain, &hal->ah_capabilities.cap_regdomain.reg_current, sizeof(ieee80211_regdomain_t)); - return(AH_TRUE); + return (AH_TRUE); } /* Try to write a new value */ memcpy(&hal->ah_capabilities.cap_regdomain.reg_current, regdomain, sizeof(ieee80211_regdomain_t)); - if(hal->ah_capabilities.cap_eeprom.ee_protect & + if (hal->ah_capabilities.cap_eeprom.ee_protect & AR5K_AR5210_EEPROM_PROTECT_128_191) - return(AH_FALSE); + return (AH_FALSE); hal->ah_capabilities.cap_eeprom.ee_regdomain = ar5k_regdomain_from_ieee(regdomain); @@ -2383,11 +2387,11 @@ ar5k_ar5210_regulation_domain(hal, write, regdomain) AR5K_PRINTF("writing new regulation domain to EEPROM: 0x%04x\n", hal->ah_capabilities.cap_eeprom.ee_regdomain); - if(ar5k_ar5210_eeprom_write(hal, AR5K_AR5210_EEPROM_REG_DOMAIN, - hal->ah_capabilities.cap_eeprom.ee_regdomain) != 0) - return(AH_FALSE); + if (ar5k_ar5210_eeprom_write(hal, AR5K_AR5210_EEPROM_REG_DOMAIN, + hal->ah_capabilities.cap_eeprom.ee_regdomain) != 0) + return (AH_FALSE); - return(AH_TRUE); + return (AH_TRUE); } /* @@ -2401,40 +2405,40 @@ ar5k_ar5210_eeprom_init(hal) int ret; /* Check if EEPROM is busy */ - if(ar5k_ar5210_eeprom_is_busy(hal) == AH_TRUE) - return(-EBUSY); + if (ar5k_ar5210_eeprom_is_busy(hal) == AH_TRUE) + return (EBUSY); /* * Read values from EEPROM and store them in the capability structure */ - if((ret = ar5k_ar5210_eeprom_read(hal, AR5K_AR5210_EEPROM_MAGIC, - &hal->ah_capabilities.cap_eeprom.ee_magic)) != 0) - return(ret); + if ((ret = ar5k_ar5210_eeprom_read(hal, AR5K_AR5210_EEPROM_MAGIC, + &hal->ah_capabilities.cap_eeprom.ee_magic)) != 0) + return (ret); - if(hal->ah_capabilities.cap_eeprom.ee_magic != + if (hal->ah_capabilities.cap_eeprom.ee_magic != AR5K_AR5210_EEPROM_MAGIC_VALUE) - return(-EFTYPE); + return (EFTYPE); - if((ret = ar5k_ar5210_eeprom_read(hal, AR5K_AR5210_EEPROM_INFO_VERSION, - &hal->ah_capabilities.cap_eeprom.ee_version)) != 0) - return(ret); + if ((ret = ar5k_ar5210_eeprom_read(hal, AR5K_AR5210_EEPROM_INFO_VERSION, + &hal->ah_capabilities.cap_eeprom.ee_version)) != 0) + return (ret); - if((ret = ar5k_ar5210_eeprom_read(hal, AR5K_AR5210_EEPROM_PROTECT, - &hal->ah_capabilities.cap_eeprom.ee_protect)) != 0) - return(ret); + if ((ret = ar5k_ar5210_eeprom_read(hal, AR5K_AR5210_EEPROM_PROTECT, + &hal->ah_capabilities.cap_eeprom.ee_protect)) != 0) + return (ret); - if((ret = ar5k_ar5210_eeprom_read(hal, AR5K_AR5210_EEPROM_REG_DOMAIN, - &hal->ah_capabilities.cap_eeprom.ee_regdomain)) != 0) - return(ret); + if ((ret = ar5k_ar5210_eeprom_read(hal, AR5K_AR5210_EEPROM_REG_DOMAIN, + &hal->ah_capabilities.cap_eeprom.ee_regdomain)) != 0) + return (ret); - return(0); + return (0); } HAL_BOOL ar5k_ar5210_eeprom_is_busy(hal) struct ath_hal *hal; { - return(AR5K_REG_READ(AR5K_AR5210_CFG) & AR5K_AR5210_CFG_EEBS ? + return (AR5K_REG_READ(AR5K_AR5210_CFG) & AR5K_AR5210_CFG_EEBS ? AH_TRUE : AH_FALSE); } @@ -2454,19 +2458,19 @@ ar5k_ar5210_eeprom_read(hal, offset, data) */ (void)AR5K_REG_READ(AR5K_AR5210_EEPROM_BASE + (4 * offset)); - for(timeout = 10000; timeout > 0; timeout--) { + for (timeout = 10000; timeout > 0; timeout--) { AR5K_DELAY(1); status = AR5K_REG_READ(AR5K_AR5210_EEPROM_STATUS); - if(status & AR5K_AR5210_EEPROM_STAT_RDDONE) { - if(status & AR5K_AR5210_EEPROM_STAT_RDERR) - return(-EIO); + if (status & AR5K_AR5210_EEPROM_STAT_RDDONE) { + if (status & AR5K_AR5210_EEPROM_STAT_RDERR) + return (EIO); *data = (u_int16_t) (AR5K_REG_READ(AR5K_AR5210_EEPROM_RDATA) & 0xffff); - return(0); + return (0); } } - return(-ETIMEDOUT); + return (ETIMEDOUT); } int @@ -2485,17 +2489,16 @@ ar5k_ar5210_eeprom_write(hal, offset, data) */ AR5K_REG_WRITE(AR5K_AR5210_EEPROM_BASE + (4 * offset), data); - for(timeout = 10000; timeout > 0; timeout--) { + for (timeout = 10000; timeout > 0; timeout--) { AR5K_DELAY(1); status = AR5K_REG_READ(AR5K_AR5210_EEPROM_STATUS); - if(status & AR5K_AR5210_EEPROM_STAT_WRDONE) { - if(status & AR5K_AR5210_EEPROM_STAT_WRERR) - return(-EIO); - return(0); + if (status & AR5K_AR5210_EEPROM_STAT_WRDONE) { + if (status & AR5K_AR5210_EEPROM_STAT_WRERR) + return (EIO); + return (0); } } - return(-ETIMEDOUT); + return (ETIMEDOUT); } -#endif /* AR5K_SUPPORT_AR5210 */ diff --git a/sys/dev/ic/ar5210reg.h b/sys/dev/ic/ar5210reg.h index 992027e8ff9..55e3b3f744f 100644 --- a/sys/dev/ic/ar5210reg.h +++ b/sys/dev/ic/ar5210reg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: ar5210reg.h,v 1.2 2004/11/02 14:05:49 reyk Exp $ */ +/* $OpenBSD: ar5210reg.h,v 1.3 2004/11/03 16:40:46 reyk Exp $ */ /* * Copyright (c) 2004 Reyk Floeter <reyk@vantronix.net>. @@ -41,36 +41,36 @@ /* * Second transmit queue descriptor pointer register ("beacon queue") */ -#define AR5K_AR5210_TXDP1 0x0004 +#define AR5K_AR5210_TXDP1 0x0004 /* * Command register */ -#define AR5K_AR5210_CR 0x0008 -#define AR5K_AR5210_CR_TXE0 0x00000001 -#define AR5K_AR5210_CR_TXE1 0x00000002 -#define AR5K_AR5210_CR_RXE 0x00000004 -#define AR5K_AR5210_CR_TXD0 0x00000008 -#define AR5K_AR5210_CR_TXD1 0x00000010 -#define AR5K_AR5210_CR_RXD 0x00000020 -#define AR5K_AR5210_CR_SWI 0x00000040 +#define AR5K_AR5210_CR 0x0008 +#define AR5K_AR5210_CR_TXE0 0x00000001 +#define AR5K_AR5210_CR_TXE1 0x00000002 +#define AR5K_AR5210_CR_RXE 0x00000004 +#define AR5K_AR5210_CR_TXD0 0x00000008 +#define AR5K_AR5210_CR_TXD1 0x00000010 +#define AR5K_AR5210_CR_RXD 0x00000020 +#define AR5K_AR5210_CR_SWI 0x00000040 /* * Receive queue descriptor pointer register */ -#define AR5K_AR5210_RXDP 0x000c +#define AR5K_AR5210_RXDP 0x000c /* * Configuration and status register */ -#define AR5K_AR5210_CFG 0x0014 -#define AR5K_AR5210_CFG_SWTD 0x00000001 -#define AR5K_AR5210_CFG_SWTB 0x00000002 -#define AR5K_AR5210_CFG_SWRD 0x00000004 -#define AR5K_AR5210_CFG_SWRB 0x00000008 -#define AR5K_AR5210_CFG_SWRG 0x00000010 -#define AR5K_AR5210_CFG_EEBS 0x00000200 -#define AR5K_AR5210_CFG_TXCNT 0x00007800 +#define AR5K_AR5210_CFG 0x0014 +#define AR5K_AR5210_CFG_SWTD 0x00000001 +#define AR5K_AR5210_CFG_SWTB 0x00000002 +#define AR5K_AR5210_CFG_SWRD 0x00000004 +#define AR5K_AR5210_CFG_SWRB 0x00000008 +#define AR5K_AR5210_CFG_SWRG 0x00000010 +#define AR5K_AR5210_CFG_EEBS 0x00000200 +#define AR5K_AR5210_CFG_TXCNT 0x00007800 #define AR5K_AR5210_CFG_TXCNT_S 11 #define AR5K_AR5210_CFG_TXFSTAT 0x00008000 #define AR5K_AR5210_CFG_TXFSTRT 0x00010000 @@ -83,15 +83,15 @@ #define AR5K_AR5210_ISR_RXDESC 0x00000002 #define AR5K_AR5210_ISR_RXERR 0x00000004 #define AR5K_AR5210_ISR_RXNOFRM 0x00000008 -#define AR5K_AR5210_ISR_RXEOL 0x00000120 -#define AR5K_AR5210_ISR_RXORN 0x00000020 -#define AR5K_AR5210_ISR_TXOK 0x00000040 -#define AR5K_AR5210_ISR_TXDESC 0x00000080 -#define AR5K_AR5210_ISR_TXERR 0x00000100 +#define AR5K_AR5210_ISR_RXEOL 0x00000120 +#define AR5K_AR5210_ISR_RXORN 0x00000020 +#define AR5K_AR5210_ISR_TXOK 0x00000040 +#define AR5K_AR5210_ISR_TXDESC 0x00000080 +#define AR5K_AR5210_ISR_TXERR 0x00000100 #define AR5K_AR5210_ISR_TXNOFRM 0x00000200 -#define AR5K_AR5210_ISR_TXEOL 0x00000400 -#define AR5K_AR5210_ISR_TXURN 0x00000800 -#define AR5K_AR5210_ISR_MIB 0x00001000 +#define AR5K_AR5210_ISR_TXEOL 0x00000400 +#define AR5K_AR5210_ISR_TXURN 0x00000800 +#define AR5K_AR5210_ISR_MIB 0x00001000 #define AR5K_AR5210_ISR_SWI 0x00002000 #define AR5K_AR5210_ISR_RXPHY 0x00004000 #define AR5K_AR5210_ISR_RXKCM 0x00008000 @@ -102,7 +102,7 @@ #define AR5K_AR5210_ISR_SSERR 0x00200000 #define AR5K_AR5210_ISR_DPERR 0x00400000 #define AR5K_AR5210_ISR_GPIO 0x01000000 -#define AR5K_AR5210_ISR_FATAL ( \ +#define AR5K_AR5210_ISR_FATAL ( \ AR5K_AR5210_ISR_MCABT | AR5K_AR5210_ISR_SSERR | \ AR5K_AR5210_ISR_DPERR | AR5K_AR5210_ISR_RXORN \ ) @@ -110,61 +110,61 @@ /* * Interrupt mask register */ -#define AR5K_AR5210_IMR 0x0020 -#define AR5K_AR5210_IMR_RXOK 0x00000001 -#define AR5K_AR5210_IMR_RXDESC 0x00000002 -#define AR5K_AR5210_IMR_RXERR 0x00000004 +#define AR5K_AR5210_IMR 0x0020 +#define AR5K_AR5210_IMR_RXOK 0x00000001 +#define AR5K_AR5210_IMR_RXDESC 0x00000002 +#define AR5K_AR5210_IMR_RXERR 0x00000004 #define AR5K_AR5210_IMR_RXNOFRM 0x00000008 #define AR5K_AR5210_IMR_RXEOL 0x00000010 -#define AR5K_AR5210_IMR_RXORN 0x00000020 -#define AR5K_AR5210_IMR_TXOK 0x00000040 -#define AR5K_AR5210_IMR_TXDESC 0x00000080 -#define AR5K_AR5210_IMR_TXERR 0x00000100 +#define AR5K_AR5210_IMR_RXORN 0x00000020 +#define AR5K_AR5210_IMR_TXOK 0x00000040 +#define AR5K_AR5210_IMR_TXDESC 0x00000080 +#define AR5K_AR5210_IMR_TXERR 0x00000100 #define AR5K_AR5210_IMR_TXNOFRM 0x00000200 -#define AR5K_AR5210_IMR_TXEOL 0x00000400 -#define AR5K_AR5210_IMR_TXURN 0x00000800 -#define AR5K_AR5210_IMR_MIB 0x00001000 -#define AR5K_AR5210_IMR_SWI 0x00002000 -#define AR5K_AR5210_IMR_RXPHY 0x00004000 -#define AR5K_AR5210_IMR_RXKCM 0x00008000 -#define AR5K_AR5210_IMR_SWBA 0x00010000 -#define AR5K_AR5210_IMR_BRSSI 0x00020000 -#define AR5K_AR5210_IMR_BMISS 0x00040000 -#define AR5K_AR5210_IMR_MCABT 0x00100000 -#define AR5K_AR5210_IMR_SSERR 0x00200000 -#define AR5K_AR5210_IMR_DPERR 0x00400000 -#define AR5K_AR5210_IMR_GPIO 0x01000000 +#define AR5K_AR5210_IMR_TXEOL 0x00000400 +#define AR5K_AR5210_IMR_TXURN 0x00000800 +#define AR5K_AR5210_IMR_MIB 0x00001000 +#define AR5K_AR5210_IMR_SWI 0x00002000 +#define AR5K_AR5210_IMR_RXPHY 0x00004000 +#define AR5K_AR5210_IMR_RXKCM 0x00008000 +#define AR5K_AR5210_IMR_SWBA 0x00010000 +#define AR5K_AR5210_IMR_BRSSI 0x00020000 +#define AR5K_AR5210_IMR_BMISS 0x00040000 +#define AR5K_AR5210_IMR_MCABT 0x00100000 +#define AR5K_AR5210_IMR_SSERR 0x00200000 +#define AR5K_AR5210_IMR_DPERR 0x00400000 +#define AR5K_AR5210_IMR_GPIO 0x01000000 /* * Interrupt enable register */ -#define AR5K_AR5210_IER 0x0024 +#define AR5K_AR5210_IER 0x0024 #define AR5K_AR5210_IER_DISABLE 0x00000000 -#define AR5K_AR5210_IER_ENABLE 0x00000001 +#define AR5K_AR5210_IER_ENABLE 0x00000001 /* * Beacon control register */ #define AR5K_AR5210_BCR 0x0028 -#define AR5K_AR5210_BCR_AP 0x00000000 -#define AR5K_AR5210_BCR_ADHOC 0x00000001 -#define AR5K_AR5210_BCR_BDMAE 0x00000002 -#define AR5K_AR5210_BCR_TQ1FV 0x00000004 -#define AR5K_AR5210_BCR_TQ1V 0x00000008 -#define AR5K_AR5210_BCR_BCGET 0x00000010 +#define AR5K_AR5210_BCR_AP 0x00000000 +#define AR5K_AR5210_BCR_ADHOC 0x00000001 +#define AR5K_AR5210_BCR_BDMAE 0x00000002 +#define AR5K_AR5210_BCR_TQ1FV 0x00000004 +#define AR5K_AR5210_BCR_TQ1V 0x00000008 +#define AR5K_AR5210_BCR_BCGET 0x00000010 /* * Beacon status register */ -#define AR5K_AR5210_BSR 0x002c -#define AR5K_AR5210_BSR_BDLYSW 0x00000001 -#define AR5K_AR5210_BSR_BDLYDMA 0x00000002 -#define AR5K_AR5210_BSR_TXQ1F 0x00000004 -#define AR5K_AR5210_BSR_ATIMDLY 0x00000008 -#define AR5K_AR5210_BSR_SNPBCMD 0x00000100 -#define AR5K_AR5210_BSR_SNPBDMAE 0x00000200 -#define AR5K_AR5210_BSR_SNPTQ1FV 0x00000400 -#define AR5K_AR5210_BSR_SNPTQ1V 0x00000800 +#define AR5K_AR5210_BSR 0x002c +#define AR5K_AR5210_BSR_BDLYSW 0x00000001 +#define AR5K_AR5210_BSR_BDLYDMA 0x00000002 +#define AR5K_AR5210_BSR_TXQ1F 0x00000004 +#define AR5K_AR5210_BSR_ATIMDLY 0x00000008 +#define AR5K_AR5210_BSR_SNPBCMD 0x00000100 +#define AR5K_AR5210_BSR_SNPBDMAE 0x00000200 +#define AR5K_AR5210_BSR_SNPTQ1FV 0x00000400 +#define AR5K_AR5210_BSR_SNPTQ1V 0x00000800 #define AR5K_AR5210_BSR_SNAPPEDBCRVALID 0x00001000 #define AR5K_AR5210_BSR_SWBA_CNT 0x00ff0000 @@ -186,9 +186,9 @@ typedef enum { * Transmit configuration register */ #define AR5K_AR5210_TXCFG 0x0030 -#define AR5K_AR5210_TXCFG_SDMAMR 0x00000007 -#define AR5K_AR5210_TXCFG_TXFSTP 0x00000008 -#define AR5K_AR5210_TXCFG_TXFULL 0x00000070 +#define AR5K_AR5210_TXCFG_SDMAMR 0x00000007 +#define AR5K_AR5210_TXCFG_TXFSTP 0x00000008 +#define AR5K_AR5210_TXCFG_TXFULL 0x00000070 #define AR5K_AR5210_TXCFG_TXCONT_EN 0x00000080 /* @@ -201,42 +201,42 @@ typedef enum { /* * MIB control register */ -#define AR5K_AR5210_MIBC 0x0040 -#define AR5K_AR5210_MIBC_COW 0x00000001 -#define AR5K_AR5210_MIBC_FMC 0x00000002 +#define AR5K_AR5210_MIBC 0x0040 +#define AR5K_AR5210_MIBC_COW 0x00000001 +#define AR5K_AR5210_MIBC_FMC 0x00000002 #define AR5K_AR5210_MIBC_CMC 0x00000004 -#define AR5K_AR5210_MIBC_MCS 0x00000008 +#define AR5K_AR5210_MIBC_MCS 0x00000008 /* * Timeout prescale register */ -#define AR5K_AR5210_TOPS 0x0044 +#define AR5K_AR5210_TOPS 0x0044 /* * Receive timeout register (no frame received) */ -#define AR5K_AR5210_RXNOFRM 0x0048 +#define AR5K_AR5210_RXNOFRM 0x0048 /* * Transmit timeout register (no frame sent) */ -#define AR5K_AR5210_TXNOFRM 0x004c +#define AR5K_AR5210_TXNOFRM 0x004c /* * Receive frame gap timeout register */ -#define AR5K_AR5210_RPGTO 0x0050 +#define AR5K_AR5210_RPGTO 0x0050 /* * Receive frame count limit register */ -#define AR5K_AR5210_RFCNT 0x0054 -#define AR5K_AR5210_RFCNT_RFCL 0x0000000f +#define AR5K_AR5210_RFCNT 0x0054 +#define AR5K_AR5210_RFCNT_RFCL 0x0000000f /* * Misc settings/status register */ -#define AR5K_AR5210_MISC 0x0058 +#define AR5K_AR5210_MISC 0x0058 #define AR5K_AR5210_MISC_LED_DECAY 0x001c0000 #define AR5K_AR5210_MISC_LED_BLINK 0x00e00000 @@ -244,13 +244,13 @@ typedef enum { * Reset control register */ #define AR5K_AR5210_RC 0x4000 -#define AR5K_AR5210_RC_PCU 0x00000001 -#define AR5K_AR5210_RC_DMA 0x00000002 -#define AR5K_AR5210_RC_MAC 0x00000004 -#define AR5K_AR5210_RC_PHY 0x00000008 -#define AR5K_AR5210_RC_PCI 0x00000010 -#define AR5K_AR5210_RC_CHIP ( \ - AR5K_AR5210_RC_PCU | AR5K_AR5210_RC_DMA | \ +#define AR5K_AR5210_RC_PCU 0x00000001 +#define AR5K_AR5210_RC_DMA 0x00000002 +#define AR5K_AR5210_RC_MAC 0x00000004 +#define AR5K_AR5210_RC_PHY 0x00000008 +#define AR5K_AR5210_RC_PCI 0x00000010 +#define AR5K_AR5210_RC_CHIP ( \ + AR5K_AR5210_RC_PCU | AR5K_AR5210_RC_DMA | \ AR5K_AR5210_RC_MAC | AR5K_AR5210_RC_PHY \ ) @@ -258,127 +258,127 @@ typedef enum { * Sleep control register */ #define AR5K_AR5210_SCR 0x4004 -#define AR5K_AR5210_SCR_SLDUR 0x0000ffff -#define AR5K_AR5210_SCR_SLE 0x00030000 -#define AR5K_AR5210_SCR_SLE_WAKE 0x00000000 -#define AR5K_AR5210_SCR_SLE_SLP 0x00010000 -#define AR5K_AR5210_SCR_SLE_ALLOW 0x00020000 +#define AR5K_AR5210_SCR_SLDUR 0x0000ffff +#define AR5K_AR5210_SCR_SLE 0x00030000 +#define AR5K_AR5210_SCR_SLE_WAKE 0x00000000 +#define AR5K_AR5210_SCR_SLE_SLP 0x00010000 +#define AR5K_AR5210_SCR_SLE_ALLOW 0x00020000 /* * Interrupt pending register */ -#define AR5K_AR5210_INTPEND 0x4008 -#define AR5K_AR5210_INTPEND_IP 0x00000001 +#define AR5K_AR5210_INTPEND 0x4008 +#define AR5K_AR5210_INTPEND_IP 0x00000001 /* * Sleep force register */ -#define AR5K_AR5210_SFR 0x400c -#define AR5K_AR5210_SFR_SF 0x00000001 +#define AR5K_AR5210_SFR 0x400c +#define AR5K_AR5210_SFR_SF 0x00000001 /* * PCI configuration register */ -#define AR5K_AR5210_PCICFG 0x4010 -#define AR5K_AR5210_PCICFG_EEAE 0x00000001 -#define AR5K_AR5210_PCICFG_CLKRUNEN 0x00000004 -#define AR5K_AR5210_PCICFG_LED_PEND 0x00000020 -#define AR5K_AR5210_PCICFG_LED_ACT 0x00000040 -#define AR5K_AR5210_PCICFG_SL_INTEN 0x00000800 -#define AR5K_AR5210_PCICFG_LED_BCTL 0x00001000 -#define AR5K_AR5210_PCICFG_SL_INPEN 0x00002800 -#define AR5K_AR5210_PCICFG_SPWR_DN 0x00010000 +#define AR5K_AR5210_PCICFG 0x4010 +#define AR5K_AR5210_PCICFG_EEAE 0x00000001 +#define AR5K_AR5210_PCICFG_CLKRUNEN 0x00000004 +#define AR5K_AR5210_PCICFG_LED_PEND 0x00000020 +#define AR5K_AR5210_PCICFG_LED_ACT 0x00000040 +#define AR5K_AR5210_PCICFG_SL_INTEN 0x00000800 +#define AR5K_AR5210_PCICFG_LED_BCTL 0x00001000 +#define AR5K_AR5210_PCICFG_SL_INPEN 0x00002800 +#define AR5K_AR5210_PCICFG_SPWR_DN 0x00010000 /* * "General Purpose Input/Output" (GPIO) control register */ -#define AR5K_AR5210_GPIOCR 0x4014 -#define AR5K_AR5210_GPIOCR_INT_ENA 0x00008000 -#define AR5K_AR5210_GPIOCR_INT_SELL 0x00000000 -#define AR5K_AR5210_GPIOCR_INT_SELH 0x00010000 -#define AR5K_AR5210_GPIOCR_IN(n) (0 << ((n) * 2)) -#define AR5K_AR5210_GPIOCR_OUT0(n) (1 << ((n) * 2)) -#define AR5K_AR5210_GPIOCR_OUT1(n) (2 << ((n) * 2)) -#define AR5K_AR5210_GPIOCR_OUT(n) (3 << ((n) * 2)) -#define AR5K_AR5210_GPIOCR_ALL(n) (3<< ((n) * 2)) -#define AR5K_AR5210_GPIOCR_INT_SEL(n) ((n) << 12) +#define AR5K_AR5210_GPIOCR 0x4014 +#define AR5K_AR5210_GPIOCR_INT_ENA 0x00008000 +#define AR5K_AR5210_GPIOCR_INT_SELL 0x00000000 +#define AR5K_AR5210_GPIOCR_INT_SELH 0x00010000 +#define AR5K_AR5210_GPIOCR_IN(n) (0 << ((n) * 2)) +#define AR5K_AR5210_GPIOCR_OUT0(n) (1 << ((n) * 2)) +#define AR5K_AR5210_GPIOCR_OUT1(n) (2 << ((n) * 2)) +#define AR5K_AR5210_GPIOCR_OUT(n) (3 << ((n) * 2)) +#define AR5K_AR5210_GPIOCR_ALL(n) (3<< ((n) * 2)) +#define AR5K_AR5210_GPIOCR_INT_SEL(n) ((n) << 12) -#define AR5K_AR5210_NUM_GPIO 6 +#define AR5K_AR5210_NUM_GPIO 6 /* * "General Purpose Input/Output" (GPIO) data output register */ -#define AR5K_AR5210_GPIODO 0x4018 +#define AR5K_AR5210_GPIODO 0x4018 /* * "General Purpose Input/Output" (GPIO) data input register */ -#define AR5K_AR5210_GPIODI 0x401c -#define AR5K_AR5210_GPIOD_MASK 0x0000002f +#define AR5K_AR5210_GPIODI 0x401c +#define AR5K_AR5210_GPIOD_MASK 0x0000002f /* * Silicon revision register */ -#define AR5K_AR5210_SREV 0x4020 -#define AR5K_AR5210_SREV_ID_M 0x000000ff -#define AR5K_AR5210_SREV_FPGA 1 -#define AR5K_AR5210_SREV_PHYPLUS 2 -#define AR5K_AR5210_SREV_PHYPLUS_MS 3 -#define AR5K_AR5210_SREV_CRETE 4 -#define AR5K_AR5210_SREV_CRETE_MS 5 -#define AR5K_AR5210_SREV_CRETE_MS23 7 -#define AR5K_AR5210_SREV_CRETE_23 8 +#define AR5K_AR5210_SREV 0x4020 +#define AR5K_AR5210_SREV_ID_M 0x000000ff +#define AR5K_AR5210_SREV_FPGA 1 +#define AR5K_AR5210_SREV_PHYPLUS 2 +#define AR5K_AR5210_SREV_PHYPLUS_MS 3 +#define AR5K_AR5210_SREV_CRETE 4 +#define AR5K_AR5210_SREV_CRETE_MS 5 +#define AR5K_AR5210_SREV_CRETE_MS23 7 +#define AR5K_AR5210_SREV_CRETE_23 8 /* * EEPROM access registers */ -#define AR5K_AR5210_EEPROM_BASE 0x6000 -#define AR5K_AR5210_EEPROM_RDATA 0x6800 -#define AR5K_AR5210_EEPROM_STATUS 0x6c00 -#define AR5K_AR5210_EEPROM_STAT_RDERR 0x0001 -#define AR5K_AR5210_EEPROM_STAT_RDDONE 0x0002 -#define AR5K_AR5210_EEPROM_STAT_WRERR 0x0004 -#define AR5K_AR5210_EEPROM_STAT_WRDONE 0x0008 +#define AR5K_AR5210_EEPROM_BASE 0x6000 +#define AR5K_AR5210_EEPROM_RDATA 0x6800 +#define AR5K_AR5210_EEPROM_STATUS 0x6c00 +#define AR5K_AR5210_EEPROM_STAT_RDERR 0x0001 +#define AR5K_AR5210_EEPROM_STAT_RDDONE 0x0002 +#define AR5K_AR5210_EEPROM_STAT_WRERR 0x0004 +#define AR5K_AR5210_EEPROM_STAT_WRDONE 0x0008 /* * AR5210 EEPROM data registers */ #define AR5K_AR5210_EEPROM_MAGIC 0x3d -#define AR5K_AR5210_EEPROM_MAGIC_VALUE 0x5aa5 +#define AR5K_AR5210_EEPROM_MAGIC_VALUE 0x5aa5 #define AR5K_AR5210_EEPROM_PROTECT 0x3f -#define AR5K_AR5210_EEPROM_PROTECT_128_191 0x80 -#define AR5K_AR5210_EEPROM_REG_DOMAIN 0xbf -#define AR5K_AR5210_EEPROM_INFO_BASE 0xc0 -#define AR5K_AR5210_EEPROM_INFO_VERSION \ +#define AR5K_AR5210_EEPROM_PROTECT_128_191 0x80 +#define AR5K_AR5210_EEPROM_REG_DOMAIN 0xbf +#define AR5K_AR5210_EEPROM_INFO_BASE 0xc0 +#define AR5K_AR5210_EEPROM_INFO_VERSION \ (AR5K_AR5210_EEPROM_INFO_BASE + 1) -#define AR5K_AR5210_EEPROM_INFO_MAX \ +#define AR5K_AR5210_EEPROM_INFO_MAX \ (0x400 - AR5K_AR5210_EEPROM_INFO_BASE) /* * PCU registers */ -#define AR5K_AR5210_PCU_MIN 0x8000 -#define AR5K_AR5210_PCU_MAX 0x8fff +#define AR5K_AR5210_PCU_MIN 0x8000 +#define AR5K_AR5210_PCU_MAX 0x8fff /* * First station id register (MAC address in lower 32 bits) */ -#define AR5K_AR5210_STA_ID0 0x8000 +#define AR5K_AR5210_STA_ID0 0x8000 /* * Second station id register (MAC address in upper 16 bits) */ -#define AR5K_AR5210_STA_ID1 0x8004 -#define AR5K_AR5210_STA_ID1_AP 0x00010000 -#define AR5K_AR5210_STA_ID1_ADHOC 0x00020000 -#define AR5K_AR5210_STA_ID1_PWR_SV 0x00040000 -#define AR5K_AR5210_STA_ID1_NO_KEYSRCH 0x00080000 -#define AR5K_AR5210_STA_ID1_NO_PSPOLL 0x00100000 -#define AR5K_AR5210_STA_ID1_PCF 0x00200000 -#define AR5K_AR5210_STA_ID1_DESC_ANTENNA 0x00400000 +#define AR5K_AR5210_STA_ID1 0x8004 +#define AR5K_AR5210_STA_ID1_AP 0x00010000 +#define AR5K_AR5210_STA_ID1_ADHOC 0x00020000 +#define AR5K_AR5210_STA_ID1_PWR_SV 0x00040000 +#define AR5K_AR5210_STA_ID1_NO_KEYSRCH 0x00080000 +#define AR5K_AR5210_STA_ID1_NO_PSPOLL 0x00100000 +#define AR5K_AR5210_STA_ID1_PCF 0x00200000 +#define AR5K_AR5210_STA_ID1_DESC_ANTENNA 0x00400000 #define AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA 0x00800000 -#define AR5K_AR5210_STA_ID1_ACKCTS_6MB 0x01000000 +#define AR5K_AR5210_STA_ID1_ACKCTS_6MB 0x01000000 /* * First BSSID register (MAC address, lower 32bits) @@ -390,65 +390,65 @@ typedef enum { * * AID: Association ID */ -#define AR5K_AR5210_BSS_ID1 0x800c -#define AR5K_AR5210_BSS_ID1_AID 0xffff0000 -#define AR5K_AR5210_BSS_ID1_AID_S 16 +#define AR5K_AR5210_BSS_ID1 0x800c +#define AR5K_AR5210_BSS_ID1_AID 0xffff0000 +#define AR5K_AR5210_BSS_ID1_AID_S 16 /* * Backoff slot time register */ -#define AR5K_AR5210_SLOT_TIME 0x8010 +#define AR5K_AR5210_SLOT_TIME 0x8010 /* * ACK/CTS timeout register */ -#define AR5K_AR5210_TIME_OUT 0x8014 -#define AR5K_AR5210_TIME_OUT_ACK 0x00001fff +#define AR5K_AR5210_TIME_OUT 0x8014 +#define AR5K_AR5210_TIME_OUT_ACK 0x00001fff #define AR5K_AR5210_TIME_OUT_ACK_S 0 -#define AR5K_AR5210_TIME_OUT_CTS 0x1fff0000 -#define AR5K_AR5210_TIME_OUT_CTS_S 16 +#define AR5K_AR5210_TIME_OUT_CTS 0x1fff0000 +#define AR5K_AR5210_TIME_OUT_CTS_S 16 /* * RSSI threshold register */ -#define AR5K_AR5210_RSSI_THR 0x8018 -#define AR5K_AR5210_RSSI_THR_BM_THR 0x00000700 +#define AR5K_AR5210_RSSI_THR 0x8018 +#define AR5K_AR5210_RSSI_THR_BM_THR 0x00000700 #define AR5K_AR5210_RSSI_THR_BM_THR_S 8 /* * Retry limit register */ -#define AR5K_AR5210_RETRY_LMT 0x801c -#define AR5K_AR5210_RETRY_LMT_SH_RETRY 0x0000000f -#define AR5K_AR5210_RETRY_LMT_SH_RETRY_S 0 -#define AR5K_AR5210_RETRY_LMT_LG_RETRY 0x000000f0 -#define AR5K_AR5210_RETRY_LMT_LG_RETRY_S 4 -#define AR5K_AR5210_RETRY_LMT_SSH_RETRY 0x00003f00 +#define AR5K_AR5210_RETRY_LMT 0x801c +#define AR5K_AR5210_RETRY_LMT_SH_RETRY 0x0000000f +#define AR5K_AR5210_RETRY_LMT_SH_RETRY_S 0 +#define AR5K_AR5210_RETRY_LMT_LG_RETRY 0x000000f0 +#define AR5K_AR5210_RETRY_LMT_LG_RETRY_S 4 +#define AR5K_AR5210_RETRY_LMT_SSH_RETRY 0x00003f00 #define AR5K_AR5210_RETRY_LMT_SSH_RETRY_S 8 -#define AR5K_AR5210_RETRY_LMT_SLG_RETRY 0x000fc000 +#define AR5K_AR5210_RETRY_LMT_SLG_RETRY 0x000fc000 #define AR5K_AR5210_RETRY_LMT_SLG_RETRY_S 14 -#define AR5K_AR5210_RETRY_LMT_CW_MIN 0x3ff00000 -#define AR5K_AR5210_RETRY_LMT_CW_MIN_S 20 +#define AR5K_AR5210_RETRY_LMT_CW_MIN 0x3ff00000 +#define AR5K_AR5210_RETRY_LMT_CW_MIN_S 20 /* * Transmit latency register */ -#define AR5K_AR5210_USEC 0x8020 -#define AR5K_AR5210_USEC_1 0x0000007f -#define AR5K_AR5210_USEC_1_S 0 -#define AR5K_AR5210_USEC_32 0x00003f80 -#define AR5K_AR5210_USEC_32_S 7 -#define AR5K_AR5210_USEC_TX_LATENCY 0x000fc000 -#define AR5K_AR5210_USEC_TX_LATENCY_S 14 -#define AR5K_AR5210_USEC_RX_LATENCY 0x03f00000 -#define AR5K_AR5210_USEC_RX_LATENCY_S 20 +#define AR5K_AR5210_USEC 0x8020 +#define AR5K_AR5210_USEC_1 0x0000007f +#define AR5K_AR5210_USEC_1_S 0 +#define AR5K_AR5210_USEC_32 0x00003f80 +#define AR5K_AR5210_USEC_32_S 7 +#define AR5K_AR5210_USEC_TX_LATENCY 0x000fc000 +#define AR5K_AR5210_USEC_TX_LATENCY_S 14 +#define AR5K_AR5210_USEC_RX_LATENCY 0x03f00000 +#define AR5K_AR5210_USEC_RX_LATENCY_S 20 /* * PCU beacon control register */ -#define AR5K_AR5210_BEACON 0x8024 -#define AR5K_AR5210_BEACON_PERIOD 0x0000ffff -#define AR5K_AR5210_BEACON_PERIOD_S 0 +#define AR5K_AR5210_BEACON 0x8024 +#define AR5K_AR5210_BEACON_PERIOD 0x0000ffff +#define AR5K_AR5210_BEACON_PERIOD_S 0 #define AR5K_AR5210_BEACON_TIM 0x007f0000 #define AR5K_AR5210_BEACON_TIM_S 16 #define AR5K_AR5210_BEACON_EN 0x00800000 @@ -462,56 +462,56 @@ typedef enum { /* * Next beacon time register */ -#define AR5K_AR5210_TIMER0 0x802c +#define AR5K_AR5210_TIMER0 0x802c /* * Next DMA beacon alert register */ -#define AR5K_AR5210_TIMER1 0x8030 +#define AR5K_AR5210_TIMER1 0x8030 /* * Next software beacon alert register */ -#define AR5K_AR5210_TIMER2 0x8034 +#define AR5K_AR5210_TIMER2 0x8034 /* * Next ATIM window time register */ -#define AR5K_AR5210_TIMER3 0x8038 +#define AR5K_AR5210_TIMER3 0x8038 /* * First inter frame spacing register (IFS) */ -#define AR5K_AR5210_IFS0 0x8040 -#define AR5K_AR5210_IFS0_SIFS 0x000007ff -#define AR5K_AR5210_IFS0_SIFS_S 0 -#define AR5K_AR5210_IFS0_DIFS 0x007ff800 -#define AR5K_AR5210_IFS0_DIFS_S 11 +#define AR5K_AR5210_IFS0 0x8040 +#define AR5K_AR5210_IFS0_SIFS 0x000007ff +#define AR5K_AR5210_IFS0_SIFS_S 0 +#define AR5K_AR5210_IFS0_DIFS 0x007ff800 +#define AR5K_AR5210_IFS0_DIFS_S 11 /* * Second inter frame spacing register (IFS) */ -#define AR5K_AR5210_IFS1 0x8044 -#define AR5K_AR5210_IFS1_PIFS 0x00000fff -#define AR5K_AR5210_IFS1_PIFS_S 0 -#define AR5K_AR5210_IFS1_EIFS 0x03fff000 -#define AR5K_AR5210_IFS1_EIFS_S 12 -#define AR5K_AR5210_IFS1_CS_EN 0x04000000 +#define AR5K_AR5210_IFS1 0x8044 +#define AR5K_AR5210_IFS1_PIFS 0x00000fff +#define AR5K_AR5210_IFS1_PIFS_S 0 +#define AR5K_AR5210_IFS1_EIFS 0x03fff000 +#define AR5K_AR5210_IFS1_EIFS_S 12 +#define AR5K_AR5210_IFS1_CS_EN 0x04000000 /* * CFP duration register */ -#define AR5K_AR5210_CFP_DUR 0x8048 +#define AR5K_AR5210_CFP_DUR 0x8048 /* * Receive filter register */ -#define AR5K_AR5210_RX_FILTER 0x804c -#define AR5K_AR5210_RX_FILTER_UNICAST 0x00000001 +#define AR5K_AR5210_RX_FILTER 0x804c +#define AR5K_AR5210_RX_FILTER_UNICAST 0x00000001 #define AR5K_AR5210_RX_FILTER_MULTICAST 0x00000002 #define AR5K_AR5210_RX_FILTER_BROADCAST 0x00000004 -#define AR5K_AR5210_RX_FILTER_CONTROL 0x00000008 -#define AR5K_AR5210_RX_FILTER_BEACON 0x00000010 +#define AR5K_AR5210_RX_FILTER_CONTROL 0x00000008 +#define AR5K_AR5210_RX_FILTER_BEACON 0x00000010 #define AR5K_AR5210_RX_FILTER_PROMISC 0x00000020 /* @@ -547,21 +547,21 @@ typedef enum { /* * PCU control register */ -#define AR5K_AR5210_DIAG_SW 0x8068 -#define AR5K_AR5210_DIAG_SW_DIS_WEP_ACK 0x00000001 -#define AR5K_AR5210_DIAG_SW_DIS_ACK 0x00000002 -#define AR5K_AR5210_DIAG_SW_DIS_CTS 0x00000004 -#define AR5K_AR5210_DIAG_SW_DIS_ENC 0x00000008 -#define AR5K_AR5210_DIAG_SW_DIS_DEC 0x00000010 -#define AR5K_AR5210_DIAG_SW_DIS_TX 0x00000020 -#define AR5K_AR5210_DIAG_SW_DIS_RX 0x00000040 -#define AR5K_AR5210_DIAG_SW_LOOP_BACK 0x00000080 -#define AR5K_AR5210_DIAG_SW_CORR_FCS 0x00000100 -#define AR5K_AR5210_DIAG_SW_CHAN_INFO 0x00000200 -#define AR5K_AR5210_DIAG_SW_EN_SCRAM_SEED 0x00000400 -#define AR5K_AR5210_DIAG_SW_SCVRAM_SEED 0x0003f800 -#define AR5K_AR5210_DIAG_SW_DIS_SEQ_INC 0x00040000 -#define AR5K_AR5210_DIAG_SW_FRAME_NV0 0x00080000 +#define AR5K_AR5210_DIAG_SW 0x8068 +#define AR5K_AR5210_DIAG_SW_DIS_WEP_ACK 0x00000001 +#define AR5K_AR5210_DIAG_SW_DIS_ACK 0x00000002 +#define AR5K_AR5210_DIAG_SW_DIS_CTS 0x00000004 +#define AR5K_AR5210_DIAG_SW_DIS_ENC 0x00000008 +#define AR5K_AR5210_DIAG_SW_DIS_DEC 0x00000010 +#define AR5K_AR5210_DIAG_SW_DIS_TX 0x00000020 +#define AR5K_AR5210_DIAG_SW_DIS_RX 0x00000040 +#define AR5K_AR5210_DIAG_SW_LOOP_BACK 0x00000080 +#define AR5K_AR5210_DIAG_SW_CORR_FCS 0x00000100 +#define AR5K_AR5210_DIAG_SW_CHAN_INFO 0x00000200 +#define AR5K_AR5210_DIAG_SW_EN_SCRAM_SEED 0x00000400 +#define AR5K_AR5210_DIAG_SW_SCVRAM_SEED 0x0003f800 +#define AR5K_AR5210_DIAG_SW_DIS_SEQ_INC 0x00040000 +#define AR5K_AR5210_DIAG_SW_FRAME_NV0 0x00080000 /* * TSF (clock) register (lower 32 bits) @@ -571,31 +571,31 @@ typedef enum { /* * TSF (clock) register (higher 32 bits) */ -#define AR5K_AR5210_TSF_U32 0x8070 +#define AR5K_AR5210_TSF_U32 0x8070 /* * Last beacon timestamp register */ -#define AR5K_AR5210_LAST_TSTP 0x8080 +#define AR5K_AR5210_LAST_TSTP 0x8080 /* * Retry count register */ -#define AR5K_AR5210_RETRY_CNT 0x8084 -#define AR5K_AR5210_RETRY_CNT_SSH 0x0000003f -#define AR5K_AR5210_RETRY_CNT_SLG 0x00000fc0 +#define AR5K_AR5210_RETRY_CNT 0x8084 +#define AR5K_AR5210_RETRY_CNT_SSH 0x0000003f +#define AR5K_AR5210_RETRY_CNT_SLG 0x00000fc0 /* * Back-off status register */ -#define AR5K_AR5210_BACKOFF 0x8088 -#define AR5K_AR5210_BACKOFF_CW 0x000003ff -#define AR5K_AR5210_BACKOFF_CNT 0x03ff0000 +#define AR5K_AR5210_BACKOFF 0x8088 +#define AR5K_AR5210_BACKOFF_CW 0x000003ff +#define AR5K_AR5210_BACKOFF_CNT 0x03ff0000 /* * NAV register (current) */ -#define AR5K_AR5210_NAV 0x808c +#define AR5K_AR5210_NAV 0x808c /* * RTS success register @@ -626,14 +626,14 @@ typedef enum { * Key table (WEP) register */ #define AR5K_AR5210_KEYTABLE_0 0x9000 -#define AR5K_AR5210_KEYTABLE(n) (AR5K_AR5210_KEYTABLE_0 + ((n) * 32)) -#define AR5K_AR5210_KEYTABLE_TYPE_40 0x00000000 -#define AR5K_AR5210_KEYTABLE_TYPE_104 0x00000001 -#define AR5K_AR5210_KEYTABLE_TYPE_128 0x00000003 -#define AR5K_AR5210_KEYTABLE_VALID 0x00008000 +#define AR5K_AR5210_KEYTABLE(n) (AR5K_AR5210_KEYTABLE_0 + ((n) * 32)) +#define AR5K_AR5210_KEYTABLE_TYPE_40 0x00000000 +#define AR5K_AR5210_KEYTABLE_TYPE_104 0x00000001 +#define AR5K_AR5210_KEYTABLE_TYPE_128 0x00000003 +#define AR5K_AR5210_KEYTABLE_VALID 0x00008000 -#define AR5K_AR5210_KEYTABLE_SIZE 64 -#define AR5K_AR5210_KEYCACHE_SIZE 8 +#define AR5K_AR5210_KEYTABLE_SIZE 64 +#define AR5K_AR5210_KEYCACHE_SIZE 8 /* * PHY register @@ -643,33 +643,33 @@ typedef enum { /* * PHY frame control register */ -#define AR5K_AR5210_PHY_FC 0x9804 -#define AR5K_AR5210_PHY_FC_TURBO_MODE 0x00000001 -#define AR5K_AR5210_PHY_FC_TURBO_SHORT 0x00000002 -#define AR5K_AR5210_PHY_FC_TIMING_ERR 0x01000000 -#define AR5K_AR5210_PHY_FC_PARITY_ERR 0x02000000 -#define AR5K_AR5210_PHY_FC_ILLRATE_ERR 0x04000000 -#define AR5K_AR5210_PHY_FC_ILLLEN_ERR 0x08000000 -#define AR5K_AR5210_PHY_FC_SERVICE_ERR 0x20000000 -#define AR5K_AR5210_PHY_FC_TXURN_ERR 0x40000000 +#define AR5K_AR5210_PHY_FC 0x9804 +#define AR5K_AR5210_PHY_FC_TURBO_MODE 0x00000001 +#define AR5K_AR5210_PHY_FC_TURBO_SHORT 0x00000002 +#define AR5K_AR5210_PHY_FC_TIMING_ERR 0x01000000 +#define AR5K_AR5210_PHY_FC_PARITY_ERR 0x02000000 +#define AR5K_AR5210_PHY_FC_ILLRATE_ERR 0x04000000 +#define AR5K_AR5210_PHY_FC_ILLLEN_ERR 0x08000000 +#define AR5K_AR5210_PHY_FC_SERVICE_ERR 0x20000000 +#define AR5K_AR5210_PHY_FC_TXURN_ERR 0x40000000 /* * PHY agility command register */ -#define AR5K_AR5210_PHY_AGC 0x9808 -#define AR5K_AR5210_PHY_AGC_DISABLE 0x08000000 +#define AR5K_AR5210_PHY_AGC 0x9808 +#define AR5K_AR5210_PHY_AGC_DISABLE 0x08000000 /* * PHY chip revision register */ -#define AR5K_AR5210_PHY_CHIP_ID 0x9818 +#define AR5K_AR5210_PHY_CHIP_ID 0x9818 /* * PHY activation register */ #define AR5K_AR5210_PHY_ACTIVE 0x981c -#define AR5K_AR5210_PHY_ENABLE 0x00000001 -#define AR5K_AR5210_PHY_DISABLE 0x00000002 +#define AR5K_AR5210_PHY_ENABLE 0x00000001 +#define AR5K_AR5210_PHY_DISABLE 0x00000002 /* * PHY agility control register diff --git a/sys/dev/ic/ar5210var.h b/sys/dev/ic/ar5210var.h index ac67c93bcdb..8a8a2ac4092 100644 --- a/sys/dev/ic/ar5210var.h +++ b/sys/dev/ic/ar5210var.h @@ -1,4 +1,4 @@ -/* $OpenBSD: ar5210var.h,v 1.2 2004/11/02 14:05:49 reyk Exp $ */ +/* $OpenBSD: ar5210var.h,v 1.3 2004/11/03 16:40:46 reyk Exp $ */ /* * Copyright (c) 2004 Reyk Floeter <reyk@vantronix.net>. @@ -43,16 +43,15 @@ #define AR5K_AR5210_TX_NUM_QUEUES 2 #if BYTE_ORDER == BIG_ENDIAN -#define AR5K_AR5210_INIT_CFG ( \ - AR5K_AR5210_CFG_SWTD | AR5K_AR5210_CFG_SWTB | \ - AR5K_AR5210_CFG_SWRD | AR5K_AR5210_CFG_SWRB | \ +#define AR5K_AR5210_INIT_CFG ( \ + AR5K_AR5210_CFG_SWTD | AR5K_AR5210_CFG_SWTB | \ + AR5K_AR5210_CFG_SWRD | AR5K_AR5210_CFG_SWRB | \ AR5K_AR5210_CFG_SWRG \ ) #else #define AR5K_AR5210_INIT_CFG 0x00000000 #endif - /* * Internal RX/TX descriptor structures * (rX: reserved fields possibily used by future versions of the ar5k chipset) @@ -89,87 +88,87 @@ struct ar5k_ar5210_rx_status { * Second word */ u_int32_t done:1; - u_int32_t frame_receive_ok:1; - u_int32_t crc_error:1; - u_int32_t fifo_overrun:1; - u_int32_t decrypt_crc_error:1; - u_int32_t phy_error:3; - u_int32_t key_index_valid:1; - u_int32_t key_index:6; - u_int32_t receive_timestamp:13; - u_int32_t key_cache_miss:1; - u_int32_t r3:3; + u_int32_t frame_receive_ok:1; + u_int32_t crc_error:1; + u_int32_t fifo_overrun:1; + u_int32_t decrypt_crc_error:1; + u_int32_t phy_error:3; + u_int32_t key_index_valid:1; + u_int32_t key_index:6; + u_int32_t receive_timestamp:13; + u_int32_t key_cache_miss:1; + u_int32_t r3:3; } __attribute__ ((__packed__)); #define AR5K_AR5210_DESC_RX_PHY_ERROR_NONE 0x00 #define AR5K_AR5210_DESC_RX_PHY_ERROR_TIMING 0x20 -#define AR5K_AR5210_DESC_RX_PHY_ERROR_PARITY 0x40 -#define AR5K_AR5210_DESC_RX_PHY_ERROR_RATE 0x60 -#define AR5K_AR5210_DESC_RX_PHY_ERROR_LENGTH 0x80 -#define AR5K_AR5210_DESC_RX_PHY_ERROR_64QAM 0xa0 -#define AR5K_AR5210_DESC_RX_PHY_ERROR_SERVICE 0xc0 -#define AR5K_AR5210_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0 +#define AR5K_AR5210_DESC_RX_PHY_ERROR_PARITY 0x40 +#define AR5K_AR5210_DESC_RX_PHY_ERROR_RATE 0x60 +#define AR5K_AR5210_DESC_RX_PHY_ERROR_LENGTH 0x80 +#define AR5K_AR5210_DESC_RX_PHY_ERROR_64QAM 0xa0 +#define AR5K_AR5210_DESC_RX_PHY_ERROR_SERVICE 0xc0 +#define AR5K_AR5210_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0 struct ar5k_ar5210_tx_desc { /* * First word */ - u_int32_t frame_len:12; - u_int32_t header_len:6; - u_int32_t xmit_rate:4; - u_int32_t rts_cts_enable:1; - u_int32_t long_packet:1; - u_int32_t clear_dest_mask:1; - u_int32_t ant_mode_xmit:1; - u_int32_t frame_type:3; - u_int32_t inter_req:1; - u_int32_t encrypt_key_valid:1; - u_int32_t r1:1; + u_int32_t frame_len:12; + u_int32_t header_len:6; + u_int32_t xmit_rate:4; + u_int32_t rts_cts_enable:1; + u_int32_t long_packet:1; + u_int32_t clear_dest_mask:1; + u_int32_t ant_mode_xmit:1; + u_int32_t frame_type:3; + u_int32_t inter_req:1; + u_int32_t encrypt_key_valid:1; + u_int32_t r1:1; /* * Second word */ - u_int32_t buf_len:12; - u_int32_t more:1; - u_int32_t encrypt_key_index:6; - u_int32_t rts_duration:13; + u_int32_t buf_len:12; + u_int32_t more:1; + u_int32_t encrypt_key_index:6; + u_int32_t rts_duration:13; } __attribute__ ((__packed__)); -#define AR5K_AR5210_DESC_TX_XMIT_RATE_6 0xb -#define AR5K_AR5210_DESC_TX_XMIT_RATE_9 0xf +#define AR5K_AR5210_DESC_TX_XMIT_RATE_6 0xb +#define AR5K_AR5210_DESC_TX_XMIT_RATE_9 0xf #define AR5K_AR5210_DESC_TX_XMIT_RATE_12 0xa -#define AR5K_AR5210_DESC_TX_XMIT_RATE_18 0xe -#define AR5K_AR5210_DESC_TX_XMIT_RATE_24 0x9 -#define AR5K_AR5210_DESC_TX_XMIT_RATE_36 0xd -#define AR5K_AR5210_DESC_TX_XMIT_RATE_48 0x8 -#define AR5K_AR5210_DESC_TX_XMIT_RATE_54 0xc +#define AR5K_AR5210_DESC_TX_XMIT_RATE_18 0xe +#define AR5K_AR5210_DESC_TX_XMIT_RATE_24 0x9 +#define AR5K_AR5210_DESC_TX_XMIT_RATE_36 0xd +#define AR5K_AR5210_DESC_TX_XMIT_RATE_48 0x8 +#define AR5K_AR5210_DESC_TX_XMIT_RATE_54 0xc -#define AR5K_AR5210_DESC_TX_FRAME_TYPE_NORMAL 0x00 -#define AR5K_AR5210_DESC_TX_FRAME_TYPE_ATIM 0x04 -#define AR5K_AR5210_DESC_TX_FRAME_TYPE_PSPOLL 0x08 +#define AR5K_AR5210_DESC_TX_FRAME_TYPE_NORMAL 0x00 +#define AR5K_AR5210_DESC_TX_FRAME_TYPE_ATIM 0x04 +#define AR5K_AR5210_DESC_TX_FRAME_TYPE_PSPOLL 0x08 #define AR5K_AR5210_DESC_TX_FRAME_TYPE_NO_DELAY 0x0c -#define AR5K_AR5210_DESC_TX_FRAME_TYPE_PIFS 0x10 +#define AR5K_AR5210_DESC_TX_FRAME_TYPE_PIFS 0x10 struct ar5k_ar5210_tx_status { /* * First word */ - u_int32_t frame_xmit_ok:1; - u_int32_t excessive_retries:1; - u_int32_t fifo_underrun:1; - u_int32_t filtered:1; - u_int32_t short_retry_count:4; - u_int32_t long_retry_count:4; - u_int32_t r1:4; - u_int32_t send_timestamp:16; + u_int32_t frame_xmit_ok:1; + u_int32_t excessive_retries:1; + u_int32_t fifo_underrun:1; + u_int32_t filtered:1; + u_int32_t short_retry_count:4; + u_int32_t long_retry_count:4; + u_int32_t r1:4; + u_int32_t send_timestamp:16; /* * Second word */ - u_int32_t done:1; - u_int32_t seq_num:12; - u_int32_t ack_sig_strength:8; - u_int32_t r2:11; + u_int32_t done:1; + u_int32_t seq_num:12; + u_int32_t ack_sig_strength:8; + u_int32_t r2:11; } __attribute__ ((__packed__)); /* @@ -181,44 +180,44 @@ extern ar5k_attach_t ar5k_ar5210_attach; * Initial mode settings ("Base Mode" or "Turbo Mode") */ -#define AR5K_AR5210_INI_MODE(_aifs) { \ - { AR5K_AR5210_SLOT_TIME, \ - AR5K_INIT_SLOT_TIME, \ - AR5K_INIT_SLOT_TIME_TURBO }, \ - { AR5K_AR5210_SLOT_TIME, \ - AR5K_INIT_ACK_CTS_TIMEOUT, \ - AR5K_INIT_ACK_CTS_TIMEOUT_TURBO }, \ - { AR5K_AR5210_USEC, \ - AR5K_INIT_TRANSMIT_LATENCY, \ - AR5K_INIT_TRANSMIT_LATENCY_TURBO}, \ - { AR5K_AR5210_IFS0, \ - ((AR5K_INIT_SIFS + (_aifs) * AR5K_INIT_SLOT_TIME) \ - << AR5K_AR5210_IFS0_DIFS_S) | AR5K_INIT_SIFS, \ +#define AR5K_AR5210_INI_MODE(_aifs) { \ + { AR5K_AR5210_SLOT_TIME, \ + AR5K_INIT_SLOT_TIME, \ + AR5K_INIT_SLOT_TIME_TURBO }, \ + { AR5K_AR5210_SLOT_TIME, \ + AR5K_INIT_ACK_CTS_TIMEOUT, \ + AR5K_INIT_ACK_CTS_TIMEOUT_TURBO }, \ + { AR5K_AR5210_USEC, \ + AR5K_INIT_TRANSMIT_LATENCY, \ + AR5K_INIT_TRANSMIT_LATENCY_TURBO}, \ + { AR5K_AR5210_IFS0, \ + ((AR5K_INIT_SIFS + (_aifs) * AR5K_INIT_SLOT_TIME) \ + << AR5K_AR5210_IFS0_DIFS_S) | AR5K_INIT_SIFS, \ ((AR5K_INIT_SIFS_TURBO + (_aifs) * AR5K_INIT_SLOT_TIME_TURBO) \ - << AR5K_AR5210_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO }, \ - { AR5K_AR5210_IFS1, \ - AR5K_INIT_PROTO_TIME_CNTRL, \ - AR5K_INIT_PROTO_TIME_CNTRL_TURBO }, \ - { AR5K_AR5210_PHY(17), \ - (AR5K_REG_READ(AR5K_AR5210_PHY(17)) & ~0x7F) | 0x1C, \ - (AR5K_REG_READ(AR5K_AR5210_PHY(17)) & ~0x7F) | 0x38 }, \ - { AR5K_AR5210_PHY_FC, \ + << AR5K_AR5210_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO }, \ + { AR5K_AR5210_IFS1, \ + AR5K_INIT_PROTO_TIME_CNTRL, \ + AR5K_INIT_PROTO_TIME_CNTRL_TURBO }, \ + { AR5K_AR5210_PHY(17), \ + (AR5K_REG_READ(AR5K_AR5210_PHY(17)) & ~0x7F) | 0x1C, \ + (AR5K_REG_READ(AR5K_AR5210_PHY(17)) & ~0x7F) | 0x38 }, \ + { AR5K_AR5210_PHY_FC, \ \ - AR5K_AR5210_PHY_FC_SERVICE_ERR | \ - AR5K_AR5210_PHY_FC_TXURN_ERR | \ - AR5K_AR5210_PHY_FC_ILLLEN_ERR | \ - AR5K_AR5210_PHY_FC_ILLRATE_ERR | \ - AR5K_AR5210_PHY_FC_PARITY_ERR | \ - AR5K_AR5210_PHY_FC_TIMING_ERR | 0x1020, \ + AR5K_AR5210_PHY_FC_SERVICE_ERR | \ + AR5K_AR5210_PHY_FC_TXURN_ERR | \ + AR5K_AR5210_PHY_FC_ILLLEN_ERR | \ + AR5K_AR5210_PHY_FC_ILLRATE_ERR | \ + AR5K_AR5210_PHY_FC_PARITY_ERR | \ + AR5K_AR5210_PHY_FC_TIMING_ERR | 0x1020, \ \ - AR5K_AR5210_PHY_FC_SERVICE_ERR | \ - AR5K_AR5210_PHY_FC_TXURN_ERR | \ - AR5K_AR5210_PHY_FC_ILLLEN_ERR | \ - AR5K_AR5210_PHY_FC_ILLRATE_ERR | \ - AR5K_AR5210_PHY_FC_PARITY_ERR | \ - AR5K_AR5210_PHY_FC_TURBO_MODE | \ + AR5K_AR5210_PHY_FC_SERVICE_ERR | \ + AR5K_AR5210_PHY_FC_TXURN_ERR | \ + AR5K_AR5210_PHY_FC_ILLLEN_ERR | \ + AR5K_AR5210_PHY_FC_ILLRATE_ERR | \ + AR5K_AR5210_PHY_FC_PARITY_ERR | \ + AR5K_AR5210_PHY_FC_TURBO_MODE | \ AR5K_AR5210_PHY_FC_TURBO_SHORT | \ - AR5K_AR5210_PHY_FC_TIMING_ERR | 0x2020 }, \ + AR5K_AR5210_PHY_FC_TIMING_ERR | 0x2020 }, \ } /* @@ -226,7 +225,7 @@ extern ar5k_attach_t ar5k_ar5210_attach; * card at boot time and after each reset. */ -#define AR5K_AR5210_INI { \ +#define AR5K_AR5210_INI { \ /* PCU and MAC registers */ \ { AR5K_AR5210_TXDP0, 0 }, \ { AR5K_AR5210_TXDP1, 0 }, \ @@ -298,7 +297,7 @@ extern ar5k_attach_t ar5k_ar5210_attach; { AR5K_AR5210_PHY(67), 0x00800000 }, \ { AR5K_AR5210_PHY(68), 0x00000003 }, \ /* BB gain table (64bytes) */ \ - { AR5K_AR5210_BB_GAIN(0), 0x00000000 }, \ + { AR5K_AR5210_BB_GAIN(0), 0x00000000 }, \ { AR5K_AR5210_BB_GAIN(0x01), 0x00000020 }, \ { AR5K_AR5210_BB_GAIN(0x02), 0x00000010 }, \ { AR5K_AR5210_BB_GAIN(0x03), 0x00000030 }, \ diff --git a/sys/dev/ic/ar5xxx.c b/sys/dev/ic/ar5xxx.c index bb3fc622e4c..13337399494 100644 --- a/sys/dev/ic/ar5xxx.c +++ b/sys/dev/ic/ar5xxx.c @@ -1,4 +1,4 @@ -/* $OpenBSD: ar5xxx.c,v 1.2 2004/11/02 14:05:49 reyk Exp $ */ +/* $OpenBSD: ar5xxx.c,v 1.3 2004/11/03 16:40:46 reyk Exp $ */ /* * Copyright (c) 2004 Reyk Floeter <reyk@vantronix.net>. @@ -34,18 +34,12 @@ #include <dev/ic/ar5xxx.h> -#ifdef AR5K_SUPPORT_AR5210 extern ar5k_attach_t ar5k_ar5210_attach; -#endif #ifdef notyet -#ifdef AR5K_SUPPORT_AR5211 extern ar5k_attach_t ar5k_ar5211_attach; -#endif -#ifdef AR5K_SUPPORT_AR5212 extern ar5k_attach_t ar5k_ar5212_attach; #endif -#endif static const struct ieee80211_regchannel ar5k_5ghz_channels[] = IEEE80211_CHANNELS_5GHZ; @@ -54,24 +48,21 @@ static const struct ieee80211_regchannel ar5k_2ghz_channels[] = IEEE80211_CHANNELS_2GHZ; static const struct { - u_int16_t vendor; - u_int16_t device; + u_int16_t vendor; + u_int16_t device; const char * name; - ar5k_attach_t (*attach); + ar5k_attach_t (*attach); } ar5k_known_products[] = { /* * From pcidevs_data.h */ -#ifdef AR5K_SUPPORT_AR5210 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210, "AR5210 Wireless LAN", ar5k_ar5210_attach }, { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210_AP, "AR5210 Wireless LAN (AP11)", ar5k_ar5210_attach }, { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5210_DEFAULT, "AR5210 Wireless LAN (no eeprom)", ar5k_ar5210_attach }, -#endif #ifdef notyet -#ifdef AR5K_SUPPORT_AR5211 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211, "AR5211 Wireless LAN", ar5k_ar5211_attach }, { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211_DEFAULT, @@ -82,8 +73,6 @@ static const struct { "AR5211 Wireless LAN Reference Card", ar5k_ar5211_attach }, { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5211_LEGACY, "AR5211 Wireless LAN Reference Card", ar5k_ar5211_attach }, -#endif -#ifdef AR5K_SUPPORT_AR5212 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212, "AR5212 Wireless LAN", ar5k_ar5212_attach }, { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_DEFAULT, @@ -91,7 +80,6 @@ static const struct { { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5212_FPGA, "AR5212 Wireless LAN Reference Card", ar5k_ar5212_attach }, #endif -#endif }; /* @@ -107,13 +95,13 @@ ath_hal_probe(vendor, device) /* * Perform a linear search on the table of supported devices */ - for(i = 0; i < AR5K_ELEMENTS(ar5k_known_products); i++) { - if(vendor == ar5k_known_products[i].vendor && + for (i = 0; i < AR5K_ELEMENTS(ar5k_known_products); i++) { + if (vendor == ar5k_known_products[i].vendor && device == ar5k_known_products[i].device) - return(ar5k_known_products[i].name); + return (ar5k_known_products[i].name); } - return(NULL); + return (NULL); } /* @@ -136,27 +124,28 @@ ath_hal_attach(device, sc, st, sh, status) u_int8_t mac[IEEE80211_ADDR_LEN]; int i; - *status = -EINVAL; + *status = EINVAL; /* * Call the chipset-dependent attach routine by device id */ - for(i = 0; i < AR5K_ELEMENTS(ar5k_known_products); i++) { - if(device == ar5k_known_products[i].device && + for (i = 0; i < AR5K_ELEMENTS(ar5k_known_products); i++) { + if (device == ar5k_known_products[i].device && ar5k_known_products[i].attach != NULL) attach = ar5k_known_products[i].attach; } - if(attach == NULL) { - *status = -ENXIO; + if (attach == NULL) { + *status = ENXIO; AR5K_PRINTF("device not supported\n"); - return(NULL); + return (NULL); } - if((hal = malloc(sizeof(struct ath_hal), M_DEVBUF, M_NOWAIT)) == NULL) { - *status = -ENOMEM; + if ((hal = malloc(sizeof(struct ath_hal), + M_DEVBUF, M_NOWAIT)) == NULL) { + *status = ENOMEM; AR5K_PRINTF("out of memory\n"); - return(NULL); + return (NULL); } bzero(hal, sizeof(struct ath_hal)); @@ -183,41 +172,41 @@ ath_hal_attach(device, sc, st, sh, status) hal->ah_limit_tx_retries = AR5K_INIT_TX_RETRY; hal->ah_software_retry = AH_FALSE; - if(attach(device, hal, st, sh, status) == NULL) + if (attach(device, hal, st, sh, status) == NULL) goto failed; /* * Get card capabilities, values, ... */ - if(hal->ah_get_capabilities(hal) != AH_TRUE) { + if (hal->ah_get_capabilities(hal) != AH_TRUE) { AR5K_PRINTF("unable to get device capabilities\n"); goto failed; } - if((*status = ar5k_eeprom_read_mac(hal, mac)) != HAL_OK) { + if ((*status = ar5k_eeprom_read_mac(hal, mac)) != HAL_OK) { AR5K_PRINTF("unable to read address from EEPROM\n"); goto failed; } hal->ah_setMacAddress(hal, mac); - if(hal->ah_capabilities.cap_mode & HAL_MODE_11A) + if (hal->ah_capabilities.cap_mode & HAL_MODE_11A) ar5k_rt_copy(&hal->ah_rt_11a, &rt_11a); - if(hal->ah_capabilities.cap_mode & HAL_MODE_11B) + if (hal->ah_capabilities.cap_mode & HAL_MODE_11B) ar5k_rt_copy(&hal->ah_rt_11b, &rt_11b); - if(hal->ah_capabilities.cap_mode & HAL_MODE_11G) + if (hal->ah_capabilities.cap_mode & HAL_MODE_11G) ar5k_rt_copy(&hal->ah_rt_11g, &rt_11g); - if(hal->ah_capabilities.cap_mode & HAL_MODE_TURBO) + if (hal->ah_capabilities.cap_mode & HAL_MODE_TURBO) ar5k_rt_copy(&hal->ah_rt_turbo, &rt_turbo); *status = HAL_OK; - return(hal); + return (hal); failed: free(hal, M_DEVBUF); - return(NULL); + return (NULL); } u_int16_t @@ -241,7 +230,7 @@ ath_hal_computetxtime(hal, rates, frame_length, rate_index, short_preamble) /* * Calculate the transmission time by operation (PHY) mode */ - switch(rate->phy) { + switch (rate->phy) { case IEEE80211_T_CCK: /* * CCK / DS mode (802.11b) @@ -254,8 +243,8 @@ ath_hal_computetxtime(hal, rates, frame_length, rate_index, short_preamble) /* * Orthogonal Frequency Division Multiplexing */ - if(AR5K_OFDM_NUM_BITS_PER_SYM(rate->rateKbps) == 0) - return(0); + if (AR5K_OFDM_NUM_BITS_PER_SYM(rate->rateKbps) == 0) + return (0); value = AR5K_OFDM_TX_TIME(rate->rateKbps, frame_length); break; @@ -264,8 +253,8 @@ ath_hal_computetxtime(hal, rates, frame_length, rate_index, short_preamble) * Orthogonal Frequency Division Multiplexing * Atheros "Turbo Mode" (doubled rates) */ - if(AR5K_TURBO_NUM_BITS_PER_SYM(rate->rateKbps) == 0) - return(0); + if (AR5K_TURBO_NUM_BITS_PER_SYM(rate->rateKbps) == 0) + return (0); value = AR5K_TURBO_TX_TIME(rate->rateKbps, frame_length); break; @@ -274,16 +263,16 @@ ath_hal_computetxtime(hal, rates, frame_length, rate_index, short_preamble) * Orthogonal Frequency Division Multiplexing * Atheros "eXtended Range" (XR) */ - if(AR5K_XR_NUM_BITS_PER_SYM(rate->rateKbps) == 0) - return(0); + if (AR5K_XR_NUM_BITS_PER_SYM(rate->rateKbps) == 0) + return (0); value = AR5K_XR_TX_TIME(rate->rateKbps, frame_length); break; default: - return(0); + return (0); } - return(value); + return (value); } u_int @@ -291,7 +280,7 @@ ath_hal_mhz2ieee(mhz, flags) u_int mhz; u_int flags; { - return(ieee80211_mhz2ieee(mhz, flags)); + return (ieee80211_mhz2ieee(mhz, flags)); } u_int @@ -299,7 +288,7 @@ ath_hal_ieee2mhz(ieee, flags) u_int ieee; u_int flags; { - return(ieee80211_ieee2mhz(ieee, flags)); + return (ieee80211_ieee2mhz(ieee, flags)); } HAL_BOOL @@ -330,26 +319,26 @@ ath_hal_init_channels(hal, channels, max_channels, channels_size, country, mode, * Create channel list based on chipset capabilities, regulation domain * and mode. 5GHz... */ - for(i = 0; (hal->ah_capabilities.cap_range.range_5ghz_max > 0) && - (i < (sizeof(ar5k_5ghz_channels) / - sizeof(ar5k_5ghz_channels[0]))) && - (c < max_channels); i++) { + for (i = 0; (hal->ah_capabilities.cap_range.range_5ghz_max > 0) && + (i < (sizeof(ar5k_5ghz_channels) / + sizeof(ar5k_5ghz_channels[0]))) && + (c < max_channels); i++) { /* Check if channel is supported by the chipset */ - if((ar5k_5ghz_channels[i].rc_channel < - hal->ah_capabilities.cap_range.range_5ghz_min) || + if ((ar5k_5ghz_channels[i].rc_channel < + hal->ah_capabilities.cap_range.range_5ghz_min) || (ar5k_5ghz_channels[i].rc_channel > hal->ah_capabilities.cap_range.range_5ghz_max)) continue; /* Match regulation domain */ - if((IEEE80211_DMN(ar5k_5ghz_channels[i].rc_domains) & - IEEE80211_DMN(domain_5ghz)) == 0) + if ((IEEE80211_DMN(ar5k_5ghz_channels[i].rc_domains) & + IEEE80211_DMN(domain_5ghz)) == 0) continue; /* Match modes */ - if(ar5k_5ghz_channels[i].rc_mode & IEEE80211_CHAN_TURBO) + if (ar5k_5ghz_channels[i].rc_mode & IEEE80211_CHAN_TURBO) all_channels[c].channelFlags = CHANNEL_T; - else if(ar5k_5ghz_channels[i].rc_mode & IEEE80211_CHAN_OFDM) + else if (ar5k_5ghz_channels[i].rc_mode & IEEE80211_CHAN_OFDM) all_channels[c].channelFlags = CHANNEL_A; else continue; @@ -362,27 +351,27 @@ ath_hal_init_channels(hal, channels, max_channels, channels_size, country, mode, * ...and 2GHz. */ for (i = 0; (hal->ah_capabilities.cap_range.range_2ghz_max > 0) && - (i < (sizeof(ar5k_2ghz_channels) / - sizeof(ar5k_2ghz_channels[0]))) && - (c < max_channels); i++) { + (i < (sizeof(ar5k_2ghz_channels) / + sizeof(ar5k_2ghz_channels[0]))) && + (c < max_channels); i++) { /* Check if channel is supported by the chipset */ - if((ar5k_2ghz_channels[i].rc_channel < - hal->ah_capabilities.cap_range.range_2ghz_min) || + if ((ar5k_2ghz_channels[i].rc_channel < + hal->ah_capabilities.cap_range.range_2ghz_min) || (ar5k_2ghz_channels[i].rc_channel > hal->ah_capabilities.cap_range.range_2ghz_max)) continue; /* Match regulation domain */ - if((IEEE80211_DMN(ar5k_2ghz_channels[i].rc_domains) & - IEEE80211_DMN(domain_2ghz)) == 0) + if ((IEEE80211_DMN(ar5k_2ghz_channels[i].rc_domains) & + IEEE80211_DMN(domain_2ghz)) == 0) continue; /* Match modes */ - if(ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_CCK) + if (ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_CCK) all_channels[c].channelFlags = CHANNEL_B; - else if(ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_TURBO) + else if (ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_TURBO) all_channels[c].channelFlags = CHANNEL_TG; - else if(ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_OFDM) + else if (ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_OFDM) all_channels[c].channelFlags = CHANNEL_G; else continue; @@ -394,7 +383,7 @@ ath_hal_init_channels(hal, channels, max_channels, channels_size, country, mode, memcpy(channels, &all_channels, sizeof(all_channels)); *channels_size = c; - return(AH_TRUE); + return (AH_TRUE); } /* @@ -408,7 +397,7 @@ ar5k_radar_alert(hal) /* * Limit ~1/s */ - if(hal->ah_radar.r_last_channel.channel == + if (hal->ah_radar.r_last_channel.channel == hal->ah_current_channel.channel && tick < (hal->ah_radar.r_last_alert + hz)) return; @@ -436,19 +425,19 @@ ar5k_eeprom_read_mac(hal, mac) bzero(mac, IEEE80211_ADDR_LEN); bzero(&mac_d, IEEE80211_ADDR_LEN); - if(hal->ah_eeprom_is_busy(hal)) - return(-EBUSY); + if (hal->ah_eeprom_is_busy(hal)) + return (EBUSY); /* * XXX Does this work with newer EEPROMs? */ - if(hal->ah_eeprom_read(hal, 0x20, &data) != 0) - return(-EIO); + if (hal->ah_eeprom_read(hal, 0x20, &data) != 0) + return (EIO); - for(offset = 0x1f, octet = 0, total = 0; - offset >= 0x1d; offset--) { - if(hal->ah_eeprom_read(hal, offset, &data) != 0) - return(-EIO); + for (offset = 0x1f, octet = 0, total = 0; + offset >= 0x1d; offset--) { + if (hal->ah_eeprom_read(hal, offset, &data) != 0) + return (EIO); total += data; mac_d[octet + 1] = data & 0xff; @@ -458,10 +447,10 @@ ar5k_eeprom_read_mac(hal, mac) memcpy(mac, &mac_d, IEEE80211_ADDR_LEN); - if((!total) || total == (3 * 0xffff)) - return(-EINVAL); + if ((!total) || total == (3 * 0xffff)) + return (EINVAL); - return(0); + return (0); } u_int8_t @@ -471,7 +460,7 @@ ar5k_regdomain_from_ieee(regdomain) /* * XXX Fix */ - return((u_int8_t)*regdomain); + return ((u_int8_t)*regdomain); } ieee80211_regdomain_t * @@ -481,7 +470,7 @@ ar5k_regdomain_to_ieee(regdomain) /* * XXX Fix */ - return((ieee80211_regdomain_t*)®domain); + return ((ieee80211_regdomain_t*)®domain); } u_int32_t @@ -496,7 +485,7 @@ ar5k_bitswap(val, bits) retval = (retval << 1) | bit; } - return(retval); + return (retval); } u_int @@ -504,7 +493,7 @@ ar5k_htoclock(usec, turbo) u_int usec; HAL_BOOL turbo; { - return(turbo == AH_TRUE ? (usec * 80) : (usec * 40)); + return (turbo == AH_TRUE ? (usec * 80) : (usec * 40)); } u_int @@ -512,7 +501,7 @@ ar5k_clocktoh(clock, turbo) u_int clock; HAL_BOOL turbo; { - return(turbo == AH_TRUE ? (clock / 80) : (clock / 40)); + return (turbo == AH_TRUE ? (clock / 80) : (clock / 40)); } void @@ -535,16 +524,16 @@ ar5k_register_timeout(hal, reg, flag, val, is_set) { int i; - for(i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { - if((is_set == AH_TRUE) && (AR5K_REG_READ(reg) & flag)) + for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { + if ((is_set == AH_TRUE) && (AR5K_REG_READ(reg) & flag)) break; - else if((AR5K_REG_READ(reg) & flag) == val) + else if ((AR5K_REG_READ(reg) & flag) == val) break; AR5K_DELAY(15); } - if(i <= 0) - return(AH_FALSE); + if (i <= 0) + return (AH_FALSE); - return(AH_TRUE); + return (AH_TRUE); } diff --git a/sys/dev/ic/ar5xxx.h b/sys/dev/ic/ar5xxx.h index 2bafa3f9259..212eec26af8 100644 --- a/sys/dev/ic/ar5xxx.h +++ b/sys/dev/ic/ar5xxx.h @@ -1,4 +1,4 @@ -/* $OpenBSD: ar5xxx.h,v 1.2 2004/11/02 14:05:49 reyk Exp $ */ +/* $OpenBSD: ar5xxx.h,v 1.3 2004/11/03 16:40:46 reyk Exp $ */ /* * Copyright (c) 2004 Reyk Floeter <reyk@vantronix.net>. @@ -70,27 +70,6 @@ #include <net80211/ieee80211_regdomain.h> /* - * Enable support the first AR5000 chipset (AR5210 + AR5110) - */ -#define AR5K_SUPPORT_AR5210 1 - -/* - * NOTE: support for the newer AR5001+ chipsets has not been finished yet - * and will be included very soon. Work is in progress... - */ -#ifdef notyet -/* - * Enable support for the AR5001 chipset (AR5211 [AR5111] [AR2111]) - */ -#define AR5K_SUPPORT_AR5211 1 - -/* - * Enable support for the AR5002 chipset (AR5210 [AR5110] [AR2112]) - */ -#define AR5K_SUPPORT_AR5212 1 -#endif - -/* * Generic definitions */ @@ -119,7 +98,7 @@ typedef enum { typedef int HAL_STATUS; #define HAL_OK 0 -#define HAL_EINPROGRESS -EINPROGRESS +#define HAL_EINPROGRESS EINPROGRESS /* * TX queues @@ -151,18 +130,18 @@ typedef enum { #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0020 typedef struct { - u_int32_t tqi_ver; - HAL_TX_QUEUE tqi_type; - HAL_TX_QUEUE_SUBTYPE tqi_subtype; - u_int16_t tqi_flags; - u_int32_t tqi_priority; - u_int32_t tqi_aifs; + u_int32_t tqi_ver; + HAL_TX_QUEUE tqi_type; + HAL_TX_QUEUE_SUBTYPE tqi_subtype; + u_int16_t tqi_flags; + u_int32_t tqi_priority; + u_int32_t tqi_aifs; int32_t tqi_cw_min; int32_t tqi_cw_max; - u_int32_t tqi_cbr_period; - u_int32_t tqi_cbr_overflow_limit; - u_int32_t tqi_burst_time; - u_int32_t tqi_ready_time; + u_int32_t tqi_cbr_period; + u_int32_t tqi_cbr_overflow_limit; + u_int32_t tqi_burst_time; + u_int32_t tqi_ready_time; } HAL_TXQ_INFO; typedef enum { @@ -182,26 +161,26 @@ typedef enum { #define AR5K_CCK_PREAMBLE_BITS 144 #define AR5K_CCK_PLCP_BITS 48 #define AR5K_CCK_NUM_BITS(_frmlen) (_frmlen << 3) -#define AR5K_CCK_PHY_TIME(_sp) (_sp ? \ - ((AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS) >> 1) : \ +#define AR5K_CCK_PHY_TIME(_sp) (_sp ? \ + ((AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS) >> 1) : \ (AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS)) -#define AR5K_CCK_TX_TIME(_kbps, _frmlen, _sp) \ - AR5K_CCK_PHY_TIME(_sp) + \ - ((AR5K_CCK_NUM_BITS(_frmlen) * 1000) / _kbps) + \ +#define AR5K_CCK_TX_TIME(_kbps, _frmlen, _sp) \ + AR5K_CCK_PHY_TIME(_sp) + \ + ((AR5K_CCK_NUM_BITS(_frmlen) * 1000) / _kbps) + \ AR5K_CCK_SIFS_TIME #define AR5K_OFDM_SIFS_TIME 16 -#define AR5K_OFDM_PREAMBLE_TIME 20 -#define AR5K_OFDM_PLCP_BITS 22 -#define AR5K_OFDM_SYMBOL_TIME 4 +#define AR5K_OFDM_PREAMBLE_TIME 20 +#define AR5K_OFDM_PLCP_BITS 22 +#define AR5K_OFDM_SYMBOL_TIME 4 #define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) -#define AR5K_OFDM_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ +#define AR5K_OFDM_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ AR5K_OFDM_SYMBOL_TIME) / 1000) #define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) -#define AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) \ +#define AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) \ howmany(AR5K_OFDM_NUM_BITS(_frmlen), AR5K_OFDM_NUM_BITS_PER_SYM(_kbps)) -#define AR5K_OFDM_TX_TIME(_kbps, _frmlen) \ - AR5K_OFDM_PREAMBLE_TIME + AR5K_OFDM_SIFS_TIME + \ +#define AR5K_OFDM_TX_TIME(_kbps, _frmlen) \ + AR5K_OFDM_PREAMBLE_TIME + AR5K_OFDM_SIFS_TIME + \ (AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_OFDM_SYMBOL_TIME) #define AR5K_TURBO_SIFS_TIME 8 @@ -209,49 +188,49 @@ typedef enum { #define AR5K_TURBO_PLCP_BITS 22 #define AR5K_TURBO_SYMBOL_TIME 4 #define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) -#define AR5K_TURBO_NUM_BITS_PER_SYM(_kbps) (((_kbps << 1) * \ +#define AR5K_TURBO_NUM_BITS_PER_SYM(_kbps) (((_kbps << 1) * \ AR5K_TURBO_SYMBOL_TIME) / 1000) #define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) -#define AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) \ - howmany(AR5K_TURBO_NUM_BITS(_frmlen), \ +#define AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) \ + howmany(AR5K_TURBO_NUM_BITS(_frmlen), \ AR5K_TURBO_NUM_BITS_PER_SYM(_kbps)) -#define AR5K_TURBO_TX_TIME(_kbps, _frmlen) \ +#define AR5K_TURBO_TX_TIME(_kbps, _frmlen) \ AR5K_TURBO_PREAMBLE_TIME + AR5K_TURBO_SIFS_TIME + \ (AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_TURBO_SYMBOL_TIME) #define AR5K_XR_SIFS_TIME 16 -#define AR5K_XR_PLCP_BITS 22 -#define AR5K_XR_SYMBOL_TIME 4 +#define AR5K_XR_PLCP_BITS 22 +#define AR5K_XR_SYMBOL_TIME 4 #define AR5K_XR_PREAMBLE_TIME(_kbps) (((_kbps) < 1000) ? 173 : 76) -#define AR5K_XR_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ +#define AR5K_XR_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ AR5K_XR_SYMBOL_TIME) / 1000) #define AR5K_XR_NUM_BITS(_frmlen) (AR5K_XR_PLCP_BITS + (_frmlen << 3)) -#define AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) \ +#define AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) \ howmany(AR5K_XR_NUM_BITS(_frmlen), AR5K_XR_NUM_BITS_PER_SYM(_kbps)) -#define AR5K_XR_TX_TIME(_kbps, _frmlen) \ - AR5K_XR_PREAMBLE_TIME(_kbps) + AR5K_XR_SIFS_TIME + \ +#define AR5K_XR_TX_TIME(_kbps, _frmlen) \ + AR5K_XR_PREAMBLE_TIME(_kbps) + AR5K_XR_SIFS_TIME + \ (AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_XR_SYMBOL_TIME) /* * RX definitions */ -#define HAL_RX_FILTER_UCAST 0x00000001 -#define HAL_RX_FILTER_MCAST 0x00000002 -#define HAL_RX_FILTER_BCAST 0x00000004 -#define HAL_RX_FILTER_CONTROL 0x00000008 -#define HAL_RX_FILTER_BEACON 0x00000010 -#define HAL_RX_FILTER_PROM 0x00000020 -#define HAL_RX_FILTER_PROBEREQ 0x00000080 -#define HAL_RX_FILTER_PHYERR 0x00000100 -#define HAL_RX_FILTER_PHYRADAR 0x00000200 +#define HAL_RX_FILTER_UCAST 0x00000001 +#define HAL_RX_FILTER_MCAST 0x00000002 +#define HAL_RX_FILTER_BCAST 0x00000004 +#define HAL_RX_FILTER_CONTROL 0x00000008 +#define HAL_RX_FILTER_BEACON 0x00000010 +#define HAL_RX_FILTER_PROM 0x00000020 +#define HAL_RX_FILTER_PROBEREQ 0x00000080 +#define HAL_RX_FILTER_PHYERR 0x00000100 +#define HAL_RX_FILTER_PHYRADAR 0x00000200 typedef struct { - u_int32_t ackrcv_bad; - u_int32_t rts_bad; - u_int32_t rts_good; - u_int32_t fcs_bad; - u_int32_t beacons; + u_int32_t ackrcv_bad; + u_int32_t rts_bad; + u_int32_t rts_good; + u_int32_t fcs_bad; + u_int32_t beacons; } HAL_MIB_STATS; /* @@ -259,8 +238,8 @@ typedef struct { */ #define HAL_BEACON_PERIOD 0x0000ffff -#define HAL_BEACON_ENA 0x00800000 -#define HAL_BEACON_RESET_TSF 0x01000000 +#define HAL_BEACON_ENA 0x00800000 +#define HAL_BEACON_RESET_TSF 0x01000000 typedef struct { u_int32_t bs_next_beacon; @@ -274,12 +253,12 @@ typedef struct { u_int16_t bs_sleep_duration; u_int16_t bs_bmiss_threshold; -#define bs_nexttbtt bs_next_beacon -#define bs_intval bs_interval +#define bs_nexttbtt bs_next_beacon +#define bs_intval bs_interval #define bs_nextdtim bs_next_dtim #define bs_bmissthreshold bs_bmiss_threshold -#define bs_sleepduration bs_sleep_duration -#define bs_dtimperiod bs_dtim_period +#define bs_sleepduration bs_sleep_duration +#define bs_dtimperiod bs_dtim_period } HAL_BEACON_STATE; @@ -305,35 +284,35 @@ typedef enum { HAL_CIPHER_CKIP, } HAL_CIPHER; -#define AR5K_MAX_KEYS 16 +#define AR5K_MAX_KEYS 16 typedef struct { - int wk_len; + int wk_len; u_int8_t wk_key[AR5K_MAX_KEYS]; } HAL_KEYVAL; -#define AR5K_ASSERT_ENTRY(_e, _s) do { \ - if(_e >= _s) \ - return(AH_FALSE); \ -} while(0) +#define AR5K_ASSERT_ENTRY(_e, _s) do { \ + if (_e >= _s) \ + return (AH_FALSE); \ +} while (0) /* * PHY */ -#define AR5K_MAX_RATES 32 +#define AR5K_MAX_RATES 32 typedef struct { - u_int8_t valid; - u_int8_t phy; - u_int16_t rateKbps; + u_int8_t valid; + u_int8_t phy; + u_int16_t rateKbps; u_int8_t rateCode; u_int8_t shortPreamble; u_int8_t dot11Rate; u_int8_t controlRate; -#define r_valid valid -#define r_phy phy +#define r_valid valid +#define r_phy phy #define r_rate_kbps rateKbps #define r_short_preamble short_preamble #define r_dot11_rate dot11Rate @@ -342,7 +321,7 @@ typedef struct { } HAL_RATE; typedef struct { - u_int16_t rateCount; + u_int16_t rateCount; u_int8_t rateCodeToIndex[AR5K_MAX_RATES]; HAL_RATE info[AR5K_MAX_RATES]; @@ -352,26 +331,26 @@ typedef struct { } HAL_RATE_TABLE; -#define AR5K_RATES_11A { 8, { 0 }, { \ - { 1, IEEE80211_T_OFDM, 6000, 11, 0, 140, 0 }, \ - { 1, IEEE80211_T_OFDM, 9000, 15, 0, 18, 0 }, \ - { 1, IEEE80211_T_OFDM, 12000, 10, 0, 152, 2 }, \ - { 1, IEEE80211_T_OFDM, 18000, 14, 0, 36, 2 }, \ - { 1, IEEE80211_T_OFDM, 24000, 9, 0, 176, 4 }, \ - { 1, IEEE80211_T_OFDM, 36000, 13, 0, 72, 4 }, \ - { 1, IEEE80211_T_OFDM, 48000, 8, 0, 96, 4 }, \ - { 1, IEEE80211_T_OFDM, 54000, 12, 0, 108, 4 } } \ +#define AR5K_RATES_11A { 8, { 0 }, { \ + { 1, IEEE80211_T_OFDM, 6000, 11, 0, 140, 0 }, \ + { 1, IEEE80211_T_OFDM, 9000, 15, 0, 18, 0 }, \ + { 1, IEEE80211_T_OFDM, 12000, 10, 0, 152, 2 }, \ + { 1, IEEE80211_T_OFDM, 18000, 14, 0, 36, 2 }, \ + { 1, IEEE80211_T_OFDM, 24000, 9, 0, 176, 4 }, \ + { 1, IEEE80211_T_OFDM, 36000, 13, 0, 72, 4 }, \ + { 1, IEEE80211_T_OFDM, 48000, 8, 0, 96, 4 }, \ + { 1, IEEE80211_T_OFDM, 54000, 12, 0, 108, 4 } } \ } -#define AR5K_RATES_TURBO { 8, { 0 }, { \ - { 1, IEEE80211_T_TURBO, 6000, 11, 0, 140, 0 }, \ - { 1, IEEE80211_T_TURBO, 9000, 15, 0, 18, 0 }, \ - { 1, IEEE80211_T_TURBO, 12000, 10, 0, 152, 2 }, \ - { 1, IEEE80211_T_TURBO, 18000, 14, 0, 36, 2 }, \ - { 1, IEEE80211_T_TURBO, 24000, 9, 0, 176, 4 }, \ - { 1, IEEE80211_T_TURBO, 36000, 13, 0, 72, 4 }, \ - { 1, IEEE80211_T_TURBO, 48000, 8, 0, 96, 4 }, \ - { 1, IEEE80211_T_TURBO, 54000, 12, 0, 108, 4 } } \ +#define AR5K_RATES_TURBO { 8, { 0 }, { \ + { 1, IEEE80211_T_TURBO, 6000, 11, 0, 140, 0 }, \ + { 1, IEEE80211_T_TURBO, 9000, 15, 0, 18, 0 }, \ + { 1, IEEE80211_T_TURBO, 12000, 10, 0, 152, 2 }, \ + { 1, IEEE80211_T_TURBO, 18000, 14, 0, 36, 2 }, \ + { 1, IEEE80211_T_TURBO, 24000, 9, 0, 176, 4 }, \ + { 1, IEEE80211_T_TURBO, 36000, 13, 0, 72, 4 }, \ + { 1, IEEE80211_T_TURBO, 48000, 8, 0, 96, 4 }, \ + { 1, IEEE80211_T_TURBO, 54000, 12, 0, 108, 4 } } \ } /* XXX TODO: 2GHz rates for 11b/11g */ @@ -385,8 +364,8 @@ typedef enum { } HAL_RFGAIN; typedef struct { - u_int16_t channel; /* MHz */ - u_int16_t channelFlags; + u_int16_t channel; /* MHz */ + u_int16_t channelFlags; #define c_channel channel #define c_channel_flags cnannelFlags @@ -394,16 +373,16 @@ typedef struct { } HAL_CHANNEL; #define HAL_SLOT_TIME_9 9 -#define HAL_SLOT_TIME_20 20 +#define HAL_SLOT_TIME_20 20 #define HAL_SLOT_TIME_MAX ar5k_clocktoh(0xffff, hal->ah_turbo) -#define CHANNEL_A (IEEE80211_CHAN_5GHZ | IEEE80211_CHAN_OFDM) -#define CHANNEL_B (IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_CCK) -#define CHANNEL_G (IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_OFDM) /* _DYN */ -#define CHANNEL_PUREG (IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_OFDM) -#define CHANNEL_T (CHANNEL_A | IEEE80211_CHAN_TURBO) -#define CHANNEL_TG (CHANNEL_PUREG | IEEE80211_CHAN_TURBO) -#define CHANNEL_XR (CHANNEL_A | IEEE80211_CHAN_XR) +#define CHANNEL_A (IEEE80211_CHAN_5GHZ | IEEE80211_CHAN_OFDM) +#define CHANNEL_B (IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_CCK) +#define CHANNEL_G (IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_OFDM) /* _DYN */ +#define CHANNEL_PUREG (IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_OFDM) +#define CHANNEL_T (CHANNEL_A | IEEE80211_CHAN_TURBO) +#define CHANNEL_TG (CHANNEL_PUREG | IEEE80211_CHAN_TURBO) +#define CHANNEL_XR (CHANNEL_A | IEEE80211_CHAN_XR) /* * Regulation stuff @@ -415,16 +394,16 @@ typedef enum ieee80211_countrycode HAL_CTRY_CODE; * HAL interrupt abstraction */ -#define HAL_INT_RX 0x00000001 -#define HAL_INT_RXDESC 0x00000002 +#define HAL_INT_RX 0x00000001 +#define HAL_INT_RXDESC 0x00000002 #define HAL_INT_RXNOFRM 0x00000008 -#define HAL_INT_RXEOL 0x00000010 +#define HAL_INT_RXEOL 0x00000010 #define HAL_INT_RXORN 0x00000020 #define HAL_INT_TX 0x00000040 -#define HAL_INT_TXDESC 0x00000080 -#define HAL_INT_TXURN 0x00000800 +#define HAL_INT_TXDESC 0x00000080 +#define HAL_INT_TXURN 0x00000800 #define HAL_INT_MIB 0x00001000 -#define HAL_INT_RXPHY 0x00004000 +#define HAL_INT_RXPHY 0x00004000 #define HAL_INT_RXKCM 0x00008000 #define HAL_INT_SWBA 0x00010000 #define HAL_INT_BMISS 0x00040000 @@ -432,11 +411,11 @@ typedef enum ieee80211_countrycode HAL_CTRY_CODE; #define HAL_INT_GPIO 0x01000000 #define HAL_INT_FATAL 0x40000000 #define HAL_INT_GLOBAL 0x80000000 -#define HAL_INT_NOCARD 0xffffffff +#define HAL_INT_NOCARD 0xffffffff #define HAL_INT_COMMON ( \ - HAL_INT_RXNOFRM | HAL_INT_RXDESC | HAL_INT_RXEOL | \ - HAL_INT_RXORN | HAL_INT_TXURN | HAL_INT_TXDESC | \ - HAL_INT_MIB | HAL_INT_RXPHY | HAL_INT_RXKCM | \ + HAL_INT_RXNOFRM | HAL_INT_RXDESC | HAL_INT_RXEOL | \ + HAL_INT_RXORN | HAL_INT_TXURN | HAL_INT_TXDESC | \ + HAL_INT_MIB | HAL_INT_RXPHY | HAL_INT_RXKCM | \ HAL_INT_SWBA | HAL_INT_BMISS | HAL_INT_GPIO \ ) @@ -449,10 +428,10 @@ typedef u_int32_t HAL_INT; typedef enum ieee80211_state HAL_LED_STATE; #define HAL_LED_INIT IEEE80211_S_INIT -#define HAL_LED_SCAN IEEE80211_S_SCAN -#define HAL_LED_AUTH IEEE80211_S_AUTH -#define HAL_LED_ASSOC IEEE80211_S_ASSOC -#define HAL_LED_RUN IEEE80211_S_RUN +#define HAL_LED_SCAN IEEE80211_S_SCAN +#define HAL_LED_AUTH IEEE80211_S_AUTH +#define HAL_LED_ASSOC IEEE80211_S_ASSOC +#define HAL_LED_RUN IEEE80211_S_RUN /* * Chipset capabilities @@ -538,7 +517,7 @@ struct ath_rx_status { #define HAL_RXERR_CRC 0x01 #define HAL_RXERR_PHY 0x02 -#define HAL_RXERR_FIFO 0x04 +#define HAL_RXERR_FIFO 0x04 #define HAL_RXERR_DECRYPT 0x08 #define HAL_RXERR_MIC 0x10 #define HAL_RXKEYIX_INVALID ((u_int8_t) - 1) @@ -558,19 +537,19 @@ struct ath_rx_status { #define HAL_PHYERR_OFDM_LENGTH_ILLEGAL 0x14 #define HAL_PHYERR_OFDM_POWER_DROP 0x15 #define HAL_PHYERR_OFDM_SERVICE 0x16 -#define HAL_PHYERR_OFDM_RESTART 0x17 +#define HAL_PHYERR_OFDM_RESTART 0x17 #define HAL_PHYERR_CCK_TIMING 0x19 -#define HAL_PHYERR_CCK_HEADER_CRC 0x1a -#define HAL_PHYERR_CCK_RATE_ILLEGAL 0x1b -#define HAL_PHYERR_CCK_SERVICE 0x1e -#define HAL_PHYERR_CCK_RESTART 0x1f +#define HAL_PHYERR_CCK_HEADER_CRC 0x1a +#define HAL_PHYERR_CCK_RATE_ILLEGAL 0x1b +#define HAL_PHYERR_CCK_SERVICE 0x1e +#define HAL_PHYERR_CCK_RESTART 0x1f struct ath_desc { - u_int32_t ds_link; - u_int32_t ds_data; - u_int32_t ds_ctl0; - u_int32_t ds_ctl1; - u_int32_t ds_hw[4]; + u_int32_t ds_link; + u_int32_t ds_data; + u_int32_t ds_ctl0; + u_int32_t ds_ctl1; + u_int32_t ds_hw[4]; union { struct ath_rx_status rx; @@ -582,13 +561,13 @@ struct ath_desc { } __attribute__((__packed__)); -#define HAL_RXDESC_INTREQ 0x0020 +#define HAL_RXDESC_INTREQ 0x0020 -#define HAL_TXDESC_CLRDMASK 0x0001 -#define HAL_TXDESC_NOACK 0x0002 -#define HAL_TXDESC_RTSENA 0x0004 -#define HAL_TXDESC_CTSENA 0x0008 -#define HAL_TXDESC_INTREQ 0x0010 +#define HAL_TXDESC_CLRDMASK 0x0001 +#define HAL_TXDESC_NOACK 0x0002 +#define HAL_TXDESC_RTSENA 0x0004 +#define HAL_TXDESC_CTSENA 0x0008 +#define HAL_TXDESC_INTREQ 0x0010 #define HAL_TXDESC_VEOL 0x0020 /* @@ -597,15 +576,18 @@ struct ath_desc { #define AR5K_HAL_FUNCTION(_hal, _n, _f) (_hal)->ah_##_f = ar5k_##_n##_##_f #define AR5K_HAL_FUNCTIONS(_t, _n, _a) \ - _t const HAL_RATE_TABLE *(_a ##_n##_getRateTable)(struct ath_hal *, u_int mode); \ + _t const HAL_RATE_TABLE *(_a ##_n##_getRateTable)(struct ath_hal *, \ + u_int mode); \ _t void (_a ##_n##_detach)(struct ath_hal *); \ /* Reset functions */ \ - _t HAL_BOOL (_a ##_n##_reset)(struct ath_hal *, HAL_OPMODE, HAL_CHANNEL *, \ - HAL_BOOL change_channel, HAL_STATUS *status); \ + _t HAL_BOOL (_a ##_n##_reset)(struct ath_hal *, HAL_OPMODE, \ + HAL_CHANNEL *, HAL_BOOL change_channel, HAL_STATUS *status); \ _t void (_a ##_n##_setPCUConfig)(struct ath_hal *); \ - _t HAL_BOOL (_a ##_n##_perCalibration)(struct ath_hal*, HAL_CHANNEL *); \ + _t HAL_BOOL (_a ##_n##_perCalibration)(struct ath_hal*, \ + HAL_CHANNEL *); \ /* Transmit functions */ \ - _t HAL_BOOL (_a ##_n##_updateTxTrigLevel)(struct ath_hal*, HAL_BOOL level); \ + _t HAL_BOOL (_a ##_n##_updateTxTrigLevel)(struct ath_hal*, \ + HAL_BOOL level); \ _t int (_a ##_n##_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, \ const HAL_TXQ_INFO *); \ _t HAL_BOOL (_a ##_n##_setTxQueueProps)(struct ath_hal *, int queue, \ @@ -613,20 +595,25 @@ struct ath_desc { _t HAL_BOOL (_a ##_n##_releaseTxQueue)(struct ath_hal *, u_int queue); \ _t HAL_BOOL (_a ##_n##_resetTxQueue)(struct ath_hal *, u_int queue); \ _t u_int32_t (_a ##_n##_getTxDP)(struct ath_hal *, u_int queue); \ - _t HAL_BOOL (_a ##_n##_setTxDP)(struct ath_hal *, u_int, u_int32_t phys_addr); \ + _t HAL_BOOL (_a ##_n##_setTxDP)(struct ath_hal *, u_int, \ + u_int32_t phys_addr); \ _t HAL_BOOL (_a ##_n##_startTxDma)(struct ath_hal *, u_int queue); \ _t HAL_BOOL (_a ##_n##_stopTxDma)(struct ath_hal *, u_int queue); \ - _t HAL_BOOL (_a ##_n##_setupTxDesc)(struct ath_hal *, struct ath_desc *, \ + _t HAL_BOOL (_a ##_n##_setupTxDesc)(struct ath_hal *, \ + struct ath_desc *, \ u_int packet_length, u_int header_length, HAL_PKT_TYPE type, \ u_int txPower, u_int tx_rate0, u_int tx_tries0, u_int key_index, \ u_int antenna_mode, u_int flags, u_int rtscts_rate, \ u_int rtscts_duration); \ - _t HAL_BOOL (_a ##_n##_setupXTxDesc)(struct ath_hal *, struct ath_desc *, \ + _t HAL_BOOL (_a ##_n##_setupXTxDesc)(struct ath_hal *, \ + struct ath_desc *, \ u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, \ u_int tx_rate3, u_int tx_tries3); \ - _t HAL_BOOL (_a ##_n##_fillTxDesc)(struct ath_hal *, struct ath_desc *, \ + _t HAL_BOOL (_a ##_n##_fillTxDesc)(struct ath_hal *, \ + struct ath_desc *, \ u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg); \ - _t HAL_STATUS (_a ##_n##_procTxDesc)(struct ath_hal *, struct ath_desc *); \ + _t HAL_STATUS (_a ##_n##_procTxDesc)(struct ath_hal *, \ + struct ath_desc *); \ _t HAL_BOOL (_a ##_n##_hasVEOL)(struct ath_hal *); \ /* Receive Functions */ \ _t u_int32_t (_a ##_n##_getRxDP)(struct ath_hal*); \ @@ -635,65 +622,78 @@ struct ath_desc { _t HAL_BOOL (_a ##_n##_stopDmaReceive)(struct ath_hal*); \ _t void (_a ##_n##_startPcuReceive)(struct ath_hal*); \ _t void (_a ##_n##_stopPcuReceive)(struct ath_hal*); \ - _t void (_a ##_n##_setMulticastFilter)(struct ath_hal*, u_int32_t filter0, \ - u_int32_t filter1); \ - _t HAL_BOOL (_a ##_n##_setMulticastFilterIndex)(struct ath_hal*, u_int32_t index); \ - _t HAL_BOOL (_a ##_n##_clrMulticastFilterIndex)(struct ath_hal*, u_int32_t index); \ + _t void (_a ##_n##_setMulticastFilter)(struct ath_hal*, \ + u_int32_t filter0, u_int32_t filter1); \ + _t HAL_BOOL (_a ##_n##_setMulticastFilterIndex)(struct ath_hal*, \ + u_int32_t index); \ + _t HAL_BOOL (_a ##_n##_clrMulticastFilterIndex)(struct ath_hal*, \ + u_int32_t index); \ _t u_int32_t (_a ##_n##_getRxFilter)(struct ath_hal*); \ _t void (_a ##_n##_setRxFilter)(struct ath_hal*, u_int32_t); \ - _t HAL_BOOL (_a ##_n##_setupRxDesc)(struct ath_hal *, struct ath_desc *, \ - u_int32_t size, u_int flags); \ - _t HAL_STATUS (_a ##_n##_procRxDesc)(struct ath_hal *, struct ath_desc *, \ - u_int32_t phyAddr, struct ath_desc *next); \ + _t HAL_BOOL (_a ##_n##_setupRxDesc)(struct ath_hal *, \ + struct ath_desc *, u_int32_t size, u_int flags); \ + _t HAL_STATUS (_a ##_n##_procRxDesc)(struct ath_hal *, \ + struct ath_desc *, u_int32_t phyAddr, struct ath_desc *next); \ _t void (_a ##_n##_rxMonitor)(struct ath_hal *); \ /* Misc Functions */ \ _t void (_a ##_n##_dumpState)(struct ath_hal *); \ - _t HAL_BOOL (_a ##_n##_getDiagState)(struct ath_hal *, int, void **, u_int *); \ + _t HAL_BOOL (_a ##_n##_getDiagState)(struct ath_hal *, int, void **, \ + u_int *); \ _t void (_a ##_n##_getMacAddress)(struct ath_hal *, u_int8_t *); \ _t HAL_BOOL (_a ##_n##_setMacAddress)(struct ath_hal *, const u_int8_t*); \ - _t HAL_BOOL (_a ##_n##_setRegulatoryDomain)(struct ath_hal*, u_int16_t, HAL_STATUS *); \ + _t HAL_BOOL (_a ##_n##_setRegulatoryDomain)(struct ath_hal*, \ + u_int16_t, HAL_STATUS *); \ _t void (_a ##_n##_setLedState)(struct ath_hal*, HAL_LED_STATE); \ - _t void (_a ##_n##_writeAssocid)(struct ath_hal*, const u_int8_t *bssid, \ - u_int16_t assocId, u_int16_t timOffset); \ - _t HAL_BOOL (_a ##_n##_gpioCfgOutput)(struct ath_hal *, u_int32_t gpio); \ - _t HAL_BOOL (_a ##_n##_gpioCfgInput)(struct ath_hal *, u_int32_t gpio); \ + _t void (_a ##_n##_writeAssocid)(struct ath_hal*, \ + const u_int8_t *bssid, u_int16_t assocId, u_int16_t timOffset); \ + _t HAL_BOOL (_a ##_n##_gpioCfgOutput)(struct ath_hal *, \ + u_int32_t gpio); \ + _t HAL_BOOL (_a ##_n##_gpioCfgInput)(struct ath_hal *, \ + u_int32_t gpio); \ _t u_int32_t (_a ##_n##_gpioGet)(struct ath_hal *, u_int32_t gpio); \ - _t HAL_BOOL (_a ##_n##_gpioSet)(struct ath_hal *, u_int32_t gpio, u_int32_t val); \ + _t HAL_BOOL (_a ##_n##_gpioSet)(struct ath_hal *, u_int32_t gpio, \ + u_int32_t val); \ _t void (_a ##_n##_gpioSetIntr)(struct ath_hal*, u_int, u_int32_t); \ _t u_int32_t (_a ##_n##_getTsf32)(struct ath_hal*); \ _t u_int64_t (_a ##_n##_getTsf64)(struct ath_hal*); \ _t void (_a ##_n##_resetTsf)(struct ath_hal*); \ _t u_int16_t (_a ##_n##_getRegDomain)(struct ath_hal*); \ _t HAL_BOOL (_a ##_n##_detectCardPresent)(struct ath_hal*); \ - _t void (_a ##_n##_updateMibCounters)(struct ath_hal*, HAL_MIB_STATS*); \ - _t HAL_BOOL (_a ##_n##_isHwCipherSupported)(struct ath_hal*, HAL_CIPHER); \ + _t void (_a ##_n##_updateMibCounters)(struct ath_hal*, \ + HAL_MIB_STATS*); \ + _t HAL_BOOL (_a ##_n##_isHwCipherSupported)(struct ath_hal*, \ + HAL_CIPHER); \ _t HAL_RFGAIN (_a ##_n##_getRfGain)(struct ath_hal*); \ - /* \ - u_int32_t (_a ##_n##_getCurRssi)(struct ath_hal*); \ - u_int32_t (_a ##_n##_getDefAntenna)(struct ath_hal*); \ - void (_a ##_n##_setDefAntenna)(struct ath_hal*, u_int32_t ant); \ - */ \ - _t HAL_BOOL (_a ##_n##_setSlotTime)(struct ath_hal*, u_int); \ - _t u_int (_a ##_n##_getSlotTime)(struct ath_hal*); \ + /* \ + u_int32_t (_a ##_n##_getCurRssi)(struct ath_hal*); \ + u_int32_t (_a ##_n##_getDefAntenna)(struct ath_hal*); \ + void (_a ##_n##_setDefAntenna)(struct ath_hal*, u_int32_t ant); \ + */ \ + _t HAL_BOOL (_a ##_n##_setSlotTime)(struct ath_hal*, u_int); \ + _t u_int (_a ##_n##_getSlotTime)(struct ath_hal*); \ _t HAL_BOOL (_a ##_n##_setAckTimeout)(struct ath_hal *, u_int); \ - _t u_int (_a ##_n##_getAckTimeout)(struct ath_hal*); \ - _t HAL_BOOL (_a ##_n##_setCTSTimeout)(struct ath_hal*, u_int); \ - _t u_int (_a ##_n##_getCTSTimeout)(struct ath_hal*); \ + _t u_int (_a ##_n##_getAckTimeout)(struct ath_hal*); \ + _t HAL_BOOL (_a ##_n##_setCTSTimeout)(struct ath_hal*, u_int); \ + _t u_int (_a ##_n##_getCTSTimeout)(struct ath_hal*); \ /* Key Cache Functions */ \ _t u_int32_t (_a ##_n##_getKeyCacheSize)(struct ath_hal*); \ - _t HAL_BOOL (_a ##_n##_resetKeyCacheEntry)(struct ath_hal*, u_int16_t); \ - _t HAL_BOOL (_a ##_n##_isKeyCacheEntryValid)(struct ath_hal *,u_int16_t); \ + _t HAL_BOOL (_a ##_n##_resetKeyCacheEntry)(struct ath_hal*, \ + u_int16_t); \ + _t HAL_BOOL (_a ##_n##_isKeyCacheEntryValid)(struct ath_hal *, \ + u_int16_t); \ _t HAL_BOOL (_a ##_n##_setKeyCacheEntry)(struct ath_hal*, u_int16_t, \ const HAL_KEYVAL *, const u_int8_t *, int); \ - _t HAL_BOOL (_a ##_n##_setKeyCacheEntryMac)(struct ath_hal*, u_int16_t, \ - const u_int8_t *); \ + _t HAL_BOOL (_a ##_n##_setKeyCacheEntryMac)(struct ath_hal*, \ + u_int16_t, const u_int8_t *); \ /* Power Management Functions */ \ - _t HAL_BOOL (_a ##_n##_setPowerMode)(struct ath_hal*, HAL_POWER_MODE mode, \ + _t HAL_BOOL (_a ##_n##_setPowerMode)(struct ath_hal*, \ + HAL_POWER_MODE mode, \ int setChip, u_int16_t sleepDuration); \ _t HAL_POWER_MODE (_a ##_n##_getPowerMode)(struct ath_hal*); \ _t HAL_BOOL (_a ##_n##_queryPSPollSupport)(struct ath_hal*); \ _t HAL_BOOL (_a ##_n##_initPSPoll)(struct ath_hal*); \ - _t HAL_BOOL (_a ##_n##_enablePSPoll)(struct ath_hal *, u_int8_t *, u_int16_t); \ + _t HAL_BOOL (_a ##_n##_enablePSPoll)(struct ath_hal *, u_int8_t *, \ + u_int16_t); \ _t HAL_BOOL (_a ##_n##_disablePSPoll)(struct ath_hal *); \ /* Beacon Management Functions */ \ _t void (_a ##_n##_beaconInit)(struct ath_hal *, u_int32_t nexttbtt, \ @@ -702,17 +702,19 @@ struct ath_desc { const HAL_BEACON_STATE *, u_int32_t tsf, u_int32_t dtimCount, \ u_int32_t cfpCcount); \ _t void (_a ##_n##_resetStationBeaconTimers)(struct ath_hal *); \ - _t HAL_BOOL (_a ##_n##_waitForBeaconDone)(struct ath_hal *, bus_addr_t); \ + _t HAL_BOOL (_a ##_n##_waitForBeaconDone)(struct ath_hal *, \ + bus_addr_t); \ /* Interrupt functions */ \ _t HAL_BOOL (_a ##_n##_isInterruptPending)(struct ath_hal *); \ - _t HAL_BOOL (_a ##_n##_getPendingInterrupts)(struct ath_hal *, u_int32_t *); \ + _t HAL_BOOL (_a ##_n##_getPendingInterrupts)(struct ath_hal *, \ + u_int32_t *); \ _t u_int32_t (_a ##_n##_getInterrupts)(struct ath_hal *); \ _t HAL_INT (_a ##_n##_setInterrupts)(struct ath_hal *, HAL_INT); \ /* Chipset functions (ar5k-specific, non-HAL) */ \ _t HAL_BOOL (_a ##_n##_get_capabilities)(struct ath_hal *); \ _t void (_a ##_n##_radar_alert)(struct ath_hal *, HAL_BOOL enable); \ - _t HAL_BOOL (_a ##_n##_regulation_domain)(struct ath_hal *, HAL_BOOL read, \ - ieee80211_regdomain_t *); \ + _t HAL_BOOL (_a ##_n##_regulation_domain)(struct ath_hal *, \ + HAL_BOOL read, ieee80211_regdomain_t *); \ _t int (_a ##_n##_eeprom_init)(struct ath_hal *); \ _t HAL_BOOL (_a ##_n##_eeprom_is_busy)(struct ath_hal *); \ _t int (_a ##_n##_eeprom_read)(struct ath_hal *, u_int32_t offset, \ @@ -720,38 +722,38 @@ struct ath_desc { _t int (_a ##_n##_eeprom_write)(struct ath_hal *, u_int32_t offset, \ u_int16_t data); -#define AR5K_MAX_GPIO 10 +#define AR5K_MAX_GPIO 10 struct ath_hal { - u_int32_t ah_magic; - u_int32_t ah_abi; - u_int16_t ah_device; - u_int16_t ah_sub_vendor; + u_int32_t ah_magic; + u_int32_t ah_abi; + u_int16_t ah_device; + u_int16_t ah_sub_vendor; - void *ah_sc; - bus_space_tag_t ah_st; - bus_space_handle_t ah_sh; + void *ah_sc; + bus_space_tag_t ah_st; + bus_space_handle_t ah_sh; - HAL_INT ah_imr; + HAL_INT ah_imr; - HAL_CTRY_CODE ah_country_code; - HAL_OPMODE ah_op_mode; - HAL_POWER_MODE ah_power_mode; - HAL_CHANNEL ah_current_channel; - HAL_BOOL ah_turbo; + HAL_CTRY_CODE ah_country_code; + HAL_OPMODE ah_op_mode; + HAL_POWER_MODE ah_power_mode; + HAL_CHANNEL ah_current_channel; + HAL_BOOL ah_turbo; -#define ah_countryCode ah_country_code +#define ah_countryCode ah_country_code - HAL_RATE_TABLE ah_rt_11a; - HAL_RATE_TABLE ah_rt_11b; - HAL_RATE_TABLE ah_rt_11g; - HAL_RATE_TABLE ah_rt_turbo; + HAL_RATE_TABLE ah_rt_11a; + HAL_RATE_TABLE ah_rt_11b; + HAL_RATE_TABLE ah_rt_11g; + HAL_RATE_TABLE ah_rt_turbo; - u_int32_t ah_mac_version; - u_int16_t ah_mac_revision; - u_int16_t ah_phy_revision; - u_int16_t ah_radio_5ghz_revision; - u_int16_t ah_radio_2ghz_revision; + u_int32_t ah_mac_version; + u_int16_t ah_mac_revision; + u_int16_t ah_phy_revision; + u_int16_t ah_radio_5ghz_revision; + u_int16_t ah_radio_2ghz_revision; #define ah_macVersion ah_mac_version #define ah_macRev ah_mac_revision @@ -760,8 +762,8 @@ struct ath_hal { #define ah_analog2GhzRev ah_radio_2ghz_revision #define ah_regdomain ah_capabilities.cap_eeprom.ee_regdomain - u_int32_t ah_atim_window; - u_int32_t ah_aifs; + u_int32_t ah_atim_window; + u_int32_t ah_aifs; u_int32_t ah_cw_min; HAL_BOOL ah_software_retry; u_int32_t ah_limit_tx_retries; @@ -808,7 +810,7 @@ typedef struct ath_hal*(ar5k_attach_t) #define AR5K_TUNE_DMA_BEACON_RESP 2 #define AR5K_TUNE_SW_BEACON_RESP 10 -#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 +#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 #define AR5K_TUNE_RADAR_ALERT AH_FALSE #define AR5K_TUNE_MIN_TX_FIFO_THRES 1 #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1) @@ -816,7 +818,7 @@ typedef struct ath_hal*(ar5k_attach_t) #define AR5K_TUNE_REGISTER_TIMEOUT 20000 #define AR5K_TUNE_REGISTER_DWELL_TIME 20000 #define AR5K_TUNE_BEACON_INTERVAL 100 -#define AR5K_TUNE_AIFS 2 +#define AR5K_TUNE_AIFS 2 #define AR5K_TUNE_CWMIN 15 /* @@ -824,9 +826,9 @@ typedef struct ath_hal*(ar5k_attach_t) */ #define AR5K_INIT_TX_LATENCY 502 -#define AR5K_INIT_USEC 39 -#define AR5K_INIT_USEC_TURBO 79 -#define AR5K_INIT_USEC_32 31 +#define AR5K_INIT_USEC 39 +#define AR5K_INIT_USEC_TURBO 79 +#define AR5K_INIT_USEC_32 31 #define AR5K_INIT_CARR_SENSE_EN 1 #define AR5K_INIT_PROG_IFS 920 #define AR5K_INIT_PROG_IFS_TURBO 960 @@ -856,19 +858,19 @@ typedef struct ath_hal*(ar5k_attach_t) (AR5K_INIT_USEC) \ ) #define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \ - (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ - (AR5K_INIT_USEC_TURBO) \ + (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ + (AR5K_INIT_USEC_TURBO) \ ) #define AR5K_INIT_PROTO_TIME_CNTRL ( \ - (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \ + (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \ (AR5K_INIT_PROG_IFS) \ ) -#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \ +#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \ (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) |\ (AR5K_INIT_PROG_IFS_TURBO) \ ) -#define AR5K_INIT_BEACON_CONTROL ( \ - (AR5K_INIT_RESET_TSF << 24) | (AR5K_INIT_BEACON_EN << 23) | \ +#define AR5K_INIT_BEACON_CONTROL ( \ + (AR5K_INIT_RESET_TSF << 24) | (AR5K_INIT_BEACON_EN << 23) | \ (AR5K_INIT_TIM_OFFSET << 16) | (AR5K_INIT_BEACON_PERIOD) \ ) @@ -876,21 +878,21 @@ typedef struct ath_hal*(ar5k_attach_t) * AR5k register access */ -#define AR5K_REG_WRITE(_reg, _val) \ +#define AR5K_REG_WRITE(_reg, _val) \ bus_space_write_4(hal->ah_st, hal->ah_sh, (_reg), (_val)) -#define AR5K_REG_READ(_reg) \ +#define AR5K_REG_READ(_reg) \ ((u_int32_t)bus_space_read_4(hal->ah_st, hal->ah_sh, (_reg))) -#define AR5K_REG_SM(_val, _flags) \ +#define AR5K_REG_SM(_val, _flags) \ (((_val) << _flags##_S) & (_flags)) -#define AR5K_REG_MS(_val, _flags) \ +#define AR5K_REG_MS(_val, _flags) \ (((_val) & (_flags)) >> _flags##_S) -#define AR5K_REG_WRITE_BITS(_reg, _flags, _val) \ - AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) &~ (_flags)) | \ +#define AR5K_REG_WRITE_BITS(_reg, _flags, _val) \ + AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) &~ (_flags)) | \ (((_val) << _flags##_S) & (_flags))) -#define AR5K_REG_ENABLE_BITS(_reg, _flags) \ +#define AR5K_REG_ENABLE_BITS(_reg, _flags) \ AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) | (_flags)) -#define AR5K_REG_DISABLE_BITS(_reg, _flags) \ +#define AR5K_REG_DISABLE_BITS(_reg, _flags) \ AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) &~ (_flags)) /* @@ -911,17 +913,17 @@ struct ar5k_ini { * Unaligned little endian access */ -#define AR5K_LE_READ_2(_p) \ +#define AR5K_LE_READ_2(_p) \ (((u_int8_t *)(_p))[0] | (((u_int8_t *)(_p))[1] << 8)) #define AR5K_LE_READ_4(_p) \ - (((u_int8_t *)(_p))[0] | (((u_int8_t *)(_p))[1] << 8) | \ + (((u_int8_t *)(_p))[0] | (((u_int8_t *)(_p))[1] << 8) | \ (((u_int8_t *)(_p))[2] << 16) | (((u_int8_t *)(_p))[3] << 24)) #define AR5K_LE_WRITE_2(_p, _val) \ - ((((u_int8_t *)(_p))[0] = ((u_int32_t)(_val) & 0xff)), \ - (((u_int8_t *)(_p))[1] = (((u_int32_t)(_val) >> 8) & 0xff))) -#define AR5K_LE_WRITE_4(_p, _val) \ ((((u_int8_t *)(_p))[0] = ((u_int32_t)(_val) & 0xff)), \ - (((u_int8_t *)(_p))[1] = (((u_int32_t)(_val) >> 8) & 0xff)), \ + (((u_int8_t *)(_p))[1] = (((u_int32_t)(_val) >> 8) & 0xff))) +#define AR5K_LE_WRITE_4(_p, _val) \ + ((((u_int8_t *)(_p))[0] = ((u_int32_t)(_val) & 0xff)), \ + (((u_int8_t *)(_p))[1] = (((u_int32_t)(_val) >> 8) & 0xff)), \ (((u_int8_t *)(_p))[2] = (((u_int32_t)(_val) >> 16) & 0xff)), \ (((u_int8_t *)(_p))[3] = (((u_int32_t)(_val) >> 24) & 0xff))) @@ -934,21 +936,21 @@ __BEGIN_DECLS const char *ath_hal_probe(u_int16_t, u_int16_t); struct ath_hal *ath_hal_attach(u_int16_t, void *, bus_space_tag_t, - bus_space_handle_t, HAL_STATUS *); + bus_space_handle_t, HAL_STATUS *); -u_int16_t ath_hal_computetxtime(struct ath_hal *, +u_int16_t ath_hal_computetxtime(struct ath_hal *, const HAL_RATE_TABLE *, u_int32_t, u_int16_t, HAL_BOOL); u_int ath_hal_mhz2ieee(u_int, u_int); -u_int ath_hal_ieee2mhz(u_int, u_int); +u_int ath_hal_ieee2mhz(u_int, u_int); HAL_BOOL ath_hal_init_channels(struct ath_hal *, HAL_CHANNEL *, u_int, u_int *, HAL_CTRY_CODE, u_int16_t, HAL_BOOL, HAL_BOOL); -void ar5k_radar_alert(struct ath_hal *); -int ar5k_eeprom_read_mac(struct ath_hal *, u_int8_t *); -ieee80211_regdomain_t *ar5k_regdomain_to_ieee(u_int8_t); -u_int8_t ar5k_regdomain_from_ieee(ieee80211_regdomain_t *); +void ar5k_radar_alert(struct ath_hal *); +int ar5k_eeprom_read_mac(struct ath_hal *, u_int8_t *); +ieee80211_regdomain_t *ar5k_regdomain_to_ieee(u_int8_t); +u_int8_t ar5k_regdomain_from_ieee(ieee80211_regdomain_t *); u_int32_t ar5k_bitswap(u_int32_t, u_int); u_int ar5k_clocktoh(u_int, HAL_BOOL); u_int ar5k_htoclock(u_int, HAL_BOOL); |