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-rw-r--r--sys/dev/fdt/rkpcie.c4
-rw-r--r--sys/dev/ic/elink3.c4
-rw-r--r--sys/dev/ic/malo.c4
-rw-r--r--sys/dev/ic/tcic2reg.h4
-rw-r--r--sys/dev/ic/twereg.h4
-rw-r--r--sys/dev/pci/if_de.c6
-rw-r--r--sys/dev/pci/if_em_hw.c6
-rw-r--r--sys/dev/pci/if_iwm.c4
-rw-r--r--sys/dev/pci/if_tl.c4
-rw-r--r--sys/dev/pv/hypervic.c2
-rw-r--r--sys/dev/pv/xenstore.c6
-rw-r--r--sys/dev/sbus/stp4020.c4
-rw-r--r--sys/dev/sdmmc/sdhc.c4
-rw-r--r--sys/dev/usb/umcs.h10
14 files changed, 33 insertions, 33 deletions
diff --git a/sys/dev/fdt/rkpcie.c b/sys/dev/fdt/rkpcie.c
index 3cd05af2b45..78fe0a4932b 100644
--- a/sys/dev/fdt/rkpcie.c
+++ b/sys/dev/fdt/rkpcie.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: rkpcie.c,v 1.16 2022/01/09 05:42:37 jsg Exp $ */
+/* $OpenBSD: rkpcie.c,v 1.17 2023/04/11 00:45:08 jsg Exp $ */
/*
* Copyright (c) 2018 Mark Kettenis <kettenis@openbsd.org>
*
@@ -168,7 +168,7 @@ void rkpcie_intr_disestablish(void *, void *);
* It is important to have reached L0 state before beginning Gen 2 training,
* as it is documented that setting the Retrain Link bit while currently
* in Recovery or Configuration states is a race condition that may result
- * in missing the retraining. See See PCIE 2.0 Base Specification, 7.8.7
+ * in missing the retraining. See PCIE 2.0 Base Specification, 7.8.7
* Link Control Register implementation notes on Retrain Link bit.
*/
diff --git a/sys/dev/ic/elink3.c b/sys/dev/ic/elink3.c
index 46a920d2b3a..ccec2d00ac7 100644
--- a/sys/dev/ic/elink3.c
+++ b/sys/dev/ic/elink3.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: elink3.c,v 1.98 2020/12/12 11:48:52 jan Exp $ */
+/* $OpenBSD: elink3.c,v 1.99 2023/04/11 00:45:08 jsg Exp $ */
/* $NetBSD: elink3.c,v 1.32 1997/05/14 00:22:00 thorpej Exp $ */
/*
@@ -609,7 +609,7 @@ epinit(struct ep_softc *sc)
for (i = 0; i < 31; i++)
bus_space_read_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS));
- /* Set threshold for for Tx-space available interrupt. */
+ /* Set threshold for Tx-space available interrupt. */
bus_space_write_2(iot, ioh, EP_COMMAND,
SET_TX_AVAIL_THRESH | (1600 >> sc->txashift));
diff --git a/sys/dev/ic/malo.c b/sys/dev/ic/malo.c
index ab5511d082c..ef922c00648 100644
--- a/sys/dev/ic/malo.c
+++ b/sys/dev/ic/malo.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: malo.c,v 1.123 2022/04/21 21:03:02 stsp Exp $ */
+/* $OpenBSD: malo.c,v 1.124 2023/04/11 00:45:08 jsg Exp $ */
/*
* Copyright (c) 2006 Claudio Jeker <claudio@openbsd.org>
@@ -1662,7 +1662,7 @@ malo_rx_intr(struct malo_softc *sc)
}
/*
- * New mbuf mbuf successfully loaded
+ * New mbuf successfully loaded
*/
m = data->m;
data->m = mnew;
diff --git a/sys/dev/ic/tcic2reg.h b/sys/dev/ic/tcic2reg.h
index 236a6879f76..b8d12b95b4f 100644
--- a/sys/dev/ic/tcic2reg.h
+++ b/sys/dev/ic/tcic2reg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: tcic2reg.h,v 1.5 2022/01/09 05:42:42 jsg Exp $ */
+/* $OpenBSD: tcic2reg.h,v 1.6 2023/04/11 00:45:08 jsg Exp $ */
/* $NetBSD: tcic2reg.h,v 1.1 1999/03/23 20:04:14 bad Exp $ */
/*-
@@ -304,7 +304,7 @@
/*
* If set, use full address (a[12:23]) for MCS16 generation.
* If clear, run in ISA-compatible mode (only using a[17:23]).
- * With many chip sets, the TCIC-2/N's timing will will allow full
+ * With many chip sets, the TCIC-2/N's timing will allow full
* address decoding to be used rather than limiting us to LA[17:23];
* thus we can get around the ISA spec which limits the granularity
* of bus sizing to 128K blocks.
diff --git a/sys/dev/ic/twereg.h b/sys/dev/ic/twereg.h
index 53d24492caa..72c6ea5fa3e 100644
--- a/sys/dev/ic/twereg.h
+++ b/sys/dev/ic/twereg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: twereg.h,v 1.9 2008/09/01 17:30:56 deraadt Exp $ */
+/* $OpenBSD: twereg.h,v 1.10 2023/04/11 00:45:08 jsg Exp $ */
/*
* Copyright (c) 2000 Michael Shalayeff
@@ -108,7 +108,7 @@
* From 3ware's documentation:
*
* All parameters maintained by the controller are grouped into related
- * tables. Tables are are accessed indirectly via get and set parameter
+ * tables. Tables are accessed indirectly via get and set parameter
* commands. To access a specific parameter in a table, the table ID and
* parameter index are used to uniquely identify a parameter. Table
* 0xffff is the directory table and provides a list of the table IDs and
diff --git a/sys/dev/pci/if_de.c b/sys/dev/pci/if_de.c
index a4ef36cd42e..b178a4aeeef 100644
--- a/sys/dev/pci/if_de.c
+++ b/sys/dev/pci/if_de.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: if_de.c,v 1.141 2022/08/15 02:07:11 jsg Exp $ */
+/* $OpenBSD: if_de.c,v 1.142 2023/04/11 00:45:08 jsg Exp $ */
/* $NetBSD: if_de.c,v 1.58 1998/01/12 09:39:58 thorpej Exp $ */
/*-
@@ -960,7 +960,7 @@ tulip_21041_media_poll(tulip_softc_t * const sc, const tulip_mediapoll_event_t e
}
/*
- * If we've been been asked to start a poll or link change interrupt
+ * If we've been asked to start a poll or link change interrupt
* restart the probe (and reset the tulip to a known state).
*/
if (event == TULIP_MEDIAPOLL_START) {
@@ -3747,7 +3747,7 @@ tulip_txput(tulip_softc_t * const sc, struct mbuf *m, int notonqueue)
* a bit reminiscent of going on the Ark two by two
* since each descriptor for the TULIP can describe
* two buffers. So we advance through packet filling
- * each of the two entries at a time to to fill each
+ * each of the two entries at a time to fill each
* descriptor. Clear the first and last segment bits
* in each descriptor (actually just clear everything
* but the end-of-ring or chain bits) to make sure
diff --git a/sys/dev/pci/if_em_hw.c b/sys/dev/pci/if_em_hw.c
index 6d230587e99..7db048d482a 100644
--- a/sys/dev/pci/if_em_hw.c
+++ b/sys/dev/pci/if_em_hw.c
@@ -31,7 +31,7 @@
*******************************************************************************/
-/* $OpenBSD: if_em_hw.c,v 1.116 2022/06/23 09:47:04 jsg Exp $ */
+/* $OpenBSD: if_em_hw.c,v 1.117 2023/04/11 00:45:08 jsg Exp $ */
/*
* if_em_hw.c Shared functions for accessing and configuring the MAC
*/
@@ -3975,7 +3975,7 @@ em_force_mac_fc(struct em_hw *hw)
* The possible values of the "fc" parameter are: 0: Flow control is
* completely disabled 1: Rx flow control is enabled (we can receive
* pause frames but not send pause frames). 2: Tx flow control is
- * enabled (we can send pause frames frames but we do not receive
+ * enabled (we can send pause frames but we do not receive
* pause frames). 3: Both Rx and TX flow control (symmetric) is
* enabled. other: No other values should be possible at this point.
*/
@@ -4466,7 +4466,7 @@ em_check_for_link(struct em_hw *hw)
* TBI link partner, we will store bad
* packets. Some frames have an additional
* byte on the end and will look like CRC
- * errors to to the hardware.
+ * errors to the hardware.
*/
if (!hw->tbi_compatibility_on) {
hw->tbi_compatibility_on = TRUE;
diff --git a/sys/dev/pci/if_iwm.c b/sys/dev/pci/if_iwm.c
index 437a2b9f372..6c75baca82c 100644
--- a/sys/dev/pci/if_iwm.c
+++ b/sys/dev/pci/if_iwm.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: if_iwm.c,v 1.405 2022/12/16 13:49:35 stsp Exp $ */
+/* $OpenBSD: if_iwm.c,v 1.406 2023/04/11 00:45:08 jsg Exp $ */
/*
* Copyright (c) 2014, 2016 genua gmbh <info@genua.de>
@@ -10121,7 +10121,7 @@ iwm_send_paging_cmd(struct iwm_softc *sc, const struct iwm_fw_sects *fw)
.block_num = htole32(sc->num_of_paging_blk),
};
- /* loop for for all paging blocks + CSS block */
+ /* loop for all paging blocks + CSS block */
for (blk_idx = 0; blk_idx < sc->num_of_paging_blk + 1; blk_idx++) {
dev_phy_addr = htole32(
sc->fw_paging_db[blk_idx].fw_paging_block.paddr >>
diff --git a/sys/dev/pci/if_tl.c b/sys/dev/pci/if_tl.c
index 961189859db..bea6f1ba0e6 100644
--- a/sys/dev/pci/if_tl.c
+++ b/sys/dev/pci/if_tl.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: if_tl.c,v 1.76 2022/03/11 18:00:50 mpi Exp $ */
+/* $OpenBSD: if_tl.c,v 1.77 2023/04/11 00:45:08 jsg Exp $ */
/*
* Copyright (c) 1997, 1998
@@ -1015,7 +1015,7 @@ tl_newbuf(struct tl_softc *sc, struct tl_chain_onefrag *c)
* into mbufs. This saves us from having to do a buffer copy: we can
* just hand the mbufs directly to the network stack. Once the frame
* has been sent on its way, the 'list' structure is assigned a new
- * buffer and moved to the end of the RX chain. As long we we stay
+ * buffer and moved to the end of the RX chain. As long we stay
* ahead of the chip, it will always think it has an endless receive
* channel.
*
diff --git a/sys/dev/pv/hypervic.c b/sys/dev/pv/hypervic.c
index a7455d03e5b..b3ce2d91bea 100644
--- a/sys/dev/pv/hypervic.c
+++ b/sys/dev/pv/hypervic.c
@@ -889,7 +889,7 @@ kvp_get_ip_info(struct hv_kvp *kvp, const uint8_t *mac, uint8_t *family,
TAILQ_FOREACH(ifa, &ifp->if_addrlist, ifa_list) {
/*
* First IPv4 address is always a best match unless
- * we were asked for for an IPv6 address.
+ * we were asked for an IPv6 address.
*/
if ((af == AF_INET || af == AF_UNSPEC) &&
(ifa->ifa_addr->sa_family == AF_INET)) {
diff --git a/sys/dev/pv/xenstore.c b/sys/dev/pv/xenstore.c
index 1f4c2307bdd..27199590fbd 100644
--- a/sys/dev/pv/xenstore.c
+++ b/sys/dev/pv/xenstore.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: xenstore.c,v 1.48 2023/01/07 06:40:21 asou Exp $ */
+/* $OpenBSD: xenstore.c,v 1.49 2023/04/11 00:45:08 jsg Exp $ */
/*
* Copyright (c) 2015 Mike Belopuhov
@@ -471,7 +471,7 @@ xs_ring_put(struct xs_softc *xs, void *src, size_t size)
size = MIN(size, avail);
/* How many contiguous bytes can we memcpy... */
left = XS_RING_SIZE - prod;
- /* ...bounded by by how much we need to write? */
+ /* ...bounded by how much we need to write? */
left = MIN(left, size);
memcpy(&xsr->xsr_req[prod], src, left);
@@ -498,7 +498,7 @@ xs_ring_get(struct xs_softc *xs, void *dst, size_t size)
size = MIN(size, avail);
/* How many contiguous bytes can we memcpy... */
left = XS_RING_SIZE - cons;
- /* ...bounded by by how much we need to read? */
+ /* ...bounded by how much we need to read? */
left = MIN(left, size);
memcpy(dst, &xsr->xsr_rsp[cons], left);
diff --git a/sys/dev/sbus/stp4020.c b/sys/dev/sbus/stp4020.c
index 8d469dadc2e..744e4313bf0 100644
--- a/sys/dev/sbus/stp4020.c
+++ b/sys/dev/sbus/stp4020.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: stp4020.c,v 1.22 2020/02/18 00:10:22 cheloha Exp $ */
+/* $OpenBSD: stp4020.c,v 1.23 2023/04/11 00:45:09 jsg Exp $ */
/* $NetBSD: stp4020.c,v 1.23 2002/06/01 23:51:03 lukem Exp $ */
/*-
@@ -796,7 +796,7 @@ stp4020_chip_intr_establish(pcmcia_chipset_handle_t pch,
/*
* Note that this code relies on softintr_establish() to be
* used with real, hardware ipl values. All platforms with
- * SBus support support this.
+ * SBus support this.
*/
h->intrhandler = handler;
h->intrarg = arg;
diff --git a/sys/dev/sdmmc/sdhc.c b/sys/dev/sdmmc/sdhc.c
index ce748b515ec..2ed10fea48b 100644
--- a/sys/dev/sdmmc/sdhc.c
+++ b/sys/dev/sdmmc/sdhc.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: sdhc.c,v 1.73 2022/01/19 10:51:04 patrick Exp $ */
+/* $OpenBSD: sdhc.c,v 1.74 2023/04/11 00:45:09 jsg Exp $ */
/*
* Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
@@ -149,7 +149,7 @@ struct cfdriver sdhc_cd = {
* for the Transfer Mode register that we write out when we write the
* Command register.
*
- * The Arasan controller controller integrated on the Broadcom SoCs
+ * The Arasan controller integrated on the Broadcom SoCs
* used in the Raspberry Pi has an interesting bug where writing the
* same 32-bit register twice doesn't work. This means that we lose
* writes to the Block Sine and/or Block Count register. We work
diff --git a/sys/dev/usb/umcs.h b/sys/dev/usb/umcs.h
index af0316b559e..3062d7dc28b 100644
--- a/sys/dev/usb/umcs.h
+++ b/sys/dev/usb/umcs.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: umcs.h,v 1.5 2022/02/21 12:41:39 jsg Exp $ */
+/* $OpenBSD: umcs.h,v 1.6 2023/04/11 00:45:09 jsg Exp $ */
/* $NetBSD: umcs.h,v 1.1 2014/03/16 09:34:45 martin Exp $ */
/*-
@@ -48,7 +48,7 @@
* All these registers are documented only in full datasheet, which
* can be requested from MosChip tech support.
*/
-#define UMCS_SP1 0x00 /* Options for for UART 1, R/W */
+#define UMCS_SP1 0x00 /* Option bits for UART 1, R/W */
#define UMCS_CTRL1 0x01 /* Control bits for UART 1, R/W */
#define UMCS_PINPONGHIGH 0x02 /* High bits of ping-pong reg, R/W */
#define UMCS_PINPONGLOW 0x03 /* Low bits of ping-pong reg, R/W */
@@ -56,11 +56,11 @@
/* DCRx_1 Registers goes here (see below, they are documented) */
#define UMCS_GPIO 0x07 /* GPIO_0 and GPIO_1 bits, R/W */
-#define UMCS_SP2 0x08 /* Options for for UART 2, R/W */
+#define UMCS_SP2 0x08 /* Option bits for UART 2, R/W */
#define UMCS_CTRL2 0x09 /* Control bits for UART 2, R/W */
-#define UMCS_SP3 0x0a /* Options for for UART 3, R/W */
+#define UMCS_SP3 0x0a /* Option bits for UART 3, R/W */
#define UMCS_CTRL3 0x0b /* Control bits for UART 3, R/W */
-#define UMCS_SP4 0x0c /* Options for for UART 4, R/W */
+#define UMCS_SP4 0x0c /* Option bits for UART 4, R/W */
#define UMCS_CTRL4 0x0d /* Control bits for UART 4, R/W */
#define UMCS_PLL_DIV_M 0x0e /* Pre-divider for PLL, R/W */
#define UMCS_UNKNOWN1 0x0f /* NOT MENTIONED AND NOT USED */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 02:04:05 +0000