diff options
Diffstat (limited to 'sys/dev')
| -rw-r--r-- | sys/dev/pci/if_rl.c | 1541 | ||||
| -rw-r--r-- | sys/dev/pci/if_rlreg.h | 480 |
2 files changed, 0 insertions, 2021 deletions
diff --git a/sys/dev/pci/if_rl.c b/sys/dev/pci/if_rl.c deleted file mode 100644 index 95cd9948cf8..00000000000 --- a/sys/dev/pci/if_rl.c +++ /dev/null @@ -1,1541 +0,0 @@ -/* $OpenBSD: if_rl.c,v 1.27 2001/03/25 03:53:00 fgsch Exp $ */ - -/* - * Copyright (c) 1997, 1998 - * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Bill Paul. - * 4. Neither the name of the author nor the names of any co-contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: src/sys/pci/if_rl.c,v 1.38 1999/12/28 06:04:29 billf Exp $ - */ - -/* - * RealTek 8129/8139 PCI NIC driver - * - * Supports several extremely cheap PCI 10/100 adapters based on - * the RealTek chipset. Datasheets can be obtained from - * www.realtek.com.tw. - * - * Written by Bill Paul <wpaul@ctr.columbia.edu> - * Electrical Engineering Department - * Columbia University, New York City - */ - -/* - * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is - * probably the worst PCI ethernet controller ever made, with the possible - * exception of the FEAST chip made by SMC. The 8139 supports bus-master - * DMA, but it has a terrible interface that nullifies any performance - * gains that bus-master DMA usually offers. - * - * For transmission, the chip offers a series of four TX descriptor - * registers. Each transmit frame must be in a contiguous buffer, aligned - * on a longword (32-bit) boundary. This means we almost always have to - * do mbuf copies in order to transmit a frame, except in the unlikely - * case where a) the packet fits into a single mbuf, and b) the packet - * is 32-bit aligned within the mbuf's data area. The presence of only - * four descriptor registers means that we can never have more than four - * packets queued for transmission at any one time. - * - * Reception is not much better. The driver has to allocate a single large - * buffer area (up to 64K in size) into which the chip will DMA received - * frames. Because we don't know where within this region received packets - * will begin or end, we have no choice but to copy data from the buffer - * area into mbufs in order to pass the packets up to the higher protocol - * levels. - * - * It's impossible given this rotten design to really achieve decent - * performance at 100Mbps, unless you happen to have a 400Mhz PII or - * some equally overmuscled CPU to drive it. - * - * On the bright side, the 8139 does have a built-in PHY, although - * rather than using an MDIO serial interface like most other NICs, the - * PHY registers are directly accessible through the 8139's register - * space. The 8139 supports autonegotiation, as well as a 64-bit multicast - * filter. - * - * The 8129 chip is an older version of the 8139 that uses an external PHY - * chip. The 8129 has a serial MDIO interface for accessing the MII where - * the 8139 lets you directly access the on-board PHY registers. We need - * to select which interface to use depending on the chip type. - */ - -#include "bpfilter.h" - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/sockio.h> -#include <sys/mbuf.h> -#include <sys/malloc.h> -#include <sys/kernel.h> -#include <sys/socket.h> -#include <sys/device.h> -#include <sys/timeout.h> - -#include <net/if.h> -#include <net/if_dl.h> -#include <net/if_types.h> - -#ifdef INET -#include <netinet/in.h> -#include <netinet/in_systm.h> -#include <netinet/in_var.h> -#include <netinet/ip.h> -#include <netinet/if_ether.h> -#endif - -#include <net/if_media.h> - -#if NBPFILTER > 0 -#include <net/bpf.h> -#endif - -#include <vm/vm.h> /* for vtophys */ -#include <vm/pmap.h> /* for vtophys */ -#include <vm/vm_kern.h> -#include <vm/vm_extern.h> -#include <machine/bus.h> - -#include <dev/mii/mii.h> -#include <dev/mii/miivar.h> -#include <dev/pci/pcireg.h> -#include <dev/pci/pcivar.h> -#include <dev/pci/pcidevs.h> - -/* - * Default to using PIO access for this driver. On SMP systems, - * there appear to be problems with memory mapped mode: it looks like - * doing too many memory mapped access back to back in rapid succession - * can hang the bus. I'm inclined to blame this on crummy design/construction - * on the part of RealTek. Memory mapped mode does appear to work on - * uniprocessor systems though. - */ -#define RL_USEIOSPACE - -#include <dev/pci/if_rlreg.h> - -/* - * Various supported PHY vendors/types and their names. Note that - * this driver will work with pretty much any MII-compliant PHY, - * so failure to positively identify the chip is not a fatal error. - */ - -int rl_probe __P((struct device *, void *, void *)); -void rl_attach __P((struct device *, struct device *, void *)); -int rl_intr __P((void *)); -void rl_tick __P((void *)); -void rl_shutdown __P((void *)); - -int rl_encap __P((struct rl_softc *, struct mbuf * )); - -void rl_rxeof __P((struct rl_softc *)); -void rl_txeof __P((struct rl_softc *)); -void rl_start __P((struct ifnet *)); -int rl_ioctl __P((struct ifnet *, u_long, caddr_t)); -void rl_init __P((void *)); -void rl_stop __P((struct rl_softc *)); -void rl_watchdog __P((struct ifnet *)); -int rl_ifmedia_upd __P((struct ifnet *)); -void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); - -void rl_eeprom_putbyte __P((struct rl_softc *, int)); -void rl_eeprom_getword __P((struct rl_softc *, int, u_int16_t *)); -void rl_read_eeprom __P((struct rl_softc *, caddr_t, - int, int, int)); -void rl_mii_sync __P((struct rl_softc *)); -void rl_mii_send __P((struct rl_softc *, u_int32_t, int)); -int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *)); -int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *)); - -int rl_miibus_readreg __P((struct device *, int, int)); -void rl_miibus_writereg __P((struct device *, int, int, int)); -void rl_miibus_statchg __P((struct device *)); - -u_int8_t rl_calchash __P((caddr_t)); -void rl_setmulti __P((struct rl_softc *)); -void rl_reset __P((struct rl_softc *)); -int rl_list_tx_init __P((struct rl_softc *)); - -struct rl_type rl_devs[] = { - { PCI_VENDOR_ACCTON, PCI_PRODUCT_ACCTON_5030 }, - { PCI_VENDOR_ADDTRON, PCI_PRODUCT_ADDTRON_8139 }, - { PCI_VENDOR_DELTA, PCI_PRODUCT_DELTA_8139 }, - { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_530TXPLUS }, - { PCI_VENDOR_NORTEL, PCI_PRODUCT_NORTEL_BS21 }, - { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8129 }, - { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139 }, - { 0, 0 } -}; - -#define EE_SET(x) \ - CSR_WRITE_1(sc, RL_EECMD, \ - CSR_READ_1(sc, RL_EECMD) | x) - -#define EE_CLR(x) \ - CSR_WRITE_1(sc, RL_EECMD, \ - CSR_READ_1(sc, RL_EECMD) & ~x) - -/* - * Send a read command and address to the EEPROM, check for ACK. - */ -void rl_eeprom_putbyte(sc, addr) - struct rl_softc *sc; - int addr; -{ - register int d, i; - - d = addr | RL_EECMD_READ; - - /* - * Feed in each bit and strobe the clock. - */ - for (i = 0x400; i; i >>= 1) { - if (d & i) { - EE_SET(RL_EE_DATAIN); - } else { - EE_CLR(RL_EE_DATAIN); - } - DELAY(100); - EE_SET(RL_EE_CLK); - DELAY(150); - EE_CLR(RL_EE_CLK); - DELAY(100); - } - - return; -} - -/* - * Read a word of data stored in the EEPROM at address 'addr.' - */ -void rl_eeprom_getword(sc, addr, dest) - struct rl_softc *sc; - int addr; - u_int16_t *dest; -{ - register int i; - u_int16_t word = 0; - - /* Enter EEPROM access mode. */ - CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); - - /* - * Send address of word we want to read. - */ - rl_eeprom_putbyte(sc, addr); - - CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); - - /* - * Start reading bits from EEPROM. - */ - for (i = 0x8000; i; i >>= 1) { - EE_SET(RL_EE_CLK); - DELAY(100); - if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) - word |= i; - EE_CLR(RL_EE_CLK); - DELAY(100); - } - - /* Turn off EEPROM access mode. */ - CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); - - *dest = word; - - return; -} - -/* - * Read a sequence of words from the EEPROM. - */ -void rl_read_eeprom(sc, dest, off, cnt, swap) - struct rl_softc *sc; - caddr_t dest; - int off; - int cnt; - int swap; -{ - int i; - u_int16_t word = 0, *ptr; - - for (i = 0; i < cnt; i++) { - rl_eeprom_getword(sc, off + i, &word); - ptr = (u_int16_t *)(dest + (i * 2)); - if (swap) - *ptr = ntohs(word); - else - *ptr = word; - } - - return; -} - - -/* - * MII access routines are provided for the 8129, which - * doesn't have a built-in PHY. For the 8139, we fake things - * up by diverting rl_phy_readreg()/rl_phy_writereg() to the - * direct access PHY registers. - */ -#define MII_SET(x) \ - CSR_WRITE_1(sc, RL_MII, \ - CSR_READ_1(sc, RL_MII) | x) - -#define MII_CLR(x) \ - CSR_WRITE_1(sc, RL_MII, \ - CSR_READ_1(sc, RL_MII) & ~x) - -/* - * Sync the PHYs by setting data bit and strobing the clock 32 times. - */ -void rl_mii_sync(sc) - struct rl_softc *sc; -{ - register int i; - - MII_SET(RL_MII_DIR|RL_MII_DATAOUT); - - for (i = 0; i < 32; i++) { - MII_SET(RL_MII_CLK); - DELAY(1); - MII_CLR(RL_MII_CLK); - DELAY(1); - } - - return; -} - -/* - * Clock a series of bits through the MII. - */ -void rl_mii_send(sc, bits, cnt) - struct rl_softc *sc; - u_int32_t bits; - int cnt; -{ - int i; - - MII_CLR(RL_MII_CLK); - - for (i = (0x1 << (cnt - 1)); i; i >>= 1) { - if (bits & i) { - MII_SET(RL_MII_DATAOUT); - } else { - MII_CLR(RL_MII_DATAOUT); - } - DELAY(1); - MII_CLR(RL_MII_CLK); - DELAY(1); - MII_SET(RL_MII_CLK); - } -} - -/* - * Read an PHY register through the MII. - */ -int rl_mii_readreg(sc, frame) - struct rl_softc *sc; - struct rl_mii_frame *frame; - -{ - int i, ack, s; - - s = splimp(); - - /* - * Set up frame for RX. - */ - frame->mii_stdelim = RL_MII_STARTDELIM; - frame->mii_opcode = RL_MII_READOP; - frame->mii_turnaround = 0; - frame->mii_data = 0; - - CSR_WRITE_2(sc, RL_MII, 0); - - /* - * Turn on data xmit. - */ - MII_SET(RL_MII_DIR); - - rl_mii_sync(sc); - - /* - * Send command/address info. - */ - rl_mii_send(sc, frame->mii_stdelim, 2); - rl_mii_send(sc, frame->mii_opcode, 2); - rl_mii_send(sc, frame->mii_phyaddr, 5); - rl_mii_send(sc, frame->mii_regaddr, 5); - - /* Idle bit */ - MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); - DELAY(1); - MII_SET(RL_MII_CLK); - DELAY(1); - - /* Turn off xmit. */ - MII_CLR(RL_MII_DIR); - - /* Check for ack */ - MII_CLR(RL_MII_CLK); - DELAY(1); - MII_SET(RL_MII_CLK); - DELAY(1); - ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; - - /* - * Now try reading data bits. If the ack failed, we still - * need to clock through 16 cycles to keep the PHY(s) in sync. - */ - if (ack) { - for(i = 0; i < 16; i++) { - MII_CLR(RL_MII_CLK); - DELAY(1); - MII_SET(RL_MII_CLK); - DELAY(1); - } - goto fail; - } - - for (i = 0x8000; i; i >>= 1) { - MII_CLR(RL_MII_CLK); - DELAY(1); - if (!ack) { - if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) - frame->mii_data |= i; - DELAY(1); - } - MII_SET(RL_MII_CLK); - DELAY(1); - } - -fail: - - MII_CLR(RL_MII_CLK); - DELAY(1); - MII_SET(RL_MII_CLK); - DELAY(1); - - splx(s); - - if (ack) - return(1); - return(0); -} - -/* - * Write to a PHY register through the MII. - */ -int rl_mii_writereg(sc, frame) - struct rl_softc *sc; - struct rl_mii_frame *frame; - -{ - int s; - - s = splimp(); - /* - * Set up frame for TX. - */ - - frame->mii_stdelim = RL_MII_STARTDELIM; - frame->mii_opcode = RL_MII_WRITEOP; - frame->mii_turnaround = RL_MII_TURNAROUND; - - /* - * Turn on data output. - */ - MII_SET(RL_MII_DIR); - - rl_mii_sync(sc); - - rl_mii_send(sc, frame->mii_stdelim, 2); - rl_mii_send(sc, frame->mii_opcode, 2); - rl_mii_send(sc, frame->mii_phyaddr, 5); - rl_mii_send(sc, frame->mii_regaddr, 5); - rl_mii_send(sc, frame->mii_turnaround, 2); - rl_mii_send(sc, frame->mii_data, 16); - - /* Idle bit. */ - MII_SET(RL_MII_CLK); - DELAY(1); - MII_CLR(RL_MII_CLK); - DELAY(1); - - /* - * Turn off xmit. - */ - MII_CLR(RL_MII_DIR); - - splx(s); - - return(0); -} - -/* - * Calculate CRC of a multicast group address, return the upper 6 bits. - */ -u_int8_t rl_calchash(addr) - caddr_t addr; -{ - u_int32_t crc, carry; - int i, j; - u_int8_t c; - - /* Compute CRC for the address value. */ - crc = 0xFFFFFFFF; /* initial value */ - - for (i = 0; i < 6; i++) { - c = *(addr + i); - for (j = 0; j < 8; j++) { - carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); - crc <<= 1; - c >>= 1; - if (carry) - crc = (crc ^ 0x04c11db6) | carry; - } - } - - /* return the filter bit position */ - return(crc >> 26); -} - -/* - * Program the 64-bit multicast hash filter. - */ -void rl_setmulti(sc) - struct rl_softc *sc; -{ - struct ifnet *ifp; - int h = 0; - u_int32_t hashes[2] = { 0, 0 }; - struct arpcom *ac = &sc->arpcom; - struct ether_multi *enm; - struct ether_multistep step; - u_int32_t rxfilt; - int mcnt = 0; - - ifp = &sc->arpcom.ac_if; - - rxfilt = CSR_READ_4(sc, RL_RXCFG); - - if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { - rxfilt |= RL_RXCFG_RX_MULTI; - CSR_WRITE_4(sc, RL_RXCFG, rxfilt); - CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); - CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); - return; - } - - /* first, zot all the existing hash bits */ - CSR_WRITE_4(sc, RL_MAR0, 0); - CSR_WRITE_4(sc, RL_MAR4, 0); - - /* now program new ones */ - ETHER_FIRST_MULTI(step, ac, enm); - while (enm != NULL) { - mcnt++; - h = rl_calchash(enm->enm_addrlo); - if (h < 32) - hashes[0] |= (1 << h); - else - hashes[1] |= (1 << (h - 32)); - mcnt++; - ETHER_NEXT_MULTI(step, enm); - } - - if (mcnt) - rxfilt |= RL_RXCFG_RX_MULTI; - else - rxfilt &= ~RL_RXCFG_RX_MULTI; - - CSR_WRITE_4(sc, RL_RXCFG, rxfilt); - CSR_WRITE_4(sc, RL_MAR0, hashes[0]); - CSR_WRITE_4(sc, RL_MAR4, hashes[1]); - - return; -} - -void rl_reset(sc) - struct rl_softc *sc; -{ - register int i; - - CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); - - for (i = 0; i < RL_TIMEOUT; i++) { - DELAY(10); - if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) - break; - } - if (i == RL_TIMEOUT) - printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); - - return; -} - -/* - * Initialize the transmit descriptors. - */ -int rl_list_tx_init(sc) - struct rl_softc *sc; -{ - struct rl_chain_data *cd; - int i; - - cd = &sc->rl_cdata; - for (i = 0; i < RL_TX_LIST_CNT; i++) { - cd->rl_tx_chain[i] = NULL; - CSR_WRITE_4(sc, - RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); - } - - sc->rl_cdata.cur_tx = 0; - sc->rl_cdata.last_tx = 0; - - return(0); -} - -/* - * A frame has been uploaded: pass the resulting mbuf chain up to - * the higher level protocols. - * - * You know there's something wrong with a PCI bus-master chip design - * when you have to use m_devget(). - * - * The receive operation is badly documented in the datasheet, so I'll - * attempt to document it here. The driver provides a buffer area and - * places its base address in the RX buffer start address register. - * The chip then begins copying frames into the RX buffer. Each frame - * is preceeded by a 32-bit RX status word which specifies the length - * of the frame and certain other status bits. Each frame (starting with - * the status word) is also 32-bit aligned. The frame length is in the - * first 16 bits of the status word; the lower 15 bits correspond with - * the 'rx status register' mentioned in the datasheet. - * - * Note: to make the Alpha happy, the frame payload needs to be aligned - * on a 32-bit boundary. To achieve this, we cheat a bit by copying from - * the ring buffer starting at an address two bytes before the actual - * data location. We can then shave off the first two bytes using m_adj(). - * The reason we do this is because m_devget() doesn't let us specify an - * offset into the mbuf storage space, so we have to artificially create - * one. The ring is allocated in such a way that there are a few unused - * bytes of space preceecing it so that it will be safe for us to do the - * 2-byte backstep even if reading from the ring at offset 0. - */ -void rl_rxeof(sc) - struct rl_softc *sc; -{ - struct ether_header *eh; - struct mbuf *m; - struct ifnet *ifp; - int total_len = 0; - u_int32_t rxstat; - caddr_t rxbufpos; - int wrap = 0; - u_int16_t cur_rx; - u_int16_t limit; - u_int16_t rx_bytes = 0, max_bytes; - - ifp = &sc->arpcom.ac_if; - - cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; - - /* Do not try to read past this point. */ - limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; - - if (limit < cur_rx) - max_bytes = (RL_RXBUFLEN - cur_rx) + limit; - else - max_bytes = limit - cur_rx; - - while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { - rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; - rxstat = *(u_int32_t *)rxbufpos; - - /* - * Here's a totally undocumented fact for you. When the - * RealTek chip is in the process of copying a packet into - * RAM for you, the length will be 0xfff0. If you spot a - * packet header with this value, you need to stop. The - * datasheet makes absolutely no mention of this and - * RealTek should be shot for this. - */ - if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) - break; - - if (!(rxstat & RL_RXSTAT_RXOK)) { - ifp->if_ierrors++; - rl_init(sc); - return; - } - - /* No errors; receive the packet. */ - total_len = rxstat >> 16; - rx_bytes += total_len + 4; - - /* - * XXX The RealTek chip includes the CRC with every - * received frame, and there's no way to turn this - * behavior off (at least, I can't find anything in - * the manual that explains how to do it) so we have - * to trim off the CRC manually. - */ - total_len -= ETHER_CRC_LEN; - - /* - * Avoid trying to read more bytes than we know - * the chip has prepared for us. - */ - if (rx_bytes > max_bytes) - break; - - rxbufpos = sc->rl_cdata.rl_rx_buf + - ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); - - if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) - rxbufpos = sc->rl_cdata.rl_rx_buf; - - wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; - - if (total_len > wrap) { - m = m_devget(rxbufpos - RL_ETHER_ALIGN, - wrap + RL_ETHER_ALIGN, 0, ifp, NULL); - if (m == NULL) - ifp->if_ierrors++; - else { - m_adj(m, RL_ETHER_ALIGN); - m_copyback(m, wrap, total_len - wrap, - sc->rl_cdata.rl_rx_buf); - m = m_pullup(m, sizeof(struct ether_header)); - if (m == NULL) - ifp->if_ierrors++; - } - cur_rx = (total_len - wrap + ETHER_CRC_LEN); - } else { - m = m_devget(rxbufpos - RL_ETHER_ALIGN, - total_len + RL_ETHER_ALIGN, 0, ifp, NULL); - if (m == NULL) - ifp->if_ierrors++; - else - m_adj(m, RL_ETHER_ALIGN); - cur_rx += total_len + 4 + ETHER_CRC_LEN; - } - - /* - * Round up to 32-bit boundary. - */ - cur_rx = (cur_rx + 3) & ~3; - CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); - - if (m == NULL) - continue; - - eh = mtod(m, struct ether_header *); - ifp->if_ipackets++; - -#if NBPFILTER > 0 - /* - * Handle BPF listeners. Let the BPF user see the packet. - */ - if (ifp->if_bpf) - bpf_mtap(ifp->if_bpf, m); -#endif - /* Remove header from mbuf and pass it on. */ - m_adj(m, sizeof(struct ether_header)); - ether_input(ifp, eh, m); - } - - return; -} - -/* - * A frame was downloaded to the chip. It's safe for us to clean up - * the list buffers. - */ -void rl_txeof(sc) - struct rl_softc *sc; -{ - struct ifnet *ifp; - u_int32_t txstat; - - ifp = &sc->arpcom.ac_if; - - /* Clear the timeout timer. */ - ifp->if_timer = 0; - - /* - * Go through our tx list and free mbufs for those - * frames that have been uploaded. - */ - do { - txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); - if (!(txstat & (RL_TXSTAT_TX_OK| - RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) - break; - - ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; - - if (RL_LAST_TXMBUF(sc) != NULL) { - m_freem(RL_LAST_TXMBUF(sc)); - RL_LAST_TXMBUF(sc) = NULL; - } - if (txstat & RL_TXSTAT_TX_OK) - ifp->if_opackets++; - else { - int oldthresh; - - ifp->if_oerrors++; - if ((txstat & RL_TXSTAT_TXABRT) || - (txstat & RL_TXSTAT_OUTOFWIN)) - CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); - oldthresh = sc->rl_txthresh; - /* error recovery */ - rl_reset(sc); - rl_init(sc); - /* - * If there was a transmit underrun, - * bump the TX threshold. - */ - if (txstat & RL_TXSTAT_TX_UNDERRUN) - sc->rl_txthresh = oldthresh + 32; - return; - } - RL_INC(sc->rl_cdata.last_tx); - ifp->if_flags &= ~IFF_OACTIVE; - } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); -} - -int rl_intr(arg) - void *arg; -{ - struct rl_softc *sc; - struct ifnet *ifp; - int claimed = 0; - u_int16_t status; - - sc = arg; - ifp = &sc->arpcom.ac_if; - - /* Disable interrupts. */ - CSR_WRITE_2(sc, RL_IMR, 0x0000); - - for (;;) { - - status = CSR_READ_2(sc, RL_ISR); - if (status) - CSR_WRITE_2(sc, RL_ISR, status); - - if ((status & RL_INTRS) == 0) - break; - - if (status & RL_ISR_RX_OK) - rl_rxeof(sc); - - if (status & RL_ISR_RX_ERR) - rl_rxeof(sc); - - if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) - rl_txeof(sc); - - if (status & RL_ISR_SYSTEM_ERR) { - rl_reset(sc); - rl_init(sc); - } - claimed = 1; - } - - /* Re-enable interrupts. */ - CSR_WRITE_2(sc, RL_IMR, RL_INTRS); - - if (ifp->if_snd.ifq_head != NULL) - rl_start(ifp); - - return (claimed); -} - -/* - * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data - * pointers to the fragment pointers. - */ -int rl_encap(sc, m_head) - struct rl_softc *sc; - struct mbuf *m_head; -{ - struct mbuf *m_new = NULL; - - /* - * The RealTek is brain damaged and wants longword-aligned - * TX buffers, plus we can only have one fragment buffer - * per packet. We have to copy pretty much all the time. - */ - - MGETHDR(m_new, M_DONTWAIT, MT_DATA); - if (m_new == NULL) - return(1); - if (m_head->m_pkthdr.len > MHLEN) { - MCLGET(m_new, M_DONTWAIT); - - if (!(m_new->m_flags & M_EXT)) { - m_freem(m_new); - return(1); - } - } - m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); - m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; - m_freem(m_head); - m_head = m_new; - - /* Pad frames to at least 60 bytes. */ - if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { - /* - * Make security concious people happy: zero out the - * bytes in the pad area, since we don't know what - * this mbuf cluster buffer's previous user might - * have left in it. - */ - bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, - RL_MIN_FRAMELEN - m_head->m_pkthdr.len); - m_head->m_pkthdr.len += - (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); - m_head->m_len = m_head->m_pkthdr.len; - } - - RL_CUR_TXMBUF(sc) = m_head; - - return(0); -} - -/* - * Main transmit routine. - */ - -void rl_start(ifp) - struct ifnet *ifp; -{ - struct rl_softc *sc; - struct mbuf *m_head = NULL; - - sc = ifp->if_softc; - - while(RL_CUR_TXMBUF(sc) == NULL) { - IF_DEQUEUE(&ifp->if_snd, m_head); - if (m_head == NULL) - break; - - /* Pack the data into the descriptor. */ - rl_encap(sc, m_head); - -#if NBPFILTER > 0 - /* - * If there's a BPF listener, bounce a copy of this frame - * to him. - */ - if (ifp->if_bpf) - bpf_mtap(ifp->if_bpf, RL_CUR_TXMBUF(sc)); -#endif - /* - * Transmit the frame. - */ - CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), - vtophys(mtod(RL_CUR_TXMBUF(sc), caddr_t))); - CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), - RL_TXTHRESH(sc->rl_txthresh) | - RL_CUR_TXMBUF(sc)->m_pkthdr.len); - - RL_INC(sc->rl_cdata.cur_tx); - } - - /* - * We broke out of the loop because all our TX slots are - * full. Mark the NIC as busy until it drains some of the - * packets from the queue. - */ - if (RL_CUR_TXMBUF(sc) != NULL) - ifp->if_flags |= IFF_OACTIVE; - - /* - * Set a timeout in case the chip goes out to lunch. - */ - ifp->if_timer = 5; - - return; -} - -void rl_init(xsc) - void *xsc; -{ - struct rl_softc *sc = xsc; - struct ifnet *ifp = &sc->arpcom.ac_if; - int s, i; - u_int32_t rxcfg = 0; - - s = splimp(); - - /* - * Cancel pending I/O and free all RX/TX buffers. - */ - rl_stop(sc); - - /* Init our MAC address */ - for (i = 0; i < ETHER_ADDR_LEN; i++) { - CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); - } - - /* Init the RX buffer pointer register. */ - CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf)); - - /* Init TX descriptors. */ - rl_list_tx_init(sc); - - /* - * Enable transmit and receive. - */ - CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); - - /* - * Set the inital TX and RX configuration. - */ - CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); - CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); - - /* Set the individual bit to receive frames for this host only. */ - rxcfg = CSR_READ_4(sc, RL_RXCFG); - rxcfg |= RL_RXCFG_RX_INDIV; - - /* If we want promiscuous mode, set the allframes bit. */ - if (ifp->if_flags & IFF_PROMISC) { - rxcfg |= RL_RXCFG_RX_ALLPHYS; - CSR_WRITE_4(sc, RL_RXCFG, rxcfg); - } else { - rxcfg &= ~RL_RXCFG_RX_ALLPHYS; - CSR_WRITE_4(sc, RL_RXCFG, rxcfg); - } - - /* - * Set capture broadcast bit to capture broadcast frames. - */ - if (ifp->if_flags & IFF_BROADCAST) { - rxcfg |= RL_RXCFG_RX_BROAD; - CSR_WRITE_4(sc, RL_RXCFG, rxcfg); - } else { - rxcfg &= ~RL_RXCFG_RX_BROAD; - CSR_WRITE_4(sc, RL_RXCFG, rxcfg); - } - - /* - * Program the multicast filter, if necessary. - */ - rl_setmulti(sc); - - /* - * Enable interrupts. - */ - CSR_WRITE_2(sc, RL_IMR, RL_INTRS); - - /* Set initial TX threshold */ - sc->rl_txthresh = RL_TX_THRESH_INIT; - - /* Start RX/TX process. */ - CSR_WRITE_4(sc, RL_MISSEDPKT, 0); - - /* Enable receiver and transmitter. */ - CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); - - mii_mediachg(&sc->sc_mii); - - CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); - - ifp->if_flags |= IFF_RUNNING; - ifp->if_flags &= ~IFF_OACTIVE; - - (void)splx(s); - - timeout_set(&sc->sc_tick_tmo, rl_tick, sc); - timeout_add(&sc->sc_tick_tmo, hz); - - return; -} - -/* - * Set media options. - */ -int rl_ifmedia_upd(ifp) - struct ifnet *ifp; -{ - struct rl_softc *sc = (struct rl_softc *)ifp->if_softc; - - mii_mediachg(&sc->sc_mii); - return (0); -} - -/* - * Report current media status. - */ -void rl_ifmedia_sts(ifp, ifmr) - struct ifnet *ifp; - struct ifmediareq *ifmr; -{ - struct rl_softc *sc = ifp->if_softc; - - mii_pollstat(&sc->sc_mii); - ifmr->ifm_status = sc->sc_mii.mii_media_status; - ifmr->ifm_active = sc->sc_mii.mii_media_active; -} - -int rl_ioctl(ifp, command, data) - struct ifnet *ifp; - u_long command; - caddr_t data; -{ - struct rl_softc *sc = ifp->if_softc; - struct ifreq *ifr = (struct ifreq *) data; - struct ifaddr *ifa = (struct ifaddr *)data; - int s, error = 0; - - s = splimp(); - - if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) { - splx(s); - return error; - } - - switch(command) { - case SIOCSIFADDR: - ifp->if_flags |= IFF_UP; - switch (ifa->ifa_addr->sa_family) { -#ifdef INET - case AF_INET: - rl_init(sc); - arp_ifinit(&sc->arpcom, ifa); - break; -#endif /* INET */ - default: - rl_init(sc); - break; - } - break; - case SIOCSIFFLAGS: - if (ifp->if_flags & IFF_UP) { - rl_init(sc); - } else { - if (ifp->if_flags & IFF_RUNNING) - rl_stop(sc); - } - error = 0; - break; - case SIOCADDMULTI: - case SIOCDELMULTI: - error = (command == SIOCADDMULTI) ? - ether_addmulti(ifr, &sc->arpcom) : - ether_delmulti(ifr, &sc->arpcom); - - if (error == ENETRESET) { - /* - * Multicast list has changed; set the hardware - * filter accordingly. - */ - rl_setmulti(sc); - error = 0; - } - break; - case SIOCGIFMEDIA: - case SIOCSIFMEDIA: - error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); - break; - default: - error = EINVAL; - break; - } - - (void)splx(s); - - return(error); -} - -void rl_watchdog(ifp) - struct ifnet *ifp; -{ - struct rl_softc *sc; - - sc = ifp->if_softc; - - printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); - ifp->if_oerrors++; - rl_txeof(sc); - rl_rxeof(sc); - rl_init(sc); - - return; -} - -/* - * Stop the adapter and free any mbufs allocated to the - * RX and TX lists. - */ -void rl_stop(sc) - struct rl_softc *sc; -{ - register int i; - struct ifnet *ifp; - - ifp = &sc->arpcom.ac_if; - ifp->if_timer = 0; - - timeout_del(&sc->sc_tick_tmo); - - CSR_WRITE_1(sc, RL_COMMAND, 0x00); - CSR_WRITE_2(sc, RL_IMR, 0x0000); - - /* - * Free the TX list buffers. - */ - for (i = 0; i < RL_TX_LIST_CNT; i++) { - if (sc->rl_cdata.rl_tx_chain[i] != NULL) { - m_freem(sc->rl_cdata.rl_tx_chain[i]); - sc->rl_cdata.rl_tx_chain[i] = NULL; - CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x00000000); - } - } - - ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); - - return; -} - -int -rl_probe(parent, match, aux) - struct device *parent; - void *match; - void *aux; -{ - struct pci_attach_args *pa = (struct pci_attach_args *)aux; - struct rl_type *t; - - for (t = rl_devs; t->rl_vid != 0; t++) { - if ((PCI_VENDOR(pa->pa_id) == t->rl_vid) && - (PCI_PRODUCT(pa->pa_id) == t->rl_did)) - return (1); - } - return (0); -} - -void -rl_attach(parent, self, aux) - struct device *parent, *self; - void *aux; -{ - struct rl_softc *sc = (struct rl_softc *)self; - struct pci_attach_args *pa = aux; - pci_chipset_tag_t pc = pa->pa_pc; - pci_intr_handle_t ih; - const char *intrstr = NULL; - struct ifnet *ifp = &sc->arpcom.ac_if; - bus_addr_t iobase; - bus_size_t iosize; - bus_dma_segment_t seg; - bus_dmamap_t dmamap; - int rseg; - u_int32_t command; - u_int16_t rl_did; - caddr_t kva; - - command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); - -#ifdef RL_USEIOSPACE - if (!(command & PCI_COMMAND_IO_ENABLE)) { - printf(": failed to enable i/o ports\n"); - return; - } - - /* - * Map control/status registers. - */ - if (pci_io_find(pc, pa->pa_tag, RL_PCI_LOIO, &iobase, &iosize)) { - printf(": can't find i/o space\n"); - return; - } - if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &sc->rl_bhandle)) { - printf(": can't map i/o space\n"); - return; - } - sc->rl_btag = pa->pa_iot; -#else - if (!(command & PCI_COMMAND_MEM_ENABLE)) { - printf(": failed to enable memory mapping\n"); - return; - } - if (pci_mem_find(pc, pa->pa_tag, RL_PCI_LOMEM, &iobase, &iosize, NULL)){ - printf(": can't find mem space\n"); - return; - } - if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->rl_bhandle)) { - printf(": can't map mem space\n"); - return; - } - sc->rl_btag = pa->pa_memt; -#endif - - /* - * Allocate our interrupt. - */ - if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, - pa->pa_intrline, &ih)) { - printf(": couldn't map interrupt\n"); - return; - } - - intrstr = pci_intr_string(pc, ih); - sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, rl_intr, sc, - self->dv_xname); - if (sc->sc_ih == NULL) { - printf(": couldn't establish interrupt"); - if (intrstr != NULL) - printf(" at %s", intrstr); - printf("\n"); - return; - } - printf(": %s", intrstr); - - rl_reset(sc); - - rl_read_eeprom(sc, (caddr_t)sc->arpcom.ac_enaddr, RL_EE_EADDR, 3, 0); - printf(" address %s\n", ether_sprintf(sc->arpcom.ac_enaddr)); - - rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); - - if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || - rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139) - sc->rl_type = RL_8139; - else if (rl_did == RT_DEVICEID_8129) - sc->rl_type = RL_8129; - else { - printf("\n%s: unknown device id: %x\n", sc->sc_dev.dv_xname, - rl_did); - return; - } - - sc->sc_dmat = pa->pa_dmat; - if (bus_dmamem_alloc(sc->sc_dmat, RL_RXBUFLEN + 32, PAGE_SIZE, 0, - &seg, 1, &rseg, BUS_DMA_NOWAIT)) { - printf("\n%s: can't alloc rx buffers\n", sc->sc_dev.dv_xname); - return; - } - if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, RL_RXBUFLEN + 32, &kva, - BUS_DMA_NOWAIT)) { - printf("%s: can't map dma buffers (%d bytes)\n", - sc->sc_dev.dv_xname, RL_RXBUFLEN + 32); - bus_dmamem_free(sc->sc_dmat, &seg, rseg); - return; - } - if (bus_dmamap_create(sc->sc_dmat, RL_RXBUFLEN + 32, 1, - RL_RXBUFLEN + 32, 0, BUS_DMA_NOWAIT, &dmamap)) { - printf("%s: can't create dma map\n", sc->sc_dev.dv_xname); - bus_dmamem_unmap(sc->sc_dmat, kva, RL_RXBUFLEN + 32); - bus_dmamem_free(sc->sc_dmat, &seg, rseg); - return; - } - if (bus_dmamap_load(sc->sc_dmat, dmamap, kva, RL_RXBUFLEN + 32, - NULL, BUS_DMA_NOWAIT)) { - printf("%s: can't load dma map\n", sc->sc_dev.dv_xname); - bus_dmamap_destroy(sc->sc_dmat, dmamap); - bus_dmamem_unmap(sc->sc_dmat, kva, RL_RXBUFLEN + 32); - bus_dmamem_free(sc->sc_dmat, &seg, rseg); - return; - } - sc->rl_cdata.rl_rx_buf = kva; - bzero(sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 32); - - /* Leave a few bytes before the start of the RX ring buffer. */ - sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; - sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); - - ifp->if_softc = sc; - ifp->if_mtu = ETHERMTU; - ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; - ifp->if_ioctl = rl_ioctl; - ifp->if_output = ether_output; - ifp->if_start = rl_start; - ifp->if_watchdog = rl_watchdog; - ifp->if_baudrate = 10000000; - ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; - - bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); - - /* - * Initialize our media structures and probe the MII. - */ - sc->sc_mii.mii_ifp = ifp; - sc->sc_mii.mii_readreg = rl_miibus_readreg; - sc->sc_mii.mii_writereg = rl_miibus_writereg; - sc->sc_mii.mii_statchg = rl_miibus_statchg; - ifmedia_init(&sc->sc_mii.mii_media, 0, rl_ifmedia_upd, rl_ifmedia_sts); - mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, - 0); - if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { - ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); - ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); - } else - ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); - - /* - * Attach us everywhere - */ - if_attach(ifp); - ether_ifattach(ifp); - - shutdownhook_establish(rl_shutdown, sc); -} - -void rl_shutdown(arg) - void *arg; -{ - struct rl_softc *sc = (struct rl_softc *)arg; - - rl_stop(sc); -} - -int -rl_miibus_readreg(self, phy, reg) - struct device *self; - int phy, reg; -{ - struct rl_softc *sc = (struct rl_softc *)self; - struct rl_mii_frame frame; - u_int16_t rl8139_reg; - - if (sc->rl_type == RL_8139) { - /* - * The RTL8139 PHY is mapped into PCI registers, unforunately - * it has no phyid, or phyaddr, so assume it is phyaddr 0. - */ - if (phy != 0) - return(0); - - switch (reg) { - case MII_BMCR: - rl8139_reg = RL_BMCR; - break; - case MII_BMSR: - rl8139_reg = RL_BMSR; - break; - case MII_ANAR: - rl8139_reg = RL_ANAR; - break; - case MII_ANER: - rl8139_reg = RL_ANER; - break; - case MII_ANLPAR: - rl8139_reg = RL_LPAR; - break; - case MII_PHYIDR1: - case MII_PHYIDR2: - return (0); - break; - } - return (CSR_READ_2(sc, rl8139_reg)); - } - - bzero((char *)&frame, sizeof(frame)); - - frame.mii_phyaddr = phy; - frame.mii_regaddr = reg; - rl_mii_readreg(sc, &frame); - - return(frame.mii_data); -} - -void -rl_miibus_writereg(self, phy, reg, val) - struct device *self; - int phy, reg, val; -{ - struct rl_softc *sc = (struct rl_softc *)self; - struct rl_mii_frame frame; - u_int16_t rl8139_reg = 0; - - if (sc->rl_type == RL_8139) { - if (phy) - return; - - switch (reg) { - case MII_BMCR: - rl8139_reg = RL_BMCR; - break; - case MII_BMSR: - rl8139_reg = RL_BMSR; - break; - case MII_ANAR: - rl8139_reg = RL_ANAR; - break; - case MII_ANER: - rl8139_reg = RL_ANER; - break; - case MII_ANLPAR: - rl8139_reg = RL_LPAR; - break; - case MII_PHYIDR1: - case MII_PHYIDR2: - return; - } - CSR_WRITE_2(sc, rl8139_reg, val); - return; - } - - bzero((char *)&frame, sizeof(frame)); - frame.mii_phyaddr = phy; - frame.mii_regaddr = reg; - frame.mii_data = val; - rl_mii_writereg(sc, &frame); -} - -void -rl_miibus_statchg(self) - struct device *self; -{ - return; -} - -void -rl_tick(v) - void *v; -{ - struct rl_softc *sc = v; - - mii_tick(&sc->sc_mii); - timeout_add(&sc->sc_tick_tmo, hz); -} - -struct cfattach rl_ca = { - sizeof(struct rl_softc), rl_probe, rl_attach, -}; - -struct cfdriver rl_cd = { - 0, "rl", DV_IFNET -}; diff --git a/sys/dev/pci/if_rlreg.h b/sys/dev/pci/if_rlreg.h deleted file mode 100644 index 5e7025f99ec..00000000000 --- a/sys/dev/pci/if_rlreg.h +++ /dev/null @@ -1,480 +0,0 @@ -/* $OpenBSD: if_rlreg.h,v 1.12 2001/02/20 19:10:14 jason Exp $ */ - -/* - * Copyright (c) 1997, 1998 - * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Bill Paul. - * 4. Neither the name of the author nor the names of any co-contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.14 1999/10/21 19:42:03 wpaul Exp $ - */ - -/* - * RealTek 8129/8139 register offsets - */ -#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ -#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ -#define RL_IDR2 0x0002 -#define RL_IDR3 0x0003 -#define RL_IDR4 0x0004 -#define RL_IDR5 0x0005 - /* 0006-0007 reserved */ -#define RL_MAR0 0x0008 /* Multicast hash table */ -#define RL_MAR1 0x0009 -#define RL_MAR2 0x000A -#define RL_MAR3 0x000B -#define RL_MAR4 0x000C -#define RL_MAR5 0x000D -#define RL_MAR6 0x000E -#define RL_MAR7 0x000F - -#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ -#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ -#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ -#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ - -#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ -#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ -#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ -#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ - -#define RL_RXADDR 0x0030 /* RX ring start address */ -#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ -#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ -#define RL_COMMAND 0x0037 /* command register */ -#define RL_CURRXADDR 0x0038 /* current address of packet read */ -#define RL_CURRXBUF 0x003A /* current RX buffer address */ -#define RL_IMR 0x003C /* interrupt mask register */ -#define RL_ISR 0x003E /* interrupt status register */ -#define RL_TXCFG 0x0040 /* transmit config */ -#define RL_RXCFG 0x0044 /* receive config */ -#define RL_TIMERCNT 0x0048 /* timer count register */ -#define RL_MISSEDPKT 0x004C /* missed packet counter */ -#define RL_EECMD 0x0050 /* EEPROM command register */ -#define RL_CFG0 0x0051 /* config register #0 */ -#define RL_CFG1 0x0052 /* config register #1 */ - /* 0053-0057 reserved */ -#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ - /* 0059-005A reserved */ -#define RL_MII 0x005A /* 8129 chip only */ -#define RL_HALTCLK 0x005B -#define RL_MULTIINTR 0x005C /* multiple interrupt */ -#define RL_PCIREV 0x005E /* PCI revision value */ - /* 005F reserved */ -#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ - -/* Direct PHY access registers only available on 8139 */ -#define RL_BMCR 0x0062 /* PHY basic mode control */ -#define RL_BMSR 0x0064 /* PHY basic mode status */ -#define RL_ANAR 0x0066 /* PHY autoneg advert */ -#define RL_LPAR 0x0068 /* PHY link partner ability */ -#define RL_ANER 0x006A /* PHY autoneg expansion */ - -#define RL_DISCCNT 0x006C /* disconnect counter */ -#define RL_FALSECAR 0x006E /* false carrier counter */ -#define RL_NWAYTST 0x0070 /* NWAY test register */ -#define RL_RX_ER 0x0072 /* RX_ER counter */ -#define RL_CSCFG 0x0074 /* CS configuration register */ - - -/* - * TX config register bits - */ -#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ -#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ -#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ -#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ -#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ - -#define RL_TXDMA_16BYTES 0x00000000 -#define RL_TXDMA_32BYTES 0x00000100 -#define RL_TXDMA_64BYTES 0x00000200 -#define RL_TXDMA_128BYTES 0x00000300 -#define RL_TXDMA_256BYTES 0x00000400 -#define RL_TXDMA_512BYTES 0x00000500 -#define RL_TXDMA_1024BYTES 0x00000600 -#define RL_TXDMA_2048BYTES 0x00000700 - -/* - * Transmit descriptor status register bits. - */ -#define RL_TXSTAT_LENMASK 0x00001FFF -#define RL_TXSTAT_OWN 0x00002000 -#define RL_TXSTAT_TX_UNDERRUN 0x00004000 -#define RL_TXSTAT_TX_OK 0x00008000 -#define RL_TXSTAT_EARLY_THRESH 0x003F0000 -#define RL_TXSTAT_COLLCNT 0x0F000000 -#define RL_TXSTAT_CARR_HBEAT 0x10000000 -#define RL_TXSTAT_OUTOFWIN 0x20000000 -#define RL_TXSTAT_TXABRT 0x40000000 -#define RL_TXSTAT_CARRLOSS 0x80000000 - -/* - * Interrupt status register bits. - */ -#define RL_ISR_RX_OK 0x0001 -#define RL_ISR_RX_ERR 0x0002 -#define RL_ISR_TX_OK 0x0004 -#define RL_ISR_TX_ERR 0x0008 -#define RL_ISR_RX_OVERRUN 0x0010 -#define RL_ISR_PKT_UNDERRUN 0x0020 -#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ -#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ -#define RL_ISR_SYSTEM_ERR 0x8000 - -#define RL_INTRS \ - (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ - RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ - RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) - -/* - * Media status register. (8139 only) - */ -#define RL_MEDIASTAT_RXPAUSE 0x01 -#define RL_MEDIASTAT_TXPAUSE 0x02 -#define RL_MEDIASTAT_LINK 0x04 -#define RL_MEDIASTAT_SPEED10 0x08 -#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ -#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ - -/* - * Receive config register. - */ -#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ -#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ -#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ -#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ -#define RL_RXCFG_RX_RUNT 0x00000010 -#define RL_RXCFG_RX_ERRPKT 0x00000020 -#define RL_RXCFG_WRAP 0x00000080 -#define RL_RXCFG_MAXDMA 0x00000700 -#define RL_RXCFG_BURSZ 0x00001800 -#define RL_RXCFG_FIFOTHRESH 0x0000E000 -#define RL_RXCFG_EARLYTHRESH 0x07000000 - -#define RL_RXDMA_16BYTES 0x00000000 -#define RL_RXDMA_32BYTES 0x00000100 -#define RL_RXDMA_64BYTES 0x00000200 -#define RL_RXDMA_128BYTES 0x00000300 -#define RL_RXDMA_256BYTES 0x00000400 -#define RL_RXDMA_512BYTES 0x00000500 -#define RL_RXDMA_1024BYTES 0x00000600 -#define RL_RXDMA_UNLIMITED 0x00000700 - -#define RL_RXBUF_8 0x00000000 -#define RL_RXBUF_16 0x00000800 -#define RL_RXBUF_32 0x00001000 -#define RL_RXBUF_64 0x00001800 - -#define RL_RXFIFO_16BYTES 0x00000000 -#define RL_RXFIFO_32BYTES 0x00002000 -#define RL_RXFIFO_64BYTES 0x00004000 -#define RL_RXFIFO_128BYTES 0x00006000 -#define RL_RXFIFO_256BYTES 0x00008000 -#define RL_RXFIFO_512BYTES 0x0000A000 -#define RL_RXFIFO_1024BYTES 0x0000C000 -#define RL_RXFIFO_NOTHRESH 0x0000E000 - -/* - * Bits in RX status header (included with RX'ed packet - * in ring buffer). - */ -#define RL_RXSTAT_RXOK 0x00000001 -#define RL_RXSTAT_ALIGNERR 0x00000002 -#define RL_RXSTAT_CRCERR 0x00000004 -#define RL_RXSTAT_GIANT 0x00000008 -#define RL_RXSTAT_RUNT 0x00000010 -#define RL_RXSTAT_BADSYM 0x00000020 -#define RL_RXSTAT_BROAD 0x00002000 -#define RL_RXSTAT_INDIV 0x00004000 -#define RL_RXSTAT_MULTI 0x00008000 -#define RL_RXSTAT_LENMASK 0xFFFF0000 - -#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ -/* - * Command register. - */ -#define RL_CMD_EMPTY_RXBUF 0x0001 -#define RL_CMD_TX_ENB 0x0004 -#define RL_CMD_RX_ENB 0x0008 -#define RL_CMD_RESET 0x0010 - -/* - * EEPROM control register - */ -#define RL_EE_DATAOUT 0x01 /* Data out */ -#define RL_EE_DATAIN 0x02 /* Data in */ -#define RL_EE_CLK 0x04 /* clock */ -#define RL_EE_SEL 0x08 /* chip select */ -#define RL_EE_MODE (0x40|0x80) - -#define RL_EEMODE_OFF 0x00 -#define RL_EEMODE_AUTOLOAD 0x40 -#define RL_EEMODE_PROGRAM 0x80 -#define RL_EEMODE_WRITECFG (0x80|0x40) - -/* 9346 EEPROM commands */ -#define RL_EECMD_WRITE 0x140 -#define RL_EECMD_READ 0x180 -#define RL_EECMD_ERASE 0x1c0 - -#define RL_EE_ID 0x00 -#define RL_EE_PCI_VID 0x01 -#define RL_EE_PCI_DID 0x02 -/* Location of station address inside EEPROM */ -#define RL_EE_EADDR 0x07 - -/* - * MII register (8129 only) - */ -#define RL_MII_CLK 0x01 -#define RL_MII_DATAIN 0x02 -#define RL_MII_DATAOUT 0x04 -#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ - -/* - * Config 0 register - */ -#define RL_CFG0_ROM0 0x01 -#define RL_CFG0_ROM1 0x02 -#define RL_CFG0_ROM2 0x04 -#define RL_CFG0_PL0 0x08 -#define RL_CFG0_PL1 0x10 -#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ -#define RL_CFG0_PCS 0x40 -#define RL_CFG0_SCR 0x80 - -/* - * Config 1 register - */ -#define RL_CFG1_PWRDWN 0x01 -#define RL_CFG1_SLEEP 0x02 -#define RL_CFG1_IOMAP 0x04 -#define RL_CFG1_MEMMAP 0x08 -#define RL_CFG1_RSVD 0x10 -#define RL_CFG1_DRVLOAD 0x20 -#define RL_CFG1_LED0 0x40 -#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ -#define RL_CFG1_LED1 0x80 - -/* - * The RealTek doesn't use a fragment-based descriptor mechanism. - * Instead, there are only four register sets, each or which represents - * one 'descriptor.' Basically, each TX descriptor is just a contiguous - * packet buffer (32-bit aligned!) and we place the buffer addresses in - * the registers so the chip knows where they are. - * - * We can sort of kludge together the same kind of buffer management - * used in previous drivers, but we have to do buffer copies almost all - * the time, so it doesn't really buy us much. - * - * For reception, there's just one large buffer where the chip stores - * all received packets. - */ - -#define RL_RX_BUF_SZ RL_RXBUF_64 -#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) -#define RL_TX_LIST_CNT 4 -#define RL_MIN_FRAMELEN 60 -#define RL_TXTHRESH(x) ((x) << 11) -#define RL_TX_THRESH_INIT 96 -#define RL_RX_FIFOTHRESH RL_RXFIFO_256BYTES -#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED -#define RL_TX_MAXDMA RL_TXDMA_2048BYTES - -#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) -#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) - -#define RL_ETHER_ALIGN 2 - -struct rl_chain_data { - u_int16_t cur_rx; - caddr_t rl_rx_buf; - caddr_t rl_rx_buf_ptr; - - struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; - u_int8_t last_tx; - u_int8_t cur_tx; -}; - -#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) -#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) -#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) -#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) -#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) -#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) -#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) - -struct rl_type { - u_int16_t rl_vid; - u_int16_t rl_did; -}; - -struct rl_mii_frame { - u_int8_t mii_stdelim; - u_int8_t mii_opcode; - u_int8_t mii_phyaddr; - u_int8_t mii_regaddr; - u_int8_t mii_turnaround; - u_int16_t mii_data; -}; - -/* - * MII constants - */ -#define RL_MII_STARTDELIM 0x01 -#define RL_MII_READOP 0x02 -#define RL_MII_WRITEOP 0x01 -#define RL_MII_TURNAROUND 0x02 - -#define RL_8129 1 -#define RL_8139 2 - -struct rl_softc { - struct device sc_dev; /* us, as a device */ - void * sc_ih; /* interrupt vectoring */ - bus_space_handle_t rl_bhandle; /* bus space handle */ - bus_space_tag_t rl_btag; /* bus space tag */ - bus_dma_tag_t sc_dmat; - struct arpcom arpcom; /* interface info */ - struct mii_data sc_mii; /* MII information */ - u_int8_t rl_type; - int rl_txthresh; - struct rl_chain_data rl_cdata; - struct timeout sc_tick_tmo; -}; - -/* - * register space access macros - */ -#define CSR_WRITE_4(sc, csr, val) \ - bus_space_write_4(sc->rl_btag, sc->rl_bhandle, csr, val) -#define CSR_WRITE_2(sc, csr, val) \ - bus_space_write_2(sc->rl_btag, sc->rl_bhandle, csr, val) -#define CSR_WRITE_1(sc, csr, val) \ - bus_space_write_1(sc->rl_btag, sc->rl_bhandle, csr, val) - -#define CSR_READ_4(sc, csr) \ - bus_space_read_4(sc->rl_btag, sc->rl_bhandle, csr) -#define CSR_READ_2(sc, csr) \ - bus_space_read_2(sc->rl_btag, sc->rl_bhandle, csr) -#define CSR_READ_1(sc, csr) \ - bus_space_read_1(sc->rl_btag, sc->rl_bhandle, csr) - -#define RL_TIMEOUT 1000 - -/* - * General constants that are fun to know. - * - * RealTek PCI vendor ID - */ -#define RT_VENDORID 0x10EC - -/* - * RealTek chip device IDs. - */ -#define RT_DEVICEID_8129 0x8129 -#define RT_DEVICEID_8139 0x8139 - -/* - * Accton PCI vendor ID - */ -#define ACCTON_VENDORID 0x1113 - -/* - * Accton MPX 5030/5038 device ID. - */ -#define ACCTON_DEVICEID_5030 0x1211 - -/* - * Delta Electronics Vendor ID. - */ -#define DELTA_VENDORID 0x1500 - -/* - * Delta device IDs. - */ -#define DELTA_DEVICEID_8139 0x1360 - -/* - * Addtron vendor ID. - */ -#define ADDTRON_VENDORID 0x4033 - -/* - * Addtron device IDs. - */ -#define ADDTRON_DEVICEID_8139 0x1360 - -/* - * PCI low memory base and low I/O base register, and - * other PCI registers. Note: some are only available on - * the 3c905B, in particular those that related to power management. - */ - -#define RL_PCI_VENDOR_ID 0x00 -#define RL_PCI_DEVICE_ID 0x02 -#define RL_PCI_COMMAND 0x04 -#define RL_PCI_STATUS 0x06 -#define RL_PCI_CLASSCODE 0x09 -#define RL_PCI_LATENCY_TIMER 0x0D -#define RL_PCI_HEADER_TYPE 0x0E -#define RL_PCI_LOIO 0x10 -#define RL_PCI_LOMEM 0x14 -#define RL_PCI_BIOSROM 0x30 -#define RL_PCI_INTLINE 0x3C -#define RL_PCI_INTPIN 0x3D -#define RL_PCI_MINGNT 0x3E -#define RL_PCI_MINLAT 0x0F -#define RL_PCI_RESETOPT 0x48 -#define RL_PCI_EEPROM_DATA 0x4C - -#define RL_PCI_CAPID 0x50 /* 8 bits */ -#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ -#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ -#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ - -#define RL_PSTATE_MASK 0x0003 -#define RL_PSTATE_D0 0x0000 -#define RL_PSTATE_D1 0x0002 -#define RL_PSTATE_D2 0x0002 -#define RL_PSTATE_D3 0x0003 -#define RL_PME_EN 0x0010 -#define RL_PME_STATUS 0x8000 - -/* - * FreeBSDism - */ -#ifndef ETHER_CRC_LEN -#define ETHER_CRC_LEN 4 -#endif - -#ifdef __alpha__ -#undef vtophys -#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) -#endif |