diff options
Diffstat (limited to 'sys/dev')
| -rw-r--r-- | sys/dev/pci/files.pci | 7 | ||||
| -rw-r--r-- | sys/dev/pci/if_mx.c | 2332 | ||||
| -rw-r--r-- | sys/dev/pci/if_mxreg.h | 705 |
3 files changed, 3043 insertions, 1 deletions
diff --git a/sys/dev/pci/files.pci b/sys/dev/pci/files.pci index 7261850466a..6a7a1545dc8 100644 --- a/sys/dev/pci/files.pci +++ b/sys/dev/pci/files.pci @@ -1,4 +1,4 @@ -# $OpenBSD: files.pci,v 1.32 1998/12/26 18:31:22 niklas Exp $ +# $OpenBSD: files.pci,v 1.33 1999/01/08 04:43:18 jason Exp $ # $NetBSD: files.pci,v 1.20 1996/09/24 17:47:15 christos Exp $ # # Config file and device description for machine-independent PCI code. @@ -103,6 +103,11 @@ device rl: ether, ifnet, mii, ifmedia attach rl at pci file dev/pci/if_rl.c rl +# Macronix +device mx: ether, ifnet, ifmedia +attach mx at pci +file dev/pci/if_mx.c mx + # Texas Instruments ThunderLAN device tl: ether, ifnet, mii, ifmedia attach tl at pci diff --git a/sys/dev/pci/if_mx.c b/sys/dev/pci/if_mx.c new file mode 100644 index 00000000000..ed5a3721da4 --- /dev/null +++ b/sys/dev/pci/if_mx.c @@ -0,0 +1,2332 @@ +/* + * Copyright (c) 1997, 1998 + * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD: if_mx.c,v 1.8 1999/01/06 17:30:06 wpaul Exp $ + */ + +/* + * Macronix PMAC fast ethernet PCI NIC driver + * + * Written by Bill Paul <wpaul@ctr.columbia.edu> + * Electrical Engineering Department + * Columbia University, New York City + */ + +/* + * The Macronix 98713, 98715 and 98725 chips are still more tulip clones. + * The 98713 has an internal transceiver and an MII bus for external PHYs. + * The other two chips have only the internal transceiver. All have + * support for built-in autonegotiation. Additionally, there are 98713A + * and 98715A chips which support power management. The 98725 chip + * supports power management as well. + * + * Datasheets for the Macronix parts can be obtained from www.macronix.com. + * Note however that the datasheets do not describe the TX and RX + * descriptor structures or the setup frame format(s). For this, you should + * obtain a DEC 21x4x datasheet from developer.intel.com. The Macronix + * chips look to be fairly straightforward tulip clones, except for + * the NWAY support. + */ + +#include "bpfilter.h" + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/sockio.h> +#include <sys/mbuf.h> +#include <sys/malloc.h> +#include <sys/kernel.h> +#include <sys/socket.h> + +#include <net/if.h> + +#include <sys/device.h> +#ifdef INET +#include <netinet/in.h> +#include <netinet/in_systm.h> +#include <netinet/in_var.h> +#include <netinet/ip.h> +#include <netinet/if_ether.h> +#endif /* INET */ + +#include <net/if_dl.h> +#include <net/if_media.h> + +#if NBPFILTER > 0 +#include <net/bpf.h> +#endif + +#include <vm/vm.h> /* for vtophys */ +#include <vm/pmap.h> /* for vtophys */ + +#include <dev/pci/pcireg.h> +#include <dev/pci/pcivar.h> +#include <dev/pci/pcidevs.h> +#define bootverbose 0 + +#define MX_USEIOSPACE + +/* #define MX_BACKGROUND_AUTONEG */ + +#include <dev/pci/if_mxreg.h> + +/* + * Various supported PHY vendors/types and their names. Note that + * this driver will work with pretty much any MII-compliant PHY, + * so failure to positively identify the chip is not a fatal error. + */ + +static struct mx_type mx_phys[] = { + { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" }, + { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" }, + { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"}, + { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" }, + { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" }, + { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" }, + { 0, 0, "<MII-compliant physical interface>" } +}; + +static int mx_probe __P((struct device *, void *, void *)); +static void mx_attach __P((struct device *, struct device *self, void *aux)); + +static int mx_newbuf __P((struct mx_softc *, + struct mx_chain_onefrag *)); +static int mx_encap __P((struct mx_softc *, struct mx_chain *, + struct mbuf *)); + +static void mx_rxeof __P((struct mx_softc *)); +static void mx_rxeoc __P((struct mx_softc *)); +static void mx_txeof __P((struct mx_softc *)); +static void mx_txeoc __P((struct mx_softc *)); +static int mx_intr __P((void *)); +static void mx_start __P((struct ifnet *)); +static int mx_ioctl __P((struct ifnet *, u_long, caddr_t)); +static void mx_init __P((void *)); +static void mx_stop __P((struct mx_softc *)); +static void mx_watchdog __P((struct ifnet *)); +static void mx_shutdown __P((void *)); +static int mx_ifmedia_upd __P((struct ifnet *)); +static void mx_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); + +static void mx_delay __P((struct mx_softc *)); +static void mx_eeprom_idle __P((struct mx_softc *)); +static void mx_eeprom_putbyte __P((struct mx_softc *, u_int8_t)); +static void mx_eeprom_getword __P((struct mx_softc *, u_int8_t, u_int16_t *)); +static void mx_read_eeprom __P((struct mx_softc *, caddr_t, int, + int, int)); + +static void mx_mii_writebit __P((struct mx_softc *, int)); +static int mx_mii_readbit __P((struct mx_softc *)); +static void mx_mii_sync __P((struct mx_softc *)); +static void mx_mii_send __P((struct mx_softc *, u_int32_t, int)); +static int mx_mii_readreg __P((struct mx_softc *, struct mx_mii_frame *)); +static int mx_mii_writereg __P((struct mx_softc *, struct mx_mii_frame *)); +static u_int16_t mx_phy_readreg __P((struct mx_softc *, int)); +static void mx_phy_writereg __P((struct mx_softc *, u_int16_t, u_int16_t)); + +static void mx_autoneg_xmit __P((struct mx_softc *)); +static void mx_autoneg_mii __P((struct mx_softc *, int, int)); +static void mx_autoneg __P((struct mx_softc *, int, int)); +static void mx_setmode_mii __P((struct mx_softc *, int)); +static void mx_setmode __P((struct mx_softc *, int, int)); +static void mx_getmode_mii __P((struct mx_softc *)); +static void mx_setcfg __P((struct mx_softc *, u_int16_t)); +static u_int32_t mx_calchash __P((u_int8_t *)); +static void mx_setfilt __P((struct mx_softc *)); +static void mx_reset __P((struct mx_softc *)); +static int mx_list_rx_init __P((struct mx_softc *)); +static int mx_list_tx_init __P((struct mx_softc *)); + +#define MX_SETBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, \ + CSR_READ_4(sc, reg) | x) + +#define MX_CLRBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, \ + CSR_READ_4(sc, reg) & ~x) + +#define SIO_SET(x) \ + CSR_WRITE_4(sc, MX_SIO, \ + CSR_READ_4(sc, MX_SIO) | x) + +#define SIO_CLR(x) \ + CSR_WRITE_4(sc, MX_SIO, \ + CSR_READ_4(sc, MX_SIO) & ~x) + +static void mx_delay(sc) + struct mx_softc *sc; +{ + int idx; + + for (idx = (300 / 33) + 1; idx > 0; idx--) + CSR_READ_4(sc, MX_BUSCTL); +} + +static void mx_eeprom_idle(sc) + struct mx_softc *sc; +{ + register int i; + + CSR_WRITE_4(sc, MX_SIO, MX_SIO_EESEL); + mx_delay(sc); + MX_SETBIT(sc, MX_SIO, MX_SIO_ROMCTL_READ); + mx_delay(sc); + MX_SETBIT(sc, MX_SIO, MX_SIO_EE_CS); + mx_delay(sc); + MX_SETBIT(sc, MX_SIO, MX_SIO_EE_CLK); + mx_delay(sc); + + for (i = 0; i < 25; i++) { + MX_CLRBIT(sc, MX_SIO, MX_SIO_EE_CLK); + mx_delay(sc); + MX_SETBIT(sc, MX_SIO, MX_SIO_EE_CLK); + mx_delay(sc); + } + + MX_CLRBIT(sc, MX_SIO, MX_SIO_EE_CLK); + mx_delay(sc); + MX_CLRBIT(sc, MX_SIO, MX_SIO_EE_CS); + mx_delay(sc); + CSR_WRITE_4(sc, MX_SIO, 0x00000000); + + return; +} + +/* + * Send a read command and address to the EEPROM, check for ACK. + */ +static void mx_eeprom_putbyte(sc, addr) + struct mx_softc *sc; + u_int8_t addr; +{ + register int d, i; + + d = addr | MX_EECMD_READ; + + /* + * Feed in each bit and stobe the clock. + */ + for (i = 0x400; i; i >>= 1) { + if (d & i) { + SIO_SET(MX_SIO_EE_DATAIN); + } else { + SIO_CLR(MX_SIO_EE_DATAIN); + } + mx_delay(sc); + SIO_SET(MX_SIO_EE_CLK); + mx_delay(sc); + SIO_CLR(MX_SIO_EE_CLK); + mx_delay(sc); + } + + return; +} + +/* + * Read a word of data stored in the EEPROM at address 'addr.' + */ +static void mx_eeprom_getword(sc, addr, dest) + struct mx_softc *sc; + u_int8_t addr; + u_int16_t *dest; +{ + register int i; + u_int16_t word = 0; + + /* Force EEPROM to idle state. */ + mx_eeprom_idle(sc); + + /* Enter EEPROM access mode. */ + CSR_WRITE_4(sc, MX_SIO, MX_SIO_EESEL); + mx_delay(sc); + MX_SETBIT(sc, MX_SIO, MX_SIO_ROMCTL_READ); + mx_delay(sc); + MX_SETBIT(sc, MX_SIO, MX_SIO_EE_CS); + mx_delay(sc); + MX_SETBIT(sc, MX_SIO, MX_SIO_EE_CLK); + mx_delay(sc); + + /* + * Send address of word we want to read. + */ + mx_eeprom_putbyte(sc, addr); + + /* + * Start reading bits from EEPROM. + */ + for (i = 0x8000; i; i >>= 1) { + SIO_SET(MX_SIO_EE_CLK); + mx_delay(sc); + if (CSR_READ_4(sc, MX_SIO) & MX_SIO_EE_DATAOUT) + word |= i; + mx_delay(sc); + SIO_CLR(MX_SIO_EE_CLK); + mx_delay(sc); + } + + /* Turn off EEPROM access mode. */ + mx_eeprom_idle(sc); + + *dest = word; + + return; +} + +/* + * Read a sequence of words from the EEPROM. + */ +static void mx_read_eeprom(sc, dest, off, cnt, swap) + struct mx_softc *sc; + caddr_t dest; + int off; + int cnt; + int swap; +{ + int i; + u_int16_t word = 0, *ptr; + + for (i = 0; i < cnt; i++) { + mx_eeprom_getword(sc, off + i, &word); + ptr = (u_int16_t *)(dest + (i * 2)); + if (swap) + *ptr = ntohs(word); + else + *ptr = word; + } + + return; +} + +/* + * The following two routines are taken from the Macronix 98713 + * Application Notes pp.19-21. + */ +/* + * Write a bit to the MII bus. + */ +static void mx_mii_writebit(sc, bit) + struct mx_softc *sc; + int bit; +{ + if (bit) + CSR_WRITE_4(sc, MX_SIO, MX_SIO_ROMCTL_WRITE|MX_SIO_MII_DATAOUT); + else + CSR_WRITE_4(sc, MX_SIO, MX_SIO_ROMCTL_WRITE); + + MX_SETBIT(sc, MX_SIO, MX_SIO_MII_CLK); + MX_CLRBIT(sc, MX_SIO, MX_SIO_MII_CLK); + + return; +} + +/* + * Read a bit from the MII bus. + */ +static int mx_mii_readbit(sc) + struct mx_softc *sc; +{ + CSR_WRITE_4(sc, MX_SIO, MX_SIO_ROMCTL_READ|MX_SIO_MII_DIR); + CSR_READ_4(sc, MX_SIO); + MX_SETBIT(sc, MX_SIO, MX_SIO_MII_CLK); + MX_CLRBIT(sc, MX_SIO, MX_SIO_MII_CLK); + if (CSR_READ_4(sc, MX_SIO) & MX_SIO_MII_DATAIN) + return(1); + + return(0); +} + +/* + * Sync the PHYs by setting data bit and strobing the clock 32 times. + */ +static void mx_mii_sync(sc) + struct mx_softc *sc; +{ + register int i; + + CSR_WRITE_4(sc, MX_SIO, MX_SIO_ROMCTL_WRITE); + + for (i = 0; i < 32; i++) + mx_mii_writebit(sc, 1); + + return; +} + +/* + * Clock a series of bits through the MII. + */ +static void mx_mii_send(sc, bits, cnt) + struct mx_softc *sc; + u_int32_t bits; + int cnt; +{ + int i; + + for (i = (0x1 << (cnt - 1)); i; i >>= 1) + mx_mii_writebit(sc, bits & i); +} + +/* + * Read an PHY register through the MII. + */ +static int mx_mii_readreg(sc, frame) + struct mx_softc *sc; + struct mx_mii_frame *frame; + +{ + int i, ack, s; + + s = splimp(); + + /* + * Set up frame for RX. + */ + frame->mii_stdelim = MX_MII_STARTDELIM; + frame->mii_opcode = MX_MII_READOP; + frame->mii_turnaround = 0; + frame->mii_data = 0; + + /* + * Sync the PHYs. + */ + mx_mii_sync(sc); + + /* + * Send command/address info. + */ + mx_mii_send(sc, frame->mii_stdelim, 2); + mx_mii_send(sc, frame->mii_opcode, 2); + mx_mii_send(sc, frame->mii_phyaddr, 5); + mx_mii_send(sc, frame->mii_regaddr, 5); + +#ifdef notdef + /* Idle bit */ + mx_mii_writebit(sc, 1); + mx_mii_writebit(sc, 0); +#endif + + /* Check for ack */ + ack = mx_mii_readbit(sc); + + /* + * Now try reading data bits. If the ack failed, we still + * need to clock through 16 cycles to keep the PHY(s) in sync. + */ + if (ack) { + for(i = 0; i < 16; i++) { + mx_mii_readbit(sc); + } + goto fail; + } + + for (i = 0x8000; i; i >>= 1) { + if (!ack) { + if (mx_mii_readbit(sc)) + frame->mii_data |= i; + } + } + +fail: + + mx_mii_writebit(sc, 0); + mx_mii_writebit(sc, 0); + + splx(s); + + if (ack) + return(1); + return(0); +} + +/* + * Write to a PHY register through the MII. + */ +static int mx_mii_writereg(sc, frame) + struct mx_softc *sc; + struct mx_mii_frame *frame; + +{ + int s; + + s = splimp(); + /* + * Set up frame for TX. + */ + + frame->mii_stdelim = MX_MII_STARTDELIM; + frame->mii_opcode = MX_MII_WRITEOP; + frame->mii_turnaround = MX_MII_TURNAROUND; + + /* + * Sync the PHYs. + */ + mx_mii_sync(sc); + + mx_mii_send(sc, frame->mii_stdelim, 2); + mx_mii_send(sc, frame->mii_opcode, 2); + mx_mii_send(sc, frame->mii_phyaddr, 5); + mx_mii_send(sc, frame->mii_regaddr, 5); + mx_mii_send(sc, frame->mii_turnaround, 2); + mx_mii_send(sc, frame->mii_data, 16); + + /* Idle bit. */ + mx_mii_writebit(sc, 0); + mx_mii_writebit(sc, 0); + + splx(s); + + return(0); +} + +static u_int16_t mx_phy_readreg(sc, reg) + struct mx_softc *sc; + int reg; +{ + struct mx_mii_frame frame; + u_int32_t cfg; + + bzero((char *)&frame, sizeof(frame)); + + frame.mii_phyaddr = sc->mx_phy_addr; + frame.mii_regaddr = reg; + cfg = CSR_READ_4(sc, MX_NETCFG); + MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_PORTSEL); + mx_mii_readreg(sc, &frame); + CSR_WRITE_4(sc, MX_NETCFG, cfg); + + return(frame.mii_data); +} + +static void mx_phy_writereg(sc, reg, data) + struct mx_softc *sc; + u_int16_t reg; + u_int16_t data; +{ + struct mx_mii_frame frame; + u_int32_t cfg; + + bzero((char *)&frame, sizeof(frame)); + + frame.mii_phyaddr = sc->mx_phy_addr; + frame.mii_regaddr = reg; + frame.mii_data = data; + + cfg = CSR_READ_4(sc, MX_NETCFG); + MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_PORTSEL); + mx_mii_writereg(sc, &frame); + CSR_WRITE_4(sc, MX_NETCFG, cfg); + + return; +} + +#define MX_POLY 0xEDB88320 +#define MX_BITS 9 + +static u_int32_t mx_calchash(addr) + u_int8_t *addr; +{ + u_int32_t idx, bit, data, crc; + + /* Compute CRC for the address value. */ + crc = 0xFFFFFFFF; /* initial value */ + + for (idx = 0; idx < 6; idx++) { + for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) + crc = (crc >> 1) ^ (((crc ^ data) & 1) ? MX_POLY : 0); + } + + return (crc & ((1 << MX_BITS) - 1)); +} + +/* + * Initiate an autonegotiation session. + */ +static void mx_autoneg_xmit(sc) + struct mx_softc *sc; +{ + u_int16_t phy_sts; + + mx_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); + DELAY(500); + while(mx_phy_readreg(sc, PHY_BMCR) + & PHY_BMCR_RESET); + + phy_sts = mx_phy_readreg(sc, PHY_BMCR); + phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR; + mx_phy_writereg(sc, PHY_BMCR, phy_sts); + + return; +} + +/* + * Invoke autonegotiation on a PHY. + */ +static void mx_autoneg_mii(sc, flag, verbose) + struct mx_softc *sc; + int flag; + int verbose; +{ + u_int16_t phy_sts = 0, media, advert, ability; + struct ifnet *ifp; + struct ifmedia *ifm; + + ifm = &sc->ifmedia; + ifp = &sc->arpcom.ac_if; + + ifm->ifm_media = IFM_ETHER | IFM_AUTO; + + /* + * The 100baseT4 PHY on the 3c905-T4 has the 'autoneg supported' + * bit cleared in the status register, but has the 'autoneg enabled' + * bit set in the control register. This is a contradiction, and + * I'm not sure how to handle it. If you want to force an attempt + * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR + * and see what happens. + */ +#ifndef FORCE_AUTONEG_TFOUR + /* + * First, see if autoneg is supported. If not, there's + * no point in continuing. + */ + phy_sts = mx_phy_readreg(sc, PHY_BMSR); + if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { + if (verbose) + printf("mx%d: autonegotiation not supported\n", + sc->mx_unit); + ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; + return; + } +#endif + + switch (flag) { + case MX_FLAG_FORCEDELAY: + /* + * XXX Never use this option anywhere but in the probe + * routine: making the kernel stop dead in its tracks + * for three whole seconds after we've gone multi-user + * is really bad manners. + */ + mx_autoneg_xmit(sc); + DELAY(5000000); + break; + case MX_FLAG_SCHEDDELAY: + /* + * Wait for the transmitter to go idle before starting + * an autoneg session, otherwise mx_start() may clobber + * our timeout, and we don't want to allow transmission + * during an autoneg session since that can screw it up. + */ + if (sc->mx_cdata.mx_tx_head != NULL) { + sc->mx_want_auto = 1; + return; + } + mx_autoneg_xmit(sc); + ifp->if_timer = 5; + sc->mx_autoneg = 1; + sc->mx_want_auto = 0; + return; + break; + case MX_FLAG_DELAYTIMEO: + ifp->if_timer = 0; + sc->mx_autoneg = 0; + break; + default: + printf("mx%d: invalid autoneg flag: %d\n", sc->mx_unit, flag); + return; + } + + if (mx_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { + if (verbose) + printf("mx%d: autoneg complete, ", sc->mx_unit); + phy_sts = mx_phy_readreg(sc, PHY_BMSR); + } else { + if (verbose) + printf("mx%d: autoneg not complete, ", sc->mx_unit); + } + + media = mx_phy_readreg(sc, PHY_BMCR); + + /* Link is good. Report modes and set duplex mode. */ + if (mx_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { + if (verbose) + printf("link status good "); + advert = mx_phy_readreg(sc, PHY_ANAR); + ability = mx_phy_readreg(sc, PHY_LPAR); + + if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { + ifm->ifm_media = IFM_ETHER|IFM_100_T4; + media |= PHY_BMCR_SPEEDSEL; + media &= ~PHY_BMCR_DUPLEX; + printf("(100baseT4)\n"); + } else if (advert & PHY_ANAR_100BTXFULL && + ability & PHY_ANAR_100BTXFULL) { + ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; + media |= PHY_BMCR_SPEEDSEL; + media |= PHY_BMCR_DUPLEX; + printf("(full-duplex, 100Mbps)\n"); + } else if (advert & PHY_ANAR_100BTXHALF && + ability & PHY_ANAR_100BTXHALF) { + ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; + media |= PHY_BMCR_SPEEDSEL; + media &= ~PHY_BMCR_DUPLEX; + printf("(half-duplex, 100Mbps)\n"); + } else if (advert & PHY_ANAR_10BTFULL && + ability & PHY_ANAR_10BTFULL) { + ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; + media &= ~PHY_BMCR_SPEEDSEL; + media |= PHY_BMCR_DUPLEX; + printf("(full-duplex, 10Mbps)\n"); + } else if (advert & PHY_ANAR_10BTHALF && + ability & PHY_ANAR_10BTHALF) { + ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; + media &= ~PHY_BMCR_SPEEDSEL; + media &= ~PHY_BMCR_DUPLEX; + printf("(half-duplex, 10Mbps)\n"); + } + + media &= ~PHY_BMCR_AUTONEGENBL; + + /* Set ASIC's duplex mode to match the PHY. */ + mx_setcfg(sc, media); + mx_phy_writereg(sc, PHY_BMCR, media); + } else { + if (verbose) + printf("no carrier\n"); + } + + mx_init(sc); + + if (sc->mx_tx_pend) { + sc->mx_autoneg = 0; + sc->mx_tx_pend = 0; + mx_start(ifp); + } + + return; +} + +/* + * Invoke autoneg using internal NWAY. + */ +static void mx_autoneg(sc, flag, verbose) + struct mx_softc *sc; + int flag; + int verbose; +{ + u_int32_t media, ability; + struct ifnet *ifp; + struct ifmedia *ifm; + + ifm = &sc->ifmedia; + ifp = &sc->arpcom.ac_if; + + ifm->ifm_media = IFM_ETHER | IFM_AUTO; + + switch (flag) { + case MX_FLAG_FORCEDELAY: + /* + * XXX Never use this option anywhere but in the probe + * routine: making the kernel stop dead in its tracks + * for three whole seconds after we've gone multi-user + * is really bad manners. + */ + MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_PORTSEL); + MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_FULLDUPLEX); + MX_SETBIT(sc, MX_10BTCTRL, MX_TCTL_AUTONEGENBL); + MX_SETBIT(sc, MX_10BTCTRL, MX_ASTAT_TXDISABLE); + DELAY(5000000); + break; + case MX_FLAG_SCHEDDELAY: + /* + * Wait for the transmitter to go idle before starting + * an autoneg session, otherwise mx_start() may clobber + * our timeout, and we don't want to allow transmission + * during an autoneg session since that can screw it up. + */ + if (sc->mx_cdata.mx_tx_head != NULL) { + sc->mx_want_auto = 1; + return; + } + MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_PORTSEL); + MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_FULLDUPLEX); + MX_SETBIT(sc, MX_10BTCTRL, MX_TCTL_AUTONEGENBL); + MX_SETBIT(sc, MX_10BTCTRL, MX_ASTAT_TXDISABLE); + ifp->if_timer = 5; + sc->mx_autoneg = 1; + sc->mx_want_auto = 0; + return; + break; + case MX_FLAG_DELAYTIMEO: + ifp->if_timer = 0; + sc->mx_autoneg = 0; + break; + default: + printf("mx%d: invalid autoneg flag: %d\n", sc->mx_unit, flag); + return; + } + + if ((CSR_READ_4(sc, MX_10BTSTAT) & MX_TSTAT_ANEGSTAT) == + MX_ASTAT_AUTONEGCMP) { + if (verbose) + printf("mx%d: autoneg complete, ", sc->mx_unit); + } else { + if (verbose) + printf("mx%d: autoneg not complete, ", sc->mx_unit); + } + + media = CSR_READ_4(sc, MX_NETCFG); + + /* Link is good. Report modes and set duplex mode. */ + if (!(CSR_READ_4(sc, MX_10BTSTAT) & MX_TSTAT_LS10) || + !(CSR_READ_4(sc, MX_10BTSTAT) & MX_TSTAT_LS100)) { + if (verbose) + printf("link status good "); + ability = CSR_READ_4(sc, MX_NWAYSTAT); + if (ability & MX_NWAY_100BT4) { + ifm->ifm_media = IFM_ETHER|IFM_100_T4; + media |= MX_NETCFG_PORTSEL|MX_NETCFG_PCS| + MX_NETCFG_SCRAMBLER; + media &= ~(MX_NETCFG_FULLDUPLEX|MX_NETCFG_SPEEDSEL); + printf("(100baseT4)\n"); + } else if (ability & MX_NWAY_100BTFULL) { + ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; + media |= MX_NETCFG_PORTSEL|MX_NETCFG_PCS| + MX_NETCFG_SCRAMBLER; + media |= MX_NETCFG_FULLDUPLEX; + media &= ~MX_NETCFG_SPEEDSEL; + printf("(full-duplex, 100Mbps)\n"); + } else if (ability & MX_NWAY_100BTHALF) { + ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; + media |= MX_NETCFG_PORTSEL|MX_NETCFG_PCS| + MX_NETCFG_SCRAMBLER; + media &= ~(MX_NETCFG_FULLDUPLEX|MX_NETCFG_SPEEDSEL); + printf("(half-duplex, 100Mbps)\n"); + } else if (ability & MX_NWAY_10BTFULL) { + ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; + media &= ~MX_NETCFG_PORTSEL; + media |= (MX_NETCFG_FULLDUPLEX|MX_NETCFG_SPEEDSEL); + printf("(full-duplex, 10Mbps)\n"); + } else { + ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; + media &= ~MX_NETCFG_PORTSEL; + media &= ~MX_NETCFG_FULLDUPLEX; + media |= MX_NETCFG_SPEEDSEL; + printf("(half-duplex, 10Mbps)\n"); + } + + CSR_WRITE_4(sc, MX_NETCFG, media); + MX_CLRBIT(sc, MX_10BTCTRL, MX_TCTL_AUTONEGENBL); + } else { + if (verbose) + printf("no carrier\n"); + } + + mx_init(sc); + + if (sc->mx_tx_pend) { + sc->mx_autoneg = 0; + sc->mx_tx_pend = 0; + mx_start(ifp); + } + + return; +} + +static void mx_getmode_mii(sc) + struct mx_softc *sc; +{ + u_int16_t bmsr; + struct ifnet *ifp; + + ifp = &sc->arpcom.ac_if; + + bmsr = mx_phy_readreg(sc, PHY_BMSR); + if (bootverbose) + printf("mx%d: PHY status word: %x\n", sc->mx_unit, bmsr); + + /* fallback */ + sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; + + if (bmsr & PHY_BMSR_10BTHALF) { + if (bootverbose) + printf("mx%d: 10Mbps half-duplex mode supported\n", + sc->mx_unit); + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); + } + + if (bmsr & PHY_BMSR_10BTFULL) { + if (bootverbose) + printf("mx%d: 10Mbps full-duplex mode supported\n", + sc->mx_unit); + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); + sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; + } + + if (bmsr & PHY_BMSR_100BTXHALF) { + if (bootverbose) + printf("mx%d: 100Mbps half-duplex mode supported\n", + sc->mx_unit); + ifp->if_baudrate = 100000000; + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); + sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; + } + + if (bmsr & PHY_BMSR_100BTXFULL) { + if (bootverbose) + printf("mx%d: 100Mbps full-duplex mode supported\n", + sc->mx_unit); + ifp->if_baudrate = 100000000; + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); + sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; + } + + /* Some also support 100BaseT4. */ + if (bmsr & PHY_BMSR_100BT4) { + if (bootverbose) + printf("mx%d: 100baseT4 mode supported\n", sc->mx_unit); + ifp->if_baudrate = 100000000; + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL); + sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4; +#ifdef FORCE_AUTONEG_TFOUR + if (bootverbose) + printf("mx%d: forcing on autoneg support for BT4\n", + sc->mx_unit); + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL): + sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; +#endif + } + + if (bmsr & PHY_BMSR_CANAUTONEG) { + if (bootverbose) + printf("mx%d: autoneg supported\n", sc->mx_unit); + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); + sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; + } + + return; +} + +/* + * Set speed and duplex mode. + */ +static void mx_setmode_mii(sc, media) + struct mx_softc *sc; + int media; +{ + u_int16_t bmcr; + struct ifnet *ifp; + + ifp = &sc->arpcom.ac_if; + + /* + * If an autoneg session is in progress, stop it. + */ + if (sc->mx_autoneg) { + printf("mx%d: canceling autoneg session\n", sc->mx_unit); + ifp->if_timer = sc->mx_autoneg = sc->mx_want_auto = 0; + bmcr = mx_phy_readreg(sc, PHY_BMCR); + bmcr &= ~PHY_BMCR_AUTONEGENBL; + mx_phy_writereg(sc, PHY_BMCR, bmcr); + } + + printf("mx%d: selecting MII, ", sc->mx_unit); + + bmcr = mx_phy_readreg(sc, PHY_BMCR); + + bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL| + PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK); + + if (IFM_SUBTYPE(media) == IFM_100_T4) { + printf("100Mbps/T4, half-duplex\n"); + bmcr |= PHY_BMCR_SPEEDSEL; + bmcr &= ~PHY_BMCR_DUPLEX; + } + + if (IFM_SUBTYPE(media) == IFM_100_TX) { + printf("100Mbps, "); + bmcr |= PHY_BMCR_SPEEDSEL; + } + + if (IFM_SUBTYPE(media) == IFM_10_T) { + printf("10Mbps, "); + bmcr &= ~PHY_BMCR_SPEEDSEL; + } + + if ((media & IFM_GMASK) == IFM_FDX) { + printf("full duplex\n"); + bmcr |= PHY_BMCR_DUPLEX; + } else { + printf("half duplex\n"); + bmcr &= ~PHY_BMCR_DUPLEX; + } + + mx_setcfg(sc, bmcr); + mx_phy_writereg(sc, PHY_BMCR, bmcr); + + return; +} + +/* + * Set speed and duplex mode on internal transceiver. + */ +static void mx_setmode(sc, media, verbose) + struct mx_softc *sc; + int media; + int verbose; +{ + struct ifnet *ifp; + u_int32_t mode; + + ifp = &sc->arpcom.ac_if; + + /* + * If an autoneg session is in progress, stop it. + */ + if (sc->mx_autoneg) { + printf("mx%d: canceling autoneg session\n", sc->mx_unit); + ifp->if_timer = sc->mx_autoneg = sc->mx_want_auto = 0; + MX_CLRBIT(sc, MX_10BTCTRL, MX_TCTL_AUTONEGENBL); + } + + if (verbose) + printf("mx%d: selecting NWAY, ", sc->mx_unit); + + mode = CSR_READ_4(sc, MX_NETCFG); + + mode &= ~(MX_NETCFG_FULLDUPLEX|MX_NETCFG_PORTSEL| + MX_NETCFG_PCS|MX_NETCFG_SCRAMBLER|MX_NETCFG_SPEEDSEL); + + if (IFM_SUBTYPE(media) == IFM_100_T4) { + if (verbose) + printf("100Mbps/T4, half-duplex\n"); + mode |= MX_NETCFG_PORTSEL|MX_NETCFG_PCS|MX_NETCFG_SCRAMBLER; + } + + if (IFM_SUBTYPE(media) == IFM_100_TX) { + if (verbose) + printf("100Mbps, "); + mode |= MX_NETCFG_PORTSEL|MX_NETCFG_PCS|MX_NETCFG_SCRAMBLER; + } + + if (IFM_SUBTYPE(media) == IFM_10_T) { + if (verbose) + printf("10Mbps, "); + mode &= ~MX_NETCFG_PORTSEL; + mode |= MX_NETCFG_SPEEDSEL; + } + + if ((media & IFM_GMASK) == IFM_FDX) { + if (verbose) + printf("full duplex\n"); + mode |= MX_NETCFG_FULLDUPLEX; + } else { + if (verbose) + printf("half duplex\n"); + mode &= ~MX_NETCFG_FULLDUPLEX; + } + + CSR_WRITE_4(sc, MX_NETCFG, mode); + + return; +} + +/* + * Programming the receiver filter on the tulip/PMAC is gross. You + * have to construct a special setup frame and download it to the + * chip via the transmit DMA engine. This routine is also somewhat + * gross, as the setup frame is sent synchronously rather than putting + * on the transmit queue. The transmitter has to be stopped, then we + * can download the frame and wait for the 'owned' bit to clear. + * + * We always program the chip using 'hash perfect' mode, i.e. one perfect + * address (our node address) and a 512-bit hash filter for multicast + * frames. We also sneak the broadcast address into the hash filter since + * we need that too. + */ +void mx_setfilt(sc) + struct mx_softc *sc; +{ + struct mx_desc *sframe; + u_int32_t h, *sp; + struct arpcom *ac = &sc->arpcom; + struct ether_multi *enm; + struct ether_multistep step; + struct ifnet *ifp; + int i; + + ifp = &sc->arpcom.ac_if; + + MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_TX_ON); + MX_SETBIT(sc, MX_ISR, MX_ISR_TX_IDLE); + + sframe = &sc->mx_cdata.mx_sframe; + sp = (u_int32_t *)&sc->mx_cdata.mx_sbuf; + bzero((char *)sp, MX_SFRAME_LEN); + + sframe->mx_next = vtophys(&sc->mx_ldata->mx_tx_list[0]); + sframe->mx_data = vtophys(&sc->mx_cdata.mx_sbuf); + sframe->mx_ctl = MX_SFRAME_LEN | MX_TXCTL_TLINK | + MX_TXCTL_SETUP | MX_FILTER_HASHPERF; + + /* If we want promiscuous mode, set the allframes bit. */ + if (ifp->if_flags & IFF_PROMISC) + MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_RX_PROMISC); + else + MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_RX_PROMISC); + + if (ifp->if_flags & IFF_ALLMULTI) + MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_RX_ALLMULTI); + + ETHER_FIRST_MULTI(step, ac, enm); + while (enm != NULL) { + h = mx_calchash(enm->enm_addrlo); + ETHER_NEXT_MULTI(step, enm); + } + + if (ifp->if_flags & IFF_BROADCAST) { + h = mx_calchash(etherbroadcastaddr); + sp[h >> 4] |= 1 << (h & 0xF); + } + + sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; + sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; + sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; + + CSR_WRITE_4(sc, MX_TXADDR, vtophys(sframe)); + MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_TX_ON); + sframe->mx_status = MX_TXSTAT_OWN; + CSR_WRITE_4(sc, MX_TXSTART, 0xFFFFFFFF); + + /* + * Wait for chip to clear the 'own' bit. + */ + for (i = 0; i < MX_TIMEOUT; i++) { + DELAY(10); + if (sframe->mx_status != MX_TXSTAT_OWN) + break; + } + + if (i == MX_TIMEOUT) + printf("mx%d: failed to send setup frame\n", sc->mx_unit); + + MX_SETBIT(sc, MX_ISR, MX_ISR_TX_NOBUF|MX_ISR_TX_IDLE); + + return; +} + +/* + * In order to fiddle with the + * 'full-duplex' and '100Mbps' bits in the netconfig register, we + * first have to put the transmit and/or receive logic in the idle state. + */ +static void mx_setcfg(sc, bmcr) + struct mx_softc *sc; + u_int16_t bmcr; +{ + int i, restart = 0; + + if (CSR_READ_4(sc, MX_NETCFG) & (MX_NETCFG_TX_ON|MX_NETCFG_RX_ON)) { + restart = 1; + MX_CLRBIT(sc, MX_NETCFG, (MX_NETCFG_TX_ON|MX_NETCFG_RX_ON)); + + for (i = 0; i < MX_TIMEOUT; i++) { + DELAY(10); + if (CSR_READ_4(sc, MX_ISR) & MX_ISR_TX_IDLE) + break; + } + + if (i == MX_TIMEOUT) + printf("mx%d: failed to force tx and " + "rx to idle state\n", sc->mx_unit); + + } + + if (bmcr & PHY_BMCR_SPEEDSEL) { + MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_SPEEDSEL); + if (sc->mx_phy_addr == 0) { + MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_PORTSEL| + MX_NETCFG_PCS|MX_NETCFG_SCRAMBLER); + } + } else + MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_SPEEDSEL); + + if (bmcr & PHY_BMCR_DUPLEX) + MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_FULLDUPLEX); + else + MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_FULLDUPLEX); + + if (restart) + MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_TX_ON|MX_NETCFG_RX_ON); + + return; +} + +static void mx_reset(sc) + struct mx_softc *sc; +{ + register int i; + + MX_SETBIT(sc, MX_BUSCTL, MX_BUSCTL_RESET); + + for (i = 0; i < MX_TIMEOUT; i++) { + DELAY(10); + if (!(CSR_READ_4(sc, MX_BUSCTL) & MX_BUSCTL_RESET)) + break; + } + if (i == MX_TIMEOUT) + printf("mx%d: reset never completed!\n", sc->mx_unit); + + /* Wait a little while for the chip to get its brains in order. */ + DELAY(1000); + return; +} + +/* + * Initialize the transmit descriptors. + */ +static int mx_list_tx_init(sc) + struct mx_softc *sc; +{ + struct mx_chain_data *cd; + struct mx_list_data *ld; + int i; + + cd = &sc->mx_cdata; + ld = sc->mx_ldata; + for (i = 0; i < MX_TX_LIST_CNT; i++) { + cd->mx_tx_chain[i].mx_ptr = &ld->mx_tx_list[i]; + if (i == (MX_TX_LIST_CNT - 1)) + cd->mx_tx_chain[i].mx_nextdesc = + &cd->mx_tx_chain[0]; + else + cd->mx_tx_chain[i].mx_nextdesc = + &cd->mx_tx_chain[i + 1]; + } + + cd->mx_tx_free = &cd->mx_tx_chain[0]; + cd->mx_tx_tail = cd->mx_tx_head = NULL; + + return(0); +} + + +/* + * Initialize the RX descriptors and allocate mbufs for them. Note that + * we arrange the descriptors in a closed ring, so that the last descriptor + * points back to the first. + */ +static int mx_list_rx_init(sc) + struct mx_softc *sc; +{ + struct mx_chain_data *cd; + struct mx_list_data *ld; + int i; + + cd = &sc->mx_cdata; + ld = sc->mx_ldata; + + for (i = 0; i < MX_RX_LIST_CNT; i++) { + cd->mx_rx_chain[i].mx_ptr = + (struct mx_desc *)&ld->mx_rx_list[i]; + if (mx_newbuf(sc, &cd->mx_rx_chain[i]) == ENOBUFS) + return(ENOBUFS); + if (i == (MX_RX_LIST_CNT - 1)) { + cd->mx_rx_chain[i].mx_nextdesc = &cd->mx_rx_chain[0]; + ld->mx_rx_list[i].mx_next = + vtophys(&ld->mx_rx_list[0]); + } else { + cd->mx_rx_chain[i].mx_nextdesc = &cd->mx_rx_chain[i + 1]; + ld->mx_rx_list[i].mx_next = + vtophys(&ld->mx_rx_list[i + 1]); + } + } + + cd->mx_rx_head = &cd->mx_rx_chain[0]; + + return(0); +} + +/* + * Initialize an RX descriptor and attach an MBUF cluster. + * Note: the length fields are only 11 bits wide, which means the + * largest size we can specify is 2047. This is important because + * MCLBYTES is 2048, so we have to subtract one otherwise we'll + * overflow the field and make a mess. + */ +static int mx_newbuf(sc, c) + struct mx_softc *sc; + struct mx_chain_onefrag *c; +{ + struct mbuf *m_new = NULL; + + MGETHDR(m_new, M_DONTWAIT, MT_DATA); + if (m_new == NULL) + return(ENOBUFS); + + MCLGET(m_new, M_DONTWAIT); + if (!(m_new->m_flags & M_EXT)) { + m_freem(m_new); + return(ENOBUFS); + } + + c->mx_mbuf = m_new; + c->mx_ptr->mx_status = MX_RXSTAT; + c->mx_ptr->mx_data = vtophys(mtod(m_new, caddr_t)); + c->mx_ptr->mx_ctl = MX_RXCTL_RLINK | (MCLBYTES - 1); + + return(0); +} + +/* + * A frame has been uploaded: pass the resulting mbuf chain up to + * the higher level protocols. + */ +static void mx_rxeof(sc) + struct mx_softc *sc; +{ + struct ether_header *eh; + struct mbuf *m; + struct ifnet *ifp; + struct mx_chain_onefrag *cur_rx; + int total_len = 0; + u_int32_t rxstat; + + ifp = &sc->arpcom.ac_if; + + while(!((rxstat = sc->mx_cdata.mx_rx_head->mx_ptr->mx_status) & + MX_RXSTAT_OWN)) { + cur_rx = sc->mx_cdata.mx_rx_head; + sc->mx_cdata.mx_rx_head = cur_rx->mx_nextdesc; + + /* + * If an error occurs, update stats, clear the + * status word and leave the mbuf cluster in place: + * it should simply get re-used next time this descriptor + * comes up in the ring. + */ + if (rxstat & MX_RXSTAT_RXERR) { + ifp->if_ierrors++; + if (rxstat & MX_RXSTAT_COLLSEEN) + ifp->if_collisions++; + cur_rx->mx_ptr->mx_status = MX_RXSTAT; + cur_rx->mx_ptr->mx_ctl = + MX_RXCTL_RLINK | (MCLBYTES - 1); + continue; + } + + /* No errors; receive the packet. */ + m = cur_rx->mx_mbuf; + total_len = MX_RXBYTES(cur_rx->mx_ptr->mx_status); + + /* + * XXX The Macronix chips includes the CRC with every + * received frame, and there's no way to turn this + * behavior off (at least, I can't find anything in + * the manual that explains how to do it) so we have + * to trim off the CRC manually. + */ + total_len -= ETHER_CRC_LEN; + + /* + * Try to conjure up a new mbuf cluster. If that + * fails, it means we have an out of memory condition and + * should leave the buffer in place and continue. This will + * result in a lost packet, but there's little else we + * can do in this situation. + */ + if (mx_newbuf(sc, cur_rx) == ENOBUFS) { + ifp->if_ierrors++; + cur_rx->mx_ptr->mx_status = MX_RXSTAT; + cur_rx->mx_ptr->mx_ctl = + MX_RXCTL_RLINK | (MCLBYTES - 1); + continue; + } + + ifp->if_ipackets++; + eh = mtod(m, struct ether_header *); + m->m_pkthdr.rcvif = ifp; + m->m_pkthdr.len = m->m_len = total_len; +#if NBPFILTER > 0 + /* + * Handle BPF listeners. Let the BPF user see the packet, but + * don't pass it up to the ether_input() layer unless it's + * a broadcast packet, multicast packet, matches our ethernet + * address or the interface is in promiscuous mode. + */ + if (ifp->if_bpf) { + bpf_mtap(ifp->if_bpf, m); + if (ifp->if_flags & IFF_PROMISC && + (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, + ETHER_ADDR_LEN) && + (eh->ether_dhost[0] & 1) == 0)) { + m_freem(m); + continue; + } + } +#endif + /* Remove header from mbuf and pass it on. */ + m_adj(m, sizeof(struct ether_header)); + ether_input(ifp, eh, m); + } + + return; +} + +void mx_rxeoc(sc) + struct mx_softc *sc; +{ + + mx_rxeof(sc); + MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_RX_ON); + CSR_WRITE_4(sc, MX_RXADDR, vtophys(sc->mx_cdata.mx_rx_head->mx_ptr)); + MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_RX_ON); + CSR_WRITE_4(sc, MX_RXSTART, 0xFFFFFFFF); + + return; +} + +/* + * A frame was downloaded to the chip. It's safe for us to clean up + * the list buffers. + */ + +static void mx_txeof(sc) + struct mx_softc *sc; +{ + struct mx_chain *cur_tx; + struct ifnet *ifp; + + ifp = &sc->arpcom.ac_if; + + /* Clear the timeout timer. */ + ifp->if_timer = 0; + + if (sc->mx_cdata.mx_tx_head == NULL) + return; + + /* + * Go through our tx list and free mbufs for those + * frames that have been transmitted. + */ + while(sc->mx_cdata.mx_tx_head->mx_mbuf != NULL) { + u_int32_t txstat; + + cur_tx = sc->mx_cdata.mx_tx_head; + txstat = MX_TXSTATUS(cur_tx); + + if ((txstat & MX_TXSTAT_OWN) || txstat == MX_UNSENT) + break; + + if (txstat & MX_TXSTAT_ERRSUM) { + ifp->if_oerrors++; + if (txstat & MX_TXSTAT_EXCESSCOLL) + ifp->if_collisions++; + if (txstat & MX_TXSTAT_LATECOLL) + ifp->if_collisions++; + } + + ifp->if_collisions += (txstat & MX_TXSTAT_COLLCNT) >> 3; + + ifp->if_opackets++; + m_freem(cur_tx->mx_mbuf); + cur_tx->mx_mbuf = NULL; + + if (sc->mx_cdata.mx_tx_head == sc->mx_cdata.mx_tx_tail) { + sc->mx_cdata.mx_tx_head = NULL; + sc->mx_cdata.mx_tx_tail = NULL; + break; + } + + sc->mx_cdata.mx_tx_head = cur_tx->mx_nextdesc; + } + + return; +} + +/* + * TX 'end of channel' interrupt handler. + */ +static void mx_txeoc(sc) + struct mx_softc *sc; +{ + struct ifnet *ifp; + + ifp = &sc->arpcom.ac_if; + + ifp->if_timer = 0; + + if (sc->mx_cdata.mx_tx_head == NULL) { + ifp->if_flags &= ~IFF_OACTIVE; + sc->mx_cdata.mx_tx_tail = NULL; + if (sc->mx_want_auto) { + if (sc->mx_type == MX_TYPE_98713 && + sc->mx_pinfo != NULL) + mx_autoneg_mii(sc, MX_FLAG_DELAYTIMEO, 1); + else + mx_autoneg(sc, MX_FLAG_DELAYTIMEO, 1); + } + } else { + if (MX_TXOWN(sc->mx_cdata.mx_tx_head) == MX_UNSENT) { + MX_TXOWN(sc->mx_cdata.mx_tx_head) = MX_TXSTAT_OWN; + ifp->if_timer = 5; + CSR_WRITE_4(sc, MX_TXSTART, 0xFFFFFFFF); + } + } + + return; +} + +static int mx_intr(arg) + void *arg; +{ + struct mx_softc *sc; + struct ifnet *ifp; + u_int32_t status; + int claimed = 0; + + sc = arg; + ifp = &sc->arpcom.ac_if; + + /* Supress unwanted interrupts */ + if (!(ifp->if_flags & IFF_UP)) { + mx_stop(sc); + return 0; + } + + /* Disable interrupts. */ + CSR_WRITE_4(sc, MX_IMR, 0x00000000); + + for (;;) { + status = CSR_READ_4(sc, MX_ISR); + if (status) + CSR_WRITE_4(sc, MX_ISR, status); + + if ((status & MX_INTRS) == 0) + break; + + claimed = 1; + + if (status & MX_ISR_TX_OK) + mx_txeof(sc); + + if (status & MX_ISR_TX_NOBUF) + mx_txeoc(sc); + + if (status & MX_ISR_TX_IDLE) { + mx_txeof(sc); + if (sc->mx_cdata.mx_tx_head != NULL) { + MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_TX_ON); + CSR_WRITE_4(sc, MX_TXSTART, 0xFFFFFFFF); + } + } + + if (status & MX_ISR_TX_UNDERRUN) { + u_int32_t cfg; + cfg = CSR_READ_4(sc, MX_NETCFG); + if ((cfg & MX_NETCFG_TX_THRESH) == MX_TXTHRESH_160BYTES) + MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_STORENFWD); + else + CSR_WRITE_4(sc, MX_NETCFG, cfg + 0x4000); + } + + if (status & MX_ISR_RX_OK) + mx_rxeof(sc); + + if ((status & MX_ISR_RX_WATDOGTIMEO) + || (status & MX_ISR_RX_NOBUF)) + mx_rxeoc(sc); + + if (status & MX_ISR_BUS_ERR) { + mx_reset(sc); + mx_init(sc); + } + } + + /* Re-enable interrupts. */ + CSR_WRITE_4(sc, MX_IMR, MX_INTRS); + + if (ifp->if_snd.ifq_head != NULL) { + mx_start(ifp); + } + + return (claimed); +} + +/* + * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data + * pointers to the fragment pointers. + */ +static int mx_encap(sc, c, m_head) + struct mx_softc *sc; + struct mx_chain *c; + struct mbuf *m_head; +{ + int frag = 0; + volatile struct mx_desc *f = NULL; + int total_len; + struct mbuf *m; + + /* + * Start packing the mbufs in this chain into + * the fragment pointers. Stop when we run out + * of fragments or hit the end of the mbuf chain. + */ + m = m_head; + total_len = 0; + + for (m = m_head, frag = 0; m != NULL; m = m->m_next) { + if (m->m_len != 0) { + if (frag == MX_MAXFRAGS) + break; + total_len += m->m_len; + f = &c->mx_ptr->mx_frag[frag]; + f->mx_ctl = MX_TXCTL_TLINK | m->m_len; + if (frag == 0) { + f->mx_status = 0; + f->mx_ctl |= MX_TXCTL_FIRSTFRAG; + } else + f->mx_status = MX_TXSTAT_OWN; + f->mx_next = vtophys(&c->mx_ptr->mx_frag[frag + 1]); + f->mx_data = vtophys(mtod(m, vm_offset_t)); + frag++; + } + } + + /* + * Handle special case: we ran out of fragments, + * but we have more mbufs left in the chain. Copy the + * data into an mbuf cluster. Note that we don't + * bother clearing the values in the other fragment + * pointers/counters; it wouldn't gain us anything, + * and would waste cycles. + */ + if (m != NULL) { + struct mbuf *m_new = NULL; + + MGETHDR(m_new, M_DONTWAIT, MT_DATA); + if (m_new == NULL) { + return(1); + } + if (m_head->m_pkthdr.len > MHLEN) { + MCLGET(m_new, M_DONTWAIT); + if (!(m_new->m_flags & M_EXT)) { + m_freem(m_new); + return(1); + } + } + m_copydata(m_head, 0, m_head->m_pkthdr.len, + mtod(m_new, caddr_t)); + m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; + m_freem(m_head); + m_head = m_new; + f = &c->mx_ptr->mx_frag[0]; + f->mx_status = 0; + f->mx_data = vtophys(mtod(m_new, caddr_t)); + f->mx_ctl = total_len = m_new->m_len; + f->mx_ctl |= MX_TXCTL_TLINK|MX_TXCTL_FIRSTFRAG; + frag = 1; + } + + + if (total_len < MX_MIN_FRAMELEN) { + f = &c->mx_ptr->mx_frag[frag]; + f->mx_ctl = MX_MIN_FRAMELEN - total_len; + f->mx_data = vtophys(&sc->mx_cdata.mx_pad); + f->mx_ctl |= MX_TXCTL_TLINK; + f->mx_status = MX_TXSTAT_OWN; + frag++; + } + + c->mx_mbuf = m_head; + c->mx_lastdesc = frag - 1; + MX_TXCTL(c) |= MX_TXCTL_LASTFRAG; + MX_TXNEXT(c) = vtophys(&c->mx_nextdesc->mx_ptr->mx_frag[0]); + return(0); +} + +/* + * Main transmit routine. To avoid having to do mbuf copies, we put pointers + * to the mbuf data regions directly in the transmit lists. We also save a + * copy of the pointers since the transmit list fragment pointers are + * physical addresses. + */ + +static void mx_start(ifp) + struct ifnet *ifp; +{ + struct mx_softc *sc; + struct mbuf *m_head = NULL; + struct mx_chain *cur_tx = NULL, *start_tx; + + sc = ifp->if_softc; + + if (sc->mx_autoneg) { + sc->mx_tx_pend = 1; + return; + } + + /* + * Check for an available queue slot. If there are none, + * punt. + */ + if (sc->mx_cdata.mx_tx_free->mx_mbuf != NULL) { + ifp->if_flags |= IFF_OACTIVE; + return; + } + + start_tx = sc->mx_cdata.mx_tx_free; + + while(sc->mx_cdata.mx_tx_free->mx_mbuf == NULL) { + IF_DEQUEUE(&ifp->if_snd, m_head); + if (m_head == NULL) + break; + + /* Pick a descriptor off the free list. */ + cur_tx = sc->mx_cdata.mx_tx_free; + sc->mx_cdata.mx_tx_free = cur_tx->mx_nextdesc; + + /* Pack the data into the descriptor. */ + mx_encap(sc, cur_tx, m_head); + if (cur_tx != start_tx) + MX_TXOWN(cur_tx) = MX_TXSTAT_OWN; + +#if NBPFILTER > 0 + /* + * If there's a BPF listener, bounce a copy of this frame + * to him. + */ + if (ifp->if_bpf) + bpf_mtap(ifp->if_bpf, cur_tx->mx_mbuf); +#endif + } + + /* + * If there are no frames queued, bail. + */ + if (cur_tx == NULL) + return; + + /* + * Place the request for the upload interrupt + * in the last descriptor in the chain. This way, if + * we're chaining several packets at once, we'll only + * get an interupt once for the whole chain rather than + * once for each packet. + */ + MX_TXCTL(cur_tx) |= MX_TXCTL_FINT; + sc->mx_cdata.mx_tx_tail = cur_tx; + + if (sc->mx_cdata.mx_tx_head == NULL) { + sc->mx_cdata.mx_tx_head = start_tx; + MX_TXOWN(start_tx) = MX_TXSTAT_OWN; + CSR_WRITE_4(sc, MX_TXSTART, 0xFFFFFFFF); + } else { + MX_TXOWN(start_tx) = MX_UNSENT; + } + + /* + * Set a timeout in case the chip goes out to lunch. + */ + ifp->if_timer = 5; + + return; +} + +static void mx_init(xsc) + void *xsc; +{ + struct mx_softc *sc = xsc; + struct ifnet *ifp = &sc->arpcom.ac_if; + u_int16_t phy_bmcr = 0; + int s; + + if (sc->mx_autoneg) + return; + + s = splimp(); + + if (sc->mx_pinfo != NULL) + phy_bmcr = mx_phy_readreg(sc, PHY_BMCR); + + /* + * Cancel pending I/O and free all RX/TX buffers. + */ + mx_stop(sc); + mx_reset(sc); + + /* + * Set cache alignment and burst length. + */ + CSR_WRITE_4(sc, MX_BUSCTL, MX_BUSCTL_CONFIG); + + MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_NO_RXCRC); + MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_HEARTBEAT); + MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_STORENFWD); + MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_TX_BACKOFF); + + /* + * The app notes for the 98713 and 98715A say that + * in order to have the chips operate properly, a magic + * number must be written to CSR16. Macronix does not + * document the meaning of these bits so there's no way + * to know exactly what they mean. The 98713 has a magic + * number all its own; the rest all use a different one. + */ + MX_CLRBIT(sc, MX_MAGICPACKET, 0xFFFF0000); + if (sc->mx_type == MX_TYPE_98713) + MX_SETBIT(sc, MX_MAGICPACKET, MX_MAGIC_98713); + else + MX_SETBIT(sc, MX_MAGICPACKET, MX_MAGIC_98715); + + if (sc->mx_pinfo != NULL) { + MX_SETBIT(sc, MX_WATCHDOG, MX_WDOG_JABBERDIS); + mx_setcfg(sc, mx_phy_readreg(sc, PHY_BMCR)); + } else + mx_setmode(sc, sc->ifmedia.ifm_media, 0); + + MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_TX_THRESH); + MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_SPEEDSEL); + + if (IFM_SUBTYPE(sc->ifmedia.ifm_media) == IFM_10_T) + MX_SETBIT(sc, MX_NETCFG, MX_TXTHRESH_160BYTES); + else + MX_SETBIT(sc, MX_NETCFG, MX_TXTHRESH_72BYTES); + + /* Init circular RX list. */ + if (mx_list_rx_init(sc) == ENOBUFS) { + printf("mx%d: initialization failed: no " + "memory for rx buffers\n", sc->mx_unit); + mx_stop(sc); + (void)splx(s); + return; + } + + /* + * Init tx descriptors. + */ + mx_list_tx_init(sc); + + /* + * Load the address of the RX list. + */ + CSR_WRITE_4(sc, MX_RXADDR, vtophys(sc->mx_cdata.mx_rx_head->mx_ptr)); + + /* + * Load the RX/multicast filter. + */ + mx_setfilt(sc); + + /* + * Enable interrupts. + */ + CSR_WRITE_4(sc, MX_IMR, MX_INTRS); + CSR_WRITE_4(sc, MX_ISR, 0xFFFFFFFF); + + /* Enable receiver and transmitter. */ + MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_TX_ON|MX_NETCFG_RX_ON); + CSR_WRITE_4(sc, MX_RXSTART, 0xFFFFFFFF); + + /* Restore state of BMCR */ + if (sc->mx_pinfo != NULL) + mx_phy_writereg(sc, PHY_BMCR, phy_bmcr); + + ifp->if_flags |= IFF_RUNNING; + ifp->if_flags &= ~IFF_OACTIVE; + + (void)splx(s); + + return; +} + +/* + * Set media options. + */ +static int mx_ifmedia_upd(ifp) + struct ifnet *ifp; +{ + struct mx_softc *sc; + struct ifmedia *ifm; + + sc = ifp->if_softc; + ifm = &sc->ifmedia; + + if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) + return(EINVAL); + + if (sc->mx_type == MX_TYPE_98713 && sc->mx_pinfo != NULL) { + if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) + mx_autoneg_mii(sc, MX_FLAG_SCHEDDELAY, 1); + else + mx_setmode_mii(sc, ifm->ifm_media); + } else { + if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) + mx_autoneg(sc, MX_FLAG_SCHEDDELAY, 1); + else + mx_setmode(sc, ifm->ifm_media, 1); + } + + return(0); +} + +/* + * Report current media status. + */ +static void mx_ifmedia_sts(ifp, ifmr) + struct ifnet *ifp; + struct ifmediareq *ifmr; +{ + struct mx_softc *sc; + u_int16_t advert = 0, ability = 0; + u_int32_t media = 0; + + sc = ifp->if_softc; + + ifmr->ifm_active = IFM_ETHER; + + if (sc->mx_type != MX_TYPE_98713 || sc->mx_pinfo == NULL) { + media = CSR_READ_4(sc, MX_NETCFG); + if (media & MX_NETCFG_PORTSEL) + ifmr->ifm_active = IFM_ETHER|IFM_100_TX; + else + ifmr->ifm_active = IFM_ETHER|IFM_10_T; + if (media & MX_NETCFG_FULLDUPLEX) + ifmr->ifm_active |= IFM_FDX; + else + ifmr->ifm_active |= IFM_HDX; + return; + } + + if (!(mx_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { + if (mx_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) + ifmr->ifm_active = IFM_ETHER|IFM_100_TX; + else + ifmr->ifm_active = IFM_ETHER|IFM_10_T; + if (mx_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) + ifmr->ifm_active |= IFM_FDX; + else + ifmr->ifm_active |= IFM_HDX; + return; + } + + ability = mx_phy_readreg(sc, PHY_LPAR); + advert = mx_phy_readreg(sc, PHY_ANAR); + if (advert & PHY_ANAR_100BT4 && + ability & PHY_ANAR_100BT4) { + ifmr->ifm_active = IFM_ETHER|IFM_100_T4; + } else if (advert & PHY_ANAR_100BTXFULL && + ability & PHY_ANAR_100BTXFULL) { + ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX; + } else if (advert & PHY_ANAR_100BTXHALF && + ability & PHY_ANAR_100BTXHALF) { + ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX; + } else if (advert & PHY_ANAR_10BTFULL && + ability & PHY_ANAR_10BTFULL) { + ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX; + } else if (advert & PHY_ANAR_10BTHALF && + ability & PHY_ANAR_10BTHALF) { + ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX; + } + + return; +} + +static int mx_ioctl(ifp, command, data) + struct ifnet *ifp; + u_long command; + caddr_t data; +{ + struct mx_softc *sc = ifp->if_softc; + struct ifreq *ifr = (struct ifreq *) data; + int s, error = 0; + struct ifaddr *ifa = (struct ifaddr *)data; + + s = splimp(); + + if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) { + splx(s); + return error; + } + + switch(command) { + case SIOCSIFADDR: + ifp->if_flags |= IFF_UP; + switch (ifa->ifa_addr->sa_family) { +#ifdef INET + case AF_INET: + mx_init(sc); + arp_ifinit(&sc->arpcom, ifa); + break; +#endif /* INET */ + default: + mx_init(sc); + break; + } + break; + case SIOCSIFFLAGS: + if (ifp->if_flags & IFF_UP) { + mx_init(sc); + } else { + if (ifp->if_flags & IFF_RUNNING) + mx_stop(sc); + } + error = 0; + break; + case SIOCADDMULTI: + case SIOCDELMULTI: + mx_init(sc); + error = 0; + break; + case SIOCGIFMEDIA: + case SIOCSIFMEDIA: + error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); + break; + default: + error = EINVAL; + break; + } + + (void)splx(s); + + return(error); +} + +static void mx_watchdog(ifp) + struct ifnet *ifp; +{ + struct mx_softc *sc; + + sc = ifp->if_softc; + + if (sc->mx_autoneg) { + if (sc->mx_type == MX_TYPE_98713 && sc->mx_pinfo != NULL) + mx_autoneg_mii(sc, MX_FLAG_DELAYTIMEO, 1); + else + mx_autoneg(sc, MX_FLAG_DELAYTIMEO, 1); + return; + } + + ifp->if_oerrors++; + printf("mx%d: watchdog timeout\n", sc->mx_unit); + + if (sc->mx_pinfo == NULL) { + if (!(CSR_READ_4(sc, MX_10BTSTAT) & MX_TSTAT_LS10) || + !(CSR_READ_4(sc, MX_10BTSTAT) & MX_TSTAT_LS100)) + printf("mx%d: no carrier - transceiver " + "cable problem?\n", sc->mx_unit); + } else { + if (!(mx_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) + printf("mx%d: no carrier - transceiver " + "cable problem?\n", sc->mx_unit); + } + + mx_stop(sc); + mx_reset(sc); + mx_init(sc); + + if (ifp->if_snd.ifq_head != NULL) + mx_start(ifp); + + return; +} + +/* + * Stop the adapter and free any mbufs allocated to the + * RX and TX lists. + */ +static void mx_stop(sc) + struct mx_softc *sc; +{ + register int i; + struct ifnet *ifp; + + ifp = &sc->arpcom.ac_if; + ifp->if_timer = 0; + + MX_CLRBIT(sc, MX_NETCFG, (MX_NETCFG_RX_ON|MX_NETCFG_TX_ON)); + CSR_WRITE_4(sc, MX_IMR, 0x00000000); + CSR_WRITE_4(sc, MX_TXADDR, 0x00000000); + CSR_WRITE_4(sc, MX_RXADDR, 0x00000000); + + /* + * Free data in the RX lists. + */ + for (i = 0; i < MX_RX_LIST_CNT; i++) { + if (sc->mx_cdata.mx_rx_chain[i].mx_mbuf != NULL) { + m_freem(sc->mx_cdata.mx_rx_chain[i].mx_mbuf); + sc->mx_cdata.mx_rx_chain[i].mx_mbuf = NULL; + } + } + bzero((char *)&sc->mx_ldata->mx_rx_list, + sizeof(sc->mx_ldata->mx_rx_list)); + + /* + * Free the TX list buffers. + */ + for (i = 0; i < MX_TX_LIST_CNT; i++) { + if (sc->mx_cdata.mx_tx_chain[i].mx_mbuf != NULL) { + m_freem(sc->mx_cdata.mx_tx_chain[i].mx_mbuf); + sc->mx_cdata.mx_tx_chain[i].mx_mbuf = NULL; + } + } + + bzero((char *)&sc->mx_ldata->mx_tx_list, + sizeof(sc->mx_ldata->mx_tx_list)); + + ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); + + return; +} + +static int +mx_probe(parent, match, aux) + struct device *parent; + void *match, *aux; +{ + struct pci_attach_args *pa = (struct pci_attach_args *)aux; + + if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_MACRONIX) { + switch (PCI_PRODUCT(pa->pa_id)) { + case PCI_PRODUCT_MACRONIX_MX98713: + case PCI_PRODUCT_MACRONIX_MX98715: + return (1); + } + } + + return (0); +} + +static void +mx_attach(parent, self, aux) + struct device *parent, *self; + void *aux; +{ + struct mx_softc *sc = (struct mx_softc *)self; + struct pci_attach_args *pa = aux; + pci_chipset_tag_t pc = pa->pa_pc; + pci_intr_handle_t ih; + const char *intrstr = NULL; + struct ifnet *ifp = &sc->arpcom.ac_if; + bus_addr_t iobase; + bus_size_t iosize; + unsigned int round; + caddr_t roundptr; + u_int32_t command; + u_int16_t phy_sts, phy_did, phy_vid, mac_offset = 0; + int s, i, media; + struct mx_type *p = NULL; + + s = splimp(); + + sc->mx_unit = sc->sc_dev.dv_unit; + + command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); + +#ifdef MX_USEIOSPACE + if (!(command & PCI_COMMAND_IO_ENABLE)) { + printf(": failed to enable I/O ports\n"); + return; + } + if (pci_io_find(pc, pa->pa_tag, MX_PCI_LOIO, &iobase, &iosize)) { + printf(": failed to find i/o space\n"); + return; + } + if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &sc->mx_bhandle)) { + printf(": failed map i/o space\n"); + return; + } + sc->mx_btag = pa->pa_iot; +#else + if (!(command & PCI_COMMAND_MEM_ENABLE)) { + printf(": failed to enable memory mapping\n"); + return; + } + if (pci_mem_find(pc, pa->pa_tag, MX_PCI_LOMEM, &iobase, &iosize)) { + printf(": failed to find memory space\n"); + return; + } + if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->mx_bhandle)) { + printf(": failed map memory space\n"); + return; + } + sc->mx_btag = pa->pa_memt; +#endif + + if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, + pa->pa_intrline, &ih)) { + printf(": couldn't map interrupt\n"); + return; + } + intrstr = pci_intr_string(pc, ih); + sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, mx_intr, sc, + self->dv_xname); + if (sc->sc_ih == NULL) { + printf(": could not establish interrupt"); + if (intrstr != NULL) + printf(" at %s", intrstr); + printf("\n"); + return; + } + printf(": %s", intrstr); + + if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_MACRONIX) { + if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_MACRONIX_MX98713) { + if (PCI_REVISION(pa->pa_class) < MX_REVISION_98713A) + sc->mx_type = MX_TYPE_98713; + else + sc->mx_type = MX_TYPE_98713A; + } + if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_MACRONIX_MX98715) { + sc->mx_type = MX_TYPE_987x5; + } + } + + mx_reset(sc); + + mx_read_eeprom(sc, (caddr_t)&mac_offset, + (MX_EE_NODEADDR_OFFSET / 2), 1, 0); + mx_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, + (mac_offset / 2), 3, 0); + printf(" address %s\n", ether_sprintf(sc->arpcom.ac_enaddr)); + + sc->mx_ldata_ptr = malloc(sizeof(struct mx_list_data) + 8, + M_DEVBUF, M_NOWAIT); + if (sc->mx_ldata_ptr == NULL) { + printf("%s: no memory for list buffers\n", sc->sc_dev.dv_xname); + return; + } + sc->mx_ldata = (struct mx_list_data *)sc->mx_ldata_ptr; + round = (unsigned int)sc->mx_ldata_ptr & 0xf; + roundptr = sc->mx_ldata_ptr; + for (i = 0; i < 8; i++) { + if (round % 8) { + round++; + roundptr++; + } + else + break; + } + sc->mx_ldata = (struct mx_list_data *)roundptr; + bzero(sc->mx_ldata, sizeof(struct mx_list_data)); + + ifp = &sc->arpcom.ac_if; + ifp->if_softc = sc; + ifp->if_mtu = ETHERMTU; + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_ioctl = mx_ioctl; + ifp->if_output = ether_output; + ifp->if_start = mx_start; + ifp->if_watchdog = mx_watchdog; + ifp->if_baudrate = 10000000; + bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); + + if (sc->mx_type == MX_TYPE_98713) { + for (i = MX_PHYADDR_MIN; i < MX_PHYADDR_MAX + 1; i++) { + sc->mx_phy_addr = i; + mx_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); + while (mx_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); + if ((phy_sts = mx_phy_readreg(sc, PHY_BMSR))) + break; + } + if (phy_sts) { + phy_vid = mx_phy_readreg(sc, PHY_VENID); + phy_did = mx_phy_readreg(sc, PHY_DEVID); + p = mx_phys; + while (p->mx_vid) { + if (phy_vid == p->mx_vid && + (phy_did|0xf) == p->mx_did) { + sc->mx_pinfo = p; + break; + } + p++; + } + if (sc->mx_pinfo == NULL) + sc->mx_pinfo = &mx_phys[PHY_UNKNOWN]; + } + else { + printf("%s: MII without any phy!\n", + sc->sc_dev.dv_xname); + return; + } + } + + ifmedia_init(&sc->ifmedia, 0, mx_ifmedia_upd, mx_ifmedia_sts); + if (sc->mx_type == MX_TYPE_98713 && sc->mx_pinfo != NULL) { + mx_getmode_mii(sc); + mx_autoneg_mii(sc, MX_FLAG_FORCEDELAY, 1); + } else { + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); + mx_autoneg(sc, MX_FLAG_FORCEDELAY, 1); + } + media = sc->ifmedia.ifm_media; + mx_stop(sc); + ifmedia_set(&sc->ifmedia, media); + + if_attach(ifp); + ether_ifattach(ifp); +#if NBPFILTER > 0 + bpfattach(&sc->arpcom.ac_if.if_bpf, ifp, + DLT_EN10MB, sizeof(struct ether_header)); +#endif + shutdownhook_establish(mx_shutdown, sc); + splx(s); +} + +static void +mx_shutdown(v) + void *v; +{ + struct mx_softc *sc = (struct mx_softc *)v; + + mx_stop(sc); +} + +struct cfattach mx_ca = { + sizeof(struct mx_softc), mx_probe, mx_attach +}; + +struct cfdriver mx_cd = { + 0, "mx", DV_IFNET +}; diff --git a/sys/dev/pci/if_mxreg.h b/sys/dev/pci/if_mxreg.h new file mode 100644 index 00000000000..4da5c64c52d --- /dev/null +++ b/sys/dev/pci/if_mxreg.h @@ -0,0 +1,705 @@ +/* $OpenBSD: if_mxreg.h,v 1.1 1999/01/08 04:43:18 jason Exp $ */ + +/* + * Copyright (c) 1997, 1998 + * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD: if_mxreg.h,v 1.2 1998/12/04 21:48:12 wpaul Exp $ + */ + +/* + * Macronix register definitions. + */ + +#define MX_BUSCTL 0x00 /* bus control */ +#define MX_TXSTART 0x08 /* tx start demand */ +#define MX_RXSTART 0x10 /* rx start demand */ +#define MX_RXADDR 0x18 /* rx descriptor list start addr */ +#define MX_TXADDR 0x20 /* tx descriptor list start addr */ +#define MX_ISR 0x28 /* interrupt status register */ +#define MX_NETCFG 0x30 /* network config register */ +#define MX_IMR 0x38 /* interrupt mask */ +#define MX_FRAMESDISCARDED 0x40 /* # of discarded frames */ +#define MX_SIO 0x48 /* MII and ROM/EEPROM access */ +#define MX_RESERVED 0x50 +#define MX_TIMER 0x58 /* general timer */ +#define MX_10BTSTAT 0x60 +#define MX_SIARESET 0x68 +#define MX_10BTCTRL 0x70 +#define MX_WATCHDOG 0x78 +#define MX_MAGICPACKET 0x80 +#define MX_NWAYSTAT 0xA0 + +/* + * These are magic values that must be written into CSR16 + * (MX_MAGICPACKET) in order to put the chip into proper + * operating mode. The magic numbers are documented in the + * Macronix 98715 application notes. + */ +#define MX_MAGIC_98713 0x0F370000 +#define MX_MAGIC_98713A 0x0B3C0000 +#define MX_MAGIC_98715 0x0B3C0000 +#define MX_MAGIC_98725 0x0B3C0000 + +#define MX_REVISION_98713 0x00 +#define MX_REVISION_98713A 0x10 +#define MX_REVISION_98715 0x20 +#define MX_REVISION_98725 0x30 + +/* + * As far as the driver is concerned, there are two 'types' of + * chips to be concerned with. One is a 98713 with an external + * PHY on the MII. The other covers pretty much everything else, + * since all the other Macronix chips have built-in transceivers. + * This type setting governs what which mode selection routines + * we use (MII or built-in). It also govers which of the 'magic' + * numbers we write into CSR16. + */ +#define MX_TYPE_98713 0x1 +#define MX_TYPE_98713A 0x2 +#define MX_TYPE_987x5 0x3 + +/* + * Bus control bits. + */ +#define MX_BUSCTL_RESET 0x00000001 +#define MX_BUSCTL_ARBITRATION 0x00000002 +#define MX_BUSCTL_SKIPLEN 0x0000007C +#define MX_BUSCTL_BUF_BIGENDIAN 0x00000080 +#define MX_BUSCTL_BURSTLEN 0x00003F00 +#define MX_BUSCTL_CACHEALIGN 0x0000C000 +#define MX_BUSCTL_XMITPOLL 0x00060000 + +#define MX_SKIPLEN_1LONG 0x00000004 +#define MX_SKIPLEN_2LONG 0x00000008 +#define MX_SKIPLEN_3LONG 0x00000010 +#define MX_SKIPLEN_4LONG 0x00000020 +#define MX_SKIPLEN_5LONG 0x00000040 + +#define MX_CACHEALIGN_8LONG 0x00004000 +#define MX_CACHEALIGN_16LONG 0x00008000 +#define MX_CACHEALIGN_32LONG 0x0000C000 + +#define MX_BURSTLEN_USECA 0x00000000 +#define MX_BURSTLEN_1LONG 0x00000100 +#define MX_BURSTLEN_2LONG 0x00000200 +#define MX_BURSTLEN_4LONG 0x00000400 +#define MX_BURSTLEN_8LONG 0x00000800 +#define MX_BURSTLEN_16LONG 0x00001000 +#define MX_BURSTLEN_32LONG 0x00002000 + +#define MX_TXPOLL_OFF 0x00000000 +#define MX_TXPOLL_200U 0x00020000 +#define MX_TXPOLL_800U 0x00040000 +#define MX_TXPOLL_1600U 0x00060000 + +#define MX_BUSCTL_CONFIG (MX_BUSCTL_ARBITRATION|MX_CACHEALIGN_8LONG| \ + MX_BURSTLEN_8LONG) + +/* + * Interrupt status bits. + */ +#define MX_ISR_TX_OK 0x00000001 +#define MX_ISR_TX_IDLE 0x00000002 +#define MX_ISR_TX_NOBUF 0x00000004 +#define MX_ISR_TX_JABBERTIMEO 0x00000008 +#define MX_ISR_LINKGOOD 0x00000010 +#define MX_ISR_TX_UNDERRUN 0x00000020 +#define MX_ISR_RX_OK 0x00000040 +#define MX_ISR_RX_NOBUF 0x00000080 +#define MX_ISR_RX_READ 0x00000100 +#define MX_ISR_RX_WATDOGTIMEO 0x00000200 +#define MX_ISR_TX_EARLY 0x00000400 +#define MX_ISR_TIMER_EXPIRED 0x00000800 +#define MX_ISR_LINKFAIL 0x00001000 +#define MX_ISR_BUS_ERR 0x00002000 +#define MX_ISR_RX_EARLY 0x00004000 +#define MX_ISR_ABNORMAL 0x00008000 +#define MX_ISR_NORMAL 0x00010000 +#define MX_ISR_RX_STATE 0x000E0000 +#define MX_ISR_TX_STATE 0x00700000 +#define MX_ISR_BUSERRTYPE 0x03800000 +#define MX_ISR_100MBPSLINK 0x08000000 +#define MX_ISR_MAGICKPACK 0x10000000 + +#define MX_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */ +#define MX_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */ +#define MX_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */ +#define MX_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */ +#define MX_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */ +#define MX_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */ +#define MX_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */ +#define MX_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */ + +#define MX_TXSTATE_RESET 0x00000000 /* 000 - reset */ +#define MX_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */ +#define MX_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */ +#define MX_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */ +#define MX_TXSTATE_RSVD 0x00400000 /* 100 - reserved */ +#define MX_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */ +#define MX_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */ +#define MX_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */ + +/* + * Network config bits. + */ +#define MX_NETCFG_RX_HASHPERF 0x00000001 +#define MX_NETCFG_RX_ON 0x00000002 +#define MX_NETCFG_RX_HASHONLY 0x00000004 +#define MX_NETCFG_RX_BADFRAMES 0x00000008 +#define MX_NETCFG_RX_INVFILT 0x00000010 +#define MX_NETCFG_BACKOFFCNT 0x00000020 +#define MX_NETCFG_RX_PROMISC 0x00000040 +#define MX_NETCFG_RX_ALLMULTI 0x00000080 +#define MX_NETCFG_FULLDUPLEX 0x00000200 +#define MX_NETCFG_LOOPBACK 0x00000C00 +#define MX_NETCFG_FORCECOLL 0x00001000 +#define MX_NETCFG_TX_ON 0x00002000 +#define MX_NETCFG_TX_THRESH 0x0000C000 +#define MX_NETCFG_TX_BACKOFF 0x00020000 +#define MX_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */ +#define MX_NETCFG_HEARTBEAT 0x00080000 +#define MX_NETCFG_STORENFWD 0x00200000 +#define MX_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */ +#define MX_NETCFG_PCS 0x00800000 +#define MX_NETCFG_SCRAMBLER 0x01000000 +#define MX_NETCFG_NO_RXCRC 0x02000000 + +#define MX_OPMODE_NORM 0x00000000 +#define MX_OPMODE_INTLOOP 0x00000400 +#define MX_OPMODE_EXTLOOP 0x00000800 + +#define MX_TXTHRESH_72BYTES 0x00000000 +#define MX_TXTHRESH_96BYTES 0x00004000 +#define MX_TXTHRESH_128BYTES 0x00008000 +#define MX_TXTHRESH_160BYTES 0x0000C000 + + +/* + * Interrupt mask bits. + */ +#define MX_IMR_TX_OK 0x00000001 +#define MX_IMR_TX_IDLE 0x00000002 +#define MX_IMR_TX_NOBUF 0x00000004 +#define MX_IMR_TX_JABBERTIMEO 0x00000008 +#define MX_IMR_LINKGOOD 0x00000010 +#define MX_IMR_TX_UNDERRUN 0x00000020 +#define MX_IMR_RX_OK 0x00000040 +#define MX_IMR_RX_NOBUF 0x00000080 +#define MX_IMR_RX_READ 0x00000100 +#define MX_IMR_RX_WATDOGTIMEO 0x00000200 +#define MX_IMR_TX_EARLY 0x00000400 +#define MX_IMR_TIMER_EXPIRED 0x00000800 +#define MX_IMR_LINKFAIL 0x00001000 +#define MX_IMR_BUS_ERR 0x00002000 +#define MX_IMR_RX_EARLY 0x00004000 +#define MX_IMR_ABNORMAL 0x00008000 +#define MX_IMR_NORMAL 0x00010000 +#define MX_IMR_100MBPSLINK 0x08000000 +#define MX_IMR_MAGICKPACK 0x10000000 + +#define MX_INTRS \ + (MX_IMR_RX_OK|MX_IMR_TX_OK|MX_IMR_RX_NOBUF|MX_IMR_RX_WATDOGTIMEO|\ + MX_IMR_TX_NOBUF|MX_IMR_TX_UNDERRUN|MX_IMR_BUS_ERR| \ + MX_IMR_ABNORMAL|MX_IMR_NORMAL/*|MX_IMR_TX_EARLY*/) +/* + * Serial I/O (EEPROM/ROM) bits. + */ +#define MX_SIO_EE_CS 0x00000001 /* EEPROM chip select */ +#define MX_SIO_EE_CLK 0x00000002 /* EEPROM clock */ +#define MX_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */ +#define MX_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */ +#define MX_SIO_ROMDATA4 0x00000010 +#define MX_SIO_ROMDATA5 0x00000020 +#define MX_SIO_ROMDATA6 0x00000040 +#define MX_SIO_ROMDATA7 0x00000080 +#define MX_SIO_EESEL 0x00000800 +#define MX_SIO_ROMSEL 0x00001000 +#define MX_SIO_ROMCTL_WRITE 0x00002000 +#define MX_SIO_ROMCTL_READ 0x00004000 +#define MX_SIO_MII_CLK 0x00010000 /* MDIO clock */ +#define MX_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */ +#define MX_SIO_MII_DIR 0x00040000 /* MDIO dir */ +#define MX_SIO_MII_DATAIN 0x00080000 /* MDIO data in */ + +#define MX_EECMD_WRITE 0x140 +#define MX_EECMD_READ 0x180 +#define MX_EECMD_ERASE 0x1c0 + +#define MX_EE_NODEADDR_OFFSET 0x70 +#define MX_EE_NODEADDR 10 + +/* + * General purpose timer register + */ +#define MX_TIMER_VALUE 0x0000FFFF +#define MX_TIMER_CONTINUUS 0x00010000 + +/* + * 10baseT status register + */ +#define MX_TSTAT_LS100 0x00000002 /* link status of 100baseTX */ +#define MX_TSTAT_LS10 0x00000004 /* link status of 10baseT */ +#define MX_TSTAT_AUTOPOLARITY 0x00000008 +#define MX_TSTAT_REMFAULT 0x00000800 +#define MX_TSTAT_ANEGSTAT 0x00007000 +#define MX_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */ +#define MX_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */ + +#define MX_ASTAT_DISABLE 0x00000000 +#define MX_ASTAT_TXDISABLE 0x00001000 +#define MX_ASTAT_ABDETECT 0x00002000 +#define MX_ASTAT_ACKDETECT 0x00003000 +#define MX_ASTAT_CMPACKDETECT 0x00004000 +#define MX_ASTAT_AUTONEGCMP 0x00005000 +#define MX_ASTAT_LINKCHECK 0x00006000 + +/* + * PHY reset register + */ +#define MX_SIA_RESET_NWAY 0x00000001 +#define MX_SIA_RESET_100TX 0x00000002 + +/* + * 10baseT control register + */ +#define MX_TCTL_LOOPBACK 0x00000002 +#define MX_TCTL_POWERDOWN 0x00000004 +#define MX_TCTL_HALFDUPLEX 0x00000040 +#define MX_TCTL_AUTONEGENBL 0x00000080 +#define MX_TCTL_RX_SQUELCH 0x00000100 +#define MX_TCTL_LINKTEST 0x00001000 +#define MX_TCTL_100BTXHALF 0x00010000 +#define MX_TCTL_100BTXFULL 0x00020000 +#define MX_TCTL_100BT4 0x00040000 + +/* + * Watchdog timer register + */ +#define MX_WDOG_JABBERDIS 0x00000001 +#define MX_WDOG_HOSTUNJAB 0x00000002 +#define MX_WDOG_JABBERCLK 0x00000004 +#define MX_WDOG_RXWDOGDIS 0x00000010 +#define MX_WDOG_RXWDOGCLK 0x00000020 +#define MX_WDOG_MUSTBEZERO 0x00000100 + +/* + * Magic packet register + */ +#define MX_MPACK_DISABLE 0x00400000 + +/* + * NWAY status register. + */ +#define MX_NWAY_10BTHALF 0x08000000 +#define MX_NWAY_10BTFULL 0x10000000 +#define MX_NWAY_100BTHALF 0x20000000 +#define MX_NWAY_100BTFULL 0x40000000 +#define MX_NWAY_100BT4 0x80000000 + +/* + * Size of a setup frame. + */ +#define MX_SFRAME_LEN 192 + +/* + * Macronix TX/RX list structure. + */ + +struct mx_desc { + volatile u_int32_t mx_status; + volatile u_int32_t mx_ctl; + volatile u_int32_t mx_ptr1; + volatile u_int32_t mx_ptr2; +}; + +#define mx_data mx_ptr1 +#define mx_next mx_ptr2 + +#define MX_RXSTAT_FIFOOFLOW 0x00000001 +#define MX_RXSTAT_CRCERR 0x00000002 +#define MX_RXSTAT_DRIBBLE 0x00000004 +#define MX_RXSTAT_WATCHDOG 0x00000010 +#define MX_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */ +#define MX_RXSTAT_COLLSEEN 0x00000040 +#define MX_RXSTAT_GIANT 0x00000080 +#define MX_RXSTAT_LASTFRAG 0x00000100 +#define MX_RXSTAT_FIRSTFRAG 0x00000200 +#define MX_RXSTAT_MULTICAST 0x00000400 +#define MX_RXSTAT_RUNT 0x00000800 +#define MX_RXSTAT_RXTYPE 0x00003000 +#define MX_RXSTAT_RXERR 0x00008000 +#define MX_RXSTAT_RXLEN 0x3FFF0000 +#define MX_RXSTAT_OWN 0x80000000 + +#define MX_RXBYTES(x) ((x & MX_RXSTAT_RXLEN) >> 16) +#define MX_RXSTAT (MX_RXSTAT_FIRSTFRAG|MX_RXSTAT_LASTFRAG|MX_RXSTAT_OWN) + +#define MX_RXCTL_BUFLEN1 0x00000FFF +#define MX_RXCTL_BUFLEN2 0x00FFF000 +#define MX_RXCTL_RLINK 0x01000000 +#define MX_RXCTL_RLAST 0x02000000 + +#define MX_TXSTAT_DEFER 0x00000001 +#define MX_TXSTAT_UNDERRUN 0x00000002 +#define MX_TXSTAT_LINKFAIl 0x00000003 +#define MX_TXSTAT_COLLCNT 0x00000078 +#define MX_TXSTAT_SQE 0x00000080 +#define MX_TXSTAT_EXCESSCOLL 0x00000100 +#define MX_TXSTAT_LATECOLL 0x00000200 +#define MX_TXSTAT_NOCARRIER 0x00000400 +#define MX_TXSTAT_CARRLOST 0x00000800 +#define MX_TXSTAT_JABTIMEO 0x00004000 +#define MX_TXSTAT_ERRSUM 0x00008000 +#define MX_TXSTAT_OWN 0x80000000 + +#define MX_TXCTL_BUFLEN1 0x000007FF +#define MX_TXCTL_BUFLEN2 0x003FF800 +#define MX_TXCTL_FILTTYPE0 0x00400000 +#define MX_TXCTL_PAD 0x00800000 +#define MX_TXCTL_TLINK 0x01000000 +#define MX_TXCTL_TLAST 0x02000000 +#define MX_TXCTL_NOCRC 0x04000000 +#define MX_TXCTL_SETUP 0x08000000 +#define MX_TXCTL_FILTTYPE1 0x10000000 +#define MX_TXCTL_FIRSTFRAG 0x20000000 +#define MX_TXCTL_LASTFRAG 0x40000000 +#define MX_TXCTL_FINT 0x80000000 + +#define MX_FILTER_PERFECT 0x00000000 +#define MX_FILTER_HASHPERF 0x00400000 +#define MX_FILTER_INVERSE 0x10000000 +#define MX_FILTER_HASHONLY 0x10400000 + +#define MX_MAXFRAGS 16 +#define MX_RX_LIST_CNT 64 +#define MX_TX_LIST_CNT 64 +#define MX_MIN_FRAMELEN 60 + +/* + * A tx 'super descriptor' is actually 16 regular descriptors + * back to back. + */ +struct mx_txdesc { + volatile struct mx_desc mx_frag[MX_MAXFRAGS]; +}; + +#define MX_TXNEXT(x) x->mx_ptr->mx_frag[x->mx_lastdesc].mx_next +#define MX_TXSTATUS(x) x->mx_ptr->mx_frag[x->mx_lastdesc].mx_status +#define MX_TXCTL(x) x->mx_ptr->mx_frag[x->mx_lastdesc].mx_ctl +#define MX_TXDATA(x) x->mx_ptr->mx_frag[x->mx_lastdesc].mx_data + +#define MX_TXOWN(x) x->mx_ptr->mx_frag[0].mx_status + +#define MX_UNSENT 0x12341234 + +struct mx_list_data { + volatile struct mx_desc mx_rx_list[MX_RX_LIST_CNT]; + volatile struct mx_txdesc mx_tx_list[MX_TX_LIST_CNT]; +}; + +struct mx_chain { + volatile struct mx_txdesc *mx_ptr; + struct mbuf *mx_mbuf; + struct mx_chain *mx_nextdesc; + u_int8_t mx_lastdesc; +}; + +struct mx_chain_onefrag { + volatile struct mx_desc *mx_ptr; + struct mbuf *mx_mbuf; + struct mx_chain_onefrag *mx_nextdesc; +}; + +struct mx_chain_data { + struct mx_desc mx_sframe; + u_int32_t mx_sbuf[MX_SFRAME_LEN/sizeof(u_int32_t)]; + u_int8_t mx_pad[MX_MIN_FRAMELEN]; + struct mx_chain_onefrag mx_rx_chain[MX_RX_LIST_CNT]; + struct mx_chain mx_tx_chain[MX_TX_LIST_CNT]; + + struct mx_chain_onefrag *mx_rx_head; + + struct mx_chain *mx_tx_head; + struct mx_chain *mx_tx_tail; + struct mx_chain *mx_tx_free; +}; + +struct mx_type { + u_int16_t mx_vid; + u_int16_t mx_did; + char *mx_name; +}; + +struct mx_mii_frame { + u_int8_t mii_stdelim; + u_int8_t mii_opcode; + u_int8_t mii_phyaddr; + u_int8_t mii_regaddr; + u_int8_t mii_turnaround; + u_int16_t mii_data; +}; + +/* + * MII constants + */ +#define MX_MII_STARTDELIM 0x01 +#define MX_MII_READOP 0x02 +#define MX_MII_WRITEOP 0x01 +#define MX_MII_TURNAROUND 0x02 + +#define MX_FLAG_FORCEDELAY 1 +#define MX_FLAG_SCHEDDELAY 2 +#define MX_FLAG_DELAYTIMEO 3 + +struct mx_softc { + struct device sc_dev; /* generic device structure */ + void * sc_ih; /* interrupt handler cookie */ + struct arpcom arpcom; /* interface info */ + struct ifmedia ifmedia; /* media info */ + bus_space_handle_t mx_bhandle; /* bus space handle */ + bus_space_tag_t mx_btag; /* bus space tag */ + struct mx_type *mx_info; /* Macronix adapter info */ + struct mx_type *mx_pinfo; /* phy info */ + u_int8_t mx_unit; /* interface number */ + u_int8_t mx_type; + u_int8_t mx_phy_addr; /* PHY address */ + u_int8_t mx_tx_pend; /* TX pending */ + u_int8_t mx_want_auto; + u_int8_t mx_autoneg; + u_int8_t mx_singlebuf; + caddr_t mx_ldata_ptr; + struct mx_list_data *mx_ldata; + struct mx_chain_data mx_cdata; +}; + +/* + * register space access macros + */ +#define CSR_WRITE_4(sc, reg, val) \ + bus_space_write_4(sc->mx_btag, sc->mx_bhandle, reg, val) +#define CSR_WRITE_2(sc, reg, val) \ + bus_space_write_2(sc->mx_btag, sc->mx_bbhandle, reg, val) +#define CSR_WRITE_1(sc, reg, val) \ + bus_space_write_1(sc->mx_btag, sc->mx_bhandle, reg, val) + +#define CSR_READ_4(sc, reg) \ + bus_space_read_4(sc->mx_btag, sc->mx_bhandle, reg) +#define CSR_READ_2(sc, reg) \ + bus_space_read_2(sc->mx_btag, sc->mx_bhandle, reg) +#define CSR_READ_1(sc, reg) \ + bus_space_read_1(sc->mx_btag, sc->mx_bhandle, reg) + +#define MX_TIMEOUT 1000 + +/* + * General constants that are fun to know. + * + * Macronix PCI vendor ID + */ +#define MX_VENDORID 0x10D9 + +/* + * Macronix PMAC device IDs. + */ +#define MX_DEVICEID_98713 0x0512 +#define MX_DEVICEID_987x5 0x0531 + +/* + * Texas Instruments PHY identifiers + */ +#define TI_PHY_VENDORID 0x4000 +#define TI_PHY_10BT 0x501F +#define TI_PHY_100VGPMI 0x502F + +/* + * These ID values are for the NS DP83840A 10/100 PHY + */ +#define NS_PHY_VENDORID 0x2000 +#define NS_PHY_83840A 0x5C0F + +/* + * Level 1 10/100 PHY + */ +#define LEVEL1_PHY_VENDORID 0x7810 +#define LEVEL1_PHY_LXT970 0x000F + +/* + * Intel 82555 10/100 PHY + */ +#define INTEL_PHY_VENDORID 0x0A28 +#define INTEL_PHY_82555 0x015F + +/* + * SEEQ 80220 10/100 PHY + */ +#define SEEQ_PHY_VENDORID 0x0016 +#define SEEQ_PHY_80220 0xF83F + + +/* + * PCI low memory base and low I/O base register, and + * other PCI registers. + */ + +#define MX_PCI_VENDOR_ID 0x00 +#define MX_PCI_DEVICE_ID 0x02 +#define MX_PCI_COMMAND 0x04 +#define MX_PCI_STATUS 0x06 +#define MX_PCI_REVID 0x08 +#define MX_PCI_CLASSCODE 0x09 +#define MX_PCI_LATENCY_TIMER 0x0D +#define MX_PCI_HEADER_TYPE 0x0E +#define MX_PCI_LOIO 0x10 +#define MX_PCI_LOMEM 0x14 +#define MX_PCI_BIOSROM 0x30 +#define MX_PCI_INTLINE 0x3C +#define MX_PCI_INTPIN 0x3D +#define MX_PCI_MINGNT 0x3E +#define MX_PCI_MINLAT 0x0F +#define MX_PCI_RESETOPT 0x48 +#define MX_PCI_EEPROM_DATA 0x4C + +/* power management registers */ +#define MX_PCI_CAPID 0x44 /* 8 bits */ +#define MX_PCI_NEXTPTR 0x45 /* 8 bits */ +#define MX_PCI_PWRMGMTCAP 0x46 /* 16 bits */ +#define MX_PCI_PWRMGMTCTRL 0x48 /* 16 bits */ + +#define MX_PSTATE_MASK 0x0003 +#define MX_PSTATE_D0 0x0000 +#define MX_PSTATE_D1 0x0001 +#define MX_PSTATE_D2 0x0002 +#define MX_PSTATE_D3 0x0003 +#define MX_PME_EN 0x0010 +#define MX_PME_STATUS 0x8000 + +#define PHY_UNKNOWN 6 + +#define MX_PHYADDR_MIN 0x00 +#define MX_PHYADDR_MAX 0x1F + +#define PHY_BMCR 0x00 +#define PHY_BMSR 0x01 +#define PHY_VENID 0x02 +#define PHY_DEVID 0x03 +#define PHY_ANAR 0x04 +#define PHY_LPAR 0x05 +#define PHY_ANEXP 0x06 + +#define PHY_ANAR_NEXTPAGE 0x8000 +#define PHY_ANAR_RSVD0 0x4000 +#define PHY_ANAR_TLRFLT 0x2000 +#define PHY_ANAR_RSVD1 0x1000 +#define PHY_ANAR_RSVD2 0x0800 +#define PHY_ANAR_RSVD3 0x0400 +#define PHY_ANAR_100BT4 0x0200 +#define PHY_ANAR_100BTXFULL 0x0100 +#define PHY_ANAR_100BTXHALF 0x0080 +#define PHY_ANAR_10BTFULL 0x0040 +#define PHY_ANAR_10BTHALF 0x0020 +#define PHY_ANAR_PROTO4 0x0010 +#define PHY_ANAR_PROTO3 0x0008 +#define PHY_ANAR_PROTO2 0x0004 +#define PHY_ANAR_PROTO1 0x0002 +#define PHY_ANAR_PROTO0 0x0001 + +/* + * These are the register definitions for the PHY (physical layer + * interface chip). + */ +/* + * PHY BMCR Basic Mode Control Register + */ +#define PHY_BMCR_RESET 0x8000 +#define PHY_BMCR_LOOPBK 0x4000 +#define PHY_BMCR_SPEEDSEL 0x2000 +#define PHY_BMCR_AUTONEGENBL 0x1000 +#define PHY_BMCR_RSVD0 0x0800 /* write as zero */ +#define PHY_BMCR_ISOLATE 0x0400 +#define PHY_BMCR_AUTONEGRSTR 0x0200 +#define PHY_BMCR_DUPLEX 0x0100 +#define PHY_BMCR_COLLTEST 0x0080 +#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */ +#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */ +#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */ +#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */ +#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */ +#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */ +#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */ +/* + * RESET: 1 == software reset, 0 == normal operation + * Resets status and control registers to default values. + * Relatches all hardware config values. + * + * LOOPBK: 1 == loopback operation enabled, 0 == normal operation + * + * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s + * Link speed is selected byt his bit or if auto-negotiation if bit + * 12 (AUTONEGENBL) is set (in which case the value of this register + * is ignored). + * + * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled + * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13 + * determine speed and mode. Should be cleared and then set if PHY configured + * for no autoneg on startup. + * + * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation + * + * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation + * + * DUPLEX: 1 == full duplex mode, 0 == half duplex mode + * + * COLLTEST: 1 == collision test enabled, 0 == normal operation + */ + +/* + * PHY, BMSR Basic Mode Status Register + */ +#define PHY_BMSR_100BT4 0x8000 +#define PHY_BMSR_100BTXFULL 0x4000 +#define PHY_BMSR_100BTXHALF 0x2000 +#define PHY_BMSR_10BTFULL 0x1000 +#define PHY_BMSR_10BTHALF 0x0800 +#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */ +#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */ +#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */ +#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ +#define PHY_BMSR_MFPRESUP 0x0040 +#define PHY_BMSR_AUTONEGCOMP 0x0020 +#define PHY_BMSR_REMFAULT 0x0010 +#define PHY_BMSR_CANAUTONEG 0x0008 +#define PHY_BMSR_LINKSTAT 0x0004 +#define PHY_BMSR_JABBER 0x0002 +#define PHY_BMSR_EXTENDED 0x0001 + +#ifndef ETHER_CRC_LEN +#define ETHER_CRC_LEN 4 +#endif |