diff options
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/dev/pci/files.pci | 9 | ||||
| -rw-r--r-- | sys/dev/pci/if_nx.c | 2161 | ||||
| -rw-r--r-- | sys/dev/pci/if_nxreg.h | 782 |
3 files changed, 1 insertions, 2951 deletions
diff --git a/sys/dev/pci/files.pci b/sys/dev/pci/files.pci index 77be9051b0c..5861aa98398 100644 --- a/sys/dev/pci/files.pci +++ b/sys/dev/pci/files.pci @@ -1,4 +1,4 @@ -# $OpenBSD: files.pci,v 1.240 2007/08/01 13:09:03 mk Exp $ +# $OpenBSD: files.pci,v 1.241 2007/08/14 18:54:39 reyk Exp $ # $NetBSD: files.pci,v 1.20 1996/09/24 17:47:15 christos Exp $ # # Config file and device description for machine-independent PCI code. @@ -351,13 +351,6 @@ device xge: ether, ifnet, ifmedia attach xge at pci file dev/pci/if_xge.c xge -# NetXen NX203x 10 Gigabit Ethernet -device nxb {} -attach nxb at pci -device nx: ether, ifnet, mii, ifmedia, firmload -attach nx at nxb -file dev/pci/if_nx.c nxb | nx - # Tehuti Networks 10Gb Ethernet device thtc {} attach thtc at pci diff --git a/sys/dev/pci/if_nx.c b/sys/dev/pci/if_nx.c deleted file mode 100644 index b914eb43150..00000000000 --- a/sys/dev/pci/if_nx.c +++ /dev/null @@ -1,2161 +0,0 @@ -/* $OpenBSD: if_nx.c,v 1.50 2007/05/28 19:44:15 reyk Exp $ */ - -/* - * Copyright (c) 2007 Reyk Floeter <reyk@openbsd.org> - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/* - * Driver for the NetXen NX2031/NX2035 10Gb and Gigabit Ethernet chipsets, - * see http://www.netxen.com/. - * - * This driver was made possible because NetXen Inc. provided hardware - * and documentation. Thanks! - */ - -#include "bpfilter.h" - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/sockio.h> -#include <sys/mbuf.h> -#include <sys/kernel.h> -#include <sys/socket.h> -#include <sys/malloc.h> -#include <sys/timeout.h> -#include <sys/proc.h> -#include <sys/device.h> -#include <sys/sensors.h> - -#include <machine/bus.h> -#include <machine/intr.h> - -#include <net/if.h> -#include <net/if_dl.h> -#include <net/if_media.h> -#include <net/if_types.h> - -#if NBPFILTER > 0 -#include <net/bpf.h> -#endif - -#ifdef INET -#include <netinet/in.h> -#include <netinet/if_ether.h> -#endif - -#include <dev/mii/mii.h> -#include <dev/mii/miivar.h> - -#include <dev/pci/pcireg.h> -#include <dev/pci/pcivar.h> -#include <dev/pci/pcidevs.h> - -#include <dev/pci/if_nxreg.h> - -#ifdef NX_DEBUG -#define NXDBG_WAIT (1<<0) /* poll registers */ -#define NXDBG_FLASH (1<<1) /* debug flash access through ROMUSB */ -#define NXDBG_CRBINIT (1<<2) /* SW register init from flash */ -#define NXDBG_STATE (1<<3) /* Firmware states */ -#define NXDBG_WINDOW (1<<4) /* Memory windows */ -#define NXDBG_INTR (1<<5) /* Interrupts */ -#define NXDBG_TX (1<<6) /* Transmit */ -#define NXDBG_ALL 0xfffe /* enable nearly all debugging messages */ -int nx_debug = 0; -#define DPRINTF(_lvl, _arg...) do { \ - if (nx_debug & (_lvl)) \ - printf(_arg); \ -} while (0) -#define DPRINTREG(_lvl, _reg) do { \ - if (nx_debug & (_lvl)) \ - printf("%s: 0x%08x: %08x\n", \ - #_reg, _reg, nxb_readcrb(sc, _reg)); \ -} while (0) -#else -#define DPRINTREG(_lvl, _reg) -#define DPRINTF(_lvl, arg...) -#endif - -#define DEVNAME(_s) ((_s)->_s##_dev.dv_xname) - -#ifdef notyet -/* - * The NetXen firmware and bootloader is about 800k big, don't even try - * to load the alternative version from disk with small kernels used by - * the install media. The driver can still try to use the primary firmware - * and bootloader found in the controller's flash memory. - */ -#ifndef SMALL_KERNEL -#define NXB_LOADFIRMWARE -#endif -#endif - -struct nx_softc; - -struct nxb_port { - u_int8_t nxp_id; - u_int8_t nxp_mode; - u_int8_t nxp_phy; - u_int8_t nxp_lladdr[ETHER_ADDR_LEN]; - bus_size_t nxp_phyregion; - - struct nx_softc *nxp_nx; -}; - -struct nxb_dmamem { - bus_dmamap_t nxm_map; - bus_dma_segment_t nxm_seg; - int nxm_nsegs; - size_t nxm_size; - caddr_t nxm_kva; - const char *nxm_name; -}; - -struct nxb_softc { - struct device sc_dev; - - pci_chipset_tag_t sc_pc; - pcitag_t sc_tag; - u_int sc_function; - - bus_dma_tag_t sc_dmat; - bus_space_tag_t sc_memt; - bus_space_handle_t sc_memh; - bus_size_t sc_mems; - bus_space_tag_t sc_dbmemt; - bus_space_handle_t sc_dbmemh; - bus_size_t sc_dbmems; - - int sc_window; /* SW memory window */ - int sc_ddrwindow; /* PCI DDR memory window */ - int sc_qdrwindow; /* PCI QDR memory window */ - - pci_intr_handle_t sc_ih; - - u_int sc_flags; -#define NXFLAG_FWINVALID (1<<0) /* update firmware from disk */ - - struct nxb_info sc_nxbinfo; /* Information from flash */ - struct nxb_imageinfo sc_nxbimage; /* Image info from flash */ - - int sc_state; /* Firmware state */ - u_int32_t sc_fwmajor; /* Load image major rev */ - u_int32_t sc_fwminor; /* Load image minor rev */ - u_int32_t sc_fwbuild; /* Load image build rev */ - - struct nxb_port sc_nxp[NX_MAX_PORTS]; /* The nx ports */ - int sc_nports; - - struct timeout sc_reload; - int sc_reloaded; - - struct ksensor sc_sensor; - struct ksensordev sc_sensordev; -}; - -struct nx_buf { - bus_dmamap_t nb_dmamap; - struct mbuf *nb_m; -}; - -struct nx_ringdata { - /* Rx and Rx status descriptors */ - struct nxb_dmamem rd_rxdma; - struct nx_rxdesc *rd_rxring; - struct nx_buf rd_rxbuf[NX_MAX_RX_DESC]; - struct nxb_dmamem rd_statusdma; - struct nx_statusdesc *rd_statusring; - struct nx_buf rd_statusbuf[NX_MAX_RX_DESC]; - - /* Tx descriptors */ - struct nxb_dmamem rd_txdma; - struct nx_txdesc *rd_txring; - struct nx_buf rd_txbuf[NX_MAX_TX_DESC]; - u_int32_t rd_txproducer; - volatile u_int rd_txpending; -}; - -struct nx_softc { - struct device nx_dev; - struct arpcom nx_ac; - struct mii_data nx_mii; - - bus_space_handle_t nx_memh; /* port phy subregion */ - - struct nx_ringcontext *nx_rc; /* Rx, Tx, Status */ - struct nxb_dmamem nx_rcdma; - - struct nxb_softc *nx_sc; /* The nxb board */ - struct nxb_port *nx_port; /* Port information */ - void *nx_ih; - - struct nx_ringdata *nx_rings; - - struct timeout nx_tick; -}; - -int nxb_match(struct device *, void *, void *); -void nxb_attach(struct device *, struct device *, void *); -int nxb_query(struct nxb_softc *sc); -int nxb_newstate(struct nxb_softc *, int); -void nxb_reload(void *); -void nxb_mountroot(void *); -int nxb_loadfirmware(struct nxb_softc *, struct nxb_firmware_header *, - u_int8_t **, size_t *); -int nxb_reloadfirmware(struct nxb_softc *, struct nxb_firmware_header *, - u_int8_t **, size_t *); -void nxb_reset(struct nxb_softc *); - -u_int32_t nxb_read(struct nxb_softc *, bus_size_t); -void nxb_write(struct nxb_softc *, bus_size_t, u_int32_t); -u_int32_t nxb_readcrb(struct nxb_softc *, bus_size_t); -void nxb_writecrb(struct nxb_softc *, bus_size_t, u_int32_t); -int nxb_writehw(struct nxb_softc *, u_int32_t, u_int32_t); -bus_size_t nxb_set_crbwindow(struct nxb_softc *, bus_size_t); -u_int64_t nxb_set_pciwindow(struct nxb_softc *, u_int64_t); -int nxb_wait(struct nxb_softc *, bus_size_t, u_int32_t, u_int32_t, - int, u_int); -int nxb_read_rom(struct nxb_softc *, u_int32_t, u_int32_t *); - -void nxb_temp_sensor(void *); -int nxb_dmamem_alloc(struct nxb_softc *, struct nxb_dmamem *, - bus_size_t, const char *); -void nxb_dmamem_free(struct nxb_softc *, struct nxb_dmamem *); - -int nx_match(struct device *, void *, void *); -void nx_attach(struct device *, struct device *, void *); -int nx_print(void *, const char *); -int nx_media_change(struct ifnet *); -void nx_media_status(struct ifnet *, struct ifmediareq *); -void nx_link_state(struct nx_softc *); -void nx_init(struct ifnet *); -void nx_start(struct ifnet *); -void nx_stop(struct ifnet *); -void nx_watchdog(struct ifnet *); -int nx_ioctl(struct ifnet *, u_long, caddr_t); -void nx_iff(struct nx_softc *); -void nx_tick(void *); -int nx_intr(void *); -void nx_setlladdr(struct nx_softc *, u_int8_t *); -void nx_doorbell(struct nx_softc *nx, u_int8_t, u_int8_t, u_int32_t); -u_int32_t nx_readphy(struct nx_softc *, bus_size_t); -void nx_writephy(struct nx_softc *, bus_size_t, u_int32_t); -u_int32_t nx_readcrb(struct nx_softc *, enum nxsw_portreg); -void nx_writecrb(struct nx_softc *, enum nxsw_portreg, u_int32_t); - -int nx_alloc(struct nx_softc *); -void nx_free(struct nx_softc *); -struct mbuf *nx_getbuf(struct nx_softc *, bus_dmamap_t, int); -int nx_init_rings(struct nx_softc *); -void nx_free_rings(struct nx_softc *); - -struct cfdriver nxb_cd = { - 0, "nxb", DV_DULL -}; -struct cfattach nxb_ca = { - sizeof(struct nxb_softc), nxb_match, nxb_attach -}; - -struct cfdriver nx_cd = { - 0, "nx", DV_IFNET -}; -struct cfattach nx_ca = { - sizeof(struct nx_softc), nx_match, nx_attach -}; - -const struct pci_matchid nxb_devices[] = { - { PCI_VENDOR_NETXEN, PCI_PRODUCT_NETXEN_NXB_10GXxR }, - { PCI_VENDOR_NETXEN, PCI_PRODUCT_NETXEN_NXB_10GCX4 }, - { PCI_VENDOR_NETXEN, PCI_PRODUCT_NETXEN_NXB_4GCU }, - { PCI_VENDOR_NETXEN, PCI_PRODUCT_NETXEN_NXB_IMEZ }, - { PCI_VENDOR_NETXEN, PCI_PRODUCT_NETXEN_NXB_HMEZ }, - { PCI_VENDOR_NETXEN, PCI_PRODUCT_NETXEN_NXB_IMEZ_2 }, - { PCI_VENDOR_NETXEN, PCI_PRODUCT_NETXEN_NXB_HMEZ_2 } -}; - -const struct nxb_board { - enum nxb_board_types brd_type; - u_int brd_mode; - u_int brd_nports; - u_int brd_phy; /* The default PHY */ -} nxb_boards[] = { - { NXB_BOARDTYPE_P2SB35_4G, NXNIU_MODE_GBE, 4, IFM_1000_T }, - { NXB_BOARDTYPE_P2SB31_10G, NXNIU_MODE_XGE, 1, IFM_10G_SR }, - { NXB_BOARDTYPE_P2SB31_2G, NXNIU_MODE_GBE, 2, IFM_1000_T }, - { NXB_BOARDTYPE_P2SB31_10GIMEZ, NXNIU_MODE_XGE, 2, IFM_10G_SR }, - { NXB_BOARDTYPE_P2SB31_10GHMEZ, NXNIU_MODE_XGE, 2, IFM_10G_SR }, - { NXB_BOARDTYPE_P2SB31_10GCX4, NXNIU_MODE_XGE, 1, IFM_10G_CX4 } -}; - -/* Use mapping table, see if_nxreg.h for details */ -const u_int32_t nx_swportreg[NXSW_PORTREG_MAX][NX_MAX_PORTS] = NXSW_PORTREGS; -#define NXSW_PORTREG(_p, _r) (nx_swportreg[_r][nx->nx_port->nxp_id]) - -/* - * Routines handling the physical ''nxb'' board - */ - -int -nxb_match(struct device *parent, void *match, void *aux) -{ - return (pci_matchbyid((struct pci_attach_args *)aux, - nxb_devices, sizeof(nxb_devices) / sizeof(nxb_devices[0]))); -} - -void -nxb_attach(struct device *parent, struct device *self, void *aux) -{ - struct nxb_softc *sc = (struct nxb_softc *)self; - struct pci_attach_args *pa = aux; - pcireg_t memtype; - const char *intrstr; - bus_size_t pcisize; - paddr_t pciaddr; - int i; - - sc->sc_pc = pa->pa_pc; - sc->sc_tag = pa->pa_tag; - sc->sc_dmat = pa->pa_dmat; - sc->sc_function = pa->pa_function; - sc->sc_window = -1; - sc->sc_ddrwindow = -1; - sc->sc_qdrwindow = -1; - - /* - * The NetXen NICs can have different PCI memory layouts which - * need some special handling in the driver. Support is limited - * to 32bit 128MB memory for now (the chipset uses a configurable - * window to access the complete memory range). - */ - memtype = pci_mapreg_type(sc->sc_pc, sc->sc_tag, NXBAR0); - switch (memtype) { - case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: - break; - case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: - default: - printf(": invalid memory type: 0x%x\n", memtype); - return; - } - if (pci_mapreg_info(sc->sc_pc, sc->sc_tag, NXBAR0, - memtype, &pciaddr, &pcisize, NULL)) { - printf(": failed to get pci info\n"); - return; - } - switch (pcisize) { - case NXPCIMEM_SIZE_128MB: - break; - case NXPCIMEM_SIZE_32MB: - default: - printf(": invalid memory size: %ld\n", pcisize); - return; - } - - /* Finally map the PCI memory space */ - if (pci_mapreg_map(pa, NXBAR0, memtype, 0, &sc->sc_memt, - &sc->sc_memh, NULL, &sc->sc_mems, 0) != 0) { - printf(": unable to map register memory\n"); - return; - } - if (pci_mapreg_map(pa, NXBAR4, memtype, 0, &sc->sc_dbmemt, - &sc->sc_dbmemh, NULL, &sc->sc_dbmems, 0) != 0) { - printf(": unable to map doorbell memory\n"); - goto unmap1; - } - - /* Get the board information and initialize the h/w */ - if (nxb_query(sc) != 0) - goto unmap; - - /* Map the interrupt, the handlers will be attached later */ - if (pci_intr_map(pa, &sc->sc_ih) != 0) { - printf(": unable to map interrupt\n"); - goto unmap; - } - intrstr = pci_intr_string(pa->pa_pc, sc->sc_ih); - printf(": %s\n", intrstr); - - for (i = 0; i < sc->sc_nports; i++) - config_found(&sc->sc_dev, &sc->sc_nxp[i], nx_print); - - /* Initialize sensor data */ - strlcpy(sc->sc_sensordev.xname, DEVNAME(sc), - sizeof(sc->sc_sensordev.xname)); - sc->sc_sensor.type = SENSOR_TEMP; - sensor_attach(&sc->sc_sensordev, &sc->sc_sensor); - sensordev_install(&sc->sc_sensordev); - - timeout_set(&sc->sc_reload, nxb_reload, sc); - mountroothook_establish(nxb_mountroot, sc); - - return; - - unmap: - bus_space_unmap(sc->sc_dbmemt, sc->sc_dbmemh, sc->sc_dbmems); - sc->sc_dbmems = 0; - unmap1: - bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); - sc->sc_mems = 0; -} - -int -nxb_query(struct nxb_softc *sc) -{ - struct nxb_info *ni = &sc->sc_nxbinfo; - struct nxb_userinfo *nu; - u_int32_t *data, addr; - u_int8_t *ptr; - const struct nxb_board *board = NULL; - u_int i, j, len; - - /* - * Get the board information from flash memory - */ - addr = NXFLASHMAP_INFO; - len = sizeof(*ni) / sizeof(u_int32_t); - data = (u_int32_t *)ni; - for (i = 0; i < len; i++) { - if (nxb_read_rom(sc, addr, data) != 0) { - printf(": failed to get board info from flash\n"); - return (-1); - } - addr += sizeof(u_int32_t); - data++; - } - -#ifdef NX_DEBUG -#define _NXBINFO(_e) do { \ - if (nx_debug & NXDBG_FLASH) \ - printf("%s: %s: 0x%08x (%u)\n", \ - DEVNAME(sc), #_e, ni->_e, ni->_e); \ -} while (0) - _NXBINFO(ni_hdrver); - _NXBINFO(ni_board_mfg); - _NXBINFO(ni_board_type); - _NXBINFO(ni_board_num); - _NXBINFO(ni_chip_id); - _NXBINFO(ni_chip_minor); - _NXBINFO(ni_chip_major); - _NXBINFO(ni_chip_pkg); - _NXBINFO(ni_chip_lot); - _NXBINFO(ni_port_mask); - _NXBINFO(ni_peg_mask); - _NXBINFO(ni_icache); - _NXBINFO(ni_dcache); - _NXBINFO(ni_casper); - _NXBINFO(ni_lladdr0_low); - _NXBINFO(ni_lladdr1_low); - _NXBINFO(ni_lladdr2_low); - _NXBINFO(ni_lladdr3_low); - _NXBINFO(ni_mnsync_mode); - _NXBINFO(ni_mnsync_shift_cclk); - _NXBINFO(ni_mnsync_shift_mclk); - _NXBINFO(ni_mnwb_enable); - _NXBINFO(ni_mnfreq_crystal); - _NXBINFO(ni_mnfreq_speed); - _NXBINFO(ni_mnorg); - _NXBINFO(ni_mndepth); - _NXBINFO(ni_mnranks0); - _NXBINFO(ni_mnranks1); - _NXBINFO(ni_mnrd_latency0); - _NXBINFO(ni_mnrd_latency1); - _NXBINFO(ni_mnrd_latency2); - _NXBINFO(ni_mnrd_latency3); - _NXBINFO(ni_mnrd_latency4); - _NXBINFO(ni_mnrd_latency5); - _NXBINFO(ni_mnrd_latency6); - _NXBINFO(ni_mnrd_latency7); - _NXBINFO(ni_mnrd_latency8); - _NXBINFO(ni_mndll[0]); - _NXBINFO(ni_mnddr_mode); - _NXBINFO(ni_mnddr_extmode); - _NXBINFO(ni_mntiming0); - _NXBINFO(ni_mntiming1); - _NXBINFO(ni_mntiming2); - _NXBINFO(ni_snsync_mode); - _NXBINFO(ni_snpt_mode); - _NXBINFO(ni_snecc_enable); - _NXBINFO(ni_snwb_enable); - _NXBINFO(ni_snfreq_crystal); - _NXBINFO(ni_snfreq_speed); - _NXBINFO(ni_snorg); - _NXBINFO(ni_sndepth); - _NXBINFO(ni_sndll); - _NXBINFO(ni_snrd_latency); - _NXBINFO(ni_lladdr0_high); - _NXBINFO(ni_lladdr1_high); - _NXBINFO(ni_lladdr2_high); - _NXBINFO(ni_lladdr3_high); - _NXBINFO(ni_magic); - _NXBINFO(ni_mnrd_imm); - _NXBINFO(ni_mndll_override); -#undef _NXBINFO -#endif /* NX_DEBUG */ - - /* Validate the board information from flash */ - if (ni->ni_hdrver != NXB_VERSION) { - printf(": unsupported flash info header version %u\n", - ni->ni_hdrver); - return (-1); - } - if (ni->ni_magic != NXB_MAGIC) { - printf(": flash info magic value mismatch\n"); - return (-1); - } - - /* Lookup the board */ - for (i = 0; i < (sizeof(nxb_boards) / sizeof(nxb_boards[0])); i++) { - if (ni->ni_board_type == nxb_boards[i].brd_type) { - board = &nxb_boards[i]; - break; - } - } - if (board == NULL) { - printf(": unsupported board type %u\n", ni->ni_board_type); - return (-1); - } - - /* Configure the ports */ - sc->sc_nports = board->brd_nports; - for (i = 0; i < sc->sc_nports; i++) { - sc->sc_nxp[i].nxp_id = i; - sc->sc_nxp[i].nxp_mode = board->brd_mode; - sc->sc_nxp[i].nxp_phy = board->brd_phy; - switch (board->brd_mode) { - case NXNIU_MODE_XGE: - sc->sc_nxp[i].nxp_phyregion = NXNIU_XGE(i); - break; - case NXNIU_MODE_GBE: - sc->sc_nxp[i].nxp_phyregion = NXNIU_GBE(i); - break; - case NXNIU_MODE_FC: - sc->sc_nxp[i].nxp_phyregion = NXNIU_FC(i); - break; - } - } - - /* - * Get the user information from flash memory - */ - if ((nu = (struct nxb_userinfo *) - malloc(sizeof(*nu), M_TEMP, M_NOWAIT)) == NULL) { - printf(": failed to allocate user info\n"); - return (-1); - } - addr = NXFLASHMAP_USER; - len = sizeof(*nu) / sizeof(u_int32_t); - data = (u_int32_t *)nu; - for (i = 0; i < len; i++) { - if (nxb_read_rom(sc, addr, data) != 0) { - printf(": failed to get user info from flash\n"); - free(nu, M_TEMP); - return (-1); - } - addr += sizeof(u_int32_t); - data++; - } - - /* Copy the MAC addresses */ - for (i = 0; i < sc->sc_nports; i++) { - ptr = (u_int8_t *) - &nu->nu_lladdr[i * NXB_MAX_PORT_LLADDRS]; - /* MAC address bytes are stored in a swapped order */ - for (j = 0; j < ETHER_ADDR_LEN; j++) - sc->sc_nxp[i].nxp_lladdr[j] = - ptr[ETHER_ADDR_LEN - (j + 1)]; - } - - /* Make sure that the serial number is a NUL-terminated string */ - nu->nu_serial_num[31] = '\0'; - - /* Copy flash image information */ - bcopy(&nu->nu_image, &sc->sc_nxbimage, sizeof(sc->sc_nxbimage)); - -#ifdef NX_DEBUG -#define _NXBUSER(_e) do { \ - if (nx_debug & NXDBG_FLASH) \ - printf("%s: %s: 0x%08x (%u)\n", \ - DEVNAME(sc), #_e, nu->_e, nu->_e); \ -} while (0) - _NXBUSER(nu_image.nim_bootld_ver); - _NXBUSER(nu_image.nim_bootld_size); - _NXBUSER(nu_image.nim_image_ver); - _NXBUSER(nu_image.nim_image_size); - _NXBUSER(nu_primary); - _NXBUSER(nu_secondary); - _NXBUSER(nu_subsys_id); - DPRINTF(NXDBG_FLASH, "%s: nu_serial_num: %s\n", - DEVNAME(sc), nu->nu_serial_num); - _NXBUSER(nu_bios_ver); -#undef _NXBUSER -#endif - - free(nu, M_TEMP); - - /* - * bootstrap the firmware, the status will be polled in the - * mountroot hook. - */ - nxb_newstate(sc, NX_S_BOOT); - - return (0); -} - -int -nxb_newstate(struct nxb_softc *sc, int newstate) -{ - int oldstate = sc->sc_state; - - sc->sc_state = newstate; - DPRINTF(NXDBG_STATE, "%s(%s) state %d -> %d\n", - DEVNAME(sc), __func__, oldstate, newstate); - - switch (newstate) { - case NX_S_RESET: - timeout_del(&sc->sc_reload); - nxb_reset(sc); - break; - case NX_S_BOOT: - /* - * Initialize and bootstrap the device - */ - nxb_writecrb(sc, NXSW_CMD_PRODUCER_OFF, 0); - nxb_writecrb(sc, NXSW_CMD_CONSUMER_OFF, 0); - nxb_writecrb(sc, NXSW_DRIVER_VER, NX_FIRMWARE_VER); - nxb_writecrb(sc, NXROMUSB_GLB_PEGTUNE, - NXROMUSB_GLB_PEGTUNE_DONE); - break; - case NX_S_LOADED: - /* - * Initially wait for the device to become ready - */ - assert(oldstate == NX_S_BOOT); - timeout_del(&sc->sc_reload); - if (nxb_wait(sc, NXSW_CMDPEG_STATE, NXSW_CMDPEG_INIT_DONE, - NXSW_CMDPEG_STATE_M, 1, 2000000) != 0) { - printf("%s: bootstrap failed, code 0x%x\n", - DEVNAME(sc), - nxb_readcrb(sc, NXSW_CMDPEG_STATE)); - sc->sc_state = NX_S_FAIL; - return (-1); - } - break; - case NX_S_RELOADED: - assert(oldstate == NX_S_RESET || oldstate == NX_S_BOOT); - /* - * Wait for the device to become ready - */ - sc->sc_reloaded = 20000; - timeout_add(&sc->sc_reload, hz / 100); - break; - case NX_S_READY: - nxb_temp_sensor(sc); - break; - case NX_S_FAIL: - if (oldstate == NX_S_RELOADED) - printf("%s: failed to reset the firmware, " - "code 0x%x\n", DEVNAME(sc), - nxb_readcrb(sc, NXSW_CMDPEG_STATE)); - break; - default: - /* no action */ - break; - } - - return (0); -} - -void -nxb_mountroot(void *arg) -{ - struct nxb_softc *sc = (struct nxb_softc *)arg; - - /* - * Poll the status of the running firmware. - */ - if (nxb_newstate(sc, NX_S_LOADED) != 0) - return; - - /* Start sensor */ - sensor_task_register(sc, nxb_temp_sensor, NX_POLL_SENSOR); - - /* - * Get and validate the loaded firmware version - */ - sc->sc_fwmajor = nxb_readcrb(sc, NXSW_FW_VERSION_MAJOR); - sc->sc_fwminor = nxb_readcrb(sc, NXSW_FW_VERSION_MINOR); - sc->sc_fwbuild = nxb_readcrb(sc, NXSW_FW_VERSION_BUILD); - printf("%s: firmware %u.%u.%u", DEVNAME(sc), - sc->sc_fwmajor, sc->sc_fwminor, sc->sc_fwbuild); - if (sc->sc_fwmajor != NX_FIRMWARE_MAJOR || - sc->sc_fwminor != NX_FIRMWARE_MINOR) { - printf(", requires %u.%u.xx (%u.%u.%u)", - NX_FIRMWARE_MAJOR, NX_FIRMWARE_MINOR, - NX_FIRMWARE_MAJOR, NX_FIRMWARE_MINOR, - NX_FIRMWARE_BUILD); - sc->sc_flags |= NXFLAG_FWINVALID; - } - printf("\n"); - - nxb_newstate(sc, NX_S_RESET); -} - -void -nxb_reload(void *arg) -{ - struct nxb_softc *sc = (struct nxb_softc *)arg; - u_int32_t val; - - /* - * Check if the device is ready, other re-schedule or timeout - */ - val = nxb_readcrb(sc, NXSW_CMDPEG_STATE); - if (((val & NXSW_CMDPEG_STATE_M) != NXSW_CMDPEG_INIT_DONE) && - ((val & NXSW_CMDPEG_STATE_M) != NXSW_CMDPEG_INIT_ACK)) { - if (!sc->sc_reloaded--) - nxb_newstate(sc, NX_S_FAIL); - else - timeout_add(&sc->sc_reload, hz / 100); - return; - } - nxb_writecrb(sc, NXSW_MPORT_MODE, NXSW_MPORT_MODE_NFUNC); - nxb_writecrb(sc, NXSW_CMDPEG_STATE, NXSW_CMDPEG_INIT_ACK); - - /* Firmware is ready for operation, allow interrupts etc. */ - nxb_newstate(sc, NX_S_READY); -} - -int -nxb_loadfirmware(struct nxb_softc *sc, struct nxb_firmware_header *fh, - u_int8_t **fw, size_t *fwlen) -{ -#ifdef NXB_LOADFIRMWARE - u_int8_t *mem; - size_t memlen; - - /* - * Load a supported bootloader and firmware image from disk - */ - if (loadfirmware("nxb", &mem, &memlen) != 0) - return (-1); - - if ((memlen) < sizeof(*fh)) - goto fail; - bcopy(mem, fh, sizeof(*fh)); - if (ntohl(fh->fw_hdrver) != NX_FIRMWARE_HDRVER) - goto fail; - - *fw = mem; - *fwlen = memlen; - - return (0); - fail: - free(mem, M_DEVBUF); -#endif - return (-1); -} - -int -nxb_reloadfirmware(struct nxb_softc *sc, struct nxb_firmware_header *fh, - u_int8_t **fw, size_t *fwlen) -{ - u_int8_t *mem; - size_t memlen; - u_int32_t addr, *data; - u_int i; - size_t bsize = NXFLASHMAP_BOOTLDSIZE; - - /* - * Load the images from flash, setup a fake firmware header - */ - memlen = bsize + sizeof(*fh); - mem = (u_int8_t *)malloc(memlen, M_DEVBUF, M_NOWAIT); - if (mem == NULL) - return (-1); - - fh->fw_hdrver = htonl(NX_FIRMWARE_HDRVER); - fh->fw_image_ver = htonl(sc->sc_nxbimage.nim_image_ver); - fh->fw_image_size = 0; /* Reload firmware image from flash */ - fh->fw_bootld_ver = htonl(sc->sc_nxbimage.nim_bootld_ver); - fh->fw_bootld_size = htonl(bsize); - bcopy(fh, mem, sizeof(*fh)); - - addr = NXFLASHMAP_BOOTLOADER; - data = (u_int32_t *)(mem + sizeof(*fh)); - for (i = 0; i < (bsize / 4); i++) { - if (nxb_read_rom(sc, addr, data) != 0) - goto fail; - addr += sizeof(u_int32_t); - *data++; - } - - *fw = mem; - *fwlen = memlen; - - return (0); - fail: - free(mem, M_DEVBUF); - return (-1); -} - -void -nxb_reset(struct nxb_softc *sc) -{ - struct nxb_firmware_header fh; - u_int8_t *fw = NULL; - size_t fwlen = 0; - int bootsz, imagesz; - u_int i; - u_int32_t *data, addr, addr1, val, ncrb; - bus_size_t reg; - - /* Reset the SW state */ - nxb_writecrb(sc, NXSW_CMDPEG_STATE, 0); - - /* - * Load the firmware from disk or from flash - */ - bzero(&fh, sizeof(fh)); - if (sc->sc_flags & NXFLAG_FWINVALID) { - if (nxb_loadfirmware(sc, &fh, &fw, &fwlen) != 0) { - printf("%s: failed to load firmware from disk\n", - DEVNAME(sc)); - goto fail; - } - } else { - if (nxb_reloadfirmware(sc, &fh, &fw, &fwlen) != 0) { - printf("%s: failed to reload firmware from flash\n", - DEVNAME(sc)); - goto fail; - } - } - - /* - * Validate the information found in the extra header - */ - val = ntohl(fh.fw_image_ver); - sc->sc_fwmajor = (val & NXB_IMAGE_MAJOR_M) >> NXB_IMAGE_MAJOR_S; - sc->sc_fwminor = (val & NXB_IMAGE_MINOR_M) >> NXB_IMAGE_MINOR_S; - sc->sc_fwbuild = (val & NXB_IMAGE_BUILD_M) >> NXB_IMAGE_BUILD_S; - if (sc->sc_flags & NXFLAG_FWINVALID) - printf("%s: using firmware %u.%u.%u\n", DEVNAME(sc), - sc->sc_fwmajor, sc->sc_fwminor, sc->sc_fwbuild); - if (sc->sc_fwmajor != NX_FIRMWARE_MAJOR || - sc->sc_fwminor != NX_FIRMWARE_MINOR) { - printf("%s: unsupported firmware version\n", - DEVNAME(sc)); - goto fail; - } - - bootsz = ntohl(fh.fw_bootld_size); - imagesz = ntohl(fh.fw_image_size); - if ((imagesz + bootsz) != (fwlen - sizeof(fh)) || - (imagesz % 4) || (bootsz % 4)) { - printf("%s: invalid firmware image\n", DEVNAME(sc)); - goto fail; - } - - /* - * Reset the SW registers - */ - - /* 1. Halt the hardware */ - nxb_writecrb(sc, NXROMUSB_GLB_SW_RESET, NXROMUSB_GLB_SW_RESET_DEF); - - /* 2. Read the CRBINIT area from flash memory */ - addr = NXFLASHMAP_CRBINIT_0; - if (nxb_read_rom(sc, addr, &ncrb) != 0) - goto fail1; - ncrb &= NXFLASHMAP_CRBINIT_M; - if (ncrb == 0 || ncrb > NXFLASHMAP_CRBINIT_MAX) - goto fail1; /* ignore CRBINIT and skip step */ - - /* 3. Write the CRBINIT area to PCI memory */ - for (i = 0; i < ncrb; i++) { - addr = NXFLASHMAP_CRBINIT_0 + (i * 8); - nxb_read_rom(sc, addr + 4, &val); - nxb_read_rom(sc, addr + 8, &addr1); - - if (nxb_writehw(sc, addr1, val) != 0) - goto fail1; - } - - /* 4. Reset the Protocol Processing Engine */ - val = nxb_readcrb(sc, NXROMUSB_GLB_SW_RESET) & - ~NXROMUSB_GLB_SW_RESET_PPE; - nxb_writecrb(sc, NXROMUSB_GLB_SW_RESET, val); - - /* 5. Reset the D & I caches */ - nxb_writecrb(sc, NXPPE_D(0x0e), 0x1e); - nxb_writecrb(sc, NXPPE_D(0x4c), 0x8); - nxb_writecrb(sc, NXPPE_I(0x4c), 0x8); - - /* 6. Clear the Protocol Processing Engine */ - nxb_writecrb(sc, NXPPE_0(0x8), 0); - nxb_writecrb(sc, NXPPE_0(0xc), 0); - nxb_writecrb(sc, NXPPE_1(0x8), 0); - nxb_writecrb(sc, NXPPE_1(0xc), 0); - nxb_writecrb(sc, NXPPE_2(0x8), 0); - nxb_writecrb(sc, NXPPE_2(0xc), 0); - nxb_writecrb(sc, NXPPE_3(0x8), 0); - nxb_writecrb(sc, NXPPE_3(0xc), 0); - - /* - * Load the images into RAM - */ - - /* Reset casper boot chip */ - nxb_writecrb(sc, NXROMUSB_GLB_CAS_RESET, NXROMUSB_GLB_CAS_RESET_ENABLE); - - addr = NXFLASHMAP_BOOTLOADER; - data = (u_int32_t *)(fw + sizeof(fh)); - for (i = 0; i < (bootsz / 4); i++) { - reg = nxb_set_pciwindow(sc, (u_int64_t)addr); - if (reg == ~0) - goto fail1; - nxb_write(sc, reg, *data); - addr += sizeof(u_int32_t); - data++; - } - if (imagesz) { - addr = NXFLASHMAP_FIRMWARE_0; - for (i = 0; i < (imagesz / 4); i++) { - reg = nxb_set_pciwindow(sc, (u_int64_t)addr); - if (reg == ~0) - goto fail1; - nxb_write(sc, reg, *data); - addr += sizeof(u_int32_t); - data++; - } - /* tell the bootloader to load the firmware image from RAM */ - nxb_writecrb(sc, NXSW_BOOTLD_CONFIG, NXSW_BOOTLD_CONFIG_RAM); - } else { - /* tell the bootloader to load the firmware image from flash */ - nxb_writecrb(sc, NXSW_BOOTLD_CONFIG, NXSW_BOOTLD_CONFIG_ROM); - } - - /* Power on the clocks and unreset the casper boot chip */ - nxb_writecrb(sc, NXROMUSB_GLB_CHIPCLKCONTROL, - NXROMUSB_GLB_CHIPCLKCONTROL_ON); - nxb_writecrb(sc, NXROMUSB_GLB_CAS_RESET, - NXROMUSB_GLB_CAS_RESET_DISABLE); - free(fw, M_DEVBUF); - fw = NULL; - - /* - * bootstrap the newly loaded firmware and wait for completion - */ - nxb_newstate(sc, NX_S_BOOT); - if (nxb_newstate(sc, NX_S_RELOADED) != 0) - goto fail; - return; - fail1: - printf("%s: failed to reset firmware\n", DEVNAME(sc)); - fail: - nxb_newstate(sc, NX_S_FAIL); - if (fw != NULL) - free(fw, M_DEVBUF); -} - -u_int32_t -nxb_read(struct nxb_softc *sc, bus_size_t reg) -{ - bus_space_barrier(sc->sc_memt, sc->sc_memh, reg, 4, - BUS_SPACE_BARRIER_READ); - return (bus_space_read_4(sc->sc_memt, sc->sc_memh, reg)); -} - -void -nxb_write(struct nxb_softc *sc, bus_size_t reg, u_int32_t val) -{ - bus_space_write_4(sc->sc_memt, sc->sc_memh, reg, val); - bus_space_barrier(sc->sc_memt, sc->sc_memh, reg, 4, - BUS_SPACE_BARRIER_WRITE); -} - -u_int32_t -nxb_readcrb(struct nxb_softc *sc, bus_size_t reg) -{ - reg = nxb_set_crbwindow(sc, reg); - bus_space_barrier(sc->sc_memt, sc->sc_memh, reg, 4, - BUS_SPACE_BARRIER_READ); - return (bus_space_read_4(sc->sc_memt, sc->sc_memh, reg)); -} - -void -nxb_writecrb(struct nxb_softc *sc, bus_size_t reg, u_int32_t val) -{ - reg = nxb_set_crbwindow(sc, reg); - bus_space_write_4(sc->sc_memt, sc->sc_memh, reg, val); - bus_space_barrier(sc->sc_memt, sc->sc_memh, reg, 4, - BUS_SPACE_BARRIER_WRITE); -} - -int -nxb_writehw(struct nxb_softc *sc, u_int32_t addr, u_int32_t val) -{ - /* Translation table of NIC addresses to PCI addresses */ - static const u_int16_t hwtrans[] = { - 0x29a0, 0x7730, 0x2950, 0x2a50, 0x0000, 0x0d00, - 0x1b10, 0x0e60, 0x0e00, 0x0e10, 0x0e20, 0x0e30, - 0x7000, 0x7010, 0x7020, 0x7030, 0x7040, 0x3400, - 0x3410, 0x3420, 0x3430, 0x3450, 0x3440, 0x3c00, - 0x3c10, 0x3c20, 0x3c30, 0x3c50, 0x3c40, 0x4100, - 0x0000, 0x0d10, 0x0000, 0x0000, 0x4160, 0x0c60, - 0x0c70, 0x0c80, 0x7580, 0x7590, 0x4170, 0x0000, - 0x0890, 0x70a0, 0x70b0, 0x70c0, 0x08d0, 0x08e0, - 0x70f0, 0x4050, 0x4200, 0x4210, 0x0000, 0x0880, - 0x0000, 0x0000, 0x0000, 0x0000, 0x7180, 0x0000 - }; - u_int32_t base = (addr & NXMEMMAP_HWTRANS_M) >> 16; - bus_size_t reg = ~0; - u_int i, timo = 1; - - for (i = 0; i < (sizeof(hwtrans) / sizeof(hwtrans[0])); i++) { - if (hwtrans[i] == base) { - reg = i << 20; - break; - } - } - if (reg == ~0) - return (-1); /* Invalid address */ - reg += (addr & ~NXMEMMAP_HWTRANS_M) + NXPCIMAP_CRB; - - /* Write value to the register, enable some workarounds */ - if (reg == NXSW_BOOTLD_CONFIG) - return (0); - else if (reg == NXROMUSB_GLB_SW_RESET) { - val = NXROMUSB_GLB_SW_RESET_XDMA; - timo = hz; - } - nxb_writecrb(sc, reg, val); - delay(timo); - - DPRINTF(NXDBG_CRBINIT, "%s(%s) addr 0x%08x -> reg 0x%08x, " - "val 0x%08x\n", DEVNAME(sc), __func__, addr, reg, val); - - return (0); -} - -u_int64_t -nxb_set_pciwindow(struct nxb_softc *sc, u_int64_t reg) -{ - int32_t window = -1; - u_int64_t wreg = ~0ULL; - - /* - * Get the correct offset in the mapped PCI space - */ - if (reg <= NXADDR_DDR_NET_END) { - window = (reg >> NXDDR_WINDOW_S) & NXDDR_WINDOW_M; - reg -= (window * NXDDR_WINDOW_SIZE); - if (sc->sc_ddrwindow != window) { - sc->sc_ddrwindow = window; - wreg = NXDDR_WINDOW(sc->sc_function); - } - } else if (reg >= NXADDR_OCM0 && reg <= NXADDR_OCM0_END) { - reg -= NXADDR_OCM0; - reg += NXPCIMAP_OCM0; - } else if (reg >= NXADDR_OCM1 && reg <= NXADDR_OCM1_END) { - reg -= NXADDR_OCM1; - reg += NXPCIMAP_OCM1; - } else if (reg >= NXADDR_QDR_NET && reg <= NXADDR_QDR_NET_END) { - reg -= NXADDR_QDR_NET; - window = (reg >> NXDDR_WINDOW_S) & NXDDR_WINDOW_M; - reg -= (window * NXQDR_WINDOW_SIZE); - reg += NXPCIMAP_QDR_NET; - if (sc->sc_qdrwindow != window) { - sc->sc_qdrwindow = window; - wreg = NXQDR_WINDOW(sc->sc_function); - } - } else - reg = ~0ULL; - - /* - * Update the PCI window - */ - if (wreg != ~0ULL) { - DPRINTF(NXDBG_WINDOW, "%s(%s) reg 0x%08x window 0x%08x\n", - DEVNAME(sc), __func__, sc->sc_window, wreg, window); - - nxb_write(sc, wreg, window); - (void)nxb_read(sc, wreg); - } - - return (reg); -} - -bus_size_t -nxb_set_crbwindow(struct nxb_softc *sc, bus_size_t reg) -{ - int window = 0; - - /* Set the correct CRB window */ - if ((reg >> NXCRB_WINDOW_S) & NXCRB_WINDOW_M) { - window = 1; - reg -= NXCRB_WINDOW_SIZE; - } - if (sc->sc_window == window) - return (reg); - nxb_write(sc, NXCRB_WINDOW(sc->sc_function), - window << NXCRB_WINDOW_S); - (void)nxb_read(sc, NXCRB_WINDOW(sc->sc_function)); - - DPRINTF(NXDBG_WINDOW, "%s(%s) window %d -> %d reg 0x%08x\n", - DEVNAME(sc), __func__, sc->sc_window, window, - reg + (window * NXCRB_WINDOW_SIZE)); - - sc->sc_window = window; - - return (reg); -} - -int -nxb_wait(struct nxb_softc *sc, bus_size_t reg, u_int32_t val, - u_int32_t mask, int is_set, u_int timeout) -{ - u_int i; - u_int32_t data; - - for (i = timeout; i > 0; i--) { - data = nxb_readcrb(sc, reg) & mask; - if (is_set) { - if (data == val) - goto done; - } else { - if (data != val) - goto done; - } - delay(10); - } - - return (-1); - done: - DPRINTF(NXDBG_WAIT, "%s(%s) " - "reg 0x%08x completed after %d/%d iterations\n", - DEVNAME(sc), __func__, reg, i, timeout); - return (0); -} - -int -nxb_read_rom(struct nxb_softc *sc, u_int32_t addr, u_int32_t *val) -{ - u_int32_t data; - int ret = 0; - - /* - * Need to set a lock and the lock ID to access the flash - */ - ret = nxb_wait(sc, NXSEM_FLASH_LOCK, - NXSEM_FLASH_LOCKED, NXSEM_FLASH_LOCK_M, 1, 10000); - if (ret != 0) { - DPRINTF(NXDBG_FLASH, "%s(%s): ROM lock timeout\n", - DEVNAME(sc), __func__); - return (-1); - } - nxb_writecrb(sc, NXSW_ROM_LOCK_ID, NXSW_ROM_LOCK_DRV); - - /* - * Setup ROM data transfer - */ - - /* Set the ROM address */ - nxb_writecrb(sc, NXROMUSB_ROM_ADDR, addr); - - /* The delay is needed to prevent bursting on the chipset */ - nxb_writecrb(sc, NXROMUSB_ROM_ABYTE_CNT, 3); - delay(100); - nxb_writecrb(sc, NXROMUSB_ROM_DUMMY_BYTE_CNT, 0); - - /* Set opcode and wait for completion */ - nxb_writecrb(sc, NXROMUSB_ROM_OPCODE, NXROMUSB_ROM_OPCODE_READ); - ret = nxb_wait(sc, NXROMUSB_GLB_STATUS, - NXROMUSB_GLB_STATUS_DONE, NXROMUSB_GLB_STATUS_DONE, 1, 100); - if (ret != 0) { - DPRINTF(NXDBG_FLASH, "%s(%s): ROM operation timeout\n", - DEVNAME(sc), __func__); - goto unlock; - } - - /* Reset counters */ - nxb_writecrb(sc, NXROMUSB_ROM_ABYTE_CNT, 0); - delay(100); - nxb_writecrb(sc, NXROMUSB_ROM_DUMMY_BYTE_CNT, 0); - - /* Finally get the value */ - data = nxb_readcrb(sc, NXROMUSB_ROM_RDATA); - - /* Flash data is stored in little endian */ - *val = letoh32(data); - - unlock: - /* - * Release the lock - */ - (void)nxb_readcrb(sc, NXSEM_FLASH_UNLOCK); - - return (ret); -} - -void -nxb_temp_sensor(void *arg) -{ - struct nxb_softc *sc = (struct nxb_softc *)arg; - u_int32_t data, val, state; - - if (sc->sc_state != NX_S_READY) { - sc->sc_sensor.flags = SENSOR_FUNKNOWN; - return; - } - - data = nxb_readcrb(sc, NXSW_TEMP); - state = (data & NXSW_TEMP_STATE_M) >> NXSW_TEMP_STATE_S; - val = (data & NXSW_TEMP_VAL_M) >> NXSW_TEMP_VAL_S; - - switch (state) { - case NXSW_TEMP_STATE_NONE: - sc->sc_sensor.status = SENSOR_S_UNSPEC; - break; - case NXSW_TEMP_STATE_OK: - sc->sc_sensor.status = SENSOR_S_OK; - break; - case NXSW_TEMP_STATE_WARN: - sc->sc_sensor.status = SENSOR_S_WARN; - break; - case NXSW_TEMP_STATE_CRIT: - sc->sc_sensor.status = SENSOR_S_CRIT; - break; - default: - sc->sc_sensor.flags = SENSOR_FUNKNOWN; - return; - } - sc->sc_sensor.value = val * 1000000 + 273150000; - sc->sc_sensor.flags = 0; -} - -int -nxb_dmamem_alloc(struct nxb_softc *sc, struct nxb_dmamem *nxm, - bus_size_t size, const char *mname) -{ - nxm->nxm_size = size; - - if (bus_dmamap_create(sc->sc_dmat, nxm->nxm_size, 1, - nxm->nxm_size, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, - &nxm->nxm_map) != 0) - return (1); - if (bus_dmamem_alloc(sc->sc_dmat, nxm->nxm_size, - NX_DMA_ALIGN, 0, &nxm->nxm_seg, 1, &nxm->nxm_nsegs, - BUS_DMA_NOWAIT) != 0) - goto destroy; - if (bus_dmamem_map(sc->sc_dmat, &nxm->nxm_seg, nxm->nxm_nsegs, - nxm->nxm_size, &nxm->nxm_kva, BUS_DMA_NOWAIT) != 0) - goto free; - if (bus_dmamap_load(sc->sc_dmat, nxm->nxm_map, nxm->nxm_kva, - nxm->nxm_size, NULL, BUS_DMA_NOWAIT) != 0) - goto unmap; - - bzero(nxm->nxm_kva, nxm->nxm_size); - nxm->nxm_name = mname; - - return (0); - unmap: - bus_dmamem_unmap(sc->sc_dmat, nxm->nxm_kva, nxm->nxm_size); - free: - bus_dmamem_free(sc->sc_dmat, &nxm->nxm_seg, 1); - destroy: - bus_dmamap_destroy(sc->sc_dmat, nxm->nxm_map); - return (1); -} - -void -nxb_dmamem_free(struct nxb_softc *sc, struct nxb_dmamem *nxm) -{ - bus_dmamap_unload(sc->sc_dmat, nxm->nxm_map); - bus_dmamem_unmap(sc->sc_dmat, nxm->nxm_kva, nxm->nxm_size); - bus_dmamem_free(sc->sc_dmat, &nxm->nxm_seg, 1); - bus_dmamap_destroy(sc->sc_dmat, nxm->nxm_map); -} - -/* - * Routines handling the virtual ''nx'' ports - */ - -int -nx_match(struct device *parent, void *match, void *aux) -{ - struct nxb_port *nxp = (struct nxb_port *)aux; - - if (nxp->nxp_id >= NX_MAX_PORTS) - return (0); - - switch (nxp->nxp_mode) { - case NXNIU_MODE_XGE: - case NXNIU_MODE_GBE: - return (1); - case NXNIU_MODE_FC: - /* FibreChannel mode is not documented and not supported */ - return (0); - } - - return (0); -} - -void -nx_attach(struct device *parent, struct device *self, void *aux) -{ - struct nxb_softc *sc = (struct nxb_softc *)parent; - struct nx_softc *nx = (struct nx_softc *)self; - struct nxb_port *nxp = (struct nxb_port *)aux; - struct ifnet *ifp; - - nx->nx_sc = sc; - nx->nx_port = nxp; - nxp->nxp_nx = nx; - - if (bus_space_subregion(sc->sc_memt, sc->sc_memh, - nxp->nxp_phyregion, NXNIU_PORT_SIZE, &nx->nx_memh) != 0) { - printf(": unable to map port subregion\n"); - return; - } - - nx->nx_ih = pci_intr_establish(sc->sc_pc, sc->sc_ih, IPL_NET, - nx_intr, nx, DEVNAME(nx)); - if (nx->nx_ih == NULL) { - printf(": unable to establish interrupt\n"); - return; - } - - if (nx_alloc(nx) != 0) { - printf(": unable to allocate ring or dma memory\n"); - pci_intr_disestablish(sc->sc_pc, nx->nx_ih); - return; - } - - bcopy(nxp->nxp_lladdr, nx->nx_ac.ac_enaddr, ETHER_ADDR_LEN); - printf(": address %s\n", ether_sprintf(nx->nx_ac.ac_enaddr)); - - ifp = &nx->nx_ac.ac_if; - ifp->if_softc = nx; - ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; - ifp->if_ioctl = nx_ioctl; - ifp->if_start = nx_start; - ifp->if_watchdog = nx_watchdog; - ifp->if_hardmtu = NX_JUMBO_MTU; - strlcpy(ifp->if_xname, DEVNAME(nx), IFNAMSIZ); - IFQ_SET_MAXLEN(&ifp->if_snd, NX_MAX_TX_DESC - 1); - IFQ_SET_READY(&ifp->if_snd); - - ifp->if_capabilities = IFCAP_VLAN_MTU; -#if 0 - ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; - ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | - IFCAP_CSUM_UDPv4; -#endif - if (nxp->nxp_mode == NXNIU_MODE_GBE) - ifp->if_baudrate = IF_Gbps(1); - else - ifp->if_baudrate = ULONG_MAX; /* XXX fix if_baudrate */ - - ifmedia_init(&nx->nx_mii.mii_media, 0, - nx_media_change, nx_media_status); - ifmedia_add(&nx->nx_mii.mii_media, IFM_ETHER|nxp->nxp_phy, 0, NULL); - ifmedia_set(&nx->nx_mii.mii_media, IFM_ETHER|nxp->nxp_phy); - - if_attach(ifp); - ether_ifattach(ifp); - - timeout_set(&nx->nx_tick, nx_tick, nx); - timeout_add(&nx->nx_tick, hz); -} - -int -nx_print(void *aux, const char *parentname) -{ - struct nxb_port *nxp = (struct nxb_port *)aux; - - if (parentname) - printf("nx port %u at %s", - nxp->nxp_id, parentname); - else - printf(" port %u", nxp->nxp_id); - return (UNCONF); -} - -int -nx_media_change(struct ifnet *ifp) -{ - struct nx_softc *nx = (struct nx_softc *)ifp->if_softc; - struct nxb_port *nxp = nx->nx_port; - - switch (nxp->nxp_mode) { - case NXNIU_MODE_XGE: - /* XXX */ - break; - case NXNIU_MODE_GBE: - mii_mediachg(&nx->nx_mii); - break; - } - - return (0); -} - -void -nx_media_status(struct ifnet *ifp, struct ifmediareq *imr) -{ - struct nx_softc *nx = (struct nx_softc *)ifp->if_softc; - struct nxb_softc *sc = nx->nx_sc; - struct nxb_port *nxp = nx->nx_port; - u_int32_t val; - - switch (nxp->nxp_mode) { - case NXNIU_MODE_XGE: - imr->ifm_active = IFM_ETHER | nxp->nxp_phy | IFM_FDX; - imr->ifm_status = IFM_AVALID; - nx_link_state(nx); - if (!LINK_STATE_IS_UP(ifp->if_link_state)) - break; - imr->ifm_status |= IFM_ACTIVE; - - /* Flow control */ - imr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; - val = nxb_readcrb(sc, NXNIU_XGE_PAUSE_CONTROL); - if (((val >> NXNIU_XGE_PAUSE_S(nxp->nxp_id)) & - NXNIU_XGE_PAUSE_M) == 0) - imr->ifm_active |= IFM_ETH_TXPAUSE; - break; - case NXNIU_MODE_GBE: - mii_pollstat(&nx->nx_mii); - imr->ifm_active = nx->nx_mii.mii_media_active; - imr->ifm_status = nx->nx_mii.mii_media_status; - mii_mediachg(&nx->nx_mii); - break; - } -} - -void -nx_link_state(struct nx_softc *nx) -{ - struct nxb_port *nxp = nx->nx_port; - struct nxb_softc *sc = nx->nx_sc; - struct ifnet *ifp = &nx->nx_ac.ac_if; - u_int32_t status = 0; - int link_state = LINK_STATE_DOWN; - - switch (nxp->nxp_mode) { - case NXNIU_MODE_XGE: - status = nxb_readcrb(sc, NXSW_XG_STATE) >> (nxp->nxp_id * 8); - if (status & NXSW_XG_LINK_UP) - link_state = LINK_STATE_FULL_DUPLEX; - if (ifp->if_link_state != link_state) { - ifp->if_link_state = link_state; - if_link_state_change(ifp); - } - break; - case NXNIU_MODE_GBE: - mii_tick(&nx->nx_mii); - break; - } -} - -void -nx_watchdog(struct ifnet *ifp) -{ - return; -} - -int -nx_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) -{ - struct nx_softc *nx = (struct nx_softc *)ifp->if_softc; - struct ifaddr *ifa = (struct ifaddr *)data; - struct ifreq *ifr = (struct ifreq *)data; - int s, error = 0; - - s = splnet(); - - if ((error = ether_ioctl(ifp, &nx->nx_ac, cmd, data)) > 0) { - splx(s); - return (error); - } - - switch (cmd) { - case SIOCSIFADDR: - ifp->if_flags |= IFF_UP; -#ifdef INET - if (ifa->ifa_addr->sa_family == AF_INET) - arp_ifinit(&nx->nx_ac, ifa); -#endif - /* FALLTHROUGH */ - case SIOCSIFFLAGS: - if (ifp->if_flags & IFF_UP) { - if (ifp->if_flags & IFF_RUNNING) - nx_iff(nx); - else - nx_init(ifp); - } else { - if (ifp->if_flags & IFF_RUNNING) - nx_stop(ifp); - } - break; - - case SIOCSIFMTU: - if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ifp->if_hardmtu) - error = EINVAL; - else if (ifp->if_mtu != ifr->ifr_mtu) - ifp->if_mtu = ifr->ifr_mtu; - break; - - case SIOCADDMULTI: - case SIOCDELMULTI: - error = (cmd == SIOCADDMULTI) ? - ether_addmulti(ifr, &nx->nx_ac) : - ether_delmulti(ifr, &nx->nx_ac); - break; - - case SIOCGIFMEDIA: - case SIOCSIFMEDIA: - error = ifmedia_ioctl(ifp, ifr, &nx->nx_mii.mii_media, cmd); - break; - - default: - error = ENOTTY; - } - - if (error == ENETRESET) { - if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == - (IFF_UP | IFF_RUNNING)) - nx_iff(nx); - error = 0; - } - - splx(s); - - return (error); -} - -void -nx_init(struct ifnet *ifp) -{ - struct nx_softc *nx = (struct nx_softc *)ifp->if_softc; - struct nxb_softc *sc = nx->nx_sc; - int s; - - if (sc->sc_state != NX_S_READY) - return; - - s = splnet(); - - if (nxb_wait(sc, NXSW_PORTREG(nx, NXSW_RCVPEG_STATE), - NXSW_RCVPEG_INIT_DONE, NXSW_RCVPEG_STATE_M, 1, 2000) != 0) { - printf("%s: receive engine not ready, code 0x%x\n", - DEVNAME(nx), nx_readcrb(nx, NXSW_RCVPEG_STATE)); - goto done; - } - - nx_setlladdr(nx, LLADDR(ifp->if_sadl)); - - if (nx_init_rings(nx) != 0) - goto done; - - /* Set and enable interrupts */ - nxb_writecrb(sc, NXSW_GLOBAL_INT_COAL, 0); /* XXX */ - nxb_writecrb(sc, NXSW_INT_COAL_MODE, 0); /* XXX */ - nxb_writecrb(sc, NXISR_INT_MASK, NXISR_INT_MASK_ENABLE); - nxb_writecrb(sc, NXISR_INT_VECTOR, 0); - nxb_writecrb(sc, NXISR_TARGET_MASK, NXISR_TARGET_MASK_ENABLE); - - DPRINTF(NXDBG_INTR, "%s(%s) enabled interrupts\n", - DEVNAME(nx), __func__); - - ifp->if_flags |= IFF_RUNNING; - ifp->if_flags &= ~IFF_OACTIVE; - - done: - splx(s); -} - -void -nx_stop(struct ifnet *ifp) -{ - struct nx_softc *nx = (struct nx_softc *)ifp->if_softc; - struct nxb_softc *sc = nx->nx_sc; - int s; - - s = splnet(); - ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); - - /* Disable interrupts */ - nxb_writecrb(sc, NXISR_INT_MASK, 0); - nxb_writecrb(sc, NXISR_INT_VECTOR, 0); - nxb_writecrb(sc, NXISR_TARGET_MASK, 0); - - nx_free_rings(nx); - splx(s); -} - -#define NX_INC(_x, _y) (_x) = ((_x) + 1) % (_y) -#define NX_TXURN_WARN(_rd) ((_rd)->rd_txpending >= (NX_MAX_TX_DESC - 5)) -#define NX_TXURN(_rd) ((_rd)->rd_txpending >= NX_MAX_TX_DESC) - -void -nx_start(struct ifnet *ifp) -{ - struct nx_softc *nx = (struct nx_softc *)ifp->if_softc; - struct nxb_softc *sc = nx->nx_sc; - struct nxb_port *nxp = nx->nx_port; - struct nx_ringdata *rd = nx->nx_rings; - struct nxb_dmamem *txm; - struct mbuf *m; - struct nx_buf *nb; - struct nx_txdesc *txd; - bus_dmamap_t map; - u_int64_t port = nxp->nxp_id, nsegs, len; - u_int32_t producer; - u_int i, idx, tx = 0; - - if ((ifp->if_flags & IFF_RUNNING) == 0|| - (ifp->if_flags & IFF_OACTIVE) || - IFQ_IS_EMPTY(&ifp->if_snd)) - return; - - txm = &rd->rd_txdma; - producer = rd->rd_txproducer; - - for (;;) { - if (NX_TXURN(rd)) { - ifp->if_flags |= IFF_OACTIVE; - break; - } - - IFQ_POLL(&ifp->if_snd, m); - if (m == NULL) - break; - - idx = rd->rd_txproducer; - if (idx >= NX_MAX_TX_DESC) { - printf("%s: tx idx is corrupt\n", DEVNAME(nx)); - ifp->if_oerrors++; - break; - } - - txd = &rd->rd_txring[idx]; - bzero(txd, sizeof(*txd)); - - nb = &rd->rd_txbuf[idx]; - if (nb->nb_m != NULL) { - printf("%s: tx ring is corrupt\n", DEVNAME(nx)); - ifp->if_oerrors++; - break; - } - - /* - * we're committed to sending it now. if we cant map it into - * dma memory then we drop it. - */ - IFQ_DEQUEUE(&ifp->if_snd, m); - map = nb->nb_dmamap; - if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, - BUS_DMA_NOWAIT) != 0) { - m_freem(m); - printf("%s: could not load mbuf dma map", DEVNAME(nx)); - ifp->if_oerrors++; - break; - } - if (map->dm_nsegs > 4) { - m_freem(m); - printf("%s: too many segments for tx", DEVNAME(nx)); - ifp->if_oerrors++; - break; - } - nb->nb_m = m; - -#if NBPFILTER > 0 - if (ifp->if_bpf) - bpf_mtap(ifp->if_bpf, nb->nb_m, BPF_DIRECTION_OUT); -#endif - - len = 0; - nsegs = map->dm_nsegs; - txd->tx_buflength = 0; - for (i = 0; i < nsegs; i++) { - len += map->dm_segs[i].ds_len; - switch (i) { - case 0: - txd->tx_buflength |= - htole64((map->dm_segs[i].ds_len << - NX_TXDESC_BUFLENGTH1_S) & - NX_TXDESC_BUFLENGTH1_M); - txd->tx_addr1 = - htole64(map->dm_segs[i].ds_addr); - break; - case 1: - txd->tx_buflength |= - htole64((map->dm_segs[i].ds_len << - NX_TXDESC_BUFLENGTH2_S) & - NX_TXDESC_BUFLENGTH2_M); - txd->tx_addr2 = - htole64(map->dm_segs[i].ds_addr); - break; - case 2: - txd->tx_buflength |= - htole64(((u_int64_t) - map->dm_segs[i].ds_len << - NX_TXDESC_BUFLENGTH3_S) & - NX_TXDESC_BUFLENGTH3_M); - txd->tx_addr3 = - htole64(map->dm_segs[i].ds_addr); - break; - case 3: - txd->tx_buflength |= - htole64(((u_int64_t) - map->dm_segs[i].ds_len << - NX_TXDESC_BUFLENGTH4_S) & - NX_TXDESC_BUFLENGTH4_M); - txd->tx_addr4 = - htole64(map->dm_segs[i].ds_addr); - break; - } - } - txd->tx_word0 = htole64( - ((NX_TXDESC0_OP_TX << NX_TXDESC0_OP_S) & NX_TXDESC0_OP_M) | - ((nsegs << NX_TXDESC0_NBUF_S) & NX_TXDESC0_NBUF_M) | - ((len << NX_TXDESC0_LENGTH_S) & NX_TXDESC0_LENGTH_M)); - txd->tx_word2 = htole64( - ((idx << NX_TXDESC2_HANDLE_S) & NX_TXDESC2_HANDLE_M) | - ((port << NX_TXDESC2_PORT_S) & NX_TXDESC2_PORT_M) | - ((port << NX_TXDESC2_CTXID_S) & NX_TXDESC2_CTXID_M)); - - DPRINTF(NXDBG_TX, "%s(%s): txd w0:%016llx w2:%016llx " - "a1:%016llx a2:%016llx a3:%016llx a4:%016llx len:%016llx\n", - DEVNAME(nx), __func__, txd->tx_word0, txd->tx_word2, - txd->tx_addr1, txd->tx_addr2, txd->tx_addr3, txd->tx_addr4, - txd->tx_buflength); - - bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, - BUS_DMASYNC_PREWRITE); - - ifp->if_opackets++; - rd->rd_txpending++; - - NX_INC(rd->rd_txproducer, NX_MAX_TX_DESC); - - tx = 1; - } - - bus_dmamap_sync(sc->sc_dmat, txm->nxm_map, 0, txm->nxm_size, - BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); - - if (tx) { - DPRINTF(NXDBG_TX, "%s(%s): producer 0x%08x\n", - DEVNAME(nx), __func__, producer); - nxb_writecrb(sc, NXSW_CMD_PRODUCER_OFF, producer); - - /* Ring... */ - nx_doorbell(nx, NXDB_PEGID_TX, - NXDB_OPCODE_CMD_PROD, producer); - } - - return; -} - -void -nx_iff(struct nx_softc *nx) -{ - return; -} - -void -nx_tick(void *arg) -{ - struct nx_softc *nx = (struct nx_softc *)arg; - struct nxb_softc *sc = nx->nx_sc; - - if (sc->sc_state != NX_S_READY) - goto done; - - nx_link_state(nx); - - done: - timeout_add(&nx->nx_tick, hz); -} - -int -nx_intr(void *arg) -{ - struct nx_softc *nx = (struct nx_softc *)arg; - struct nxb_port *nxp = nx->nx_port; - struct nxb_softc *sc = nx->nx_sc; - u_int32_t inv; - u_int i; - - if (sc->sc_state != NX_S_READY) - return (0); - - /* Is the interrupt for us? */ - inv = nxb_read(sc, NXISR_INT_VECTOR); - if ((inv & NXISR_INT_VECTOR_PORT(nxp->nxp_id)) == 0) - return (0); - DPRINTF(NXDBG_INTR, "%s(%s): int vector 0x%08x\n", - DEVNAME(nx), __func__, inv); - - nxb_writecrb(sc, NXISR_INT_MASK, NXISR_INT_MASK_DISABLE); - for (i = 0; i < 32; i++) { - nxb_writecrb(sc, NXISR_TARGET_MASK, NXISR_TARGET_MASK_DISABLE); - inv = nxb_readcrb(sc, NXISR_INT_VECTOR); - if ((inv & NXISR_INT_VECTOR_PORT(nxp->nxp_id)) == 0) - break; - } - if (inv) - printf("%s: failed to disable interrupt\n", DEVNAME(nx)); - - /* Ring... */ - DPRINTF(NXDBG_INTR, "%s(%s): consumer 0x%08x\n", - DEVNAME(nx), __func__, nx->nx_rc->rc_txconsumer); - - nxb_writecrb(sc, NXISR_INT_MASK, NXISR_INT_MASK_ENABLE); - - return (1); -} - -void -nx_setlladdr(struct nx_softc *nx, u_int8_t *lladdr) -{ - struct nxb_softc *sc = nx->nx_sc; - - nxb_set_crbwindow(sc, NXMEMMAP_WINDOW0_START); - bus_space_write_region_1(sc->sc_memt, nx->nx_memh, - NX_XGE_STATION_ADDR_HI, lladdr, ETHER_ADDR_LEN); - bus_space_barrier(sc->sc_memt, nx->nx_memh, - NX_XGE_STATION_ADDR_HI, ETHER_ADDR_LEN, BUS_SPACE_BARRIER_WRITE); -} - -void -nx_doorbell(struct nx_softc *nx, u_int8_t id, u_int8_t cmd, u_int32_t count) -{ - struct nxb_softc *sc = nx->nx_sc; - struct nxb_port *nxp = nx->nx_port; - u_int32_t data; - - /* Create the doorbell message */ - data = ((NXDB_PEGID_S << id) & NXDB_PEGID_M) | - ((NXDB_COUNT_S << count) & NXDB_COUNT_M) | - ((NXDB_CTXID_S << nxp->nxp_id) & NXDB_CTXID_M) | - ((NXDB_OPCODE_S << cmd) & NXDB_OPCODE_M) | - NXDB_PRIVID; - - bus_space_write_4(sc->sc_dbmemt, sc->sc_dbmemh, 0, data); - bus_space_barrier(sc->sc_dbmemt, sc->sc_dbmemh, 0, 4, - BUS_SPACE_BARRIER_WRITE); -} - -u_int32_t -nx_readphy(struct nx_softc *nx, bus_size_t reg) -{ - struct nxb_softc *sc = nx->nx_sc; - - nxb_set_crbwindow(sc, NXMEMMAP_WINDOW0_START); - bus_space_barrier(sc->sc_memt, nx->nx_memh, reg, 4, - BUS_SPACE_BARRIER_READ); - return (bus_space_read_4(sc->sc_memt, nx->nx_memh, reg)); -} - -void -nx_writephy(struct nx_softc *nx, bus_size_t reg, u_int32_t val) -{ - struct nxb_softc *sc = nx->nx_sc; - - nxb_set_crbwindow(sc, NXMEMMAP_WINDOW0_START); - bus_space_write_4(sc->sc_memt, nx->nx_memh, reg, val); - bus_space_barrier(sc->sc_memt, nx->nx_memh, reg, 4, - BUS_SPACE_BARRIER_WRITE); -} - -u_int32_t -nx_readcrb(struct nx_softc *nx, enum nxsw_portreg n) -{ - struct nxb_softc *sc = nx->nx_sc; - u_int32_t reg; - - reg = NXSW_PORTREG(nx, n); - nxb_set_crbwindow(sc, NXMEMMAP_WINDOW1_START); - bus_space_barrier(sc->sc_memt, sc->sc_memh, reg, 4, - BUS_SPACE_BARRIER_READ); - return (bus_space_read_4(sc->sc_memt, sc->sc_memh, reg)); -} - -void -nx_writecrb(struct nx_softc *nx, enum nxsw_portreg n, u_int32_t val) -{ - struct nxb_softc *sc = nx->nx_sc; - u_int32_t reg; - - reg = NXSW_PORTREG(nx, n); - nxb_set_crbwindow(sc, NXMEMMAP_WINDOW1_START); - bus_space_write_4(sc->sc_memt, sc->sc_memh, reg, val); - bus_space_barrier(sc->sc_memt, sc->sc_memh, reg, 4, - BUS_SPACE_BARRIER_WRITE); -} - -int -nx_alloc(struct nx_softc *nx) -{ - struct nxb_softc *sc = nx->nx_sc; - struct nxb_port *nxp = nx->nx_port; - struct nxb_dmamem *nxm; - struct nx_ringcontext *rc; - u_int64_t addr; - - /* - * One DMA'ed ring context per virtual port - */ - nxm = &nx->nx_rcdma; - if (nxb_dmamem_alloc(sc, nxm, sizeof(*rc), "ringcontext") != 0) - return (1); - - rc = (struct nx_ringcontext *)nxm->nxm_kva; - - /* Initialize the ring context */ - rc->rc_id = htole32(nxp->nxp_id); - addr = nxm->nxm_map->dm_segs[0].ds_addr + /* physaddr */ - offsetof(struct nx_ringcontext, rc_txconsumer); - rc->rc_txconsumeroff = htole64(addr); - nx->nx_rc = rc; - - /* - * Ring data used by the driver - */ - nx->nx_rings = (struct nx_ringdata *) - malloc(sizeof(struct nx_ringdata), M_NOWAIT, M_DEVBUF); - if (nx->nx_rings == NULL) { - nxb_dmamem_free(sc, nxm); - return (1); - } - bzero(nx->nx_rings, sizeof(struct nx_ringdata)); - - return (0); -} - -void -nx_free(struct nx_softc *nx) -{ - struct nxb_softc *sc = nx->nx_sc; - nxb_dmamem_free(sc, &nx->nx_rcdma); -} - -struct mbuf * -nx_getbuf(struct nx_softc *nx, bus_dmamap_t map, int wait) -{ - struct nxb_softc *sc = nx->nx_sc; - struct mbuf *m = NULL; - - MGETHDR(m, wait ? M_WAIT : M_DONTWAIT, MT_DATA); - if (m == NULL) - goto merr; - - MCLGET(m, wait ? M_WAIT : M_DONTWAIT); - if ((m->m_flags & M_EXT) == 0) - goto merr; - m->m_len = m->m_pkthdr.len = MCLBYTES; - - if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, - wait ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT) != 0) { - printf("%s: could not load mbuf dma map", DEVNAME(nx)); - goto err; - } - - return (m); - merr: - printf("%s: unable to allocate mbuf", DEVNAME(nx)); - err: - if (m != NULL) - m_freem(m); - return (NULL); -} - -int -nx_init_rings(struct nx_softc *nx) -{ - struct nxb_softc *sc = nx->nx_sc; - struct nxb_port *nxp = nx->nx_port; - struct nxb_dmamem *nxm; - struct nx_ringcontext *rc = nx->nx_rc; - struct nx_ringdata *rd = nx->nx_rings; - struct nx_rxcontext *rxc; - struct nx_buf *nb; - struct nx_rxdesc *rxd; - u_int64_t addr; - int i, size; - - nxm = &nx->nx_rcdma; - bus_dmamap_sync(sc->sc_dmat, nxm->nxm_map, 0, nxm->nxm_size, - BUS_DMASYNC_PREWRITE); - - /* - * Rx descriptors - */ - nxm = &rd->rd_rxdma; - size = NX_MAX_RX_DESC * sizeof(struct nx_rxdesc); - if (nxb_dmamem_alloc(sc, nxm, size, "rxdesc") != 0) { - printf("%s: failed to alloc rx dma memory\n", - DEVNAME(nx)); - return (1); - } - - rd->rd_rxring = (struct nx_rxdesc *)nxm->nxm_kva; - addr = nxm->nxm_map->dm_segs[0].ds_addr; - rxc = &rc->rc_rxcontext[NX_RX_CONTEXT]; - rxc->rxc_ringaddr = htole64(addr); - rxc->rxc_ringsize = htole32(NX_MAX_RX_DESC); - - /* Rx buffers */ - for (i = 0; i < NX_MAX_RX_DESC; i++) { - nb = &rd->rd_rxbuf[i]; - rxd = rd->rd_rxring + i; - - if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, - MCLBYTES, 0, BUS_DMA_NOWAIT, &nb->nb_dmamap) != 0) { - printf("%s: unable to create dmamap for rx %d\n", - DEVNAME(nx), i); - goto fail; - } - - nb->nb_m = nx_getbuf(nx, nb->nb_dmamap, NX_NOWAIT); - if (nb->nb_m == NULL) { - bus_dmamap_destroy(sc->sc_dmat, nb->nb_dmamap); - goto fail; - } - - bus_dmamap_sync(sc->sc_dmat, nb->nb_dmamap, 0, - nb->nb_m->m_pkthdr.len, BUS_DMASYNC_PREREAD); - - addr = nb->nb_dmamap->dm_segs[0].ds_addr; - rxd->rx_addr = htole64(addr); - rxd->rx_length = htole32(nb->nb_m->m_pkthdr.len); - rxd->rx_handle = htole16(i); - } - - /* XXX Jumbo Rx descriptors/buffers */ - - /* - * Rx status descriptors - */ - nxm = &rd->rd_statusdma; - size = NX_MAX_STATUS_DESC * sizeof(struct nx_statusdesc); - if (nxb_dmamem_alloc(sc, nxm, size, "statusdesc") != 0) { - printf("%s: failed to alloc status dma memory\n", - DEVNAME(nx)); - return (1); - } - - rd->rd_statusring = (struct nx_statusdesc *)nxm->nxm_kva; - addr = nxm->nxm_map->dm_segs[0].ds_addr; - rc->rc_statusringaddr = htole64(addr); - rc->rc_statusringsize = htole32(NX_MAX_STATUS_DESC); - - /* - * Tx descriptors - */ - nxm = &rd->rd_txdma; - size = NX_MAX_TX_DESC * sizeof(struct nx_txdesc); - if (nxb_dmamem_alloc(sc, nxm, size, "txdesc") != 0) { - printf("%s: failed to alloc tx dma memory\n", - DEVNAME(nx)); - return (1); - } - - rd->rd_txring = (struct nx_txdesc *)nxm->nxm_kva; - addr = nxm->nxm_map->dm_segs[0].ds_addr; - rc->rc_txringaddr = htole64(addr); - rc->rc_txringsize = htole32(NX_MAX_TX_DESC); - - /* Tx buffers */ - for (i = 0; i < NX_MAX_TX_DESC; i++) { - nb = &rd->rd_txbuf[i]; - if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 4, - MCLBYTES, 0, BUS_DMA_NOWAIT, &nb->nb_dmamap) != 0) { - printf("%s: unable to create dmamap for tx %d\n", - DEVNAME(nx), i); - goto fail; - } - nb->nb_m = NULL; - } - - /* - * Sync DMA and write the ring context address to hardware - */ - nxm = &nx->nx_rcdma; - bus_dmamap_sync(sc->sc_dmat, nxm->nxm_map, 0, nxm->nxm_size, - BUS_DMASYNC_POSTWRITE); - - addr = nxm->nxm_map->dm_segs[0].ds_addr; - nx_writecrb(nx, NXSW_CONTEXT_ADDR_LO, addr & 0xffffffff); - nx_writecrb(nx, NXSW_CONTEXT_ADDR_HI, addr >> 32); - nx_writecrb(nx, NXSW_CONTEXT, nxp->nxp_id | NXSW_CONTEXT_SIG); - - return (0); - - fail: - nx_free_rings(nx); - return (1); -} - -void -nx_free_rings(struct nx_softc *nx) -{ - struct nxb_softc *sc = nx->nx_sc; - struct nxb_port *nxp = nx->nx_port; - struct nx_ringdata *rd = nx->nx_rings; - struct nxb_dmamem *nxm; - struct nx_buf *nb; - int i; - - for (i = 0; i < NX_MAX_RX_DESC; i++) { - nb = &rd->rd_rxbuf[i]; - if (nb->nb_dmamap == NULL) - continue; - bus_dmamap_sync(sc->sc_dmat, nb->nb_dmamap, 0, - nb->nb_m->m_pkthdr.len, BUS_DMASYNC_POSTREAD); - bus_dmamap_unload(sc->sc_dmat, nb->nb_dmamap); - bus_dmamap_destroy(sc->sc_dmat, nb->nb_dmamap); - if (nb->nb_m != NULL) - m_freem(nb->nb_m); - nb->nb_m = NULL; - } - - for (i = 0; i < NX_MAX_TX_DESC; i++) { - nb = &rd->rd_txbuf[i]; - if (nb->nb_dmamap == NULL) - continue; - bus_dmamap_destroy(sc->sc_dmat, nb->nb_dmamap); - if (nb->nb_m != NULL) - m_freem(nb->nb_m); - nb->nb_m = NULL; - } - - if (rd->rd_rxdma.nxm_size) - nxb_dmamem_free(sc, &rd->rd_rxdma); - if (rd->rd_statusdma.nxm_size) - nxb_dmamem_free(sc, &rd->rd_statusdma); - if (rd->rd_txdma.nxm_size) - nxb_dmamem_free(sc, &rd->rd_txdma); - - nxm = &nx->nx_rcdma; - bzero(nx->nx_rc, sizeof(struct nx_ringcontext)); - bus_dmamap_sync(sc->sc_dmat, nxm->nxm_map, 0, nxm->nxm_size, - BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); - - nx_writecrb(nx, NXSW_CONTEXT_ADDR_LO, 0); - nx_writecrb(nx, NXSW_CONTEXT_ADDR_HI, 0); - nx_writecrb(nx, NXSW_CONTEXT_SIG, nxp->nxp_id | NXSW_CONTEXT_RESET); -} diff --git a/sys/dev/pci/if_nxreg.h b/sys/dev/pci/if_nxreg.h deleted file mode 100644 index 067d448d9f9..00000000000 --- a/sys/dev/pci/if_nxreg.h +++ /dev/null @@ -1,782 +0,0 @@ -/* $OpenBSD: if_nxreg.h,v 1.28 2007/05/28 19:44:15 reyk Exp $ */ - -/* - * Copyright (c) 2007 Reyk Floeter <reyk@openbsd.org> - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/* - * NetXen NX2031/NX2035 register definitions partially based on: - * http://www.netxen.com/products/downloads/ - * Ethernet_Driver_Ref_Guide_Open_Source.pdf - */ - -#ifndef _NX_REG_H -#define _NX_REG_H - -/* - * Common definitions - */ - -#define NX_MAX_PORTS 4 -#define NX_MAX_MTU ETHER_MTU - -#define NX_MAX_TX_DESC 128 /* XXX 4096 */ -#define NX_MAX_RX_DESC 128 /* XXX 32768 */ -#define NX_MAX_JUMBO_DESC 64 /* XXX 1024 */ -#define NX_MAX_TSO_DESC 32 /* XXX 64 */ -#define NX_MAX_STATUS_DESC NX_MAX_RX_DESC - -#define NX_JUMBO_MTU 8000 /* less than 9k */ -#define NX_DMA_ALIGN 8 /* 64bit alignment */ -#define NX_POLL_SENSOR 10 /* read temp sensor every 10s */ - -#define NX_WAIT 1 -#define NX_NOWAIT 0 - -/* This driver supported the 3.4.31 (3.4.xx) NIC firmware */ -#define NX_FIRMWARE_MAJOR 3 -#define NX_FIRMWARE_MINOR 4 -#define NX_FIRMWARE_BUILD 31 - -#define NX_FIRMWARE_VER ( \ - (NX_FIRMWARE_MAJOR << 16) | (NX_FIRMWARE_MINOR << 8) | \ - NX_FIRMWARE_BUILD \ -) - -/* Used to indicate various states of the NIC and its firmware */ -enum nx_state { - NX_S_FAIL = -1, /* Failed to initialize the device */ - NX_S_OFFLINE = 0, /* Firmware is not active yet */ - NX_S_RESET = 2, /* Firmware is in reset state */ - NX_S_BOOT = 3, /* Chipset is booting the firmware */ - NX_S_LOADED = 4, /* Firmware is loaded but not initialized */ - NX_S_RELOADED = 5, /* Firmware is reloaded and initialized */ - NX_S_READY = 6 /* Device has been initialized and is ready */ -}; - -/* - * Hardware descriptors - */ - -struct nx_txdesc { - u_int64_t tx_word0; -#define NX_TXDESC0_TCPHDROFF_S 0 /* TCP header offset */ -#define NX_TXDESC0_TCPHDROFF_M 0x00000000000000ffULL -#define NX_TXDESC0_IPHDROFF_S 8 /* IP header offset */ -#define NX_TXDESC0_IPHDROFF_M 0x000000000000ff00 -#define NX_TXDESC0_F_S 16 /* flags */ -#define NX_TXDESC0_F_M 0x00000000007f0000ULL -#define NX_TXDESC0_F_VLAN (1<<8) /* VLAN tagged */ -#define NX_TXDESC0_F_TSO (1<<1) /* TSO enabled */ -#define NX_TXDESC0_F_CKSUM (1<<0) /* checksum enabled */ -#define NX_TXDESC0_OP_S 23 /* opcode */ -#define NX_TXDESC0_OP_M 0x000000001f800000ULL -#define NX_TXDESC0_OP_TX_TSO (1<<4) /* TCP packet, do TSO */ -#define NX_TXDESC0_OP_TX_IP (1<<3) /* IP packet, compute cksum */ -#define NX_TXDESC0_OP_TX_UDP (1<<2) /* UDP packet, compute cksum */ -#define NX_TXDESC0_OP_TX_TCP (1<<1) /* TCP packet, compute cksum */ -#define NX_TXDESC0_OP_TX (1<<0) /* raw Ethernet packet */ -#define NX_TXDESC0_RES0_S 29 /* Reserved */ -#define NX_TXDESC0_RES0_M 0x00000000e0000000ULL -#define NX_TXDESC0_NBUF_S 32 /* number of buffers */ -#define NX_TXDESC0_NBUF_M 0x000000ff00000000ULL -#define NX_TXDESC0_LENGTH_S 40 /* length */ -#define NX_TXDESC0_LENGTH_M 0xffffff0000000000ULL - u_int64_t tx_addr2; /* address of buffer 2 */ - u_int64_t tx_word2; -#define NX_TXDESC2_HANDLE_S 0 /* handle of the buffer */ -#define NX_TXDESC2_HANDLE_M 0x000000000000ffffULL -#define NX_TXDESC2_MSS_S 16 /* MSS for the packet */ -#define NX_TXDESC2_MSS_M 0x00000000ffff0000ULL -#define NX_TXDESC2_PORT_S 32 /* interface port */ -#define NX_TXDESC2_PORT_M 0x0000000f00000000ULL -#define NX_TXDESC2_CTXID_S 36 /* context ID */ -#define NX_TXDESC2_CTXID_M 0x000000f000000000ULL -#define NX_TXDESC2_HDRLENGTH_S 40 /* MAC+IP+TCP length for TSO */ -#define NX_TXDESC2_HDRLENGTH_M 0x0000ff0000000000ULL -#define NX_TXDESC2_IPSECID_S 48 /* IPsec offloading SA/ID */ -#define NX_TXDESC2_IPSECID_M 0xffff000000000000ULL - u_int64_t tx_addr3; /* address of buffer 3 */ - u_int64_t tx_addr1; /* address of buffer 1 */ - u_int64_t tx_buflength; -#define NX_TXDESC_BUFLENGTH1_S 0 /* length of buffer 1 */ -#define NX_TXDESC_BUFLENGTH1_M 0x000000000000ffffULL -#define NX_TXDESC_BUFLENGTH2_S 16 /* length of buffer 2 */ -#define NX_TXDESC_BUFLENGTH2_M 0x00000000ffff0000ULL -#define NX_TXDESC_BUFLENGTH3_S 32 /* length of buffer 3 */ -#define NX_TXDESC_BUFLENGTH3_M 0x0000ffff00000000ULL -#define NX_TXDESC_BUFLENGTH4_S 48 /* length of buffer 4 */ -#define NX_TXDESC_BUFLENGTH4_M 0xffff000000000000ULL - u_int64_t tx_addr4; /* address of buffer 4 */ - u_int64_t tx_word7; /* reserved */ -} __packed; - -struct nx_rxdesc { - u_int16_t rx_handle; /* handle of the buffer */ - u_int16_t rx_reserved; - u_int32_t rx_length; /* length of the buffer */ - u_int64_t rx_addr; /* address of buffer */ -} __packed; - -struct nx_statusdesc { - u_int16_t rx_port; -#define NX_STSDESC_PORT_S 0 /* interface port */ -#define NX_STSDESC_PORT_M 0x000f -#define NX_STSDESC_STS_S 4 /* completion status */ -#define NX_STSDESC_STS_M 0x00f0 -#define NX_STSDESC_STS_NOCHK 1 /* checksum not verified */ -#define NX_STSDESC_STS_CHKOK 2 /* checksum verified ok */ -#define NX_STSDESC_TYPE_S 8 /* type/index of the ring */ -#define NX_STSDESC_TYPE_M 0x0f00 -#define NX_STSDESC_OPCODE_S 12 /* opcode */ -#define NX_STSDESC_OPCODE_M 0xf000 -#define NX_STSDESC_OPCODE 0xa /* received packet */ - u_int16_t rx_length; /* total length of the packet */ - u_int16_t rx_handle; /* handle of the buffer */ - u_int16_t rx_owner; -#define NX_STSDESC_OWNER_S 0 /* owner of the descriptor */ -#define NX_STSDESC_OWNER_M 0x0003 -#define NX_STSDESC_OWNER_HOST 1 /* owner is the host (t.b.d) */ -#define NX_STSDESC_OWNER_CARD 2 /* owner is the card */ -#define NX_STSDESC_PROTO_S 2 /* protocol type */ -#define NX_STSDESC_PROTO_M 0x003c -} __packed; - -struct nx_rxcontext { - u_int64_t rxc_ringaddr; - u_int32_t rxc_ringsize; - u_int32_t rxc_reserved; -} __packed; - -#define NX_NRXCONTEXT 3 -#define NX_RX_CONTEXT 0 -#define NX_JUMBO_CONTEXT 1 -#define NX_TSO_CONTEXT 2 - -/* DMA-mapped ring context for the Rx, Tx, and Status rings */ -struct nx_ringcontext { - u_int64_t rc_txconsumeroff; - u_int64_t rc_txringaddr; - u_int32_t rc_txringsize; - u_int32_t rc_reserved; - - struct nx_rxcontext rc_rxcontext[NX_NRXCONTEXT]; - - u_int64_t rc_statusringaddr; - u_int32_t rc_statusringsize; - - u_int32_t rc_id; /* context identifier */ - - /* d3 state register, dummy dma address */ - u_int64_t rc_reserved1; - u_int64_t rc_reserved2; - - u_int32_t rc_txconsumer; -} __packed; - -/* - * Memory layout - */ - -#define NXBAR0 PCI_MAPREG_START -#define NXBAR4 (PCI_MAPREG_START + 16) - -/* PCI memory setup */ -#define NXPCIMEM_SIZE_128MB 0x08000000 /* 128MB size */ -#define NXPCIMEM_SIZE_32MB 0x02000000 /* 32MB size */ - -/* PCI memory address ranges */ -#define NXADDR_DDR_NET 0x0000000000000000ULL -#define NXADDR_DDR_NET_END 0x000000000fffffffULL -#define NXADDR_PCIE 0x0000000800000000ULL -#define NXADDR_PCIE_END 0x0000000fffffffffULL -#define NXADDR_OCM0 0x0000000200000000ULL -#define NXADDR_OCM0_END 0x00000002000fffffULL -#define NXADDR_OCM1 0x0000000200400000ULL -#define NXADDR_OCM1_END 0x00000002004fffffULL -#define NXADDR_QDR_NET 0x0000000300000000ULL -#define NXADDR_QDR_NET_END 0x00000003001fffffULL - -/* Memory mapping in the default PCI window */ -#define NXPCIMAP_DDR_NET 0x00000000 -#define NXPCIMAP_DDR_MD 0x02000000 -#define NXPCIMAP_QDR_NET 0x04000000 -#define NXPCIMAP_DIRECT_CRB 0x04400000 -#define NXPCIMAP_OCM0 0x05000000 -#define NXPCIMAP_OCM1 0x05100000 -#define NXPCIMAP_CRB 0x06000000 - -/* Offsets inside NXPCIMAP_CRB */ -#define NXMEMMAP_PCIE_0 0x00100000 -#define NXMEMMAP_NIU 0x00600000 -#define NXMEMMAP_PPE_0 0x01100000 -#define NXMEMMAP_PPE_1 0x01200000 -#define NXMEMMAP_PPE_2 0x01300000 -#define NXMEMMAP_PPE_3 0x01400000 -#define NXMEMMAP_PPE_D 0x01500000 -#define NXMEMMAP_PPE_I 0x01600000 -#define NXMEMMAP_PCIE_1 0x02100000 -#define NXMEMMAP_SW 0x02200000 -#define NXMEMMAP_SIR 0x03200000 -#define NXMEMMAP_ROMUSB 0x03300000 - -/* NXPCIMAP_CRB window (total offsets) */ -#define NXMEMMAP_WINDOW_SIZE 0x02000000 -#define NXMEMMAP_WINDOW0_START 0x06000000 -#define NXMEMMAP_WINDOW0_END 0x07ffffff -#define NXMEMMAP_WINDOW1_START 0x08000000 -#define NXMEMMAP_WINDOW1_END 0x09ffffff - -#define NXMEMMAP_HWTRANS_M 0xfff00000 - -/* Window 0 register map */ -#define NXPCIE(_x) ((_x) + 0x06100000) /* PCI Express */ -#define NXNIU(_x) ((_x) + 0x06600000) /* Network Int Unit */ -#define NXPPE_0(_x) ((_x) + 0x07100000) /* PEGNET 0 */ -#define NXPPE_1(_x) ((_x) + 0x07200000) /* PEGNET 0 */ -#define NXPPE_2(_x) ((_x) + 0x07300000) /* PEGNET 0 */ -#define NXPPE_3(_x) ((_x) + 0x07400000) /* PEGNET 0 */ -#define NXPPE_D(_x) ((_x) + 0x07500000) /* PEGNET D-Cache */ -#define NXPPE_I(_x) ((_x) + 0x07600000) /* PEGNET I-Cache */ - -/* Window 1 register map */ -#define NXPCIE_1(_x) ((_x) + 0x08100000) /* PCI Express' */ -#define NXSW(_x) ((_x) + 0x08200000) /* Software defined */ -#define NXSIR(_x) ((_x) + 0x09200000) /* 2nd interrupt */ -#define NXROMUSB(_x) ((_x) + 0x09300000) /* ROMUSB */ - -/* The IMEZ/HMEZ NICs have multiple PCI functions with different registers */ -#define NXPCIE_FUNC(_r, _f) (NXPCIE(_r) + ((_f) * 0x20)) - -/* Flash layout */ -#define NXFLASHMAP_CRBINIT_0 0x00000000 /* CRBINIT */ -#define NXFLASHMAP_CRBINIT_M 0x7fffffff /* ROM memory barrier */ -#define NXFLASHMAP_CRBINIT_MAX 1023 /* Max CRBINIT entries */ -#define NXFLASHMAP_INFO 0x00004000 /* board configuration */ -#define NXFLASHMAP_INITCODE 0x00006000 /* chipset-specific code */ -#define NXFLASHMAP_BOOTLOADER 0x00010000 /* boot loader */ -#define NXFLASHMAP_BOOTLDSIZE 0x4000 /* boot loader size */ -#define NXFLASHMAP_FIRMWARE_0 0x00043000 /* compressed firmware image */ -#define NXFLASHMAP_FIRMWARE_1 0x00200000 /* backup firmware image */ -#define NXFLASHMAP_PXE 0x003d0000 /* PXE image */ -#define NXFLASHMAP_USER 0x003e8000 /* user-specific ares */ -#define NXFLASHMAP_VPD 0x003e8c00 /* vendor private data */ -#define NXFLASHMAP_LICENSE 0x003e9000 /* firmware license (?) */ -#define NXFLASHMAP_CRBINIT_1 0x003f0000 /* backup of CRBINIT */ - -/* - * Doorbell messages - */ - -/* Register in the doorbell memory region */ -#define NXDB 0x00000000 -#define NXDB_PEGID_M 0x00000003 /* Chipset unit */ -#define NXDB_PEGID_S 0 -#define NXDB_PEGID_RX 1 /* Rx unit */ -#define NXDB_PEGID_TX 2 /* Tx unit */ -#define NXDB_PRIVID 0x00000004 /* Must be set */ -#define NXDB_COUNT_M 0x0003fff8 /* Doorbell count */ -#define NXDB_COUNT_S 3 -#define NXDB_CTXID_M 0x0ffc0000 /* Context ID */ -#define NXDB_CTXID_S 18 -#define NXDB_OPCODE_M 0xf0000000 /* Doorbell opcode */ -#define NXDB_OPCODE_S 28 -#define NXDB_OPCODE_RCV_PROD 0 -#define NXDB_OPCODE_JRCV_PROD 1 -#define NXDB_OPCODE_TSO_PROD 2 -#define NXDB_OPCODE_CMD_PROD 3 -#define NXDB_OPCODE_UPD_CONS 4 -#define NXDB_OPCODE_RESET_CTX 5 - -/* - * PCI Express Registers - */ - -/* Interrupt Vector */ -#define NXISR_INT_VECTOR NXPCIE(0x00010100) -#define NXISR_INT_VECTOR_TARGET3 (1<<10) /* interrupt for function 3 */ -#define NXISR_INT_VECTOR_TARGET2 (1<<9) /* interrupt for function 2 */ -#define NXISR_INT_VECTOR_TARGET1 (1<<8) /* interrupt for function 1 */ -#define NXISR_INT_VECTOR_TARGET0 (1<<7) /* interrupt for function 0 */ -#define NXISR_INT_VECTOR_PORT(_n) (NXISR_INT_VECTOR_TARGET0 << (_n)) -#define NXISR_INT_VECTOR_RC_INT (1<<5) /* root complex interrupt */ - -/* Interrupt Mask */ -#define NXISR_INT_MASK NXPCIE(0x00010104) -#define NXISR_INT_MASK_TARGET3 (1<<10) /* mask for function 3 */ -#define NXISR_INT_MASK_TARGET2 (1<<9) /* mask for function 2 */ -#define NXISR_INT_MASK_TARGET1 (1<<8) /* mask for function 1 */ -#define NXISR_INT_MASK_TARGET0 (1<<7) /* mask for function 0 */ -#define NXISR_INT_MASK_PORT(_n) (NXISR_INT_MASK_TARGET0 << (_n)) -#define NXISR_INT_MASK_RC_INT (1<<5) /* root complex mask */ -#define NXISR_INT_MASK_ENABLE 0x0000077f -#define NXISR_INT_MASK_DISABLE 0x000007ff - -/* Interrupt target mask and status */ -#define NXISR_TARGET_STATUS NXPCIE(0x00010118) -#define NXISR_TARGET_MASK NXPCIE(0x00010128) -#define NXISR_TARGET_MASK_ENABLE 0x00000bff -#define NXISR_TARGET_MASK_DISABLE 0xffffffff - -/* Memory windows */ -#define NXDDR_WINDOW(_f) NXPCIE_FUNC(0x00010200, _f) -#define NXDDR_WINDOW_1 (1<<25) /* Set this flag for Win 1 */ -#define NXDDR_WINDOW_S 25 -#define NXDDR_WINDOW_M 0x000003ff -#define NXDDR_WINDOW_SIZE 0x02000000 -#define NXQDR_WINDOW(_f) NXPCIE_FUNC(0x00010208, _f) -#define NXQDR_WINDOW_1 (1<<25) /* Set this flag for Win 1 */ -#define NXQDR_WINDOW_S 22 -#define NXQDR_WINDOW_M 0x0000003f -#define NXQDR_WINDOW_SIZE 0x00400000 -#define NXCRB_WINDOW(_f) NXPCIE_FUNC(0x00010210, _f) -#define NXCRB_WINDOW_1 (1<<25) /* Set this flag for Win 1 */ -#define NXCRB_WINDOW_S 25 -#define NXCRB_WINDOW_M 0x00000004 -#define NXCRB_WINDOW_SIZE 0x02000000 - -/* Lock registers (semaphores between chipset and driver) */ -#define NXSEM_FLASH_LOCK NXPCIE_1(0x0001c010) /* Flash lock */ -#define NXSEM_FLASH_LOCK_M 0xffffffff -#define NXSEM_FLASH_LOCKED (1<<0) /* R/O: is locked */ -#define NXSEM_FLASH_UNLOCK NXPCIE_1(0x0001c014) /* Flash unlock */ -#define NXSEM_PHY_LOCK NXPCIE_1(0x0001c018) /* PHY lock */ -#define NXSEM_PHY_LOCK_M 0xffffffff -#define NXSEM_PHY_LOCKED (1<<0) /* R/O: is locked */ -#define NXSEM_PHY_UNLOCK PXPCIE_1(0x0001c01c) /* PHY unlock */ - -/* - * Network Interface Unit (NIU) registers - */ - -/* Mode Register (see also NXNIU_RESET_SYS_FIFOS) */ -#define NXNIU_MODE NXNIU(0x00000000) -#define NXNIU_MODE_XGE (1<<2) /* XGE interface enabled */ -#define NXNIU_MODE_GBE (1<<1) /* 4 GbE interfaces enabled */ -#define NXNIU_MODE_FC (1<<0) /* *Fibre Channel enabled */ -#define NXNIU_MODE_DEF NUI_XGE_ENABLE - -/* 10G - 1G Mode Enable Register */ -#define NXNIU_XG_SINGLE_TERM NXNIU(0x00000004) -#define NXNIU_XG_SINGLE_TERM_ENABLE (1<<0) /* Enable 10G + 1G mode */ -#define NXNIU_XG_SINGLE_TERM_DEF 0 /* Disabled */ - -/* XGE Reset Register */ -#define NXNIU_XG_RESET NXNIU(0x0000001c) -#define NXNIU_XG_RESET_CD (1<<1) /* Reset channels CD */ -#define NXNIU_XG_RESET_AB (1<<0) /* Reset channels AB */ -#define NXNIU_XG_RESET_DEF (NXNIU_XG_RESET_AB|NXNIU_XG_RESET_CD) - -/* Interrupt Mask Register */ -#define NXNIU_INT_MASK NXNIU(0x00000040) -#define NXNIU_INT_MASK_XG (1<<6) /* XGE Interrupt Mask */ -#define NXNIU_INT_MASK_RES5 (1<<5) /* Reserved bit */ -#define NXNIU_INT_MASK_RES4 (1<<4) /* Reserved bit */ -#define NXNIU_INT_MASK_GB3 (1<<3) /* GbE 3 Interrupt Mask */ -#define NXNIU_INT_MASK_GB2 (1<<2) /* GbE 2 Interrupt Mask */ -#define NXNIU_INT_MASK_GB1 (1<<1) /* GbE 1 Interrupt Mask */ -#define NXNIU_INT_MASK_GB0 (1<<0) /* GbE 0 Interrupt Mask */ -#define NXNIU_INT_MASK_DEF ( \ - NXNIU_INT_MASK_XG|NXNIU_INT_MASK_RES5|NXNIU_INT_MASK_RES4| \ - NXNIU_INT_MASK_GB3|NXNIU_INT_MASK_GB2|NXNIU_INT_MASK_GB1| \ - NXNIU_INT_MASK_GB0) /* Reserved bits enabled */ - -/* Reset System FIFOs Register (needed before changing NXNIU_MODE) */ -#define NXNIU_RESET_SYS_FIFOS NXNIU(0x00000088) -#define NXNIU_RESET_SYS_FIFOS_RX (1<<31) /* Reset all Rx FIFOs */ -#define NXNIU_RESET_SYS_FIFOS_TX (1<<0) /* Reset all Tx FIFOs */ -#define NXNIU_RESET_SYS_FIFOS_DEF 0 /* Disabled */ - -/* Flow control registers */ -#define NXNIU_XGE_PAUSE_CONTROL NXNIU(0x00000098) -#define NXNIU_XGE_PAUSE_S(_n) ((_n) * 3) -#define NXNIU_XGE_PAUSE_M 0x00000007 -#define NXNIU_XGE_PAUSE_DISABLED (1<<0) /* Tx Pause (always Rx) */ -#define NXNIU_XGE_PAUSE_REQUEST (1<<1) /* Request pause */ -#define NXNIU_XGE_PAUSE_ONOFF (1<<2) /* Request pause on/off */ -#define NXNIU_XGE_PAUSE_LEVEL NXNIU(0x000000dc) - -/* - * Port-specific NIU registers, will be mapped to a subregion - */ - -#define NXNIU_PORT_SIZE 0x00010000 -#define NXNIU_PORT(_r, _n) NXNIU((_r) + (_n) * NXNIU_PORT_SIZE) - -#define NXNIU_FC(_n) NXNIU_PORT(0x00010000, _n) -#define NXNIU_GBE(_n) NXNIU_PORT(0x00030000, _n) -#define NXNIU_XGE(_n) NXNIU_PORT(0x00070000, _n) - -/* XGE Configuration 0 Register */ -#define NX_XGE_CONFIG0 0x0000 -#define NXNIU_XGE_CONFIG0_SOFTRST_FIFO (1<<31) /* Soft reset FIFOs */ -#define NXNIU_XGE_CONFIG0_SOFTRST_MAC (1<<4) /* Soft reset XGE MAC */ -#define NXNIU_XGE_CONFIG0_RX_ENABLE (1<<2) /* Enable frame Rx */ -#define NXNIU_XGE_CONFIG0_TX_ENABLE (1<<0) /* Enable frame Tx */ -#define NXNIU_XGE_CONFIG0_DEF 0 /* Disabled */ - -/* XGE Configuration 1 Register */ -#define NX_XGE_CONFIG1 0x0004 -#define NXNIU_XGE_CONFIG1_PROMISC (1<<13) /* Pass all Rx frames */ -#define NXNIU_XGE_CONFIG1_MCAST_ENABLE (1<<12) /* Rx all multicast frames */ -#define NXNIU_XGE_CONFIG1_SEQ_ERROR (1<<10) /* Sequence error detection */ -#define NXNIU_XGE_CONFIG1_NO_PAUSE (1<<8) /* Ignore pause frames */ -#define NXNIU_XGE_CONFIG1_LOCALERR (1<<6) /* Wire local error */ -#define NXNIU_XGE_CONFIG1_LOCALERR_FE 0 /* Signal with 0xFE */ -#define NXNIU_XGE_CONFIG1_LOCALERR_I 1 /* Signal with Ierr */ -#define NXNIU_XGE_CONFIG1_NO_MAXSIZE (1<<5) /* Ignore max Rx size */ -#define NXNIU_XGE_CONFIG1_CRC_TX (1<<1) /* Append CRC to Tx frames */ -#define NXNIU_XGE_CONFIG1_CRC_RX (1<<0) /* Remove CRC from Rx frames */ -#define NXNIU_XGE_CONFIG1_DEF 0 /* Disabled */ - -/* XGE Station Address (lladdr) Register */ -#define NX_XGE_STATION_ADDR_HI 0x000c /* High lladdr */ -#define NX_XGE_STATION_ADDR_LO 0x0010 /* low lladdr */ - -/* - * Software defined registers (used by the firmware or the driver) - */ - -/* Chipset state registers */ -#define NXSW_ROM_LOCK_ID NXSW(0x2100) /* Used for locking the ROM */ -#define NXSW_ROM_LOCK_DRV 0x0d417340 /* Driver ROM lock ID */ -#define NXSW_PHY_LOCK_ID NXSW(0x2120) /* Used for locking the PHY */ -#define NXSW_PHY_LOCK_DRV 0x44524956 /* Driver PHY lock ID */ -#define NXSW_FW_VERSION_MAJOR NXSW(0x2150) /* Major f/w version */ -#define NXSW_FW_VERSION_MINOR NXSW(0x2154) /* Minor f/w version */ -#define NXSW_FW_VERSION_BUILD NXSW(0x2158) /* Build/Sub f/w version */ -#define NXSW_BOOTLD_CONFIG NXSW(0x21fc) -#define NXSW_BOOTLD_CONFIG_ROM 0x00000000 /* Load firmware from flasg */ -#define NXSW_BOOTLD_CONFIG_RAM 0x12345678 /* Load firmware from memory */ - -/* Misc SW registers */ -#define NXSW_CMD_PRODUCER_OFF NXSW(0x2208) /* Producer CMD ring index */ -#define NXSW_CMD_CONSUMER_OFF NXSW(0x220c) /* Consumer CMD ring index */ -#define NXSW_CMD_ADDR_HI NXSW(0x2218) /* CMD ring phys address */ -#define NXSW_CMD_ADDR_LO NXSW(0x221c) /* CMD ring phys address */ -#define NXSW_CMD_RING_SIZE NXSW(0x22c8) /* Entries in the CMD ring */ -#define NXSW_CMDPEG_STATE NXSW(0x2250) /* State of the firmware */ -#define NXSW_CMDPEG_STATE_M 0xffff /* State mask */ -#define NXSW_CMDPEG_INIT_START 0xff00 /* Start of initialization */ -#define NXSW_CMDPEG_INIT_DONE 0xff01 /* Initialization complete */ -#define NXSW_CMDPEG_INIT_ACK 0xf00f /* Initialization ACKed */ -#define NXSW_CMDPEG_INIT_FAIL 0xffff /* Initialization failed */ -#define NXSW_GLOBAL_INT_COAL NXSW(0x2264) /* Interrupt coalescing */ -#define NXSW_INT_COAL_MODE NXSW(0x2268) /* Reserved */ -#define NXSW_MAX_RCV_BUFS NXSW(0x226c) /* Interrupt tuning register */ -#define NXSW_TX_INT_THRESHOLD NXSW(0x2270) /* Interrupt tuning register */ -#define NXSW_RX_PKT_TIMER NXSW(0x2274) /* Interrupt tuning register */ -#define NXSW_TX_PKT_TIMER NXSW(0x2278) /* Interrupt tuning register */ -#define NXSW_RX_PKT_CNT NXSW(0x227c) /* Rx packet count register */ -#define NXSW_RX_TMR_CNT NXSW(0x2280) /* Rx timer count register */ -#define NXSW_XG_STATE NXSW(0x2294) /* PHY state register */ -#define NXSW_XG_LINK_UP (1<<4) /* 10G PHY state up */ -#define NXSW_XG_LINK_DOWN (1<<5) /* 10G PHY state down */ -#define NXSW_MPORT_MODE NXSW(0x22c4) /* Multi port mode */ -#define NXSW_MPORT_MODE_M 0xffff /* Mode mask */ -#define NXSW_MPORT_MODE_1FUNC 0x1111 /* Single function mode */ -#define NXSW_MPORT_MODE_NFUNC 0x2222 /* Multi function mode */ - -#define NXSW_TEMP NXSW(0x23b4) /* Temperature sensor */ -#define NXSW_TEMP_STATE_M 0x0000ffff /* Temp state mask */ -#define NXSW_TEMP_STATE_S 0 /* Temp state shift */ -#define NXSW_TEMP_STATE_NONE 0x0000 /* Temp state is UNSPEC */ -#define NXSW_TEMP_STATE_OK 0x0001 /* Temp state is OK */ -#define NXSW_TEMP_STATE_WARN 0x0002 /* Temp state is WARNING */ -#define NXSW_TEMP_STATE_CRIT 0x0003 /* Temp state is CRITICAL */ -#define NXSW_TEMP_VAL_M 0xffff0000 /* Temp deg celsius mask */ -#define NXSW_TEMP_VAL_S 16 /* Temp deg celsius shift */ -#define NXSW_DRIVER_VER NXSW(0x24a0) /* Host driver version */ - -/* - * Port-specific SW registers, cannot be mapped to a subregion because - * they're using different offsets between the registers. Ugh, we have to - * define a mapping table to avoid a ton of ugly if's in the code. - */ -enum nxsw_portreg { - NXSW_RCV_PRODUCER_OFF = 0, /* Producer Rx ring index */ - NXSW_RCV_CONSUMER_OFF, /* Consumer Rx ring index */ - NXSW_GLOBALRCV_RING, /* Address of Rx buffer */ - NXSW_RCV_RING_SIZE, /* Entries in the Rx ring */ - - NXSW_JRCV_PRODUCER_OFF, /* Producer jumbo ring index */ - NXSW_JRCV_CONSUMER_OFF, /* Consumer jumbo ring index */ - NXSW_GLOBALJRCV_RING, /* Address of jumbo buffer */ - NXSW_JRCV_RING_SIZE, /* Entries in the jumbo ring */ - - NXSW_TSO_PRODUCER_OFF, /* Producer TSO ring index */ - NXSW_TSO_CONSUMER_OFF, /* Consumer TSO ring index */ - NXSW_GLOBALOTSO_RING, /* Address of TSO buffer */ - NXSW_TSO_RING_SIZE, /* Entries in the TSO ring */ - - NXSW_STATUS_RING, /* Address of status ring */ - NXSW_STATUS_PROD, /* Producer status index */ - NXSW_STATUS_CONS, /* Consumer status index */ - NXSW_RCVPEG_STATE, /* State of the NX2031 */ -#define NXSW_RCVPEG_STATE_M 0xffff /* State mask */ -#define NXSW_RCVPEG_INIT_START 0xff00 /* Start of initialization */ -#define NXSW_RCVPEG_INIT_DONE 0xff01 /* Initialization complete */ -#define NXSW_RCVPEG_INIT_ACK 0xf00f /* Initialization ACKed */ -#define NXSW_RCVPEG_INIT_FAIL 0xffff /* Initialization failed */ - NXSW_STATUS_RING_SIZE, /* Entries in the status ring */ - - NXSW_CONTEXT_ADDR_LO, /* Low address of context */ - NXSW_CONTEXT, /* Context register */ -#define NXSW_CONTEXT_M 0xffff /* Context register mask */ -#define NXSW_CONTEXT_SIG 0xdee0 /* Context signature */ -#define NXSW_CONTEXT_RESET 0xbad0 /* Context reset */ - NXSW_CONTEXT_ADDR_HI, /* High address of context */ - - NXSW_PORTREG_MAX -}; -#define NXSW_PORTREGS { \ - { NXSW(0x2300), NXSW(0x2344), NXSW(0x23d8), NXSW(0x242c) }, \ - { NXSW(0x2304), NXSW(0x2348), NXSW(0x23dc), NXSW(0x2430) }, \ - { NXSW(0x2308), NXSW(0x234c), NXSW(0x23f0), NXSW(0x2434) }, \ - { NXSW(0x230c), NXSW(0x2350), NXSW(0x23f4), NXSW(0x2438) }, \ - \ - { NXSW(0x2310), NXSW(0x2354), NXSW(0x23f8), NXSW(0x243c) }, \ - { NXSW(0x2314), NXSW(0x2358), NXSW(0x23fc), NXSW(0x2440) }, \ - { NXSW(0x2318), NXSW(0x235c), NXSW(0x2400), NXSW(0x2444) }, \ - { NXSW(0x231c), NXSW(0x2360), NXSW(0x2404), NXSW(0x2448) }, \ - \ - { NXSW(0x2320), NXSW(0x2364), NXSW(0x2408), NXSW(0x244c) }, \ - { NXSW(0x2324), NXSW(0x2368), NXSW(0x240c), NXSW(0x2450) }, \ - { NXSW(0x2328), NXSW(0x236c), NXSW(0x2410), NXSW(0x2454) }, \ - { NXSW(0x232c), NXSW(0x2370), NXSW(0x2414), NXSW(0x2458) }, \ - \ - { NXSW(0x2330), NXSW(0x2374), NXSW(0x2418), NXSW(0x245c) }, \ - { NXSW(0x2334), NXSW(0x2378), NXSW(0x241c), NXSW(0x2460) }, \ - { NXSW(0x2338), NXSW(0x237c), NXSW(0x2420), NXSW(0x2464) }, \ - { NXSW(0x233c), NXSW(0x2380), NXSW(0x2424), NXSW(0x2468) }, \ - { NXSW(0x2340), NXSW(0x2384), NXSW(0x2428), NXSW(0x246c) }, \ - \ - { NXSW(0x2388), NXSW(0x2390), NXSW(0x2398), NXSW(0x23a0) }, \ - { NXSW(0x238c), NXSW(0x2394), NXSW(0x239c), NXSW(0x23a4) }, \ - { NXSW(0x23c0), NXSW(0x23c4), NXSW(0x23c8), NXSW(0x23cc) } \ -} - -/* - * Port-specific SW registers, will be mapped to a subregion - */ - -/* - * Secondary Interrupt Registers - */ - -/* I2Q Register */ -#define NXI2Q_CLR_PCI_HI NXSIR(0x00000034) -#define NXI2Q_CLR_PCI_HI_PHY (1<<13) /* PHY interrupt */ -#define NXI2Q_CLR_PCI_HI_DEF 0 /* Cleared */ - -/* - * ROMUSB registers - */ - -/* Status Register */ -#define NXROMUSB_GLB_STATUS NXROMUSB(0x00000004) /* ROM Status */ -#define NXROMUSB_GLB_STATUS_DONE (1<<1) /* Ready */ - -/* Reset Unit Register */ -#define NXROMUSB_GLB_SW_RESET NXROMUSB(0x00000008) -#define NXROMUSB_GLB_SW_RESET_EFC_SIU (1<<30) /* EFC_SIU reset */ -#define NXROMUSB_GLB_SW_RESET_NIU (1<<29) /* NIU software reset */ -#define NXROMUSB_GLB_SW_RESET_U0QMSQG (1<<28) /* Network side QM_SQG reset */ -#define NXROMUSB_GLB_SW_RESET_U1QMSQG (1<<27) /* Storage side QM_SQG reset */ -#define NXROMUSB_GLB_SW_RESET_C2C1 (1<<26) /* Chip to Chip 1 reset */ -#define NXROMUSB_GLB_SW_RESET_C2C0 (1<<25) /* Chip to Chip 2 reset */ -#define NXROMUSB_GLB_SW_RESET_U1PEGI (1<<11) /* Storage Pegasus I-Cache */ -#define NXROMUSB_GLB_SW_RESET_U1PEGD (1<<10) /* Storage Pegasus D-Cache */ -#define NXROMUSB_GLB_SW_RESET_U1PEG3 (1<<9) /* Storage Pegasus3 reset */ -#define NXROMUSB_GLB_SW_RESET_U1PEG2 (1<<8) /* Storage Pegasus2 reset */ -#define NXROMUSB_GLB_SW_RESET_U1PEG1 (1<<7) /* Storage Pegasus1 reset */ -#define NXROMUSB_GLB_SW_RESET_U1PEG0 (1<<6) /* Storage Pegasus0 reset */ -#define NXROMUSB_GLB_SW_RESET_U0PEGI (1<<11) /* Network Pegasus I-Cache */ -#define NXROMUSB_GLB_SW_RESET_U0PEGD (1<<10) /* Network Pegasus D-Cache */ -#define NXROMUSB_GLB_SW_RESET_U0PEG3 (1<<9) /* Network Pegasus3 reset */ -#define NXROMUSB_GLB_SW_RESET_U0PEG2 (1<<8) /* Network Pegasus2 reset */ -#define NXROMUSB_GLB_SW_RESET_U0PEG1 (1<<7) /* Network Pegasus1 reset */ -#define NXROMUSB_GLB_SW_RESET_U0PEG0 (1<<6) /* Network Pegasus0 reset */ -#define NXROMUSB_GLB_SW_RESET_PPE 0xf0 /* Protocol Processing Engine */ -#define NXROMUSB_GLB_SW_RESET_XDMA 0x8000ff; -#define NXROMUSB_GLB_SW_RESET_DEF 0xffffffff - -/* Casper Reset Register */ -#define NXROMUSB_GLB_CAS_RESET NXROMUSB(0x00000038) -#define NXROMUSB_GLB_CAS_RESET_ENABLE (1<<0) /* Enable Casper reset */ -#define NXROMUSB_GLB_CAS_RESET_DISABLE 0 -#define NXROMUSB_GLB_CAS_RESET_DEF 0 /* Disabled */ - -/* Reset register */ -#define NXROMUSB_GLB_PEGTUNE NXROMUSB(0x0000005c) -#define NXROMUSB_GLB_PEGTUNE_DONE (1<<0) - -/* Chip clock control register */ -#define NXROMUSB_GLB_CHIPCLKCONTROL NXROMUSB(0x000000a8) -#define NXROMUSB_GLB_CHIPCLKCONTROL_ON 0x00003fff - -/* ROM Register */ -#define NXROMUSB_ROM_CONTROL NXROMUSB(0x00010000) -#define NXROMUSB_ROM_OPCODE NXROMUSB(0x00010004) -#define NXROMUSB_ROM_OPCODE_READ 0x0000000b -#define NXROMUSB_ROM_ADDR NXROMUSB(0x00010008) -#define NXROMUSB_ROM_WDATA NXROMUSB(0x0001000c) -#define NXROMUSB_ROM_ABYTE_CNT NXROMUSB(0x00010010) -#define NXROMUSB_ROM_DUMMY_BYTE_CNT NXROMUSB(0x00010014) -#define NXROMUSB_ROM_RDATA NXROMUSB(0x00010018) -#define NXROMUSB_ROM_AGT_TAG NXROMUSB(0x0001001c) -#define NXROMUSB_ROM_TIME_PARM NXROMUSB(0x00010020) -#define NXROMUSB_ROM_CLK_DIV NXROMUSB(0x00010024) -#define NXROMUSB_ROM_MISS_INSTR NXROMUSB(0x00010028) - -/* - * Flash data structures - */ - -enum nxb_board_types { - NXB_BOARDTYPE_P1BD = 0, - NXB_BOARDTYPE_P1SB = 1, - NXB_BOARDTYPE_P1SMAX = 2, - NXB_BOARDTYPE_P1SOCK = 3, - - NXB_BOARDTYPE_P2SOCK31 = 8, - NXB_BOARDTYPE_P2SOCK35 = 9, - - NXB_BOARDTYPE_P2SB35_4G = 10, - NXB_BOARDTYPE_P2SB31_10G = 11, - NXB_BOARDTYPE_P2SB31_2G = 12, - NXB_BOARDTYPE_P2SB31_10GIMEZ = 13, - NXB_BOARDTYPE_P2SB31_10GHMEZ = 14, - NXB_BOARDTYPE_P2SB31_10GCX4 = 15 -}; - -#define NXB_MAX_PORTS NX_MAX_PORTS /* max supported ports */ - -struct nxb_info { - u_int32_t ni_hdrver; /* Board info version */ -#define NXB_VERSION 0x00000001 /* board information version */ - - u_int32_t ni_board_mfg; - u_int32_t ni_board_type; - u_int32_t ni_board_num; - - u_int32_t ni_chip_id; - u_int32_t ni_chip_minor; - u_int32_t ni_chip_major; - u_int32_t ni_chip_pkg; - u_int32_t ni_chip_lot; - - u_int32_t ni_port_mask; - u_int32_t ni_peg_mask; - u_int32_t ni_icache; - u_int32_t ni_dcache; - u_int32_t ni_casper; - - u_int32_t ni_lladdr0_low; - u_int32_t ni_lladdr1_low; - u_int32_t ni_lladdr2_low; - u_int32_t ni_lladdr3_low; - - u_int32_t ni_mnsync_mode; - u_int32_t ni_mnsync_shift_cclk; - u_int32_t ni_mnsync_shift_mclk; - u_int32_t ni_mnwb_enable; - u_int32_t ni_mnfreq_crystal; - u_int32_t ni_mnfreq_speed; - u_int32_t ni_mnorg; - u_int32_t ni_mndepth; - u_int32_t ni_mnranks0; - u_int32_t ni_mnranks1; - u_int32_t ni_mnrd_latency0; - u_int32_t ni_mnrd_latency1; - u_int32_t ni_mnrd_latency2; - u_int32_t ni_mnrd_latency3; - u_int32_t ni_mnrd_latency4; - u_int32_t ni_mnrd_latency5; - u_int32_t ni_mnrd_latency6; - u_int32_t ni_mnrd_latency7; - u_int32_t ni_mnrd_latency8; - u_int32_t ni_mndll[18]; - u_int32_t ni_mnddr_mode; - u_int32_t ni_mnddr_extmode; - u_int32_t ni_mntiming0; - u_int32_t ni_mntiming1; - u_int32_t ni_mntiming2; - - u_int32_t ni_snsync_mode; - u_int32_t ni_snpt_mode; - u_int32_t ni_snecc_enable; - u_int32_t ni_snwb_enable; - u_int32_t ni_snfreq_crystal; - u_int32_t ni_snfreq_speed; - u_int32_t ni_snorg; - u_int32_t ni_sndepth; - u_int32_t ni_sndll; - u_int32_t ni_snrd_latency; - - u_int32_t ni_lladdr0_high; - u_int32_t ni_lladdr1_high; - u_int32_t ni_lladdr2_high; - u_int32_t ni_lladdr3_high; - - u_int32_t ni_magic; -#define NXB_MAGIC 0x12345678 /* magic value */ - - u_int32_t ni_mnrd_imm; - u_int32_t ni_mndll_override; -} __packed; - -#define NXB_MAX_PORT_LLADDRS 32 - -struct nxb_imageinfo { - u_int32_t nim_bootld_ver; - u_int32_t nim_bootld_size; - u_int32_t nim_image_ver; -#define NXB_IMAGE_MAJOR_S 0 -#define NXB_IMAGE_MAJOR_M 0x000000ff -#define NXB_IMAGE_MINOR_S 8 -#define NXB_IMAGE_MINOR_M 0x0000ff00 -#define NXB_IMAGE_BUILD_S 16 -#define NXB_IMAGE_BUILD_M 0xffff0000 - u_int32_t nim_image_size; -} __packed; - -struct nxb_userinfo { - u_int8_t nu_flash_md5[1024]; - - struct nxb_imageinfo nu_image; - - u_int32_t nu_primary; - u_int32_t nu_secondary; - u_int64_t nu_lladdr[NXB_MAX_PORTS * NXB_MAX_PORT_LLADDRS]; - u_int32_t nu_subsys_id; - u_int8_t nu_serial_num[32]; - u_int32_t nu_bios_ver; - - /* Followed by user-specific data */ -} __packed; - -/* Appended to the on-disk firmware image, values in network byte order */ -struct nxb_firmware_header { - u_int32_t fw_hdrver; -#define NX_FIRMWARE_HDRVER 0 /* version of the firmware header */ - struct nxb_imageinfo fw_image; -#define fw_image_ver fw_image.nim_image_ver -#define fw_image_size fw_image.nim_image_size -#define fw_bootld_ver fw_image.nim_bootld_ver -#define fw_bootld_size fw_image.nim_bootld_size -} __packed; - -#endif /* _NX_REG_H */ |