diff options
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/arch/amiga/amiga/conf.c | 20 | ||||
| -rw-r--r-- | sys/arch/amiga/amiga/trap.c | 4 | ||||
| -rw-r--r-- | sys/arch/amiga/conf/FILIPPA | 6 | ||||
| -rw-r--r-- | sys/arch/amiga/include/bus.h | 326 | ||||
| -rw-r--r-- | sys/arch/amiga/include/bus.old.h | 198 | ||||
| -rw-r--r-- | sys/arch/amiga/isa/cross.c | 381 | ||||
| -rw-r--r-- | sys/arch/amiga/isa/crossreg.h | 46 | ||||
| -rw-r--r-- | sys/arch/amiga/isa/crossvar.h | 6 | ||||
| -rw-r--r-- | sys/arch/amiga/isa/ggbus.c | 306 | ||||
| -rw-r--r-- | sys/arch/amiga/isa/ggbusvar.h | 5 | ||||
| -rw-r--r-- | sys/arch/amiga/isa/if_isaed.c | 577 |
11 files changed, 725 insertions, 1150 deletions
diff --git a/sys/arch/amiga/amiga/conf.c b/sys/arch/amiga/amiga/conf.c index 24fcee2a673..d21206853c0 100644 --- a/sys/arch/amiga/amiga/conf.c +++ b/sys/arch/amiga/amiga/conf.c @@ -1,4 +1,4 @@ -/* $OpenBSD: conf.c,v 1.14 1996/10/19 13:26:03 mickey Exp $ */ +/* $OpenBSD: conf.c,v 1.15 1996/11/28 23:33:02 niklas Exp $ */ /* $NetBSD: conf.c,v 1.36 1996/05/19 21:04:18 veego Exp $ */ /*- @@ -274,6 +274,24 @@ chrtoblk(dev) } /* + * Convert a character device number to a block device number. + */ +dev_t +blktochr(dev) + dev_t dev; +{ + int blkmaj = major(dev); + int i; + + if (blkmaj >= nblkdev) + return (NODEV); + for (i = 0; i < sizeof(chrtoblktab)/sizeof(chrtoblktab[0]); i++) + if (blkmaj == chrtoblktab[i]) + return (makedev(i, minor(dev))); + return (NODEV); +} + +/* * This entire table could be autoconfig()ed but that would mean that * the kernel's idea of the console would be out of sync with that of * the standalone boot. I think it best that they both use the same diff --git a/sys/arch/amiga/amiga/trap.c b/sys/arch/amiga/amiga/trap.c index aad3515dc8d..063348ac690 100644 --- a/sys/arch/amiga/amiga/trap.c +++ b/sys/arch/amiga/amiga/trap.c @@ -1,4 +1,4 @@ -/* $OpenBSD: trap.c,v 1.6 1996/06/07 05:18:40 niklas Exp $ */ +/* $OpenBSD: trap.c,v 1.7 1996/11/28 23:33:03 niklas Exp $ */ /* $NetBSD: trap.c,v 1.47 1996/05/10 14:31:08 is Exp $ */ /* @@ -508,7 +508,7 @@ nogo: type, code); panictrap(type, code, v, fp); } - trapsignal(p, (rv == KERN_PROTECTION_FAILURE) ? SIGBUS : SIGSEGV, v); + trapsignal(p, SIGSEGV, v); if ((type & T_USER) == 0) return; userret(p, fp->f_pc, sticks); diff --git a/sys/arch/amiga/conf/FILIPPA b/sys/arch/amiga/conf/FILIPPA index 51d71846f30..a48ee6a88d9 100644 --- a/sys/arch/amiga/conf/FILIPPA +++ b/sys/arch/amiga/conf/FILIPPA @@ -1,4 +1,4 @@ -# $OpenBSD: FILIPPA,v 1.10 1996/09/20 06:44:55 deraadt Exp $ +# $OpenBSD: FILIPPA,v 1.11 1996/11/28 23:33:04 niklas Exp $ # # Niklas' AMIGA with ISA support @@ -210,8 +210,8 @@ ss* at scsibus? target ? lun ? # scsi scanners ggbus* at zbus0 # Goldengate bridge isa* at ggbus? -cross* at zbus0 # CrossLink bridge -isa* at cross? +#cross* at zbus0 # CrossLink bridge +#isa* at cross? com0 at isa? port 0x3f8 irq 4 # Standard PC serial ports com1 at isa? port 0x2f8 irq 3 diff --git a/sys/arch/amiga/include/bus.h b/sys/arch/amiga/include/bus.h index f7c99b48e4e..b7bb10dcce5 100644 --- a/sys/arch/amiga/include/bus.h +++ b/sys/arch/amiga/include/bus.h @@ -1,4 +1,4 @@ -/* $OpenBSD: bus.h,v 1.2 1996/08/04 01:34:38 niklas Exp $ */ +/* $OpenBSD: bus.h,v 1.3 1996/11/28 23:33:05 niklas Exp $ */ /* * Copyright (c) 1996 Niklas Hallqvist. @@ -32,167 +32,177 @@ * SUCH DAMAGE. */ -#ifndef _MACHINE_BUS_H_ -#define _MACHINE_BUS_H_ +#ifndef _AMIGA_BUS_H_ +#define _AMIGA_BUS_H_ -/* I/O access types. */ -typedef u_long bus_io_addr_t; -typedef u_long bus_io_size_t; -typedef u_long bus_io_handle_t; +#ifdef __STDC__ +#define CAT(a,b) a##b +#define CAT3(a,b,c) a##b##c +#else +#define CAT(a,b) a/**/b +#define CAT3(a,b,c) a/**/b/**/c +#endif -/* Memory access types. */ -typedef u_long bus_mem_addr_t; -typedef u_long bus_mem_size_t; -typedef u_long bus_mem_handle_t; +/* Bus access types. */ +typedef u_int32_t bus_addr_t; +typedef u_int32_t bus_size_t; +typedef u_int32_t bus_space_handle_t; -/* - * The big switch, that delegates each bus operation to the right - * implementation. - */ -typedef struct amiga_bus_chipset *bus_chipset_tag_t; - -struct amiga_bus_chipset { - void *bc_data; - - int (*bc_io_map)(bus_chipset_tag_t, bus_io_addr_t, bus_io_size_t, - bus_io_handle_t *); - int (*bc_io_unmap)(bus_io_handle_t, bus_io_size_t); - - u_int8_t (*bc_io_read_1)(bus_io_handle_t, bus_io_size_t); - u_int16_t (*bc_io_read_2)(bus_io_handle_t, bus_io_size_t); - u_int32_t (*bc_io_read_4)(bus_io_handle_t, bus_io_size_t); - u_int64_t (*bc_io_read_8)(bus_io_handle_t, bus_io_size_t); - - void (*bc_io_read_multi_1)(bus_io_handle_t, bus_io_size_t, - u_int8_t *, bus_io_size_t); - void (*bc_io_read_multi_2)(bus_io_handle_t, bus_io_size_t, - u_int16_t *, bus_io_size_t); - void (*bc_io_read_multi_4)(bus_io_handle_t, bus_io_size_t, - u_int32_t *, bus_io_size_t); - void (*bc_io_read_multi_8)(bus_io_handle_t, bus_io_size_t, - u_int64_t *, bus_io_size_t); - - void (*bc_io_write_1)(bus_io_handle_t, bus_io_size_t, u_int8_t); - void (*bc_io_write_2)(bus_io_handle_t, bus_io_size_t, u_int16_t); - void (*bc_io_write_4)(bus_io_handle_t, bus_io_size_t, u_int32_t); - void (*bc_io_write_8)(bus_io_handle_t, bus_io_size_t, u_int64_t); - - void (*bc_io_write_multi_1)(bus_io_handle_t, bus_io_size_t, - const u_int8_t *, bus_io_size_t); - void (*bc_io_write_multi_2)(bus_io_handle_t, bus_io_size_t, - const u_int16_t *, bus_io_size_t); - void (*bc_io_write_multi_4)(bus_io_handle_t, bus_io_size_t, - const u_int32_t *, bus_io_size_t); - void (*bc_io_write_multi_8)(bus_io_handle_t, bus_io_size_t, - const u_int64_t *, bus_io_size_t); - - int (*bc_mem_map)(bus_chipset_tag_t, bus_mem_addr_t, - bus_mem_size_t, int, bus_mem_handle_t *); - int (*bc_mem_unmap)(bus_mem_handle_t, bus_mem_size_t); - - u_int8_t (*bc_mem_read_1)(bus_mem_handle_t, bus_mem_size_t); - u_int16_t (*bc_mem_read_2)(bus_mem_handle_t, bus_mem_size_t); - u_int32_t (*bc_mem_read_4)(bus_mem_handle_t, bus_mem_size_t); - u_int64_t (*bc_mem_read_8)(bus_mem_handle_t, bus_mem_size_t); - - void (*bc_mem_write_1)(bus_mem_handle_t, bus_mem_size_t, u_int8_t); - void (*bc_mem_write_2)(bus_mem_handle_t, bus_mem_size_t, u_int16_t); - void (*bc_mem_write_4)(bus_mem_handle_t, bus_mem_size_t, u_int32_t); - void (*bc_mem_write_8)(bus_mem_handle_t, bus_mem_size_t, u_int64_t); - - /* These are extensions to the general NetBSD bus interface. */ - void (*bc_io_read_raw_multi_2)(bus_io_handle_t, bus_io_size_t, - u_int8_t *, bus_io_size_t); - void (*bc_io_read_raw_multi_4)(bus_io_handle_t, bus_io_size_t, - u_int8_t *, bus_io_size_t); - void (*bc_io_read_raw_multi_8)(bus_io_handle_t, bus_io_size_t, - u_int8_t *, bus_io_size_t); - - void (*bc_io_write_raw_multi_2)(bus_io_handle_t, bus_io_size_t, - const u_int8_t *, bus_io_size_t); - void (*bc_io_write_raw_multi_4)(bus_io_handle_t, bus_io_size_t, - const u_int8_t *, bus_io_size_t); - void (*bc_io_write_raw_multi_8)(bus_io_handle_t, bus_io_size_t, - const u_int8_t *, bus_io_size_t); +typedef struct amiga_bus_space *bus_space_tag_t; + +struct amiga_bus_space { + void *bs_data; + + int (*bs_map)(bus_space_tag_t, bus_addr_t, bus_size_t, int, + bus_space_handle_t *); + int (*bs_unmap)(bus_space_tag_t, bus_space_handle_t, bus_size_t); + + /* We need swapping of 16-bit entities */ + int bs_swapped; }; -#define bus_io_map(t, port, size, iohp) \ - (*(t)->bc_io_map)((t), (port), (size), (iohp)) -#define bus_io_unmap(t, iohp, size) \ - (*(t)->bc_io_unmap)((iohp), (size)) - -#define bus_io_read_1(t, h, o) \ - (*(t)->bc_io_read_1)((h), (o)) -#define bus_io_read_2(t, h, o) \ - (*(t)->bc_io_read_2)((h), (o)) -#define bus_io_read_4(t, h, o) \ - (*(t)->bc_io_read_4)((h), (o)) -#define bus_io_read_8(t, h, o) \ - (*(t)->bc_io_read_8)((h), (o)) - -#define bus_io_read_multi_1(t, h, o, a, s) \ - (*(t)->bc_io_read_multi_1)((h), (o), (a), (s)) -#define bus_io_read_multi_2(t, h, o, a, s) \ - (*(t)->bc_io_read_multi_2)((h), (o), (a), (s)) -#define bus_io_read_multi_4(t, h, o, a, s) \ - (*(t)->bc_io_read_multi_4)((h), (o), (a), (s)) -#define bus_io_read_multi_8(t, h, o, a, s) \ - (*(t)->bc_io_read_multi_8)((h), (o), (a), (s)) - -#define bus_io_write_1(t, h, o, v) \ - (*(t)->bc_io_write_1)((h), (o), (v)) -#define bus_io_write_2(t, h, o, v) \ - (*(t)->bc_io_write_2)((h), (o), (v)) -#define bus_io_write_4(t, h, o, v) \ - (*(t)->bc_io_write_4)((h), (o), (v)) -#define bus_io_write_8(t, h, o, v) \ - (*(t)->bc_io_write_8)((h), (o), (v)) - -#define bus_io_write_multi_1(t, h, o, a, s) \ - (*(t)->bc_io_write_multi_1)((h), (o), (a), (s)) -#define bus_io_write_multi_2(t, h, o, a, s) \ - (*(t)->bc_io_write_multi_2)((h), (o), (a), (s)) -#define bus_io_write_multi_4(t, h, o, a, s) \ - (*(t)->bc_io_write_multi_4)((h), (o), (a), (s)) -#define bus_io_write_multi_8(t, h, o, a, s) \ - (*(t)->bc_io_write_multi_8)((h), (o), (a), (s)) - -#define bus_mem_map(t, port, size, cacheable, mhp) \ - (*(t)->bc_mem_map)((t), (port), (size), (cacheable), (mhp)) -#define bus_mem_unmap(t, mhp, size) \ - (*(t)->bc_mem_unmap)((mhp), (size)) - -#define bus_mem_read_1(t, h, o) \ - (*(t)->bc_mem_read_1)((h), (o)) -#define bus_mem_read_2(t, h, o) \ - (*(t)->bc_mem_read_2)((h), (o)) -#define bus_mem_read_4(t, h, o) \ - (*(t)->bc_mem_read_4)((h), (o)) -#define bus_mem_read_8(t, h, o) \ - (*(t)->bc_mem_read_8)((h), (o)) - -#define bus_mem_write_1(t, h, o, v) \ - (*(t)->bc_mem_write_1)((h), (o), (v)) -#define bus_mem_write_2(t, h, o, v) \ - (*(t)->bc_mem_write_2)((h), (o), (v)) -#define bus_mem_write_4(t, h, o, v) \ - (*(t)->bc_mem_write_4)((h), (o), (v)) -#define bus_mem_write_8(t, h, o, v) \ - (*(t)->bc_mem_write_8)((h), (o), (v)) +#define bus_space_map(t, port, size, cacheable, bshp) \ + (*(t)->bs_map)((t), (port), (size), (cacheable), (bshp)) +#define bus_space_unmap(t, bshp, size) \ + (*(t)->bs_unmap)((t), (bshp), (size)) + +/* Swap bytes in a short word. */ +static __inline u_int16_t +swap(u_int16_t x) +{ + __asm("rolw #8,%0" : "=r" (x) : "0" (x)); + return x; +} + +static __inline u_int8_t +bus_space_read_1(bus_space_tag_t bst, bus_space_handle_t bsh, bus_addr_t ba) +{ + return *(volatile u_int8_t *)(bsh + (ba << 1)); +} + +static __inline u_int16_t +bus_space_read_2(bus_space_tag_t bst, bus_space_handle_t bsh, bus_addr_t ba) +{ + register u_int16_t x = *(volatile u_int16_t *)((bsh & ~1) + (ba << 1)); + + return bst->bs_swapped ? swap(x) : x; +} + +static __inline u_int32_t +bus_space_read_4(bus_space_tag_t bst, bus_space_handle_t bsh, bus_addr_t ba) +{ + panic("bus_space_read_4: operation not allowed on this bus (tag %x)", + bst); + return 0; +} + +#define bus_space_read_8 !!! bus_space_read_8 not implemented !!! + +#define bus_space_read_multi(n, m) \ +static __inline void \ +CAT(bus_space_read_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \ + bus_addr_t ba, CAT3(u_int,m,_t) *buf, bus_size_t cnt) \ +{ \ + while (cnt--) \ + *buf++ = CAT(bus_space_read_,n)(bst, bsh, ba); \ +} + +bus_space_read_multi(1,8) +bus_space_read_multi(2,16) +bus_space_read_multi(4,32) + +#define bus_space_read_multi_8 !!! bus_space_read_multi_8 not implemented !!! + +static __inline void +bus_space_write_1(bus_space_tag_t bst, bus_space_handle_t bsh, bus_addr_t ba, + u_int8_t x) +{ + *(volatile u_int8_t *)(bsh + (ba << 1)) = x; +} + +static __inline void +bus_space_write_2(bus_space_tag_t bst, bus_space_handle_t bsh, bus_addr_t ba, + u_int16_t x) +{ + *(volatile u_int16_t *)((bsh & ~1) + (ba << 1)) = + bst->bs_swapped ? swap(x) : x; +} + +static __inline void +bus_space_write_4(bus_space_tag_t bst, bus_space_handle_t bsh, bus_addr_t ba, + u_int32_t x) +{ + panic("bus_space_write_4: operation not allowed on this bus (tag %x)", + bst); +} + +#define bus_space_write_8 !!! bus_space_write_8 not implemented !!! + +#define bus_space_write_multi(n, m) \ +static __inline void \ +CAT(bus_space_write_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \ + bus_addr_t ba, const CAT3(u_int,m,_t) *buf, bus_size_t cnt) \ +{ \ + while (cnt--) \ + CAT(bus_space_write_,n)(bst, bsh, ba, *buf++); \ +} + +bus_space_write_multi(1,8) +bus_space_write_multi(2,16) +bus_space_write_multi(4,32) + +#define bus_space_write_multi_8 !!! bus_space_write_multi_8 not implemented !!! /* OpenBSD extensions */ -#define bus_io_read_raw_multi_2(t, h, o, a, s) \ - (*(t)->bc_io_read_raw_multi_2)((h), (o), (a), (s)) -#define bus_io_read_raw_multi_4(t, h, o, a, s) \ - (*(t)->bc_io_read_raw_multi_4)((h), (o), (a), (s)) -#define bus_io_read_raw_multi_8(t, h, o, a, s) \ - (*(t)->bc_io_read_raw_multi_8)((h), (o), (a), (s)) - -#define bus_io_write_raw_multi_2(t, h, o, a, s) \ - (*(t)->bc_io_write_raw_multi_2)((h), (o), (a), (s)) -#define bus_io_write_raw_multi_4(t, h, o, a, s) \ - (*(t)->bc_io_write_raw_multi_4)((h), (o), (a), (s)) -#define bus_io_write_raw_multi_8(t, h, o, a, s) \ - (*(t)->bc_io_write_raw_multi_8)((h), (o), (a), (s)) - -#endif /* _MACHINE_BUS_H_ */ +static __inline void +bus_space_read_raw_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh, + bus_addr_t ba, u_int8_t *buf, bus_size_t cnt) +{ + register u_int16_t *buf16 = (u_int16_t *)buf; + + while (cnt) { + register u_int16_t x = + *(volatile u_int16_t *)((bsh & ~1) + (ba << 1)); + + *buf16++ = bst->bs_swapped ? x : swap(x); + cnt -= 2; + } +} + +static __inline void +bus_space_read_raw_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh, + bus_addr_t ba, u_int8_t *buf, bus_size_t cnt) +{ + panic("%s: operation not allowed on this bus (tag %x)", + "bus_space_read_raw_multi_4", bst); +} + +#define bus_space_read_raw_multi_8 \ + !!! bus_space_read_raw_multi_8 not implemented !!! + +static __inline void +bus_space_write_raw_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh, + bus_addr_t ba, const u_int8_t *buf, bus_size_t cnt) +{ + register const u_int16_t *buf16 = (const u_int16_t *)buf; + + while (cnt) { + *(volatile u_int16_t *)((bsh & ~1) + (ba << 1)) = + bst->bs_swapped ? *buf16 : swap(*buf16); + buf16++; + cnt -= 2; + } +} + +static __inline void +bus_space_write_raw_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh, + bus_addr_t ba, const u_int8_t *buf, bus_size_t cnt) +{ + panic("%s: operation not allowed on this bus (tag %x)", + "bus_space_write_raw_multi_4", bst); +} + +#define bus_space_write_raw_multi_8 \ + !!! bus_space_write_raw_multi_8 not implemented !!! + +#endif /* _AMIGA_BUS_H_ */ diff --git a/sys/arch/amiga/include/bus.old.h b/sys/arch/amiga/include/bus.old.h deleted file mode 100644 index 6e4dc4a5560..00000000000 --- a/sys/arch/amiga/include/bus.old.h +++ /dev/null @@ -1,198 +0,0 @@ -/* $OpenBSD: bus.old.h,v 1.1 1996/11/12 20:29:46 niklas Exp $ */ - -/* - * Copyright (c) 1996 Niklas Hallqvist. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the Niklas Hallqvist. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _MACHINE_BUS_H_ -#define _MACHINE_BUS_H_ - -/* I/O access types. */ -typedef u_long bus_io_addr_t; -typedef u_long bus_io_size_t; -typedef u_long bus_io_handle_t; - -/* Memory access types. */ -typedef u_long bus_mem_addr_t; -typedef u_long bus_mem_size_t; -typedef u_long bus_mem_handle_t; - -/* - * The big switch, that delegates each bus operation to the right - * implementation. - */ -typedef struct amiga_bus_chipset *bus_chipset_tag_t; - -struct amiga_bus_chipset { - void *bc_data; - - int (*bc_io_map)(bus_chipset_tag_t, bus_io_addr_t, bus_io_size_t, - bus_io_handle_t *); - int (*bc_io_unmap)(bus_io_handle_t, bus_io_size_t); - - u_int8_t (*bc_io_read_1)(bus_io_handle_t, bus_io_size_t); - u_int16_t (*bc_io_read_2)(bus_io_handle_t, bus_io_size_t); - u_int32_t (*bc_io_read_4)(bus_io_handle_t, bus_io_size_t); - u_int64_t (*bc_io_read_8)(bus_io_handle_t, bus_io_size_t); - - void (*bc_io_read_multi_1)(bus_io_handle_t, bus_io_size_t, - u_int8_t *, bus_io_size_t); - void (*bc_io_read_multi_2)(bus_io_handle_t, bus_io_size_t, - u_int16_t *, bus_io_size_t); - void (*bc_io_read_multi_4)(bus_io_handle_t, bus_io_size_t, - u_int32_t *, bus_io_size_t); - void (*bc_io_read_multi_8)(bus_io_handle_t, bus_io_size_t, - u_int64_t *, bus_io_size_t); - - void (*bc_io_write_1)(bus_io_handle_t, bus_io_size_t, u_int8_t); - void (*bc_io_write_2)(bus_io_handle_t, bus_io_size_t, u_int16_t); - void (*bc_io_write_4)(bus_io_handle_t, bus_io_size_t, u_int32_t); - void (*bc_io_write_8)(bus_io_handle_t, bus_io_size_t, u_int64_t); - - void (*bc_io_write_multi_1)(bus_io_handle_t, bus_io_size_t, - const u_int8_t *, bus_io_size_t); - void (*bc_io_write_multi_2)(bus_io_handle_t, bus_io_size_t, - const u_int16_t *, bus_io_size_t); - void (*bc_io_write_multi_4)(bus_io_handle_t, bus_io_size_t, - const u_int32_t *, bus_io_size_t); - void (*bc_io_write_multi_8)(bus_io_handle_t, bus_io_size_t, - const u_int64_t *, bus_io_size_t); - - int (*bc_mem_map)(bus_chipset_tag_t, bus_mem_addr_t, - bus_mem_size_t, int, bus_mem_handle_t *); - int (*bc_mem_unmap)(bus_mem_handle_t, bus_mem_size_t); - - u_int8_t (*bc_mem_read_1)(bus_mem_handle_t, bus_mem_size_t); - u_int16_t (*bc_mem_read_2)(bus_mem_handle_t, bus_mem_size_t); - u_int32_t (*bc_mem_read_4)(bus_mem_handle_t, bus_mem_size_t); - u_int64_t (*bc_mem_read_8)(bus_mem_handle_t, bus_mem_size_t); - - void (*bc_mem_write_1)(bus_mem_handle_t, bus_mem_size_t, u_int8_t); - void (*bc_mem_write_2)(bus_mem_handle_t, bus_mem_size_t, u_int16_t); - void (*bc_mem_write_4)(bus_mem_handle_t, bus_mem_size_t, u_int32_t); - void (*bc_mem_write_8)(bus_mem_handle_t, bus_mem_size_t, u_int64_t); - - /* These are extensions to the general NetBSD bus interface. */ - void (*bc_io_read_raw_multi_2)(bus_io_handle_t, bus_io_size_t, - u_int8_t *, bus_io_size_t); - void (*bc_io_read_raw_multi_4)(bus_io_handle_t, bus_io_size_t, - u_int8_t *, bus_io_size_t); - void (*bc_io_read_raw_multi_8)(bus_io_handle_t, bus_io_size_t, - u_int8_t *, bus_io_size_t); - - void (*bc_io_write_raw_multi_2)(bus_io_handle_t, bus_io_size_t, - const u_int8_t *, bus_io_size_t); - void (*bc_io_write_raw_multi_4)(bus_io_handle_t, bus_io_size_t, - const u_int8_t *, bus_io_size_t); - void (*bc_io_write_raw_multi_8)(bus_io_handle_t, bus_io_size_t, - const u_int8_t *, bus_io_size_t); -}; - -#define bus_io_map(t, port, size, iohp) \ - (*(t)->bc_io_map)((t), (port), (size), (iohp)) -#define bus_io_unmap(t, iohp, size) \ - (*(t)->bc_io_unmap)((iohp), (size)) - -#define bus_io_read_1(t, h, o) \ - (*(t)->bc_io_read_1)((h), (o)) -#define bus_io_read_2(t, h, o) \ - (*(t)->bc_io_read_2)((h), (o)) -#define bus_io_read_4(t, h, o) \ - (*(t)->bc_io_read_4)((h), (o)) -#define bus_io_read_8(t, h, o) \ - (*(t)->bc_io_read_8)((h), (o)) - -#define bus_io_read_multi_1(t, h, o, a, s) \ - (*(t)->bc_io_read_multi_1)((h), (o), (a), (s)) -#define bus_io_read_multi_2(t, h, o, a, s) \ - (*(t)->bc_io_read_multi_2)((h), (o), (a), (s)) -#define bus_io_read_multi_4(t, h, o, a, s) \ - (*(t)->bc_io_read_multi_4)((h), (o), (a), (s)) -#define bus_io_read_multi_8(t, h, o, a, s) \ - (*(t)->bc_io_read_multi_8)((h), (o), (a), (s)) - -#define bus_io_write_1(t, h, o, v) \ - (*(t)->bc_io_write_1)((h), (o), (v)) -#define bus_io_write_2(t, h, o, v) \ - (*(t)->bc_io_write_2)((h), (o), (v)) -#define bus_io_write_4(t, h, o, v) \ - (*(t)->bc_io_write_4)((h), (o), (v)) -#define bus_io_write_8(t, h, o, v) \ - (*(t)->bc_io_write_8)((h), (o), (v)) - -#define bus_io_write_multi_1(t, h, o, a, s) \ - (*(t)->bc_io_write_multi_1)((h), (o), (a), (s)) -#define bus_io_write_multi_2(t, h, o, a, s) \ - (*(t)->bc_io_write_multi_2)((h), (o), (a), (s)) -#define bus_io_write_multi_4(t, h, o, a, s) \ - (*(t)->bc_io_write_multi_4)((h), (o), (a), (s)) -#define bus_io_write_multi_8(t, h, o, a, s) \ - (*(t)->bc_io_write_multi_8)((h), (o), (a), (s)) - -#define bus_mem_map(t, port, size, cacheable, mhp) \ - (*(t)->bc_mem_map)((t), (port), (size), (cacheable), (mhp)) -#define bus_mem_unmap(t, mhp, size) \ - (*(t)->bc_mem_unmap)((mhp), (size)) - -#define bus_mem_read_1(t, h, o) \ - (*(t)->bc_mem_read_1)((h), (o)) -#define bus_mem_read_2(t, h, o) \ - (*(t)->bc_mem_read_2)((h), (o)) -#define bus_mem_read_4(t, h, o) \ - (*(t)->bc_mem_read_4)((h), (o)) -#define bus_mem_read_8(t, h, o) \ - (*(t)->bc_mem_read_8)((h), (o)) - -#define bus_mem_write_1(t, h, o, v) \ - (*(t)->bc_mem_write_1)((h), (o), (v)) -#define bus_mem_write_2(t, h, o, v) \ - (*(t)->bc_mem_write_2)((h), (o), (v)) -#define bus_mem_write_4(t, h, o, v) \ - (*(t)->bc_mem_write_4)((h), (o), (v)) -#define bus_mem_write_8(t, h, o, v) \ - (*(t)->bc_mem_write_8)((h), (o), (v)) - -/* OpenBSD extensions */ -#define bus_io_read_raw_multi_2(t, h, o, a, s) \ - (*(t)->bc_io_read_raw_multi_2)((h), (o), (a), (s)) -#define bus_io_read_raw_multi_4(t, h, o, a, s) \ - (*(t)->bc_io_read_raw_multi_4)((h), (o), (a), (s)) -#define bus_io_read_raw_multi_8(t, h, o, a, s) \ - (*(t)->bc_io_read_raw_multi_8)((h), (o), (a), (s)) - -#define bus_io_write_raw_multi_2(t, h, o, a, s) \ - (*(t)->bc_io_write_raw_multi_2)((h), (o), (a), (s)) -#define bus_io_write_raw_multi_4(t, h, o, a, s) \ - (*(t)->bc_io_write_raw_multi_4)((h), (o), (a), (s)) -#define bus_io_write_raw_multi_8(t, h, o, a, s) \ - (*(t)->bc_io_write_raw_multi_8)((h), (o), (a), (s)) - -#endif /* _MACHINE_BUS_H_ */ diff --git a/sys/arch/amiga/isa/cross.c b/sys/arch/amiga/isa/cross.c index e12500f1811..b5bbf779ec2 100644 --- a/sys/arch/amiga/isa/cross.c +++ b/sys/arch/amiga/isa/cross.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cross.c,v 1.7 1996/11/23 21:45:26 kstailey Exp $ */ +/* $OpenBSD: cross.c,v 1.8 1996/11/28 23:33:06 niklas Exp $ */ /* * Copyright (c) 1994, 1996 Niklas Hallqvist, Carsten Hammer @@ -37,7 +37,11 @@ #include <sys/syslog.h> #include <sys/systm.h> -#include <machine/bus.old.h> +#include <vm/vm.h> +#include <vm/vm.h> +#include <vm/vm.h> + +#include <machine/bus.h> #include <machine/cpu.h> #include <machine/intr.h> @@ -48,8 +52,8 @@ #include <amiga/amiga/isr.h> #include <amiga/dev/zbusvar.h> #include <amiga/isa/isa_machdep.h> -#include <amiga/isa/crossvar.h> #include <amiga/isa/crossreg.h> +#include <amiga/isa/crossvar.h> extern int cold; @@ -59,50 +63,12 @@ void crossattach __P((struct device *, struct device *, void *)); int crossmatch __P((struct device *, void *, void *)); int crossprint __P((void *, const char *)); -int cross_io_map __P((bus_chipset_tag_t, bus_io_addr_t, bus_io_size_t, - bus_io_handle_t *)); -int cross_mem_map __P((bus_chipset_tag_t, bus_mem_addr_t, bus_mem_size_t, - int, bus_mem_handle_t *)); - -void cross_io_read_multi_1 __P((bus_io_handle_t, bus_io_size_t, u_int8_t *, - bus_io_size_t)); -void cross_io_read_multi_2 __P((bus_io_handle_t, bus_io_size_t, u_int16_t *, - bus_io_size_t)); - -void cross_io_write_multi_1 __P((bus_io_handle_t, bus_io_size_t, - const u_int8_t *, bus_io_size_t)); -void cross_io_write_multi_2 __P((bus_io_handle_t, bus_io_size_t, - const u_int16_t *, bus_io_size_t)); - -void cross_io_read_raw_multi_2 __P((bus_io_handle_t, bus_io_size_t, - u_int8_t *, bus_io_size_t)); -void cross_io_write_raw_multi_2 __P((bus_io_handle_t, bus_io_size_t, - const u_int8_t *, bus_io_size_t)); - -/* - * Note that the following unified access functions are prototyped for the - * I/O access case. We use casts to get type correctness. - */ -int cross_unmap __P((bus_io_handle_t, bus_io_size_t)); - -__inline u_int8_t cross_read_1 __P((bus_io_handle_t, bus_io_size_t)); -__inline u_int16_t cross_read_2 __P((bus_io_handle_t, bus_io_size_t)); - -__inline void cross_write_1 __P((bus_io_handle_t, bus_io_size_t, u_int8_t)); -__inline void cross_write_2 __P((bus_io_handle_t, bus_io_size_t, u_int16_t)); - -/* - * In order to share the access function implementations for I/O and memory - * access we cast the functions for the memory access case. These typedefs - * make that casting look nicer. - */ -typedef int (*bus_mem_unmap_t) __P((bus_mem_handle_t, bus_mem_size_t)); -typedef u_int8_t (*bus_mem_read_1_t) __P((bus_mem_handle_t, bus_mem_size_t)); -typedef u_int16_t (*bus_mem_read_2_t) __P((bus_mem_handle_t, bus_mem_size_t)); -typedef void (*bus_mem_write_1_t) __P((bus_mem_handle_t, bus_mem_size_t, - u_int8_t)); -typedef void (*bus_mem_write_2_t) __P((bus_mem_handle_t, bus_mem_size_t, - u_int16_t)); +int cross_io_map __P((bus_space_tag_t, bus_addr_t, bus_size_t, int, + bus_space_handle_t *)); +int cross_mem_map __P((bus_space_tag_t, bus_addr_t, bus_size_t, int, + bus_space_handle_t *)); +int cross_io_unmap __P((bus_space_handle_t, bus_size_t)); +int cross_mem_unmap __P((bus_space_handle_t, bus_size_t)); int crossintr __P((void *)); @@ -112,34 +78,7 @@ void *cross_intr_establish __P((void *, int, int, int, int (*)(void *), void *, char *)); void cross_intr_disestablish __P((void *, void *)); -static u_int16_t swap __P((u_int16_t)); - -struct amiga_bus_chipset cross_chipset = { - 0 /* bc_data */, - - cross_io_map, cross_unmap, - cross_read_1, cross_read_2, - 0 /* bc_io_read_4 */, 0 /* bc_io_read_8 */, - cross_io_read_multi_1, cross_io_read_multi_2, - 0 /* bc_io_multi_4 */, 0 /* bc_io_multi_8 */, - cross_write_1, cross_write_2, - 0 /* bc_io_write_4 */, 0 /* bc_io_write_8 */, - cross_io_write_multi_1, cross_io_write_multi_2, - 0 /* bc_io_write_multi_4 */, 0 /* bc_io_write_multi_8 */, - - cross_mem_map, (bus_mem_unmap_t)cross_unmap, - (bus_mem_read_1_t)cross_read_1, (bus_mem_read_2_t)cross_read_2, - 0 /* bc_mem_read_4 */, 0 /* bc_mem_read_8 */, - (bus_mem_write_1_t)cross_write_1, (bus_mem_write_2_t)cross_write_2, - 0 /* bc_mem_write_4 */, 0 /* bc_mem_write_8 */, - - /* These are extensions to the general NetBSD bus interface. */ - cross_io_read_raw_multi_2, - 0 /* bc_io_read_raw_multi_4 */, 0 /* bc_io_read_raw_multi_8 */, - - cross_io_write_raw_multi_2, - 0 /* bc_io_write_raw_multi_4 */, 0 /* bc_io_write_raw_multi_8 */, -}; +int cross_pager_get_pages __P((vm_pager_t, vm_page_t *, int, boolean_t)); struct cfattach cross_ca = { sizeof(struct cross_softc), crossmatch, crossattach @@ -149,6 +88,21 @@ struct cfdriver cross_cd = { NULL, "cross", DV_DULL, 0 }; +struct pagerops crosspagerops = { + NULL, + NULL, + NULL, + cross_pager_get_pages, + NULL, + NULL, + vm_pager_clusternull, + NULL, + NULL, + NULL +}; + +struct vm_pager crosspager; + int crossmatch(parent, match, aux) struct device *parent; @@ -172,17 +126,25 @@ crossattach(parent, self, aux) struct cross_softc *sc = (struct cross_softc *)self; struct zbus_args *zap = aux; struct isabus_attach_args iba; + int i; bcopy(zap, &sc->sc_zargs, sizeof(struct zbus_args)); - bcopy(&cross_chipset, &sc->sc_bc, sizeof(struct amiga_bus_chipset)); - sc->sc_bc.bc_data = sc; + sc->sc_iot.bs_data = sc; + sc->sc_iot.bs_map = cross_io_map; + sc->sc_iot.bs_unmap = cross_io_unmap; + sc->sc_iot.bs_swapped = 1; + sc->sc_memt.bs_data = sc; + sc->sc_memt.bs_map = cross_mem_map; + sc->sc_memt.bs_unmap = cross_mem_unmap; + sc->sc_memt.bs_swapped = 1; sc->sc_status = CROSS_STATUS_ADDR(zap->va); sc->sc_imask = 1 << CROSS_MASTER; /* Enable interrupts lazily in cross_intr_establish. */ CROSS_ENABLE_INTS(zap->va, 0); + /* Default 16 bit tranfer */ - *CROSS_HANDLE_TO_XLP_LATCH((bus_io_handle_t)zap->va) = CROSS_SBHE; + *CROSS_HANDLE_TO_XLP_LATCH((bus_space_handle_t)zap->va) = CROSS_SBHE; printf(": pa 0x%08x va 0x%08x size 0x%x\n", zap->pa, zap->va, zap->size); @@ -191,8 +153,17 @@ crossattach(parent, self, aux) sc->sc_ic.ic_intr_establish = cross_intr_establish; sc->sc_ic.ic_intr_disestablish = cross_intr_disestablish; + /* Allocate a bunch of pages used for the bank-switching logic. */ + for (i = 0; i < CROSS_BANK_SIZE / NBPG; i++) { + VM_PAGE_INIT(&sc->sc_page[i], NULL, 0); + sc->sc_page[i].phys_addr = zap->pa + CROSS_XL_MEM + i * NBPG; + sc->sc_page[i].flags |= PG_FICTITIOUS; + vm_page_free(&sc->sc_page[i]); + } + iba.iba_busname = "isa"; - iba.iba_bc = &sc->sc_bc; + iba.iba_iot = &sc->sc_iot; + iba.iba_memt = &sc->sc_memt; iba.iba_ic = &sc->sc_ic; config_found(self, &iba, crossprint); } @@ -209,169 +180,94 @@ crossprint(auxp, pnp) int -cross_io_map(bct, addr, sz, handle) - bus_chipset_tag_t bct; - bus_io_addr_t addr; - bus_io_size_t sz; - bus_io_handle_t *handle; -{ - *handle = (bus_io_handle_t) - ((struct cross_softc *)bct->bc_data)->sc_zargs.va + 2 * addr; -#if 0 - printf("io_map %x %d -> %x\n", addr, sz, *handle); -#endif - return 0; -} - -int -cross_mem_map(bct, addr, sz, cacheable, handle) - bus_chipset_tag_t bct; - bus_mem_addr_t addr; - bus_mem_size_t sz; +cross_io_map(bst, addr, sz, cacheable, handle) + bus_space_tag_t bst; + bus_addr_t addr; + bus_size_t sz; int cacheable; - bus_mem_handle_t *handle; + bus_space_handle_t *handle; { - *handle = (bus_mem_handle_t) - ((struct cross_softc *)bct->bc_data)->sc_zargs.va + 2 * addr + - CROSS_MEMORY_OFFSET; -#if 0 - printf("mem_map %x %d -> %x\n", addr, sz, *handle); -#endif + *handle = (bus_space_handle_t) + ((struct cross_softc *)bst->bs_data)->sc_zargs.va + 2 * addr; return 0; } int -cross_unmap(handle, sz) - bus_io_handle_t handle; - bus_io_size_t sz; -{ - return 0; -} - -__inline u_int8_t -cross_read_1(handle, addr) - bus_io_handle_t handle; - bus_io_size_t addr; -{ - u_int8_t val; - - /* generate A13-A19 for correct page */ - *CROSS_HANDLE_TO_XLP_LATCH(handle) = addr >> 13 | CROSS_SBHE; - val = *(volatile u_int8_t *)(handle + 2 * addr); - -#if 0 - printf("read_1 @%x handle %x -> %d\n", addr, handle, val); -#endif - return val; -} - -__inline u_int16_t -cross_read_2(handle, addr) - bus_io_handle_t handle; - bus_io_size_t addr; -{ - /* generate A13-A19 for correct page */ - *CROSS_HANDLE_TO_XLP_LATCH(handle) = addr >> 13 | CROSS_SBHE; - return *(volatile u_int16_t *)(handle + 2 * addr); -} - -void -cross_io_read_multi_1(handle, addr, buf, cnt) - bus_io_handle_t handle; - bus_io_size_t addr; - u_int8_t *buf; - bus_io_size_t cnt; -{ - while (cnt--) - *buf++ = cross_read_1(handle, addr); -} - -void -cross_io_read_multi_2(handle, addr, buf, cnt) - bus_io_handle_t handle; - bus_io_size_t addr; - u_int16_t *buf; - bus_io_size_t cnt; +cross_mem_map(bst, addr, sz, cacheable, handle) + bus_space_tag_t bst; + bus_addr_t addr; + bus_size_t sz; + int cacheable; + bus_space_handle_t *handle; { - while (cnt--) - *buf++ = cross_read_2(handle, addr); -} + bus_addr_t banked_start; + bus_size_t banked_size; + vm_object_t object; + vm_offset_t kva; + int error; -void -cross_io_read_raw_multi_2(handle, addr, buf, cnt) - bus_io_handle_t handle; - bus_io_size_t addr; - u_int8_t *buf; - bus_io_size_t cnt; -{ - u_int16_t *buf16 = (u_int16_t *)buf; + /* + * XXX When we do have a good enough extent-manager do extent + * checking here. + */ - while (cnt) { - cnt -= 2; - *buf16++ = swap(cross_read_2(handle, addr)); - } -} + /* + * Compute the bank range. Note that we need to shift bus-addresses + * and sizes left one bit. + */ + banked_start = (addr << 1) & ~(CROSS_BANK_SIZE - 1); + banked_size = ((sz << 1) + CROSS_BANK_SIZE - 1) & + ~(CROSS_BANK_SIZE - 1); -__inline void -cross_write_1(handle, addr, val) - bus_io_handle_t handle; - bus_io_size_t addr; - u_int8_t val; -{ - /* generate A13-A19 for correct page */ - *CROSS_HANDLE_TO_XLP_LATCH(handle) = addr >> 13 | CROSS_SBHE; -#if 0 - printf("write_1 @%x handle %x: %d\n", addr, handle, val); -#endif - *(volatile u_int8_t *)(handle + 2 * addr + 1) = val; -} + /* Create the object that will take care of the bankswitching. */ + object = vm_allocate_object(banked_size); + if (object == NULL) + goto fail_obj; + vm_object_setpager(object, cross_pager, 0, 0); -__inline void -cross_write_2(handle, addr, val) - bus_io_handle_t handle; - bus_io_size_t addr; - u_int16_t val; -{ - /* generate A13-A19 for correct page */ - *CROSS_HANDLE_TO_XLP_LATCH(handle) = addr >> 13 | CROSS_SBHE; - *(volatile u_int16_t *)(handle + 2 * addr) = val; -} + /* + * When done like this double mappings will be possible, thus + * wasting a little mapping space. This happens when several + * bus_space_map maps stuff from the same bank. But I don't care. + */ + kva = kmem_alloc_pageable(kernel_map, banked_size); + if (kva == 0) + goto fail_alloc; + vm_map_lock(kernel_map); + error = vm_map_insert(kernel_map, object, 0, kva, kva + banked_size); + vm_map_unlock(kernel_map); + if (error != KERN_SUCCESS) + goto fail_insert; + + /* Tell caller where to find his data. */ + *handle = (bus_space_handle_t)(kva + (addr << 1) - banked_addr)); + return 0; -void -cross_io_write_multi_1(handle, addr, buf, cnt) - bus_io_handle_t handle; - bus_io_size_t addr; - const u_int8_t *buf; - bus_io_size_t cnt; -{ - while (cnt--) - cross_write_1(handle, addr, *buf++); +fail_insert: + kmem_free(kernel_map, kva, banked_size); +fail_alloc: + vm_object_deallocate(object); +fail_obj: + return -1; } -void -cross_io_write_multi_2(handle, addr, buf, cnt) - bus_io_handle_t handle; - bus_io_size_t addr; - const u_int16_t *buf; - bus_io_size_t cnt; +int +cross_io_unmap(bst, handle, sz) + bus_space_tag_t bst; + bus_space_handle_t handle; + bus_size_t sz; { - while (cnt--) - cross_write_2(handle, addr, *buf++); + return 0; } -void -cross_io_write_raw_multi_2(handle, addr, buf, cnt) - bus_io_handle_t handle; - bus_io_size_t addr; - const u_int8_t *buf; - bus_io_size_t cnt; +int +cross_mem_unmap(bst, handle, sz) + bus_space_tag_t bst; + bus_space_handle_t handle; + bus_size_t sz; { - const u_int16_t *buf16 = (const u_int16_t *)buf; - - while (cnt) { - cnt -= 2; - cross_write_2(handle, addr, swap(*buf16++)); - } + /* Remove traphandler */ + return 0; } static cross_int_map[] = { @@ -501,10 +397,37 @@ cross_intr_disestablish(ic, arg) sc->sc_intrsharetype[irq] = IST_NONE; } -/* Swap bytes in a short word. */ -static u_short -swap(u_short x) +int +cross_pager_get_pages(pager, mlist, npages, sync) + vm_pager_t pager; + vm_page_t *mlist; + int npages; + boolean_t sync; { - __asm("rolw #8,%0" : "=r" (x) : "0" (x)); - return x; + int i; + vm_object_t object, old_object; + vm_offset_t offset; + + while(npages--) { + i = ((*mlist)->offset & (CROSS_BANK_SIZE - 1)) / NBPG; + object = (*mlist)->object; + old_object = sc->sc_page[i].offset; + offset = (*mlist)->offset; + vm_page_lock_queues(); + vm_object_lock(object); + if (old_object) + vm_object_lock(old_object); + vm_page_free(*mlist); + + /* generate A13-A19 for correct page */ + *CROSS_HANDLE_TO_XLP_LATCH(handle) = addr >> 13 | CROSS_SBHE; + + vm_page_rename(sc->sc_page[i], object, offset); + if (old_object) + vm_object_unlock(old_object); + vm_object_unlock(object); + vm_page_unlock_queues(); + mlist++: + } + return VM_PAGER_OK; } diff --git a/sys/arch/amiga/isa/crossreg.h b/sys/arch/amiga/isa/crossreg.h index 46a0d483b2a..d4de90635ce 100644 --- a/sys/arch/amiga/isa/crossreg.h +++ b/sys/arch/amiga/isa/crossreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: crossreg.h,v 1.3 1996/06/04 13:40:13 niklas Exp $ */ +/* $OpenBSD: crossreg.h,v 1.4 1996/11/28 23:33:07 niklas Exp $ */ /* * Copyright (c) 1994, 1996 Niklas Hallqvist, Carsten Hammer @@ -100,36 +100,38 @@ /* hardware offsets from config address */ -#define CROSS_XL_ROM 0x8000 -#define CROSS_XL_MEM 0x4000 -#define CROSS_XL_IO 0x0000 +#define CROSS_XL_ROM 0x8000 +#define CROSS_XL_MEM 0x4000 +#define CROSS_XL_IO 0x0000 -#define CROSS_XLP_INTSTAT 0 -#define CROSS_XLP_INTABLE 0 -#define CROSS_XLP_LATCH 2 +#define CROSS_BANK_SIZE (CROSS_XL_ROM - CROSS_XL_MEM) + +#define CROSS_XLP_INTSTAT 0 +#define CROSS_XLP_INTABLE 0 +#define CROSS_XLP_LATCH 2 #define CROSS_HANDLE_TO_XLP_LATCH(va) \ ((volatile u_int16_t *)(((va) & 0xffff) | CROSS_XLP_LATCH)) -#define CROSS_MEMORY_OFFSET (CROSS_XL_MEM - 2 * 0x90000) -#define CROSS_SBHE 0x40 +#define CROSS_MEMORY_OFFSET (CROSS_XL_MEM - 2 * 0x90000) +#define CROSS_SBHE 0x40 #define CROSS_STATUS_ADDR(va) \ ((volatile u_int16_t *)((va) + CROSS_XLP_INTSTAT)) -#define CROSS_MASTER 5 +#define CROSS_MASTER 5 -#define CROSS_IRQ9 10 /* IRQ9 is an alias of IRQ2 */ -#define CROSS_IRQ3 11 -#define CROSS_IRQ4 12 -#define CROSS_IRQ5 13 -#define CROSS_IRQ6 14 -#define CROSS_IRQ7 15 -#define CROSS_IRQ10 2 -#define CROSS_IRQ11 3 -#define CROSS_IRQ12 4 -#define CROSS_IRQ14 6 -#define CROSS_IRQ15 7 -#define CROSS_IRQMASK 0xfcdc +#define CROSS_IRQ9 10 /* IRQ9 is an alias of IRQ2 */ +#define CROSS_IRQ3 11 +#define CROSS_IRQ4 12 +#define CROSS_IRQ5 13 +#define CROSS_IRQ6 14 +#define CROSS_IRQ7 15 +#define CROSS_IRQ10 2 +#define CROSS_IRQ11 3 +#define CROSS_IRQ12 4 +#define CROSS_IRQ14 6 +#define CROSS_IRQ15 7 +#define CROSS_IRQMASK 0xfcdc #define CROSS_GET_INT_STATUS(va) (CROSS_GET_STATUS(va) & CROSS_IRQMASK) #define CROSS_ENABLE_INTS(va, ints) \ diff --git a/sys/arch/amiga/isa/crossvar.h b/sys/arch/amiga/isa/crossvar.h index 7eb5b792c9c..67a77e8382e 100644 --- a/sys/arch/amiga/isa/crossvar.h +++ b/sys/arch/amiga/isa/crossvar.h @@ -1,4 +1,4 @@ -/* $OpenBSD: crossvar.h,v 1.3 1996/06/04 13:40:14 niklas Exp $ */ +/* $OpenBSD: crossvar.h,v 1.4 1996/11/28 23:33:08 niklas Exp $ */ /* * Copyright (c) 1994, 1996 Niklas Hallqvist @@ -60,8 +60,10 @@ struct cross_softc { int sc_intrsharetype[ICU_LEN]; u_int16_t sc_imask; volatile u_int16_t *sc_status; + struct vm_page sc_page[CROSS_BANK_SIZE / NBPG]; - struct amiga_bus_chipset sc_bc; + struct amiga_bus_space sc_iot; + struct amiga_bus_space sc_memt; struct amiga_isa_chipset sc_ic; }; diff --git a/sys/arch/amiga/isa/ggbus.c b/sys/arch/amiga/isa/ggbus.c index 712f4043c94..f2444d34889 100644 --- a/sys/arch/amiga/isa/ggbus.c +++ b/sys/arch/amiga/isa/ggbus.c @@ -1,4 +1,4 @@ -/* $OpenBSD: ggbus.c,v 1.7 1996/11/23 21:45:26 kstailey Exp $ */ +/* $OpenBSD: ggbus.c,v 1.8 1996/11/28 23:33:08 niklas Exp $ */ /* * Copyright (c) 1994, 1995, 1996 Niklas Hallqvist @@ -60,50 +60,13 @@ void ggbusattach __P((struct device *, struct device *, void *)); int ggbusmatch __P((struct device *, void *, void *)); int ggbusprint __P((void *, const char *)); -int ggbus_io_map __P((bus_chipset_tag_t, bus_io_addr_t, bus_io_size_t, - bus_io_handle_t *)); -int ggbus_mem_map __P((bus_chipset_tag_t, bus_mem_addr_t, bus_mem_size_t, - int, bus_mem_handle_t *)); - -void ggbus_io_read_multi_1 __P((bus_io_handle_t, bus_io_size_t, u_int8_t *, - bus_io_size_t)); -void ggbus_io_read_multi_2 __P((bus_io_handle_t, bus_io_size_t, u_int16_t *, - bus_io_size_t)); - -void ggbus_io_write_multi_1 __P((bus_io_handle_t, bus_io_size_t, - const u_int8_t *, bus_io_size_t)); -void ggbus_io_write_multi_2 __P((bus_io_handle_t, bus_io_size_t, - const u_int16_t *, bus_io_size_t)); - -/* - * Note that the following unified access functions are prototyped for the - * I/O access case. We use casts to get type correctness. - */ -int ggbus_unmap __P((bus_io_handle_t, bus_io_size_t)); - -__inline u_int8_t ggbus_read_1 __P((bus_io_handle_t, bus_io_size_t)); -__inline u_int16_t ggbus_read_2 __P((bus_io_handle_t, bus_io_size_t)); - -__inline void ggbus_write_1 __P((bus_io_handle_t, bus_io_size_t, u_int8_t)); -__inline void ggbus_write_2 __P((bus_io_handle_t, bus_io_size_t, u_int16_t)); - -void ggbus_io_read_raw_multi_2 __P((bus_io_handle_t, bus_io_size_t, - u_int8_t *, bus_io_size_t)); -void ggbus_io_write_raw_multi_2 __P((bus_io_handle_t, bus_io_size_t, - const u_int8_t *, bus_io_size_t)); - -/* - * In order to share the access function implementations for I/O and memory - * access we cast the functions for the memory access case. These typedefs - * make that casting look nicer. - */ -typedef int (*bus_mem_unmap_t) __P((bus_mem_handle_t, bus_mem_size_t)); -typedef u_int8_t (*bus_mem_read_1_t) __P((bus_mem_handle_t, bus_mem_size_t)); -typedef u_int16_t (*bus_mem_read_2_t) __P((bus_mem_handle_t, bus_mem_size_t)); -typedef void (*bus_mem_write_1_t) __P((bus_mem_handle_t, bus_mem_size_t, - u_int8_t)); -typedef void (*bus_mem_write_2_t) __P((bus_mem_handle_t, bus_mem_size_t, - u_int16_t)); +int ggbus_io_map __P((bus_space_tag_t, bus_addr_t, bus_size_t, int, + bus_space_handle_t *)); +int ggbus_mem_map __P((bus_space_tag_t, bus_addr_t, bus_size_t, int, + bus_space_handle_t *)); +int ggbus_cannot_mem_map __P((bus_space_tag_t, bus_addr_t, bus_size_t, int, + bus_space_handle_t *)); +int ggbus_unmap __P((bus_space_tag_t, bus_space_handle_t, bus_size_t)); int ggbusintr __P((void *)); @@ -113,62 +76,6 @@ void *ggbus_intr_establish __P((void *, int, int, int, int (*)(void *), void *, char *)); void ggbus_intr_disestablish __P((void *, void *)); -static u_int16_t swap __P((u_int16_t)); - -/* Golden Gate I. */ -struct amiga_bus_chipset ggbus1_chipset = { - 0 /* bc_data */, - - ggbus_io_map, ggbus_unmap, - ggbus_read_1, ggbus_read_2, - 0 /* bc_io_read_4 */, 0 /* bc_io_read_8 */, - ggbus_io_read_multi_1, ggbus_io_read_multi_2, - 0 /* bc_io_multi_4 */, 0 /* bc_io_multi_8 */, - ggbus_write_1, ggbus_write_2, - 0 /* bc_io_write_4 */, 0 /* bc_io_write_8 */, - ggbus_io_write_multi_1, ggbus_io_write_multi_2, - 0 /* bc_io_write_multi_4 */, 0 /* bc_io_write_multi_8 */, - - 0 /* bc_mem_map */, 0 /* bc_mem_unmap */, - 0 /* bc_mem_read_1 */, 0 /* bc_mem_read_2 */, - 0 /* bc_mem_read_4 */, 0 /* bc_mem_read_8 */, - 0 /* bc_mem_write_1 */, 0 /* bc_mem_write_2 */, - 0 /* bc_mem_write_4 */, 0 /* bc_mem_write_8 */, - - 0 /* bc_io_read_raw_multi_2 */, - 0 /* bc_io_read_raw_multi_4 */, 0 /* bc_io_read_raw_multi_8 */, - - 0 /* bc_io_write_raw_multi_2 */, - 0 /* bc_io_write_raw_multi_4 */, 0 /* bc_io_write_raw_multi_8 */, -}; - -/* Golden Gate II. */ -struct amiga_bus_chipset ggbus2_chipset = { - 0 /* bc_data */, - - ggbus_io_map, ggbus_unmap, - ggbus_read_1, ggbus_read_2, - 0 /* bc_io_read_4 */, 0 /* bc_io_read_8 */, - ggbus_io_read_multi_1, ggbus_io_read_multi_2, - 0 /* bc_io_multi_4 */, 0 /* bc_io_multi_8 */, - ggbus_write_1, ggbus_write_2, - 0 /* bc_io_write_4 */, 0 /* bc_io_write_8 */, - ggbus_io_write_multi_1, ggbus_io_write_multi_2, - 0 /* bc_io_write_multi_4 */, 0 /* bc_io_write_multi_8 */, - - ggbus_mem_map, (bus_mem_unmap_t)ggbus_unmap, - (bus_mem_read_1_t)ggbus_read_1, (bus_mem_read_2_t)ggbus_read_2, - 0 /* bc_mem_read_4 */, 0 /* bc_mem_read_8 */, - (bus_mem_write_1_t)ggbus_write_1, (bus_mem_write_2_t)ggbus_write_2, - 0 /* bc_mem_write_4 */, 0 /* bc_mem_write_8 */, - - ggbus_io_read_raw_multi_2, - 0 /* bc_io_read_raw_multi_4 */, 0 /* bc_io_read_raw_multi_8 */, - - ggbus_io_write_raw_multi_2, - 0 /* bc_io_write_raw_multi_4 */, 0 /* bc_io_write_raw_multi_8 */, -}; - struct cfattach ggbus_ca = { sizeof(struct ggbus_softc), ggbusmatch, ggbusattach }; @@ -202,17 +109,22 @@ ggbusattach(parent, self, aux) struct isabus_attach_args iba; bcopy(zap, &sc->sc_zargs, sizeof(struct zbus_args)); - /* XXX Is serno reliable? */ - bcopy(zap->serno < 2 ? &ggbus1_chipset : &ggbus2_chipset, - &sc->sc_bc, sizeof(struct amiga_bus_chipset)); - sc->sc_bc.bc_data = sc; - sc->sc_status = GG2_STATUS_ADDR(sc->sc_zargs.va); - + sc->sc_iot.bs_data = sc; + sc->sc_iot.bs_map = ggbus_io_map; + sc->sc_iot.bs_unmap = ggbus_unmap; + sc->sc_iot.bs_swapped = 0; if (sc->sc_zargs.serno >= 2) { + sc->sc_memt.bs_data = sc; + sc->sc_memt.bs_map = ggbus_mem_map; + sc->sc_memt.bs_unmap = ggbus_unmap; + sc->sc_memt.bs_swapped = 0; + sc->sc_status = GG2_STATUS_ADDR(sc->sc_zargs.va); + /* XXX turn on wait states unconditionally for now. */ GG2_ENABLE_WAIT(zap->va); GG2_ENABLE_INTS(zap->va); - } + } else + sc->sc_memt.bs_map = ggbus_cannot_mem_map; printf(": pa 0x%08x va 0x%08x size 0x%x\n", zap->pa, zap->va, zap->size); @@ -223,7 +135,8 @@ ggbusattach(parent, self, aux) sc->sc_ic.ic_intr_disestablish = ggbus_intr_disestablish; iba.iba_busname = "isa"; - iba.iba_bc = &sc->sc_bc; + iba.iba_iot = &sc->sc_iot; + iba.iba_memt = &sc->sc_memt; iba.iba_ic = &sc->sc_ic; config_found(self, &iba, ggbusprint); } @@ -239,159 +152,54 @@ ggbusprint(auxp, pnp) } int -ggbus_io_map(bct, addr, sz, handle) - bus_chipset_tag_t bct; - bus_io_addr_t addr; - bus_io_size_t sz; - bus_io_handle_t *handle; +ggbus_io_map(bst, addr, sz, cacheable, handle) + bus_space_tag_t bst; + bus_addr_t addr; + bus_size_t sz; + int cacheable; + bus_space_handle_t *handle; { - *handle = (bus_io_handle_t) - ((struct ggbus_softc *)bct->bc_data)->sc_zargs.va + 2 * addr; -#if 0 - printf("io_map %x %d -> %x\n", addr, sz, *handle); -#endif + *handle = (bus_space_handle_t) + ((struct ggbus_softc *)bst->bs_data)->sc_zargs.va + 2 * addr + 1; return 0; } int -ggbus_mem_map(bct, addr, sz, cacheable, handle) - bus_chipset_tag_t bct; - bus_mem_addr_t addr; - bus_mem_size_t sz; +ggbus_mem_map(bst, addr, sz, cacheable, handle) + bus_space_tag_t bst; + bus_addr_t addr; + bus_size_t sz; int cacheable; - bus_mem_handle_t *handle; + bus_space_handle_t *handle; { - *handle = (bus_mem_handle_t) - ((struct ggbus_softc *)bct->bc_data)->sc_zargs.va + 2 * addr + + *handle = (bus_space_handle_t) + ((struct ggbus_softc *)bst->bs_data)->sc_zargs.va + 2 * addr + GG2_MEMORY_OFFSET; -#if 0 - printf("mem_map %x %d -> %x\n", addr, sz, *handle); -#endif return 0; } int -ggbus_unmap(handle, sz) - bus_io_handle_t handle; - bus_io_size_t sz; -{ - return 0; -} - -__inline u_int8_t -ggbus_read_1(handle, addr) - bus_io_handle_t handle; - bus_io_size_t addr; -{ - u_int8_t val = *(volatile u_int8_t *)(handle + 2 * addr + 1); - -#if 0 - printf("read_1 @%x handle %x -> %d\n", addr, handle, val); -#endif - return val; -} - -__inline u_int16_t -ggbus_read_2(handle, addr) - bus_io_handle_t handle; - bus_io_size_t addr; -{ - return *(volatile u_int16_t *)(handle + 2 * addr); -} - -void -ggbus_io_read_multi_1(handle, addr, buf, cnt) - bus_io_handle_t handle; - bus_io_size_t addr; - u_int8_t *buf; - bus_io_size_t cnt; -{ - while (cnt--) - *buf++ = ggbus_read_1(handle, addr); -} - -void -ggbus_io_read_multi_2(handle, addr, buf, cnt) - bus_io_handle_t handle; - bus_io_size_t addr; - u_int16_t *buf; - bus_io_size_t cnt; -{ - while (cnt--) - *buf++ = ggbus_read_2(handle, addr); -} - -void -ggbus_io_read_raw_multi_2(handle, addr, buf, cnt) - bus_io_handle_t handle; - bus_io_size_t addr; - u_int8_t *buf; - bus_io_size_t cnt; -{ - u_int16_t *buf16 = (u_int16_t *)buf; - - while (cnt) { - cnt -= 2; - *buf16++ = swap(ggbus_read_2(handle, addr)); - } -} - -__inline void -ggbus_write_1(handle, addr, val) - bus_io_handle_t handle; - bus_io_size_t addr; - u_int8_t val; -{ -#if 0 - printf("write_1 @%x handle %x: %d\n", addr, handle, val); -#endif - *(volatile u_int8_t *)(handle + 2 * addr + 1) = val; -} - -__inline void -ggbus_write_2(handle, addr, val) - bus_io_handle_t handle; - bus_io_size_t addr; - u_int16_t val; -{ - *(volatile u_int16_t *)(handle + 2 * addr) = val; -} - -void -ggbus_io_write_multi_1(handle, addr, buf, cnt) - bus_io_handle_t handle; - bus_io_size_t addr; - const u_int8_t *buf; - bus_io_size_t cnt; +ggbus_cannot_mem_map(bst, addr, sz, cacheable, handle) + bus_space_tag_t bst; + bus_addr_t addr; + bus_size_t sz; + int cacheable; + bus_space_handle_t *handle; { - while (cnt--) - ggbus_write_1(handle, addr, *buf++); -} + static int have_warned = 0; -void -ggbus_io_write_multi_2(handle, addr, buf, cnt) - bus_io_handle_t handle; - bus_io_size_t addr; - const u_int16_t *buf; - bus_io_size_t cnt; -{ - while (cnt--) - ggbus_write_2(handle, addr, *buf++); + if (!have_warned++) + printf("The Golden Gate 1 cannot map ISA memory.\n"); + return -1; } -void -ggbus_io_write_raw_multi_2(handle, addr, buf, cnt) - bus_io_handle_t handle; - bus_io_size_t addr; - const u_int8_t *buf; - bus_io_size_t cnt; +int +ggbus_unmap(bst, handle, sz) + bus_space_tag_t bst; + bus_space_handle_t handle; + bus_size_t sz; { - const u_int16_t *buf16 = (const u_int16_t *)buf; - - while (cnt) { - cnt -= 2; - ggbus_write_2(handle, addr, swap(*buf16++)); - } + return 0; } static ggbus_int_map[] = { @@ -514,11 +322,3 @@ ggbus_intr_disestablish(ic, arg) if (sc->sc_intrsharetype[irq] == NULL) sc->sc_intrsharetype[irq] = IST_NONE; } - -/* Swap bytes in a short word. */ -static u_int16_t -swap(u_int16_t x) -{ - __asm("rolw #8,%0" : "=r" (x) : "0" (x)); - return x; -} diff --git a/sys/arch/amiga/isa/ggbusvar.h b/sys/arch/amiga/isa/ggbusvar.h index 0d48add4499..d3aa2b7997f 100644 --- a/sys/arch/amiga/isa/ggbusvar.h +++ b/sys/arch/amiga/isa/ggbusvar.h @@ -1,4 +1,4 @@ -/* $OpenBSD: ggbusvar.h,v 1.3 1996/06/04 13:40:14 niklas Exp $ */ +/* $OpenBSD: ggbusvar.h,v 1.4 1996/11/28 23:33:09 niklas Exp $ */ /* * Copyright (c) 1994, 1995, 1996 Niklas Hallqvist @@ -60,7 +60,8 @@ struct ggbus_softc { int sc_intrsharetype[ICU_LEN]; volatile u_int16_t *sc_status; - struct amiga_bus_chipset sc_bc; + struct amiga_bus_space sc_iot; + struct amiga_bus_space sc_memt; struct amiga_isa_chipset sc_ic; }; diff --git a/sys/arch/amiga/isa/if_isaed.c b/sys/arch/amiga/isa/if_isaed.c index fbc720e52fc..5527ccd2b52 100644 --- a/sys/arch/amiga/isa/if_isaed.c +++ b/sys/arch/amiga/isa/if_isaed.c @@ -1,8 +1,8 @@ -/* $OpenBSD: if_isaed.c,v 1.13 1996/11/12 20:29:51 niklas Exp $ */ +/* $OpenBSD: if_isaed.c,v 1.14 1996/11/28 23:33:09 niklas Exp $ */ /* * Derived from sys/dev/isa/if_ed.c: - * $NetBSD: if_ed.c,v 1.100 1996/05/12 23:52:19 mycroft Exp $ + * $NetBSD: if_ed.c,v 1.105 1996/10/21 22:40:45 thorpej Exp $ */ /* @@ -53,7 +53,7 @@ #endif #include <machine/cpu.h> -#include <machine/bus.old.h> +#include <machine/bus.h> #include <machine/intr.h> #include <dev/isa/isareg.h> @@ -66,10 +66,10 @@ */ struct ed_softc { struct device sc_dev; - void *sc_ih; + void *sc_ih; struct arpcom sc_arpcom; /* ethernet common */ - void *sc_sh; /* shutdown hook */ + void *sc_sh; /* shutdown hook */ char *type_str; /* pointer to type string */ u_char vendor; /* interface vendor */ @@ -79,13 +79,14 @@ struct ed_softc { #define ED_NOTPRESENT 0x0002 /* card not present; do not allow reconfiguration */ - bus_chipset_tag_t sc_bc; /* bus identifier */ - bus_io_handle_t sc_ioh; /* io handle */ - bus_io_handle_t sc_delayioh; /* io handle for `delay port' */ - bus_mem_handle_t sc_memh; /* bus memory handle */ + bus_space_tag_t sc_iot; /* bus identifier */ + bus_space_tag_t sc_memt; + bus_space_handle_t sc_ioh; /* io handle */ + bus_space_handle_t sc_delaybah; /* io handle for `delay port' */ + bus_space_handle_t sc_memh; /* bus memory handle */ - bus_io_size_t asic_base; /* offset of ASIC I/O port */ - bus_io_size_t nic_base; /* offset of NIC (DS8390) I/O port */ + bus_size_t asic_base; /* offset of ASIC I/O port */ + bus_size_t nic_base; /* offset of NIC (DS8390) I/O port */ /* * The following 'proto' variable is part of a work-around for 8013EBT asics @@ -123,7 +124,7 @@ int edprobe __P((struct device *, void *, void *)); void edattach __P((struct device *, struct device *, void *)); int ed_find __P((struct ed_softc *, struct cfdata *, struct isa_attach_args *ia)); -int ed_probe_generic8390 __P((bus_chipset_tag_t, bus_io_handle_t, int)); +int ed_probe_generic8390 __P((bus_space_tag_t, bus_space_handle_t, int)); int ed_find_WD80x3 __P((struct ed_softc *, struct cfdata *, struct isa_attach_args *ia)); int ed_find_3Com __P((struct ed_softc *, struct cfdata *, @@ -291,7 +292,7 @@ ed_remove(pc_link,self) shutdownhook_disestablish(sc->sc_sh); ifp->if_flags &= ~(IFF_RUNNING|IFF_UP); sc->spec_flags |= ED_NOTPRESENT; - isa_intr_disestablish(sc->sc_bc, sc->sc_ih); + isa_intr_disestablish(sc->sc_ic, sc->sc_ih); return PCMCIA_BUS_UNCONFIG(pc_link->adapter, pc_link); } @@ -366,10 +367,10 @@ ed_pcmcia_detach(self) #endif -#define NIC_PUT(bc, ioh, nic, reg, val) \ - bus_io_write_1((bc), (ioh), ((nic) + (reg)), (val)) -#define NIC_GET(bc, ioh, nic, reg) \ - bus_io_read_1((bc), (ioh), ((nic) + (reg))) +#define NIC_PUT(t, bah, nic, reg, val) \ + bus_space_write_1((t), (bah), ((nic) + (reg)), (val)) +#define NIC_GET(t, bah, nic, reg) \ + bus_space_read_1((t), (bah), ((nic) + (reg))) /* * Determine if the device is present. @@ -432,17 +433,17 @@ ed_find(sc, cf, ia) * Return 1 if 8390 was found, 0 if not. */ int -ed_probe_generic8390(bc, ioh, nicbase) - bus_chipset_tag_t bc; - bus_io_handle_t ioh; +ed_probe_generic8390(t, bah, nicbase) + bus_space_tag_t t; + bus_space_handle_t bah; int nicbase; { - if ((NIC_GET(bc, ioh, nicbase, ED_P0_CR) & + if ((NIC_GET(t, bah, nicbase, ED_P0_CR) & (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) != (ED_CR_RD2 | ED_CR_STP)) return (0); - if ((NIC_GET(bc, ioh, nicbase, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) + if ((NIC_GET(t, bah, nicbase, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) return (0); return (1); @@ -460,23 +461,25 @@ ed_find_WD80x3(sc, cf, ia) struct cfdata *cf; struct isa_attach_args *ia; { - bus_chipset_tag_t bc; - bus_io_handle_t ioh; - bus_io_handle_t delayioh = ia->ia_delayioh; - bus_mem_handle_t memh; + bus_space_tag_t iot; + bus_space_tag_t memt; + bus_space_handle_t ioh; + bus_space_handle_t delaybah = ia->ia_delaybah; + bus_space_handle_t memh; u_int memsize; u_char iptr, isa16bit, sum; int i, rv, memfail, mapped_mem = 0; int asicbase, nicbase; - bc = ia->ia_bc; + iot = ia->ia_iot; + memt = ia->ia_memt; rv = 0; /* Set initial values for width/size. */ memsize = 8192; isa16bit = 0; - if (bus_io_map(bc, ia->ia_iobase, ED_WD_IO_PORTS, &ioh)) + if (bus_space_map(iot, ia->ia_iobase, ED_WD_IO_PORTS, 0, &ioh)) return (0); sc->asic_base = asicbase = 0; @@ -484,7 +487,7 @@ ed_find_WD80x3(sc, cf, ia) sc->is790 = 0; #ifdef TOSH_ETHER - bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR, ED_WD_MSR_POW); + bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR, ED_WD_MSR_POW); delay(10000); #endif @@ -495,7 +498,7 @@ ed_find_WD80x3(sc, cf, ia) * Danpex boards for one. */ for (sum = 0, i = 0; i < 8; ++i) - sum += bus_io_read_1(bc, ioh, asicbase + ED_WD_PROM + i); + sum += bus_space_read_1(iot, ioh, asicbase + ED_WD_PROM + i); if (sum != ED_WD_ROM_CHECKSUM_TOTAL) { /* @@ -503,27 +506,27 @@ ed_find_WD80x3(sc, cf, ia) * clones. In this case, the checksum byte (the eighth byte) * seems to always be zero. */ - if (bus_io_read_1(bc, ioh, asicbase + ED_WD_CARD_ID) != + if (bus_space_read_1(iot, ioh, asicbase + ED_WD_CARD_ID) != ED_TYPE_WD8003E || - bus_io_read_1(bc, ioh, asicbase + ED_WD_PROM + 7) != 0) + bus_space_read_1(iot, ioh, asicbase + ED_WD_PROM + 7) != 0) goto out; } /* Reset card to force it into a known state. */ #ifdef TOSH_ETHER - bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR, + bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW); #else - bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR, ED_WD_MSR_RST); + bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR, ED_WD_MSR_RST); #endif delay(100); - bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR, - bus_io_read_1(bc, ioh, asicbase + ED_WD_MSR) & ~ED_WD_MSR_RST); + bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR, + bus_space_read_1(iot, ioh, asicbase + ED_WD_MSR) & ~ED_WD_MSR_RST); /* Wait in the case this card is reading it's EEROM. */ delay(5000); sc->vendor = ED_VENDOR_WD_SMC; - sc->type = bus_io_read_1(bc, ioh, asicbase + ED_WD_CARD_ID); + sc->type = bus_space_read_1(iot, ioh, asicbase + ED_WD_CARD_ID); switch (sc->type) { case ED_TYPE_WD8003S: @@ -549,7 +552,7 @@ ed_find_WD80x3(sc, cf, ia) isa16bit = 1; break; case ED_TYPE_WD8013EP: /* also WD8003EP */ - if (bus_io_read_1(bc, ioh, asicbase + ED_WD_ICR) + if (bus_space_read_1(iot, ioh, asicbase + ED_WD_ICR) & ED_WD_ICR_16BIT) { isa16bit = 1; memsize = 16384; @@ -576,10 +579,10 @@ ed_find_WD80x3(sc, cf, ia) case ED_TYPE_SMC8216T: sc->type_str = (sc->type == ED_TYPE_SMC8216C) ? "SMC8216/SMC8216C" : "SMC8216T"; - bus_io_write_1(bc, ioh, asicbase + ED_WD790_HWR, - bus_io_read_1(bc, ioh, asicbase + ED_WD790_HWR) + bus_space_write_1(iot, ioh, asicbase + ED_WD790_HWR, + bus_space_read_1(iot, ioh, asicbase + ED_WD790_HWR) | ED_WD790_HWR_SWH); - switch (bus_io_read_1(bc, ioh, asicbase + ED_WD790_RAR) & + switch (bus_space_read_1(iot, ioh, asicbase + ED_WD790_RAR) & ED_WD790_RAR_SZ64) { case ED_WD790_RAR_SZ64: memsize = 65536; @@ -597,8 +600,8 @@ ed_find_WD80x3(sc, cf, ia) memsize = 8192; break; } - bus_io_write_1(bc, ioh, asicbase + ED_WD790_HWR, - bus_io_read_1(bc, ioh, + bus_space_write_1(iot, ioh, asicbase + ED_WD790_HWR, + bus_space_read_1(iot, ioh, asicbase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); isa16bit = 1; @@ -628,7 +631,7 @@ ed_find_WD80x3(sc, cf, ia) #ifdef TOSH_ETHER (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4) && #endif - ((bus_io_read_1(bc, ioh, + ((bus_space_read_1(iot, ioh, asicbase + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) { isa16bit = 0; memsize = 8192; @@ -639,7 +642,8 @@ ed_find_WD80x3(sc, cf, ia) sc->type, sc->type_str ?: "unknown", isa16bit, memsize, ia->ia_msize); for (i = 0; i < 8; i++) - printf("%x -> %x\n", i, bus_io_read_1(bc, ioh, asicbase + i)); + printf("%x -> %x\n", i, + bus_space_read_1(iot, ioh, asicbase + i)); #endif /* Allow the user to override the autoconfiguration. */ if (ia->ia_msize) @@ -660,13 +664,13 @@ ed_find_WD80x3(sc, cf, ia) if (sc->is790) { u_char x; /* Assemble together the encoded interrupt number. */ - bus_io_write_1(bc, ioh, ED_WD790_HWR, - bus_io_read_1(bc, ioh, ED_WD790_HWR) | ED_WD790_HWR_SWH); - x = bus_io_read_1(bc, ioh, ED_WD790_GCR); + bus_space_write_1(iot, ioh, ED_WD790_HWR, + bus_space_read_1(iot, ioh, ED_WD790_HWR) | ED_WD790_HWR_SWH); + x = bus_space_read_1(iot, ioh, ED_WD790_GCR); iptr = ((x & ED_WD790_GCR_IR2) >> 4) | ((x & (ED_WD790_GCR_IR1|ED_WD790_GCR_IR0)) >> 2); - bus_io_write_1(bc, ioh, ED_WD790_HWR, - bus_io_read_1(bc, ioh, ED_WD790_HWR) & ~ED_WD790_HWR_SWH); + bus_space_write_1(iot, ioh, ED_WD790_HWR, + bus_space_read_1(iot, ioh, ED_WD790_HWR) & ~ED_WD790_HWR_SWH); /* * Translate it using translation table, and check for * correctness. @@ -681,12 +685,12 @@ ed_find_WD80x3(sc, cf, ia) } else ia->ia_irq = ed_wd790_irq[iptr]; /* Enable the interrupt. */ - bus_io_write_1(bc, ioh, ED_WD790_ICR, - bus_io_read_1(bc, ioh, ED_WD790_ICR) | ED_WD790_ICR_EIL); + bus_space_write_1(iot, ioh, ED_WD790_ICR, + bus_space_read_1(iot, ioh, ED_WD790_ICR) | ED_WD790_ICR_EIL); } else if (sc->type & ED_WD_SOFTCONFIG) { /* Assemble together the encoded interrupt number. */ - iptr = (bus_io_read_1(bc, ioh, ED_WD_ICR) & ED_WD_ICR_IR2) | - ((bus_io_read_1(bc, ioh, ED_WD_IRR) & + iptr = (bus_space_read_1(iot, ioh, ED_WD_ICR) & ED_WD_ICR_IR2) | + ((bus_space_read_1(iot, ioh, ED_WD_IRR) & (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5); /* * Translate it using translation table, and check for @@ -702,8 +706,8 @@ ed_find_WD80x3(sc, cf, ia) } else ia->ia_irq = ed_wd584_irq[iptr]; /* Enable the interrupt. */ - bus_io_write_1(bc, ioh, ED_WD_IRR, - bus_io_read_1(bc, ioh, ED_WD_IRR) | ED_WD_IRR_IEN); + bus_space_write_1(iot, ioh, ED_WD_IRR, + bus_space_read_1(iot, ioh, ED_WD_IRR) | ED_WD_IRR_IEN); } else { if (ia->ia_irq == IRQUNK) { printf("%s: %s does not have soft configuration\n", @@ -717,7 +721,7 @@ ed_find_WD80x3(sc, cf, ia) sc->isa16bit = isa16bit; sc->mem_shared = 1; ia->ia_msize = memsize; - if (bus_mem_map(bc, ia->ia_maddr, memsize, 0, &memh)) + if (bus_space_map(memt, ia->ia_maddr, memsize, 0, &memh)) goto out; mapped_mem = 1; sc->mem_start = 0; /* offset */ @@ -738,7 +742,7 @@ ed_find_WD80x3(sc, cf, ia) /* Get station address from on-board ROM. */ for (i = 0; i < ETHER_ADDR_LEN; ++i) sc->sc_arpcom.ac_enaddr[i] = - bus_io_read_1(bc, ioh, asicbase + ED_WD_PROM + i); + bus_space_read_1(iot, ioh, asicbase + ED_WD_PROM + i); /* * Set upper address bits and 8/16 bit access to shared memory. @@ -746,7 +750,7 @@ ed_find_WD80x3(sc, cf, ia) if (isa16bit) { if (sc->is790) { sc->wd_laar_proto = - bus_io_read_1(bc, ioh, asicbase + ED_WD_LAAR) & + bus_space_read_1(iot, ioh, asicbase + ED_WD_LAAR) & ~ED_WD_LAAR_M16EN; } else { sc->wd_laar_proto = @@ -754,7 +758,7 @@ ed_find_WD80x3(sc, cf, ia) ((ia->ia_maddr >> 19) & ED_WD_LAAR_ADDRHI); } - bus_io_write_1(bc, ioh, asicbase + ED_WD_LAAR, + bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR, sc->wd_laar_proto | ED_WD_LAAR_M16EN); } else { if ((sc->type & ED_WD_SOFTCONFIG) || @@ -766,7 +770,7 @@ ed_find_WD80x3(sc, cf, ia) sc->wd_laar_proto = ((ia->ia_maddr >> 19) & ED_WD_LAAR_ADDRHI); - bus_io_write_1(bc, ioh, asicbase + ED_WD_LAAR, + bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR, sc->wd_laar_proto); } } @@ -776,9 +780,9 @@ ed_find_WD80x3(sc, cf, ia) */ if (!sc->is790) { #ifdef TOSH_ETHER - bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR + 1, + bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR + 1, ((ia->ia_maddr >> 8) & 0xe0) | 4); - bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR + 2, + bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR + 2, ((ia->ia_maddr >> 16) & 0x0f)); sc->wd_msr_proto = ED_WD_MSR_POW; #else @@ -787,43 +791,43 @@ ed_find_WD80x3(sc, cf, ia) #endif sc->cr_proto = ED_CR_RD2; } else { - bus_io_write_1(bc, ioh, asicbase + 0x04, - bus_io_read_1(bc, ioh, asicbase + 0x04) | 0x80); - bus_io_write_1(bc, ioh, asicbase + 0x0b, + bus_space_write_1(iot, ioh, asicbase + 0x04, + bus_space_read_1(iot, ioh, asicbase + 0x04) | 0x80); + bus_space_write_1(iot, ioh, asicbase + 0x0b, ((ia->ia_maddr >> 13) & 0x0f) | ((ia->ia_maddr >> 11) & 0x40) | - (bus_io_read_1(bc, ioh, asicbase + 0x0b) & 0xb0)); - bus_io_write_1(bc, ioh, asicbase + 0x04, - bus_io_read_1(bc, ioh, asicbase + 0x04) & ~0x80); + (bus_space_read_1(iot, ioh, asicbase + 0x0b) & 0xb0)); + bus_space_write_1(iot, ioh, asicbase + 0x04, + bus_space_read_1(iot, ioh, asicbase + 0x04) & ~0x80); sc->wd_msr_proto = 0x00; sc->cr_proto = 0; } - bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR, + bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR, sc->wd_msr_proto | ED_WD_MSR_MENB); - (void) bus_io_read_1(bc, delayioh, 0); - (void) bus_io_read_1(bc, delayioh, 0); + (void) bus_space_read_1(iot, delaybah, 0); + (void) bus_space_read_1(iot, delaybah, 0); /* Now zero memory and verify that it is clear. */ if (isa16bit) { for (i = 0; i < memsize; i += 2) - bus_mem_write_2(bc, memh, sc->mem_start + i, 0); + bus_space_write_2(memt, memh, sc->mem_start + i, 0); } else { for (i = 0; i < memsize; ++i) - bus_mem_write_1(bc, memh, sc->mem_start + i, 0); + bus_space_write_1(memt, memh, sc->mem_start + i, 0); } memfail = 0; if (isa16bit) { for (i = 0; i < memsize; i += 2) { - if (bus_mem_read_2(bc, memh, sc->mem_start + i)) { + if (bus_space_read_2(memt, memh, sc->mem_start + i)) { memfail = 1; break; } } } else { for (i = 0; i < memsize; ++i) { - if (bus_mem_read_1(bc, memh, sc->mem_start + i)) { + if (bus_space_read_1(memt, memh, sc->mem_start + i)) { memfail = 1; break; } @@ -837,13 +841,13 @@ ed_find_WD80x3(sc, cf, ia) (ia->ia_maddr + sc->mem_start + i)); /* Disable 16 bit access to shared memory. */ - bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR, + bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR, sc->wd_msr_proto); if (isa16bit) - bus_io_write_1(bc, ioh, asicbase + ED_WD_LAAR, + bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR, sc->wd_laar_proto); - (void) bus_io_read_1(bc, delayioh, 0); - (void) bus_io_read_1(bc, delayioh, 0); + (void) bus_space_read_1(iot, delaybah, 0); + (void) bus_space_read_1(iot, delaybah, 0); goto out; } @@ -855,12 +859,12 @@ ed_find_WD80x3(sc, cf, ia) * and 2) so that other 8 bit devices with shared memory can be * used in this 128k region, too. */ - bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR, sc->wd_msr_proto); + bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR, sc->wd_msr_proto); if (isa16bit) - bus_io_write_1(bc, ioh, asicbase + ED_WD_LAAR, + bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR, sc->wd_laar_proto); - (void) bus_io_read_1(bc, delayioh, 0); - (void) bus_io_read_1(bc, delayioh, 0); + (void) bus_space_read_1(iot, delaybah, 0); + (void) bus_space_read_1(iot, delaybah, 0); ia->ia_iosize = ED_WD_IO_PORTS; rv = 1; @@ -871,20 +875,24 @@ ed_find_WD80x3(sc, cf, ia) * XXX Need to squish "indirect" first. */ if (rv == 0) { - bus_io_unmap(bc, ioh, ED_WD_IO_PORTS); + bus_space_unmap(iot, ioh, ED_WD_IO_PORTS); if (mapped_mem) - bus_mem_unmap(bc, memh, memsize); + bus_space_unmap(memt, memh, memsize); } else { /* XXX this is all "indirect" brokenness */ - sc->sc_bc = bc; + sc->sc_iot = iot; + sc->sc_memt = memt; sc->sc_ioh = ioh; sc->sc_memh = memh; } return (rv); } -int ed_3com_iobase[] = {0x2e0, 0x2a0, 0x280, 0x250, 0x350, 0x330, 0x310, 0x300}; -int ed_3com_maddr[] = {MADDRUNK, MADDRUNK, MADDRUNK, MADDRUNK, 0xc8000, 0xcc000, 0xd8000, 0xdc000}; +int ed_3com_iobase[] = + {0x2e0, 0x2a0, 0x280, 0x250, 0x350, 0x330, 0x310, 0x300}; +int ed_3com_maddr[] = { + MADDRUNK, MADDRUNK, MADDRUNK, MADDRUNK, 0xc8000, 0xcc000, 0xd8000, 0xdc000 +}; #if 0 int ed_3com_irq[] = {IRQUNK, IRQUNK, IRQUNK, IRQUNK, 9, 3, 4, 5}; #endif @@ -898,9 +906,10 @@ ed_find_3Com(sc, cf, ia) struct cfdata *cf; struct isa_attach_args *ia; { - bus_chipset_tag_t bc; - bus_io_handle_t ioh; - bus_mem_handle_t memh; + bus_space_tag_t iot; + bus_space_tag_t memt; + bus_space_handle_t ioh; + bus_space_handle_t memh; int i; u_int memsize, memfail; u_char isa16bit, x; @@ -912,9 +921,10 @@ ed_find_3Com(sc, cf, ia) */ memsize = 8192; - bc = ia->ia_bc; + iot = ia->ia_iot; + memt = ia->ia_memt; - if (bus_io_map(bc, ia->ia_iobase, ED_WD_IO_PORTS, &ioh)) + if (bus_space_map(iot, ia->ia_iobase, ED_3COM_IO_PORTS, 0, &ioh)) return (0); sc->asic_base = asicbase = ED_3COM_ASIC_OFFSET; @@ -928,7 +938,7 @@ ed_find_3Com(sc, cf, ia) * board is there; after all, we are already talking it at that * address. */ - x = bus_io_read_1(bc, ioh, asicbase + ED_3COM_BCFR); + x = bus_space_read_1(iot, ioh, asicbase + ED_3COM_BCFR); if (x == 0 || (x & (x - 1)) != 0) goto err; ptr = ffs(x) - 1; @@ -942,9 +952,14 @@ ed_find_3Com(sc, cf, ia) } else ia->ia_iobase = ed_3com_iobase[ptr]; /* XXX --thorpej */ - x = bus_io_read_1(bc, ioh, asicbase + ED_3COM_PCFR); - if (x == 0 || (x & (x - 1)) != 0) + x = bus_space_read_1(iot, ioh, asicbase + ED_3COM_PCFR); + if (x == 0 || (x & (x - 1)) != 0) { + printf("%s: The 3c503 is not currently supported with memory " + "mapping disabled.\n%s: Reconfigure the card to " + "enable memory mapping.\n", + sc->sc_dev.dv_xname, sc->sc_dev.dv_xname); goto err; + } ptr = ffs(x) - 1; if (ia->ia_maddr != MADDRUNK) { if (ia->ia_maddr != ed_3com_maddr[ptr]) { @@ -957,7 +972,7 @@ ed_find_3Com(sc, cf, ia) ia->ia_maddr = ed_3com_maddr[ptr]; #if 0 - x = bus_io_read_1(bc, ioh, asicbase + ED_3COM_IDCFR) & + x = bus_space_read_1(iot, ioh, asicbase + ED_3COM_IDCFR) & ED_3COM_IDCFR_IRQ; if (x == 0 || (x & (x - 1)) != 0) goto out; @@ -978,7 +993,7 @@ ed_find_3Com(sc, cf, ia) * sequence because it'll lock up if the cable isn't connected if we * don't. */ - bus_io_write_1(bc, ioh, asicbase + ED_3COM_CR, + bus_space_write_1(iot, ioh, asicbase + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL); /* Wait for a while, then un-reset it. */ @@ -989,7 +1004,7 @@ ed_find_3Com(sc, cf, ia) * reset - it's important to set it again after the following outb * (this is done when we map the PROM below). */ - bus_io_write_1(bc, ioh, asicbase + ED_3COM_CR, ED_3COM_CR_XSEL); + bus_space_write_1(iot, ioh, asicbase + ED_3COM_CR, ED_3COM_CR_XSEL); /* Wait a bit for the NIC to recover from the reset. */ delay(5000); @@ -1005,46 +1020,46 @@ ed_find_3Com(sc, cf, ia) * First, map ethernet address PROM over the top of where the NIC * registers normally appear. */ - bus_io_write_1(bc, ioh, asicbase + ED_3COM_CR, + bus_space_write_1(iot, ioh, asicbase + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL); for (i = 0; i < ETHER_ADDR_LEN; ++i) - sc->sc_arpcom.ac_enaddr[i] = NIC_GET(bc, ioh, nicbase, i); + sc->sc_arpcom.ac_enaddr[i] = NIC_GET(iot, ioh, nicbase, i); /* * Unmap PROM - select NIC registers. The proper setting of the * tranceiver is set in edinit so that the attach code is given a * chance to set the default based on a compile-time config option. */ - bus_io_write_1(bc, ioh, asicbase + ED_3COM_CR, ED_3COM_CR_XSEL); + bus_space_write_1(iot, ioh, asicbase + ED_3COM_CR, ED_3COM_CR_XSEL); /* Determine if this is an 8bit or 16bit board. */ /* Select page 0 registers. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_CR, + NIC_PUT(iot, ioh, nicbase, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STP); /* * Attempt to clear WTS bit. If it doesn't clear, then this is a * 16-bit board. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_DCR, 0); + NIC_PUT(iot, ioh, nicbase, ED_P0_DCR, 0); /* Select page 2 registers. */ - NIC_PUT(bc, ioh, nicbase, + NIC_PUT(iot, ioh, nicbase, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_2 | ED_CR_STP); /* The 3c503 forces the WTS bit to a one if this is a 16bit board. */ - if (NIC_GET(bc, ioh, nicbase, ED_P2_DCR) & ED_DCR_WTS) + if (NIC_GET(iot, ioh, nicbase, ED_P2_DCR) & ED_DCR_WTS) isa16bit = 1; else isa16bit = 0; /* Select page 0 registers. */ - NIC_PUT(bc, ioh, nicbase, ED_P2_CR, + NIC_PUT(iot, ioh, nicbase, ED_P2_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STP); - if (bus_mem_map(bc, ia->ia_maddr, memsize, 0, &memh)) + if (bus_space_map(memt, ia->ia_maddr, memsize, 0, &memh)) goto err; sc->mem_start = 0; /* offset */ sc->mem_size = memsize; @@ -1087,25 +1102,25 @@ ed_find_3Com(sc, cf, ia) * Initialize GA page start/stop registers. Probably only needed if * doing DMA, but what the Hell. */ - bus_io_write_1(bc, ioh, asicbase + ED_3COM_PSTR, sc->rec_page_start); - bus_io_write_1(bc, ioh, asicbase + ED_3COM_PSPR, sc->rec_page_stop); + bus_space_write_1(iot, ioh, asicbase + ED_3COM_PSTR, sc->rec_page_start); + bus_space_write_1(iot, ioh, asicbase + ED_3COM_PSPR, sc->rec_page_stop); /* Set IRQ. 3c503 only allows a choice of irq 3-5 or 9. */ switch (ia->ia_irq) { case 9: - bus_io_write_1(bc, ioh, asicbase + ED_3COM_IDCFR, + bus_space_write_1(iot, ioh, asicbase + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2); break; case 3: - bus_io_write_1(bc, ioh, asicbase + ED_3COM_IDCFR, + bus_space_write_1(iot, ioh, asicbase + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3); break; case 4: - bus_io_write_1(bc, ioh, asicbase + ED_3COM_IDCFR, + bus_space_write_1(iot, ioh, asicbase + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4); break; case 5: - bus_io_write_1(bc, ioh, asicbase + ED_3COM_IDCFR, + bus_space_write_1(iot, ioh, asicbase + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5); break; default: @@ -1118,7 +1133,7 @@ ed_find_3Com(sc, cf, ia) * Initialize GA configuration register. Set bank and enable shared * mem. */ - bus_io_write_1(bc, ioh, asicbase + ED_3COM_GACFR, + bus_space_write_1(iot, ioh, asicbase + ED_3COM_GACFR, ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); /* @@ -1127,30 +1142,30 @@ ed_find_3Com(sc, cf, ia) * shared memory is disabled. We set them to 0xffff0...allegedly the * reset vector. */ - bus_io_write_1(bc, ioh, asicbase + ED_3COM_VPTR2, 0xff); - bus_io_write_1(bc, ioh, asicbase + ED_3COM_VPTR1, 0xff); - bus_io_write_1(bc, ioh, asicbase + ED_3COM_VPTR0, 0x00); + bus_space_write_1(iot, ioh, asicbase + ED_3COM_VPTR2, 0xff); + bus_space_write_1(iot, ioh, asicbase + ED_3COM_VPTR1, 0xff); + bus_space_write_1(iot, ioh, asicbase + ED_3COM_VPTR0, 0x00); /* Now zero memory and verify that it is clear. */ if (isa16bit) { for (i = 0; i < memsize; i += 2) - bus_mem_write_2(bc, memh, sc->mem_start + i, 0); + bus_space_write_2(memt, memh, sc->mem_start + i, 0); } else { for (i = 0; i < memsize; ++i) - bus_mem_write_1(bc, memh, sc->mem_start + i, 0); + bus_space_write_1(memt, memh, sc->mem_start + i, 0); } memfail = 0; if (isa16bit) { for (i = 0; i < memsize; i += 2) { - if (bus_mem_read_2(bc, memh, sc->mem_start + i)) { + if (bus_space_read_2(memt, memh, sc->mem_start + i)) { memfail = 1; break; } } } else { for (i = 0; i < memsize; ++i) { - if (bus_mem_read_1(bc, memh, sc->mem_start + i)) { + if (bus_space_read_1(memt, memh, sc->mem_start + i)) { memfail = 1; break; } @@ -1172,15 +1187,16 @@ ed_find_3Com(sc, cf, ia) * XXX Sould always unmap, but we can't yet. * XXX Need to squish "indirect" first. */ - sc->sc_bc = bc; + sc->sc_iot = iot; + sc->sc_memt = memt; sc->sc_ioh = ioh; sc->sc_memh = memh; return 1; out: - bus_mem_unmap(bc, memh, memsize); + bus_space_unmap(memt, memh, memsize); err: - bus_io_unmap(bc, ioh, ED_3COM_IO_PORTS); + bus_space_unmap(iot, ioh, ED_3COM_IO_PORTS); return 0; } @@ -1193,17 +1209,17 @@ ed_find_Novell(sc, cf, ia) struct cfdata *cf; struct isa_attach_args *ia; { - bus_chipset_tag_t bc; - bus_io_handle_t ioh; + bus_space_tag_t iot; + bus_space_handle_t ioh; u_int memsize, n; u_char romdata[16], tmp; static u_char test_pattern[32] = "THIS is A memory TEST pattern"; u_char test_buffer[32]; int asicbase, nicbase; - bc = ia->ia_bc; + iot = ia->ia_iot; - if (bus_io_map(bc, ia->ia_iobase, ED_NOVELL_IO_PORTS, &ioh)) + if (bus_space_map(iot, ia->ia_iobase, ED_NOVELL_IO_PORTS, 0, &ioh)) return (0); sc->asic_base = asicbase = ED_NOVELL_ASIC_OFFSET; @@ -1213,10 +1229,10 @@ ed_find_Novell(sc, cf, ia) /* Reset the board. */ #ifdef GWETHER - bus_io_write_1(bc, ioh, asicbase + ED_NOVELL_RESET, 0); + bus_space_write_1(iot, ioh, asicbase + ED_NOVELL_RESET, 0); delay(200); #endif /* GWETHER */ - tmp = bus_io_read_1(bc, ioh, asicbase + ED_NOVELL_RESET); + tmp = bus_space_read_1(iot, ioh, asicbase + ED_NOVELL_RESET); /* * I don't know if this is necessary; probably cruft leftover from @@ -1226,7 +1242,7 @@ ed_find_Novell(sc, cf, ia) * complete documentation on what the 'right' thing to do is...so we do * the invasive thing for now. Yuck.] */ - bus_io_write_1(bc, ioh, asicbase + ED_NOVELL_RESET, tmp); + bus_space_write_1(iot, ioh, asicbase + ED_NOVELL_RESET, tmp); delay(5000); /* @@ -1235,13 +1251,13 @@ ed_find_Novell(sc, cf, ia) * XXX - this makes the probe invasive! ...Done against my better * judgement. -DLG */ - NIC_PUT(bc, ioh, nicbase, ED_P0_CR, + NIC_PUT(iot, ioh, nicbase, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STP); delay(5000); /* Make sure that we really have an 8390 based board. */ - if (!ed_probe_generic8390(bc, ioh, nicbase)) + if (!ed_probe_generic8390(iot, ioh, nicbase)) goto out; sc->vendor = ED_VENDOR_NOVELL; @@ -1258,20 +1274,20 @@ ed_find_Novell(sc, cf, ia) * This prevents packets from being stored in the NIC memory when the * readmem routine turns on the start bit in the CR. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_RCR, ED_RCR_MON); + NIC_PUT(iot, ioh, nicbase, ED_P0_RCR, ED_RCR_MON); /* Temporarily initialize DCR for byte operations. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); + NIC_PUT(iot, ioh, nicbase, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); - NIC_PUT(bc, ioh, nicbase, ED_P0_PSTART, 8192 >> ED_PAGE_SHIFT); - NIC_PUT(bc, ioh, nicbase, ED_P0_PSTOP, 16384 >> ED_PAGE_SHIFT); + NIC_PUT(iot, ioh, nicbase, ED_P0_PSTART, 8192 >> ED_PAGE_SHIFT); + NIC_PUT(iot, ioh, nicbase, ED_P0_PSTOP, 16384 >> ED_PAGE_SHIFT); sc->isa16bit = 0; /* * XXX indirect brokenness, used by ed_pio{read,write}mem() */ - sc->sc_bc = bc; + sc->sc_iot = iot; sc->sc_ioh = ioh; /* @@ -1285,10 +1301,10 @@ ed_find_Novell(sc, cf, ia) if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) { /* not an NE1000 - try NE2000 */ - NIC_PUT(bc, ioh, nicbase, ED_P0_DCR, + NIC_PUT(iot, ioh, nicbase, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); - NIC_PUT(bc, ioh, nicbase, ED_P0_PSTART, 16384 >> ED_PAGE_SHIFT); - NIC_PUT(bc, ioh, nicbase, ED_P0_PSTOP, 32768 >> ED_PAGE_SHIFT); + NIC_PUT(iot, ioh, nicbase, ED_P0_PSTART, 16384 >> ED_PAGE_SHIFT); + NIC_PUT(iot, ioh, nicbase, ED_P0_PSTOP, 32768 >> ED_PAGE_SHIFT); sc->isa16bit = 1; @@ -1413,7 +1429,7 @@ ed_find_Novell(sc, cf, ia) #endif /* GWETHER */ /* Clear any pending interrupts that might have occurred above. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_ISR, 0xff); + NIC_PUT(iot, ioh, nicbase, ED_P0_ISR, 0xff); ia->ia_iosize = ED_NOVELL_IO_PORTS; @@ -1421,12 +1437,12 @@ ed_find_Novell(sc, cf, ia) * XXX Sould always unmap, but we can't yet. * XXX Need to squish "indirect" first. */ - sc->sc_bc = bc; + sc->sc_iot = iot; sc->sc_ioh = ioh; /* sc_memh is not used by this driver */ return 1; out: - bus_io_unmap(bc, ioh, ED_NOVELL_IO_PORTS); + bus_space_unmap(iot, ioh, ED_NOVELL_IO_PORTS); return 0; } @@ -1439,8 +1455,8 @@ edattach(parent, self, aux) struct device *parent, *self; void *aux; { - bus_chipset_tag_t bc; - bus_io_handle_t ioh; + bus_space_tag_t iot; + bus_space_handle_t ioh; struct ed_softc *sc = (void *)self; struct isa_attach_args *ia = aux; struct cfdata *cf = sc->sc_dev.dv_cfdata; @@ -1451,11 +1467,11 @@ edattach(parent, self, aux) * XXX Should re-map io and mem, but can't * XXX until we squish "indirect" brokenness. */ - bc = sc->sc_bc; /* XXX */ + iot = sc->sc_iot; /* XXX */ ioh = sc->sc_ioh; /* XXX */ asicbase = sc->asic_base; - sc->sc_delayioh = ia->ia_delayioh; + sc->sc_delaybah = ia->ia_delaybah; /* Set interface to stopped condition (reset). */ edstop(sc); @@ -1481,7 +1497,7 @@ edattach(parent, self, aux) case ED_VENDOR_WD_SMC: if ((sc->type & ED_WD_SOFTCONFIG) == 0) break; - if ((bus_io_read_1(bc, ioh, asicbase + ED_WD_IRR) & + if ((bus_space_read_1(iot, ioh, asicbase + ED_WD_IRR) & ED_WD_IRR_OUT2) == 0) ifp->if_flags |= IFF_LINK0; break; @@ -1552,13 +1568,13 @@ void edstop(sc) struct ed_softc *sc; { - bus_chipset_tag_t bc = sc->sc_bc; - bus_io_handle_t ioh = sc->sc_ioh; + bus_space_tag_t iot = sc->sc_iot; + bus_space_handle_t ioh = sc->sc_ioh; int nicbase = sc->nic_base; int n = 5000; /* Stop everything on the interface, and select page 0 registers. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_CR, + NIC_PUT(iot, ioh, nicbase, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STP); /* @@ -1566,7 +1582,7 @@ edstop(sc) * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but * just in case it's an old one. */ - while (((NIC_GET(bc, ioh, nicbase, + while (((NIC_GET(iot, ioh, nicbase, ED_P0_ISR) & ED_ISR_RST) == 0) && --n); } @@ -1593,8 +1609,8 @@ void edinit(sc) struct ed_softc *sc; { - bus_chipset_tag_t bc = sc->sc_bc; - bus_io_handle_t ioh = sc->sc_ioh; + bus_space_tag_t iot = sc->sc_iot; + bus_space_handle_t ioh = sc->sc_ioh; struct ifnet *ifp = &sc->sc_arpcom.ac_if; int nicbase = sc->nic_base, asicbase = sc->asic_base; int i; @@ -1614,7 +1630,7 @@ edinit(sc) sc->txb_next_tx = 0; /* Set interface for page 0, remote DMA complete, stopped. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_CR, + NIC_PUT(iot, ioh, nicbase, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STP); if (sc->isa16bit) { @@ -1622,37 +1638,37 @@ edinit(sc) * Set FIFO threshold to 8, No auto-init Remote DMA, byte * order=80x86, word-wide DMA xfers, */ - NIC_PUT(bc, ioh, nicbase, ED_P0_DCR, + NIC_PUT(iot, ioh, nicbase, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS); } else { /* Same as above, but byte-wide DMA xfers. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); + NIC_PUT(iot, ioh, nicbase, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); } /* Clear remote byte count registers. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR0, 0); - NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR1, 0); + NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR0, 0); + NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR1, 0); /* Tell RCR to do nothing for now. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_RCR, ED_RCR_MON); + NIC_PUT(iot, ioh, nicbase, ED_P0_RCR, ED_RCR_MON); /* Place NIC in internal loopback mode. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_TCR, ED_TCR_LB0); + NIC_PUT(iot, ioh, nicbase, ED_P0_TCR, ED_TCR_LB0); /* Set lower bits of byte addressable framing to 0. */ if (sc->is790) - NIC_PUT(bc, ioh, nicbase, 0x09, 0); + NIC_PUT(iot, ioh, nicbase, 0x09, 0); /* Initialize receive buffer ring. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_BNRY, sc->rec_page_start); - NIC_PUT(bc, ioh, nicbase, ED_P0_PSTART, sc->rec_page_start); - NIC_PUT(bc, ioh, nicbase, ED_P0_PSTOP, sc->rec_page_stop); + NIC_PUT(iot, ioh, nicbase, ED_P0_BNRY, sc->rec_page_start); + NIC_PUT(iot, ioh, nicbase, ED_P0_PSTART, sc->rec_page_start); + NIC_PUT(iot, ioh, nicbase, ED_P0_PSTOP, sc->rec_page_stop); /* * Clear all interrupts. A '1' in each bit position clears the * corresponding flag. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_ISR, 0xff); + NIC_PUT(iot, ioh, nicbase, ED_P0_ISR, 0xff); /* * Enable the following interrupts: receive/transmit complete, @@ -1660,33 +1676,33 @@ edinit(sc) * * Counter overflow and Remote DMA complete are *not* enabled. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_IMR, + NIC_PUT(iot, ioh, nicbase, ED_P0_IMR, ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE); /* Program command register for page 1. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_CR, + NIC_PUT(iot, ioh, nicbase, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); /* Copy out our station address. */ for (i = 0; i < ETHER_ADDR_LEN; ++i) - NIC_PUT(bc, ioh, nicbase, ED_P1_PAR0 + i, + NIC_PUT(iot, ioh, nicbase, ED_P1_PAR0 + i, sc->sc_arpcom.ac_enaddr[i]); /* Set multicast filter on chip. */ isaed_getmcaf(&sc->sc_arpcom, mcaf); for (i = 0; i < 8; i++) - NIC_PUT(bc, ioh, nicbase, ED_P1_MAR0 + i, ((u_char *)mcaf)[i]); + NIC_PUT(iot, ioh, nicbase, ED_P1_MAR0 + i, ((u_char *)mcaf)[i]); /* * Set current page pointer to one page after the boundary pointer, as * recommended in the National manual. */ sc->next_packet = sc->rec_page_start + 1; - NIC_PUT(bc, ioh, nicbase, ED_P1_CURR, sc->next_packet); + NIC_PUT(iot, ioh, nicbase, ED_P1_CURR, sc->next_packet); /* Program command register for page 0. */ - NIC_PUT(bc, ioh, nicbase, ED_P1_CR, + NIC_PUT(iot, ioh, nicbase, ED_P1_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STP); i = ED_RCR_AB | ED_RCR_AM; @@ -1697,10 +1713,10 @@ edinit(sc) */ i |= ED_RCR_PRO | ED_RCR_AR | ED_RCR_SEP; } - NIC_PUT(bc, ioh, nicbase, ED_P0_RCR, i); + NIC_PUT(iot, ioh, nicbase, ED_P0_RCR, i); /* Take interface out of loopback. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_TCR, 0); + NIC_PUT(iot, ioh, nicbase, ED_P0_TCR, 0); /* * If this is a 3Com board, the tranceiver must be software enabled @@ -1710,25 +1726,25 @@ edinit(sc) u_char x; case ED_VENDOR_3COM: if (ifp->if_flags & IFF_LINK0) - bus_io_write_1(bc, ioh, asicbase + ED_3COM_CR, 0); + bus_space_write_1(iot, ioh, asicbase + ED_3COM_CR, 0); else - bus_io_write_1(bc, ioh, asicbase + ED_3COM_CR, + bus_space_write_1(iot, ioh, asicbase + ED_3COM_CR, ED_3COM_CR_XSEL); break; case ED_VENDOR_WD_SMC: if ((sc->type & ED_WD_SOFTCONFIG) == 0) break; - x = bus_io_read_1(bc, ioh, asicbase + ED_WD_IRR); + x = bus_space_read_1(iot, ioh, asicbase + ED_WD_IRR); if (ifp->if_flags & IFF_LINK0) x &= ~ED_WD_IRR_OUT2; else x |= ED_WD_IRR_OUT2; - bus_io_write_1(bc, ioh, asicbase + ED_WD_IRR, x); + bus_space_write_1(iot, ioh, asicbase + ED_WD_IRR, x); break; } /* Fire up the interface. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_CR, + NIC_PUT(iot, ioh, nicbase, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA); /* Set 'running' flag, and clear output active flag. */ @@ -1746,8 +1762,8 @@ static inline void ed_xmit(sc) struct ed_softc *sc; { - bus_chipset_tag_t bc = sc->sc_bc; - bus_io_handle_t ioh = sc->sc_ioh; + bus_space_tag_t iot = sc->sc_iot; + bus_space_handle_t ioh = sc->sc_ioh; struct ifnet *ifp = &sc->sc_arpcom.ac_if; int nicbase = sc->nic_base; u_short len; @@ -1755,19 +1771,19 @@ ed_xmit(sc) len = sc->txb_len[sc->txb_next_tx]; /* Set NIC for page 0 register access. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_CR, + NIC_PUT(iot, ioh, nicbase, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA); /* Set TX buffer start page. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_TPSR, sc->tx_page_start + + NIC_PUT(iot, ioh, nicbase, ED_P0_TPSR, sc->tx_page_start + sc->txb_next_tx * ED_TXBUF_SIZE); /* Set TX length. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_TBCR0, len); - NIC_PUT(bc, ioh, nicbase, ED_P0_TBCR1, len >> 8); + NIC_PUT(iot, ioh, nicbase, ED_P0_TBCR0, len); + NIC_PUT(iot, ioh, nicbase, ED_P0_TBCR1, len >> 8); /* Set page 0, remote DMA complete, transmit packet, and *start*. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_CR, + NIC_PUT(iot, ioh, nicbase, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_TXP | ED_CR_STA); /* Point to next transmit buffer slot and wrap if necessary. */ @@ -1793,8 +1809,8 @@ edstart(ifp) struct ifnet *ifp; { struct ed_softc *sc = ifp->if_softc; - bus_chipset_tag_t bc = sc->sc_bc; - bus_io_handle_t ioh = sc->sc_ioh; + bus_space_tag_t iot = sc->sc_iot; + bus_space_handle_t ioh = sc->sc_ioh; struct mbuf *m0, *m; int buffer; int asicbase = sc->asic_base; @@ -1839,7 +1855,7 @@ outloop: */ case ED_VENDOR_3COM: if (sc->isa16bit) - bus_io_write_1(bc, ioh, + bus_space_write_1(iot, ioh, asicbase + ED_3COM_GACFR, ED_3COM_GACFR_RSEL); break; @@ -1849,12 +1865,12 @@ outloop: */ case ED_VENDOR_WD_SMC: if (sc->isa16bit) - bus_io_write_1(bc, ioh, asicbase + ED_WD_LAAR, + bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR, sc->wd_laar_proto | ED_WD_LAAR_M16EN); - bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR, + bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR, sc->wd_msr_proto | ED_WD_MSR_MENB); - (void) bus_io_read_1(bc, sc->sc_delayioh, 0); - (void) bus_io_read_1(bc, sc->sc_delayioh, 0); + (void) bus_space_read_1(iot, sc->sc_delaybah, 0); + (void) bus_space_read_1(iot, sc->sc_delaybah, 0); break; } @@ -1869,18 +1885,18 @@ outloop: switch (sc->vendor) { case ED_VENDOR_3COM: if (sc->isa16bit) - bus_io_write_1(bc, ioh, + bus_space_write_1(iot, ioh, asicbase + ED_3COM_GACFR, ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); break; case ED_VENDOR_WD_SMC: - bus_io_write_1(bc, ioh, asicbase + ED_WD_MSR, + bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR, sc->wd_msr_proto); if (sc->isa16bit) - bus_io_write_1(bc, ioh, asicbase + ED_WD_LAAR, + bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR, sc->wd_laar_proto); - (void) bus_io_read_1(bc, sc->sc_delayioh, 0); - (void) bus_io_read_1(bc, sc->sc_delayioh, 0); + (void) bus_space_read_1(iot, sc->sc_delaybah, 0); + (void) bus_space_read_1(iot, sc->sc_delaybah, 0); break; } } else @@ -1909,8 +1925,8 @@ static inline void ed_rint(sc) struct ed_softc *sc; { - bus_chipset_tag_t bc = sc->sc_bc; - bus_io_handle_t ioh = sc->sc_ioh; + bus_space_tag_t iot = sc->sc_iot; + bus_space_handle_t ioh = sc->sc_ioh; int nicbase = sc->nic_base; u_int8_t boundary, current; u_int16_t len; @@ -1923,7 +1939,7 @@ ed_rint(sc) loop: /* Set NIC to page 1 registers to get 'current' pointer. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_CR, + NIC_PUT(iot, ioh, nicbase, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); /* @@ -1934,12 +1950,12 @@ loop: * until the logical beginning equals the logical end (or in other * words, until the ring-buffer is empty). */ - current = NIC_GET(bc, ioh, nicbase, ED_P1_CURR); + current = NIC_GET(iot, ioh, nicbase, ED_P1_CURR); if (sc->next_packet == current) return; /* Set NIC to page 0 registers to update boundary register. */ - NIC_PUT(bc, ioh, nicbase, ED_P1_CR, + NIC_PUT(iot, ioh, nicbase, ED_P1_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA); do { @@ -2024,7 +2040,7 @@ loop: boundary = sc->next_packet - 1; if (boundary < sc->rec_page_start) boundary = sc->rec_page_stop - 1; - NIC_PUT(bc, ioh, nicbase, ED_P0_BNRY, boundary); + NIC_PUT(iot, ioh, nicbase, ED_P0_BNRY, boundary); } while (sc->next_packet != current); goto loop; @@ -2036,17 +2052,17 @@ isaedintr(arg) void *arg; { struct ed_softc *sc = arg; - bus_chipset_tag_t bc = sc->sc_bc; - bus_io_handle_t ioh = sc->sc_ioh; + bus_space_tag_t iot = sc->sc_iot; + bus_space_handle_t ioh = sc->sc_ioh; struct ifnet *ifp = &sc->sc_arpcom.ac_if; int nicbase = sc->nic_base, asicbase = sc->asic_base; u_char isr; /* Set NIC to page 0 registers. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_CR, + NIC_PUT(iot, ioh, nicbase, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA); - isr = NIC_GET(bc, ioh, nicbase, ED_P0_ISR); + isr = NIC_GET(iot, ioh, nicbase, ED_P0_ISR); if (!isr) return (0); @@ -2057,14 +2073,14 @@ isaedintr(arg) * '1' to each bit position that was set. * (Writing a '1' *clears* the bit.) */ - NIC_PUT(bc, ioh, nicbase, ED_P0_ISR, isr); + NIC_PUT(iot, ioh, nicbase, ED_P0_ISR, isr); /* * Handle transmitter interrupts. Handle these first because * the receiver will reset the board under some conditions. */ if (isr & (ED_ISR_PTX | ED_ISR_TXE)) { - u_char collisions = NIC_GET(bc, ioh, nicbase, + u_char collisions = NIC_GET(iot, ioh, nicbase, ED_P0_NCR) & 0x0f; /* @@ -2076,12 +2092,12 @@ isaedintr(arg) * course, with UDP we're screwed, but this is expected * when a network is heavily loaded. */ - (void) NIC_GET(bc, ioh, nicbase, ED_P0_TSR); + (void) NIC_GET(iot, ioh, nicbase, ED_P0_TSR); if (isr & ED_ISR_TXE) { /* * Excessive collisions (16). */ - if ((NIC_GET(bc, ioh, nicbase, ED_P0_TSR) & + if ((NIC_GET(iot, ioh, nicbase, ED_P0_TSR) & ED_TSR_ABT) && (collisions == 0)) { /* * When collisions total 16, the P0_NCR @@ -2174,34 +2190,34 @@ isaedintr(arg) */ if (sc->vendor == ED_VENDOR_WD_SMC) { if (sc->isa16bit) - bus_io_write_1(bc, ioh, + bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR, sc->wd_laar_proto | ED_WD_LAAR_M16EN); - bus_io_write_1(bc, ioh, + bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR, sc->wd_msr_proto | ED_WD_MSR_MENB); - (void) bus_io_read_1(bc, - sc->sc_delayioh, 0); - (void) bus_io_read_1(bc, - sc->sc_delayioh, 0); + (void) bus_space_read_1(iot, + sc->sc_delaybah, 0); + (void) bus_space_read_1(iot, + sc->sc_delaybah, 0); } ed_rint(sc); /* Disable 16-bit access. */ if (sc->vendor == ED_VENDOR_WD_SMC) { - bus_io_write_1(bc, ioh, + bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR, sc->wd_msr_proto); if (sc->isa16bit) - bus_io_write_1(bc, ioh, + bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR, sc->wd_laar_proto); - (void) bus_io_read_1(bc, - sc->sc_delayioh, 0); - (void) bus_io_read_1(bc, - sc->sc_delayioh, 0); + (void) bus_space_read_1(iot, + sc->sc_delaybah, 0); + (void) bus_space_read_1(iot, + sc->sc_delaybah, 0); } } } @@ -2219,7 +2235,7 @@ isaedintr(arg) * set in the transmit routine, is *okay* - it is 'edge' * triggered from low to high). */ - NIC_PUT(bc, ioh, nicbase, ED_P0_CR, + NIC_PUT(iot, ioh, nicbase, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA); /* @@ -2228,12 +2244,12 @@ isaedintr(arg) * otherwise - resulting in an infinite loop. */ if (isr & ED_ISR_CNT) { - (void) NIC_GET(bc, ioh, nicbase, ED_P0_CNTR0); - (void) NIC_GET(bc, ioh, nicbase, ED_P0_CNTR1); - (void) NIC_GET(bc, ioh, nicbase, ED_P0_CNTR2); + (void) NIC_GET(iot, ioh, nicbase, ED_P0_CNTR0); + (void) NIC_GET(iot, ioh, nicbase, ED_P0_CNTR1); + (void) NIC_GET(iot, ioh, nicbase, ED_P0_CNTR2); } - isr = NIC_GET(bc, ioh, nicbase, ED_P0_ISR); + isr = NIC_GET(iot, ioh, nicbase, ED_P0_ISR); if (!isr) return (1); } @@ -2407,12 +2423,12 @@ ed_pio_readmem(sc, src, dst, amount) caddr_t dst; u_short amount; { - bus_chipset_tag_t bc = sc->sc_bc; - bus_io_handle_t ioh = sc->sc_ioh; + bus_space_tag_t iot = sc->sc_iot; + bus_space_handle_t ioh = sc->sc_ioh; int nicbase = sc->nic_base; /* Select page 0 registers. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_CR, + NIC_PUT(iot, ioh, nicbase, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STA); /* Round up to a word. */ @@ -2420,22 +2436,22 @@ ed_pio_readmem(sc, src, dst, amount) ++amount; /* Set up DMA byte count. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR0, amount); - NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR1, amount >> 8); + NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR0, amount); + NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR1, amount >> 8); /* Set up source address in NIC mem. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_RSAR0, src); - NIC_PUT(bc, ioh, nicbase, ED_P0_RSAR1, src >> 8); + NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR0, src); + NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR1, src >> 8); - NIC_PUT(bc, ioh, nicbase, ED_P0_CR, + NIC_PUT(iot, ioh, nicbase, ED_P0_CR, ED_CR_RD0 | ED_CR_PAGE_0 | ED_CR_STA); if (sc->isa16bit) - bus_io_read_raw_multi_2(bc, ioh, + bus_space_read_raw_multi_2(iot, ioh, sc->asic_base + ED_NOVELL_DATA, dst, amount); else - bus_io_read_multi_1(bc, ioh, sc->asic_base + ED_NOVELL_DATA, - dst, amount); + bus_space_read_multi_1(iot, ioh, + sc->asic_base + ED_NOVELL_DATA, dst, amount); } /* @@ -2449,36 +2465,36 @@ ed_pio_writemem(sc, src, dst, len) u_short dst; u_short len; { - bus_chipset_tag_t bc = sc->sc_bc; - bus_io_handle_t ioh = sc->sc_ioh; + bus_space_tag_t iot = sc->sc_iot; + bus_space_handle_t ioh = sc->sc_ioh; int nicbase = sc->nic_base; int maxwait = 100; /* about 120us */ /* Select page 0 registers. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_CR, + NIC_PUT(iot, ioh, nicbase, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STA); /* Reset remote DMA complete flag. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_ISR, ED_ISR_RDC); + NIC_PUT(iot, ioh, nicbase, ED_P0_ISR, ED_ISR_RDC); /* Set up DMA byte count. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR0, len); - NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR1, len >> 8); + NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR0, len); + NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR1, len >> 8); /* Set up destination address in NIC mem. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_RSAR0, dst); - NIC_PUT(bc, ioh, nicbase, ED_P0_RSAR1, dst >> 8); + NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR0, dst); + NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR1, dst >> 8); /* Set remote DMA write. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_CR, + NIC_PUT(iot, ioh, nicbase, ED_P0_CR, ED_CR_RD1 | ED_CR_PAGE_0 | ED_CR_STA); if (sc->isa16bit) - bus_io_write_raw_multi_2(bc, ioh, + bus_space_write_raw_multi_2(iot, ioh, sc->asic_base + ED_NOVELL_DATA, src, len); else - bus_io_write_multi_1(bc, ioh, sc->asic_base + ED_NOVELL_DATA, - src, len); + bus_space_write_multi_1(iot, ioh, + sc->asic_base + ED_NOVELL_DATA, src, len); /* * Wait for remote DMA complete. This is necessary because on the @@ -2487,7 +2503,7 @@ ed_pio_writemem(sc, src, dst, len) * waiting causes really bad things to happen - like the NIC * irrecoverably jamming the ISA bus. */ - while (((NIC_GET(bc, ioh, nicbase, ED_P0_ISR) & ED_ISR_RDC) != + while (((NIC_GET(iot, ioh, nicbase, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); } @@ -2501,8 +2517,8 @@ ed_pio_write_mbufs(sc, m, dst) struct mbuf *m; u_short dst; { - bus_chipset_tag_t bc = sc->sc_bc; - bus_io_handle_t ioh = sc->sc_ioh; + bus_space_tag_t iot = sc->sc_iot; + bus_space_handle_t ioh = sc->sc_ioh; int nicbase = sc->nic_base, asicbase = sc->asic_base; u_short len; int maxwait = 100; /* about 120us */ @@ -2510,22 +2526,22 @@ ed_pio_write_mbufs(sc, m, dst) len = m->m_pkthdr.len; /* Select page 0 registers. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_CR, + NIC_PUT(iot, ioh, nicbase, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STA); /* Reset remote DMA complete flag. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_ISR, ED_ISR_RDC); + NIC_PUT(iot, ioh, nicbase, ED_P0_ISR, ED_ISR_RDC); /* Set up DMA byte count. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR0, len); - NIC_PUT(bc, ioh, nicbase, ED_P0_RBCR1, len >> 8); + NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR0, len); + NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR1, len >> 8); /* Set up destination address in NIC mem. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_RSAR0, dst); - NIC_PUT(bc, ioh, nicbase, ED_P0_RSAR1, dst >> 8); + NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR0, dst); + NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR1, dst >> 8); /* Set remote DMA write. */ - NIC_PUT(bc, ioh, nicbase, ED_P0_CR, + NIC_PUT(iot, ioh, nicbase, ED_P0_CR, ED_CR_RD1 | ED_CR_PAGE_0 | ED_CR_STA); /* @@ -2538,7 +2554,7 @@ ed_pio_write_mbufs(sc, m, dst) /* NE1000s are easy. */ for (; m != 0; m = m->m_next) { if (m->m_len) { - bus_io_write_multi_1(bc, ioh, + bus_space_write_multi_1(iot, ioh, asicbase + ED_NOVELL_DATA, mtod(m, u_char *), m->m_len); } @@ -2557,7 +2573,7 @@ ed_pio_write_mbufs(sc, m, dst) /* Finish the last word. */ if (wantbyte) { savebyte[1] = *data; - bus_io_write_raw_multi_2(bc, ioh, + bus_space_write_raw_multi_2(iot, ioh, asicbase + ED_NOVELL_DATA, savebyte, 2); data++; len--; @@ -2565,7 +2581,7 @@ ed_pio_write_mbufs(sc, m, dst) } /* Output contiguous words. */ if (len > 1) { - bus_io_write_raw_multi_2(bc, ioh, + bus_space_write_raw_multi_2(iot, ioh, asicbase + ED_NOVELL_DATA, data, len & ~1); } /* Save last byte, if necessary. */ @@ -2578,7 +2594,7 @@ ed_pio_write_mbufs(sc, m, dst) if (wantbyte) { savebyte[1] = 0; - bus_io_write_raw_multi_2(bc, ioh, + bus_space_write_raw_multi_2(iot, ioh, asicbase + ED_NOVELL_DATA, savebyte, 2); } } @@ -2590,7 +2606,7 @@ ed_pio_write_mbufs(sc, m, dst) * waiting causes really bad things to happen - like the NIC * irrecoverably jamming the ISA bus. */ - while (((NIC_GET(bc, ioh, nicbase, ED_P0_ISR) & ED_ISR_RDC) != + while (((NIC_GET(iot, ioh, nicbase, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); if (!maxwait) { @@ -2770,8 +2786,8 @@ ed_shared_writemem(sc, from, card, len) caddr_t from; int card, len; { - bus_chipset_tag_t bc = sc->sc_bc; - bus_mem_handle_t memh = sc->sc_memh; + bus_space_tag_t memt = sc->sc_memt; + bus_space_handle_t memh = sc->sc_memh; u_int16_t word; /* @@ -2783,18 +2799,18 @@ ed_shared_writemem(sc, from, card, len) if (sc->isa16bit) { while (len > 1) { word = (u_int8_t)from[0] | (u_int8_t)from[1] << 8; - bus_mem_write_2(bc, memh, card, word); + bus_space_write_2(memt, memh, card, word); from += 2; card += 2; len -= 2; } if (len == 1) { word = *from; - bus_mem_write_2(bc, memh, card, word); + bus_space_write_2(memt, memh, card, word); } } else { while (len--) - bus_mem_write_1(bc, memh, card++, *from++); + bus_space_write_1(memt, memh, card++, *from++); } } @@ -2804,25 +2820,26 @@ ed_shared_readmem(sc, card, to, len) caddr_t to; int card, len; { - bus_chipset_tag_t bc = sc->sc_bc; - bus_mem_handle_t memh = sc->sc_memh; + bus_space_tag_t memt = sc->sc_memt; + bus_space_handle_t memh = sc->sc_memh; u_int16_t word; /* * See comment above re. 16-bit cards. */ if (sc->isa16bit) { + /* XXX I think maybe a bus_space_read_raw_region is needed. */ while (len > 1) { - word = bus_mem_read_2(bc, memh, card); + word = bus_space_read_2(memt, memh, card); *to++ = word & 0xff; *to++ = word >> 8 & 0xff; card += 2; len -= 2; } if (len == 1) - *to = bus_mem_read_2(bc, memh, card) & 0xff; + *to = bus_space_read_2(memt, memh, card) & 0xff; } else { while (len--) - *to++ = bus_mem_read_1(bc, memh, card++); + *to++ = bus_space_read_1(memt, memh, card++); } } |