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-rw-r--r--sys/dev/pci/drm/amd/amdgpu/soc15.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/sys/dev/pci/drm/amd/amdgpu/soc15.c b/sys/dev/pci/drm/amd/amdgpu/soc15.c
index 48eee60a01c..f1b8c925d2a 100644
--- a/sys/dev/pci/drm/amd/amdgpu/soc15.c
+++ b/sys/dev/pci/drm/amd/amdgpu/soc15.c
@@ -1160,6 +1160,11 @@ static int soc15_common_early_init(void *handle)
AMD_PG_SUPPORT_VCN_DPG |
AMD_PG_SUPPORT_JPEG;
adev->external_rev_id = adev->rev_id + 0x46;
+ /* GC 9.4.3 uses MMIO register region hole at a different offset */
+ if (!amdgpu_sriov_vf(adev)) {
+ adev->rmmio_remap.reg_offset = 0x1A000;
+ adev->rmmio_remap.bus_addr = adev->rmmio_base + 0x1A000;
+ }
break;
default:
/* FIXME: not supported yet */