diff options
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/dev/ic/ad1843reg.h | 115 | ||||
| -rw-r--r-- | sys/dev/ic/dp8573areg.h | 121 | ||||
| -rw-r--r-- | sys/dev/ic/ds1286reg.h | 182 | ||||
| -rw-r--r-- | sys/dev/ic/ds1687reg.h | 64 | ||||
| -rw-r--r-- | sys/dev/ic/seeq8003reg.h | 134 |
5 files changed, 0 insertions, 616 deletions
diff --git a/sys/dev/ic/ad1843reg.h b/sys/dev/ic/ad1843reg.h deleted file mode 100644 index fd1172839b9..00000000000 --- a/sys/dev/ic/ad1843reg.h +++ /dev/null @@ -1,115 +0,0 @@ -/* $OpenBSD: ad1843reg.h,v 1.2 2009/11/18 21:13:17 jakemsr Exp $ */ - -/* - * Copyright (c) 2005 Mark Kettenis - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/* - * AD1843 Codec register defenitions. - */ - -#define AD1843_CODEC_STATUS 0 -#define AD1843_INIT 0x8000 -#define AD1843_PDNO 0x4000 -#define AD1843_REVISION_MASK 0x000f - -#define AD1843_ADC_SOURCE_GAIN 2 -#define AD1843_LSS_MASK 0xe000 -#define AD1843_LSS_SHIFT 13 -#define AD1843_RSS_MASK 0x00e0 -#define AD1843_RSS_SHIFT 5 -#define AD1843_LMGE 0x1000 -#define AD1843_RMGE 0x0010 -#define AD1843_LIG_MASK 0x0f00 -#define AD1843_LIG_SHIFT 8 -#define AD1843_RIG_MASK 0x000f -#define AD1843_RIG_SHIFT 0 - -#define AD1843_DAC2_TO_MIXER 3 -#define AD1843_LD2MM 0x8000 -#define AD1843_RD2MM 0x0080 -#define AD1843_LD2M_MASK 0x1f00 -#define AD1843_LD2M_SHIFT 8 -#define AD1843_RD2M_MASK 0x001f -#define AD1843_RD2M_SHIFT 0 - -#define AD1843_MISC_SETTINGS 8 -#define AD1843_MNMM 0x8000 -#define AD1843_MNM_MASK 0x1f00 -#define AD1843_MNM_SHIFT 8 -#define AD1843_ALLMM 0x0080 -#define AD1843_MNOM 0x0040 -#define AD1843_HPOM 0x0020 -#define AD1843_HPOS 0x0010 -#define AD1843_SUMM 0x0008 -#define AD1843_DAC2T 0x0002 -#define AD1843_DAC1T 0x0001 - -#define AD1843_DAC1_ANALOG_GAIN 9 -#define AD1843_LDA1GM 0x8000 -#define AD1843_RDA1GM 0x0080 -#define AD1843_LDA1G_MASK 0x3f00 -#define AD1843_LDA1G_SHIFT 8 -#define AD1843_RDA1G_MASK 0x003f -#define AD1843_RDA1G_SHIFT 0 - -#define AD1843_DAC1_DIGITAL_GAIN 11 -#define AD1843_LDA1AM 0x8000 -#define AD1843_RDA1AM 0x0080 - -#define AD1843_CHANNEL_SAMPLE_RATE 15 -#define AD1843_DA1C_SHIFT 8 -#define AD1843_ADRC_SHIFT 2 -#define AD1843_ADLC_SHIFT 0 - -#define AD1843_CLOCK1_SAMPLE_RATE 17 -#define AD1843_CLOCK2_SAMPLE_RATE 20 -#define AD1843_CLOCK3_SAMPLE_RATE 13 - -#define AD1843_SERIAL_INTERFACE 26 -#define AD1843_DA2F_MASK 0x0c00 -#define AD1843_DA2F_SHIFT 10 -#define AD1843_DA1F_MASK 0x0300 -#define AD1843_DA1F_SHIFT 8 -#define AD1843_ADTLK 0x0010 -#define AD1843_ADRF_MASK 0x000c -#define AD1843_ADRF_SHIFT 2 -#define AD1843_ADLF_MASK 0x0003 -#define AD1843_ADLF_SHIFT 0 -#define AD1843_PCM8 0 -#define AD1843_PCM16 1 -#define AD1843_ULAW 2 -#define AD1843_ALAW 3 -#define AD1843_SCF 0x0080 - -#define AD1843_CHANNEL_POWER_DOWN 27 -#define AD1843_DFREE 0x8000 -#define AD1843_DDMEN 0x1000 -#define AD1843_DA2EN 0x0200 -#define AD1843_DA1EN 0x0100 -#define AD1843_ANAEN 0x0080 -#define AD1843_HPEN 0x0040 -#define AD1843_AAMEN 0x0010 -#define AD1843_ADREN 0x0002 -#define AD1843_ADLEN 0x0001 - -#define AD1843_FUNDAMENTAL_SETTINGS 28 -#define AD1843_PDNI 0x8000 -#define AD1843_ACEN 0x4000 -#define AD1843_C3EN 0x2000 -#define AD1843_C2EN 0x1000 -#define AD1843_C1EN 0x0800 - -#define AD1843_NREGS 32 diff --git a/sys/dev/ic/dp8573areg.h b/sys/dev/ic/dp8573areg.h deleted file mode 100644 index 1f3ef20971d..00000000000 --- a/sys/dev/ic/dp8573areg.h +++ /dev/null @@ -1,121 +0,0 @@ -/* $OpenBSD: dp8573areg.h,v 1.2 2014/10/11 18:40:21 miod Exp $ */ -/* $NetBSD: dp8573areg.h,v 1.1 2009/02/12 06:33:57 rumble Exp $ */ - -/* - * Copyright (c) 2003 Steve Rumble - * Copyright (c) 2001 Erik Reid - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * National Semiconductor DP8573A Real Time Clock - */ - -/* Control and Status Register Offsets and Masks */ -#define DP8573A_STATUS 0x00 /* Main Status */ -#define DP8573A_STATUS_INTSTAT 0x01 /* Interrupt Status */ -#define DP8573A_STATUS_PWRFAIL 0x02 /* Power Fail Interrupt */ -#define DP8573A_STATUS_PERINT 0x04 /* Period Interrupt */ -#define DP8573A_STATUS_ALMINT 0x08 /* Alarm Interrupt */ -#define DP8573A_STATUS_REGSEL 0x40 /* Register Select */ - -/* Register Select = 0 */ -#define DP8573A_PFLAG 0x03 /* Periodic Flag */ -#define DP8573A_PFLAG_MIN 0x01 /* Minutes */ -#define DP8573A_PFLAG_10SEC 0x02 /* Ten Second */ -#define DP8573A_PFLAG_SEC 0x04 /* Seconds */ -#define DP8573A_PFLAG_100MIL 0x08 /* 100 Millisecond */ -#define DP8573A_PFLAG_10MIL 0x10 /* 10 Millisecond */ -#define DP8573A_PFLAG_MIL 0x20 /* Milliseconds */ -#define DP8573A_PFLAG_OFSS 0x40 /* Oscillator Fail/Single Supply */ -#define DP8573A_PFLAG_TESTMODE 0x80 /* Test Mode Enable */ - -#define DP8573A_TIMESAVE_CTL 0x04 /* Time Save Control */ -#define DP8573A_TIMESAVE_CTL_EN 0x80 /* Time Save Enable */ - -/* Register Select = 1 */ -#define DP8573A_RT_MODE 0x01 /* Real Time Mode */ -#define DP8573A_RT_MODE_LYLSB 0x01 /* Leap Year LSB */ -#define DP8573A_RT_MODE_LYMSB 0x02 /* Leap Year MSB */ -#define DP8573A_RT_MODE_1224 0x04 /* 12(low)/24(high) Hour Mode */ -#define DP8573A_RT_MODE_CLKSS 0x08 /* Clock Start(high)/Stop(low) */ -#define DP8573A_RT_MODE_INTPFOP 0x10 /* Interrupt PF Operation */ - -#define DP8573A_OUT_MODE 0x02 /* Output Mode */ -#define DP8573A_OUT_MODE_MFOPO 0x80 /* MFO Pin as Oscillator */ - -#define DP8573A_INT0_CTL 0x03 /* Interrupt Control 0 */ -#define DP8573A_INT0_CTL_MIN 0x01 /* Minutes Enable */ -#define DP8573A_INT0_CTL_10SEC 0x02 /* 10 Second Enable */ -#define DP8573A_INT0_CTL_SEC 0x04 /* Seconds Enable */ -#define DP8573A_INT0_CTL_100MIL 0x08 /* 100 Millisecond Enable */ -#define DP8573A_INT0_CTL_10MIL 0x10 /* 10 Millisecond Enable */ -#define DP8573A_INT0_CTL_MIL 0x20 /* Millisecond Enable */ - -#define DP8573A_INT1_CTL 0x04 /* Interrupt Control 1 */ -#define DP8573A_INT1_CTL_SECC 0x01 /* Second Compare Enable */ -#define DP8573A_INT1_CTL_MINC 0x02 /* Minute Compare Enable */ -#define DP8573A_INT1_CTL_HOURC 0x04 /* Hour Compare Enable */ -#define DP8573A_INT1_CTL_DOMC 0x08 /* Day of Month Compare Enable */ -#define DP8573A_INT1_CTL_MONTHC 0x10 /* Month Compare Enable */ -#define DP8573A_INT1_CTL_DOWC 0x20 /* Day of Week Compare Enable */ -#define DP8573A_INT1_CTL_ALMINT 0x40 /* Alarm Interrupt Enable */ -#define DP8573A_INT1_CTL_PWRINT 0x80 /* Power Fail Interrupt Enable */ - -/* Clock Counter Offsets */ -#define DP8573A_COUNTERS 0x05 /* Start of Clock Counters */ -#define DP8573A_SUBSECOND 0x05 /* 1/100 Second */ -#define DP8573A_SECOND 0x06 /* Seconds */ -#define DP8573A_MINUTE 0x07 /* Minutes */ -#define DP8573A_HOUR 0x08 /* Hours */ -#define DP8573A_DOM 0x09 /* Day of Month */ -#define DP8573A_MONTH 0x0a /* Months */ -#define DP8573A_YEAR 0x0b /* Years */ -#define DP8573A_DOW 0x0e /* Day of Week */ - -/* Comparison Registers */ -#define DP8573A_CMP_SEC 0x13 /* Seconds */ -#define DP8573A_CMP_MIN 0x14 /* Minutes */ -#define DP8573A_CMP_HOUR 0x15 /* Hours */ -#define DP8573A_CMP_DOM 0x16 /* Day of Month */ -#define DP8573A_CMP_MONTH 0x17 /* Months */ -#define DP8573A_CMP_DOW 0x18 /* Day of Week */ - -/* Time Save Registers */ -#define DP8573A_SAVE_SEC 0x19 /* Seconds */ -#define DP8573A_SAVE_MIN 0x1a /* Minutes */ -#define DP8573A_SAVE_HOUR 0x1b /* Hours */ -#define DP8573A_SAVE_DOM 0x1c /* Day of Month */ -#define DP8573A_SAVE_MONTH 0x1d /* Months */ - -/* RAM Registers */ -#define DP8573A_RAM_0C 0x0c /* RAM */ -#define DP8573A_RAM_1E 0x1e /* RAM */ -#define DP8573A_RAM_1F 0x1f /* RAM */ - -/* 12/24 Hour Masks */ -#define DP8573A_HOUR_12HR_MASK 0x1f -#define DP8573A_HOUR_24HR_MASK 0x3f - -#define DP8573A_NREG 0x20 diff --git a/sys/dev/ic/ds1286reg.h b/sys/dev/ic/ds1286reg.h deleted file mode 100644 index 2b625fc181f..00000000000 --- a/sys/dev/ic/ds1286reg.h +++ /dev/null @@ -1,182 +0,0 @@ -/* $OpenBSD: ds1286reg.h,v 1.1 2012/03/28 20:44:23 miod Exp $ */ -/* $NetBSD: ds1286reg.h,v 1.8 2005/12/11 12:21:26 christos Exp $ */ - -/* - * Copyright (c) 2001 Rafal K. Boni - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Originally based on mc146818reg.h, with the following license: - * - * Copyright (c) 1995 Carnegie-Mellon University. - * All rights reserved. - * - * Permission to use, copy, modify and distribute this software and - * its documentation is hereby granted, provided that both the copyright - * notice and this permission notice appear in all copies of the - * software, derivative works or modified versions, and any portions - * thereof, and that both notices appear in supporting documentation. - * - * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" - * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND - * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * - * Carnegie Mellon requests users of this software to return to - * - * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU - * School of Computer Science - * Carnegie Mellon University - * Pittsburgh PA 15213-3890 - * - * any improvements or extensions that they make and grant Carnegie the - * rights to redistribute these changes. - */ - -/* - * Definitions for the Dallas Semiconductor DS1286/DS1386 Real Time Clock. - * - * Plucked right from the Dallas Semicomductor specs available at - * http://pdfserv.maxim-ic.com/arpdf/DS1286.pdf and - * http://pdfserv.maxim-ic.com/arpdf/DS1386-DS1386P.pdf - * - * The DS1286 and 1386 have 14 clock-related registers and some amount - * of user registers (50 for the 1286, 8K or 32K for the 1386). The - * first eleven registers contain time-of-day and alarm data, the rest - * contain various control bits and the watchdog timer functionality. - * - * Since the locations of these ports and the method used to access - * them can be machine-dependent, the low-level details of reading - * and writing the RTC's registers are handled by machine-specific - * functions. - * - * The DS1286/DS1386 chips always store time-of-day and alarm data in - * BCD. The "hour" time-of-year and alarm fields can either be stored - * in AM/PM format, or in 24-hour format. If AM/PM format is chosen, - * the hour fields can have the values: 1-12 (for AM) and 21-32 (for - * PM). If the 24-hour format is chosen, they can have the values 0 - * to 23. The hour format is selectable separately for the time and - * alarm fields, and is controller by bit 6 of the respective register. - */ - -/* - * The registers, and the bits within each register. - */ - -#define DS1286_SUBSEC 0x0 /* Time of year: hundredths of seconds (0-99) */ -#define DS1286_SEC 0x1 /* Time of year: seconds (0-59) */ -#define DS1286_MIN 0x2 /* Time of year: minutes (0-59) */ -#define DS1286_AMIN 0x3 /* Alarm: minutes */ -#define DS1286_HOUR 0x4 /* Time of year: hour (see above) */ - -#define DS1286_HOUR_12MODE 0x40 /* Hour mode: 12-hour (on), 24 (off) */ -#define DS1286_HOUR_12HR_PM 0x20 /* AM/PM in 12-hour mode: on = PM */ -#define DS1286_HOUR_12HR_MASK 0x1f /* Mask for hours in 12hour mode */ -#define DS1286_HOUR_24HR_MASK 0x3f /* Mask for hours in 24hour mode */ - -#define DS1286_AHOUR 0x5 /* Alarm: hour */ -#define DS1286_DOW 0x6 /* Time of year: day of week (1-7) */ -#define DS1286_ADOW 0x7 /* Alarm: day of week (1-7) */ -#define DS1286_DOM 0x8 /* Time of year: day of month (1-31) */ -#define DS1286_MONTH 0x9 /* Time of year: month (1-12), wave generator */ - -#define DS1286_MONTH_MASK 0x3f /* Mask to extract month */ -#define DS1286_WAVEGEN_MASK 0xc0 /* Mask to extract wave bits */ - -#define DS1286_YEAR 0xA /* Time of year: year in century (0-99) */ - -#define DS1286_CONTROL 0xB /* Control register A */ - -#define DS1286_TE 0x80 /* Update in progress (on == disable update) */ -#define DS1286_INTSWAP 0x40 /* Swap INTA, INTB outputs */ -#define DS1286_INTBSRC 0x20 /* INTB source (on) or sink (off) current */ -#define DS1286_INTAPLS 0x10 /* INTA pulse (on) or level (off) mode */ -#define DS1286_WAM 0x08 /* Watchdog alarm mask */ -#define DS1286_TDM 0x04 /* Time-of-day alarm mask */ -#define DS1286_WAF 0x02 /* Watchdog alarm flag */ -#define DS1286_TDF 0x01 /* Time-of-day alarm flag */ - -#define DS1286_NREGS 0xd /* 14 registers; CMOS follows */ -#define DS1286_NTODREGS 0xb /* 11 of those regs are for TOD and alarm */ - -#define DS1286_NVRAM_START 0xe /* start of NVRAM: offset 14 */ - -/* NVRAM size depends on the chip -- the 1286 only has 50 bytes, whereas - * the 1386 can have 8K or 32K - */ -#define DS1286_NVRAM_SIZE 50 /* 50 bytes of NVRAM */ - -/* - * RTC register/NVRAM read and write functions -- machine-dependent. - * Appropriately manipulate RTC registers to get/put data values. - */ -u_int ds1286_read(void *, u_int); -void ds1286_write(void *, u_int, u_int); - -/* - * A collection of TOD/Alarm registers. - */ -typedef u_int ds1286_todregs[DS1286_NTODREGS]; - -/* - * Get all of the TOD/Alarm registers - * Must be called at splhigh(), and with the RTC properly set up. - */ -#define DS1286_GETTOD(sc, regs) \ - do { \ - int i; \ - u_int ctl; \ - \ - /* turn off update for now */ \ - ctl = ds1286_read(sc, DS1286_CONTROL); \ - ds1286_write(sc, DS1286_CONTROL, ctl | DS1286_TE); \ - \ - /* read all of the tod/alarm regs */ \ - for (i = 0; i < DS1286_NTODREGS; i++) \ - (*regs)[i] = ds1286_read(sc, i); \ - \ - /* turn update back on */ \ - ds1286_write(sc, DS1286_CONTROL, ctl); \ - } while (0); - -/* - * Set all of the TOD/Alarm registers - * Must be called at splhigh(), and with the RTC properly set up. - */ -#define DS1286_PUTTOD(sc, regs) \ - do { \ - int i; \ - u_int ctl; \ - \ - /* turn off update for now */ \ - ctl = ds1286_read(sc, DS1286_CONTROL); \ - ds1286_write(sc, DS1286_CONTROL, ctl | DS1286_TE); \ - \ - /* write all of the tod/alarm regs */ \ - for (i = 0; i < DS1286_NTODREGS; i++) \ - ds1286_write(sc, i, (*regs)[i]); \ - \ - /* turn update back on */ \ - ds1286_write(sc, DS1286_CONTROL, ctl); \ - } while (0); diff --git a/sys/dev/ic/ds1687reg.h b/sys/dev/ic/ds1687reg.h deleted file mode 100644 index ae1debb9d59..00000000000 --- a/sys/dev/ic/ds1687reg.h +++ /dev/null @@ -1,64 +0,0 @@ -/* $OpenBSD: ds1687reg.h,v 1.2 2008/03/31 07:14:00 jsing Exp $ */ - -/* - * Copyright (c) 2007, Joel Sing <jsing@openbsd.org> - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/* - * Register locations/definitions for the Dallas Semiconductor (now Maxim) - * DS1685 RTC chip and DS1687 stand-alone RTC EDIP. Product details are - * available at: - * - * http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2757 - * - * Full data sheet is available from: - * - * http://datasheets.maxim-ic.com/en/ds/DS1685-DS1687.pdf - * - * The DS1687 contains a DS1685, which is an improved version of the older - * DS1287 RTC. New/extended registers are available by selecting bank 1. - * Register values are either in BCD (data mode 0) or binary (data mode 1). - */ - -/* - * DS1687 Registers. - */ -#define DS1687_SEC 0x00 /* Seconds. */ -#define DS1687_SEC_ALRM 0x01 /* Alarm seconds. */ -#define DS1687_MIN 0x02 /* Minutes. */ -#define DS1687_MIN_ALRM 0x03 /* Alarm minutes. */ -#define DS1687_HOUR 0x04 /* Hours. */ -#define DS1687_HOUR_ALRM 0x05 /* Alarm hours. */ -#define DS1687_DOW 0x06 /* Day of week (01-07). */ -#define DS1687_DAY 0x07 /* Day (01-31). */ -#define DS1687_MONTH 0x08 /* Month (01-12). */ -#define DS1687_YEAR 0x09 /* Year (00-99). */ - -#define DS1687_CTRL_A 0x0a /* Control register A. */ -#define DS1687_BANK_1 0x10 /* Bank select. */ -#define DS1687_UIP 0x80 /* Update in progress. */ -#define DS1687_CTRL_B 0x0b /* Control register B. */ -#define DS1687_24_HR 0x02 /* Use 24 hour time. */ -#define DS1687_DM_1 0x04 /* Data mode 1 (binary). */ -#define DS1687_SET_CLOCK 0x80 /* Prohibit updates. */ -#define DS1687_CTRL_C 0x0c /* Control register C. */ -#define DS1687_CTRL_D 0x0d /* Control register D. */ - -#define DS1687_CENTURY 0x48 /* Century (bank 1). */ -#define DS1687_DATE_ALRM 0x49 /* Date alarm (bank 1). */ - -#define DS1687_EXT_CTRL 0x4a /* Extended control register. */ -#define DS1687_KICKSTART 0x01 /* Kickstart flag. */ - diff --git a/sys/dev/ic/seeq8003reg.h b/sys/dev/ic/seeq8003reg.h deleted file mode 100644 index c0978c67508..00000000000 --- a/sys/dev/ic/seeq8003reg.h +++ /dev/null @@ -1,134 +0,0 @@ -/* $OpenBSD: seeq8003reg.h,v 1.1 2012/03/28 20:44:23 miod Exp $ */ -/* $NetBSD: seeq8003reg.h,v 1.3 2001/06/07 05:19:26 thorpej Exp $ */ - -/* - * Copyright (c) 2000 Soren S. Jorvang. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions, and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* - * Register definitions for the Seeq 8003 and 80C03 ethernet controllers - * - * Based on documentation available at - * http://www.lsilogic.com/techlib/techdocs/networking/eol/80c03.pdf . - */ - -#define SEEQ_ADDR0 0 /* Station Address Byte 0 */ -#define SEEQ_ADDR1 1 /* Station Address Byte 1 */ -#define SEEQ_ADDR2 2 /* Station Address Byte 2 */ -#define SEEQ_ADDR3 3 /* Station Address Byte 3 */ -#define SEEQ_ADDR4 4 /* Station Address Byte 4 */ -#define SEEQ_ADDR5 5 /* Station Address Byte 5 */ - -#define SEEQ_TXCOLLS0 0 /* Transmit Collision Counter LSB */ -#define SEEQ_TXCOLLS1 1 /* Transmit Collision Counter MSB */ -#define SEEQ_ALLCOLL0 2 /* Total Collision Counter LSB */ -#define SEEQ_ALLCOLL1 3 /* Total Collision Counter MSB */ - -#define SEEQ_TEST 4 /* "For Test Only" - Do Not Use */ - -#define SEEQ_SQE 5 /* SQE / No Carrier */ -#define SQE_FLAG 0x01 /* SQE Flag */ -#define SQE_NOCARR 0x02 /* No Carrier Flag */ - -#define SEEQ_RXCMD 6 /* Rx Command */ -#define RXCMD_IE_OFLOW 0x01 /* Interrupt on Overflow Error */ -#define RXCMD_IE_CRC 0x02 /* Interrupt on CRC Error */ -#define RXCMD_IE_DRIB 0x04 /* Interrupt on Dribble Error */ -#define RXCMD_IE_SHORT 0x08 /* Interrupt on Short Frame */ -#define RXCMD_IE_END 0x10 /* Interrupt on End of Frame */ -#define RXCMD_IE_GOOD 0x20 /* Interrupt on Good Frame */ -#define RXCMD_REC_MASK 0xc0 /* Receiver Match Mode Mask */ -#define RXCMD_REC_NONE 0x00 /* Receiver Disabled */ -#define RXCMD_REC_ALL 0x40 /* Receive All Frames */ -#define RXCMD_REC_BROAD 0x80 /* Receive Station/Broadcast Frames */ -#define RXCMD_REC_MULTI 0xc0 /* Station/Broadcast/Multicast */ - -#define SEEQ_RXSTAT 6 /* Rx Status */ -#define RXSTAT_OFLOW 0x01 /* Frame Overflow Error */ -#define RXSTAT_CRC 0x02 /* Frame CRC Error */ -#define RXSTAT_DRIB 0x04 /* Frame Dribble Error */ -#define RXSTAT_SHORT 0x08 /* Received Short Frame */ -#define RXSTAT_END 0x10 /* Received End of Frame */ -#define RXSTAT_GOOD 0x20 /* Received Good Frame */ -#define RXSTAT_OLDNEW 0x80 /* Old/New Status */ - -#define SEEQ_TXCMD 7 /* Tx Command */ -#define TXCMD_IE_UFLOW 0x01 /* Interrupt on Transmit Underflow */ -#define TXCMD_IE_COLL 0x02 /* Interrupt on Transmit Collision */ -#define TXCMD_IE_16COLL 0x04 /* Interrupt on 16 Collisions */ -#define TXCMD_IE_GOOD 0x08 /* Interrupt on Transmit Succes */ -#define TXCMD_ENABLE_C 0xf0 /* (80C03) Enable 80C03 Mode */ -#define TXCMD_BANK_MASK 0x60 /* (80C03) Register Bank Mask */ -#define TXCMD_BANK0 0x00 /* (80C03) Register Bank 0 (8003) */ -#define TXCMD_BANK1 0x20 /* (80C03) Register Bank 1 (Writes) */ -#define TXCMD_BANK2 0x40 /* (80C03) Register Bank 2 (Writes) */ - -#define SEEQ_TXSTAT 7 /* Tx Status */ -#define TXSTAT_UFLOW 0x01 /* Transmit Underflow */ -#define TXSTAT_COLL 0x02 /* Transmit Collision */ -#define TXSTAT_16COLL 0x04 /* 16 Collisions */ -#define TXSTAT_GOOD 0x08 /* Transmit Success */ -#define TXSTAT_OLDNEW 0x80 /* Old/New Status */ - -/* - * 80C03 Mode Register Bank 1 - */ - -#define SEEQ_MC_HASH0 0 /* Multicast Filter Byte 0 (LSB) */ -#define SEEQ_MC_HASH1 1 /* Multicast Filter Byte 1 */ -#define SEEQ_MC_HASH2 2 /* Multicast Filter Byte 2 */ -#define SEEQ_MC_HASH3 3 /* Multicast Filter Byte 3 */ -#define SEEQ_MC_HASH4 4 /* Multicast Filter Byte 4 */ -#define SEEQ_MC_HASH5 5 /* Multicast Filter Byte 5 */ - -/* - * 80C03 Mode Register Bank 2 - */ - -#define SEEQ_MC_HASH6 0 /* Multicast Filter Byte 6 */ -#define SEEQ_MC_HASH7 1 /* Multicast Filter Byte 7 (MSB) */ - -#define SEEQ_RESERVED0 2 /* Reserved (Set to All Zeroes) */ - -#define SEEQ_TXCTRL 3 /* Tx Control */ -#define TXCTRL_TXCOLL 0x01 /* Clear/Enable Tx Collision Counter */ -#define TXCTRL_COLL 0x02 /* Clear/Enable Collision Counter */ -#define TXCTRL_SQE 0x04 /* Clear/Enable SQE Flag */ -#define TXCTRL_HASH 0x08 /* Enable Multicast Hash Filter */ -#define TXCTRL_SHORT 0x10 /* Receive Short (<13 Bytes) Frames */ -#define TXCTRL_NOCARR 0x20 /* Clear/Enable No Carrier Flag */ - -#define SEEQ_CFG 4 /* Transmit/Receive Configuration */ -#define CFG_RX_GRPADDR 0x01 /* Ignore Last 4 Bits of Address */ -#define CFG_TX_AUTOPAD 0x02 /* Automatically Pad to 60 Bytes */ -#define CFG_TX_NOPRE 0x04 /* Do Not Add Preamble Pattern */ -#define CFG_RX_NOOWN 0x08 /* Do Not Receive Own Packets */ -#define CFG_TX_NOCRC 0x10 /* No Not Append CRC */ -#define CFG_TX_DUPLEX 0x20 /* AutoDUPLEX - Ignore Carrier */ -#define CFG_RX_CRCFIFO 0x40 /* Write CRC to FIFO */ -#define CFG_RX_FASTDISC 0x80 /* Fast Receive Discard Mode */ - -#define SEEQ_RESERVED1 5 /* Reserved */ -#define SEEQ_RESERVED2 6 /* Reserved */ -#define SEEQ_RESERVED3 7 /* Reserved */ |